Solid-state imaging device and electronic apparatus

Abstract

[Problem] To improve the performance of a solid-state imaging device. [Solution] A solid-state imaging device is formed by laminating first, second, and third substrates in this order. The first substrate has a first semiconductor substrate and a first multilayer wiring layer. The second substrate has a second semiconductor substrate and a second multilayer wiring layer. The third substrate has a third semiconductor substrate and a third multilayer wiring layer. The first substrate and the second substrate are bonded together such that the first multilayer wiring layer and the second multilayer wiring layer face each other. A first connection structure for electrically connecting two of the first, second and third substrates includes a via hole. The structure of the via hole is that: on the inner wall of a first through hole that exposes a first wiring included in one of the first, second, and third multilayer wiring layers, and on the inner wall of a second through hole that exposes a second wiring included in a multilayer wiring layer that does not include the first wiring among the first, second, and third multilayer wiring layers; the conductive material is embedded or formed as a film.

Description

[0001] This application is a divisional application of the patent application with application number 201880022382.4, filed on March 23, 2018, and with the invention name “Solid-state imaging device and electronic device”. Technical Field

[0002] The present invention relates to a solid-state imaging device and an electronic apparatus. Background Art

[0003] Solid-state imaging devices have been developed that have a structure in which a pixel chip, which includes pixel cells, and a logic chip, which includes logic circuits, are stacked. The logic circuit performs various signal processing related to the operation of the solid-state imaging device. For example, Patent Document 1 discloses a three-layer stacked solid-state imaging device in which a pixel chip, a logic chip, and a memory chip, which includes a memory circuit, are stacked. The memory circuit stores pixel signals acquired by the pixel cells of the pixel chip.

[0004] Note that when describing the structure of a solid-state imaging device, a semiconductor substrate on which a pixel chip, a logic chip or a memory chip is formed and a multilayer wiring layer formed on the semiconductor substrate are combined, and a component including such a combination is referred to as a "substrate". In addition, the "substrate" is referred to as a "first substrate", "second substrate", "third substrate"... from the upper side of the stacked structure (the side where the observation light is incident) to the lower side in order to distinguish each substrate from each other. Note that the stacked solid-state imaging device is manufactured by stacking the individual substrates in a wafer state and then cutting the stacked substrates into a plurality of stacked solid-state imaging devices (i.e., stacked solid-state imaging device chips). For convenience, this specification assumes that: "substrate" can mean the wafer state before cutting, or the chip state after cutting.

[0005] Reference List

[0006] Patent Literature

[0007] Patent Document 1: Japanese Unexamined Patent Application No. 2014-99582 Summary of the Invention

[0008] Technical Problems to be Solved by the Invention

[0009] In the stacked solid-state imaging device described in Patent Document 1, several methods have been conceived to electrically connect the signal lines included in the upper and lower substrates to each other and to electrically connect the power lines included in the upper and lower substrates to each other. Examples of the method include: a method of connecting the signal lines to each other and the power lines to each other outside the chip through pads; and a method of connecting the signal lines to each other and the power lines to each other inside the chip using through-silicon vias (TSVs), etc. So far, variations of the method of electrically connecting the signal lines included in the substrate to each other and the power lines included in the substrate to each other have not been explored in detail. A detailed study of these variations may provide insight into appropriate structures to obtain solid-state imaging devices that exhibit higher performance.

[0010] Therefore, the present invention proposes a novel and improved solid-state imaging device and electronic apparatus capable of further improving performance.

[0011] Solutions to technical problems

[0012] According to the present invention, a solid-state imaging device is provided, comprising a first substrate, a second substrate, and a third substrate. The first substrate comprises a first semiconductor substrate and a first multilayer wiring layer stacked thereon. A pixel unit having pixels arranged thereon is formed on the first semiconductor substrate. The second substrate comprises a second semiconductor substrate and a second multilayer wiring layer stacked thereon. The third substrate comprises a third semiconductor substrate and a third multilayer wiring layer stacked thereon. Circuits having predetermined functions are formed on the second and third semiconductor substrates. The first, second, and third substrates are stacked in this order. The first and second substrates are joined together with the first and second multilayer wiring layers facing each other. A first connection structure for electrically connecting two of the first, second, and third substrates to each other comprises a via. The via has a structure in which a conductive material is embedded in one through-hole and another through-hole, or a structure in which a film made of a conductive material is formed on the inner wall of the through-hole. The one through-hole is configured to expose a first wiring included in one of the first, second, and third multilayer wiring layers. The other through-hole is provided to expose a second wiring included in one of the first, second, and third multilayer wiring layers other than the multilayer wiring layer including the first wiring.

[0013] According to the present invention, an electronic device is provided, comprising a solid-state imaging device for electronically capturing an image of an object. The solid-state imaging device comprises a first substrate, a second substrate, and a third substrate. The first substrate comprises a first semiconductor substrate and a first multilayer wiring layer stacked thereon. A pixel unit having pixels arranged thereon is formed on the first semiconductor substrate. The second substrate comprises a second semiconductor substrate and a second multilayer wiring layer stacked thereon. The third substrate comprises a third semiconductor substrate and a third multilayer wiring layer stacked thereon. Circuits having predetermined functions are formed on the second and third semiconductor substrates. The first, second, and third substrates are stacked in this order. The first and second substrates are joined together with the first and second multilayer wiring layers facing each other. A first connection structure for electrically connecting two of the first, second, and third substrates to each other comprises a via. The via has a structure in which a conductive material is embedded in one through-hole and another through-hole, or a structure in which a film made of a conductive material is formed on the inner wall of the through-hole. The one through-hole is configured to expose a first wiring included in one of the first, second, and third multilayer wiring layers. The other through-hole is provided to expose a second wiring included in one of the first, second, and third multilayer wiring layers other than the multilayer wiring layer including the first wiring.

[0014] According to the present invention, in a solid-state imaging device constructed by stacking three substrates, a first substrate and a second substrate are bonded face-to-face with each other (details of which will be described later), and a via hole (i.e., a double-contact type via hole between two layers or between three layers, described later) is provided. The via hole has a structure in which a conductive material is buried in one through-hole and another through-hole, or a structure in which a film made of a conductive material is formed on the inner wall of the through-hole. The one through-hole is provided to expose a first wiring included in one of the first multilayer wiring layer of the first substrate, the second multilayer wiring layer of the second substrate, and the third multilayer wiring layer of the third substrate. The other through-hole is provided to expose a second wiring included in one of the first multilayer wiring layer, the second multilayer wiring layer, and the third multilayer wiring layer, excluding the multilayer wiring layer containing the first wiring. This arrangement provides various connection structures, including a second connection structure for electrically connecting the signal lines provided in the second and third substrates and the power lines provided in the second and third substrates, and / or a third connection structure for electrically connecting the signal lines provided in the first and third substrates and the power lines provided in the first and third substrates. This enables various variations in the connection structure. Consequently, an excellent solid-state imaging device can be realized, allowing for further improvements in performance.

[0015] Beneficial effects of the present invention

[0016] As described above, according to the present invention, the performance of solid-state imaging devices can be further improved. Note that the above-mentioned effects are not necessarily restrictive. In addition to or in place of the above-mentioned effects, any of the effects described in this specification or other effects that can be understood from this specification can be achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 is a vertical sectional view of a schematic configuration of a solid-state imaging device according to an embodiment of the present invention.

[0018] Figure 2A It is an explanatory diagram of an example of arrangement of a connection structure in a solid-state imaging device within a horizontal plane.

[0019] Figure 2B It is an explanatory diagram of an example of arrangement of a connection structure in a solid-state imaging device within a horizontal plane.

[0020] Figure 2C It is an explanatory diagram of another example of arrangement of the connection structure in the solid-state imaging device within the horizontal plane.

[0021] Figure 2DIt is an explanatory diagram of another example of arrangement of the connection structure in the solid-state imaging device within the horizontal plane.

[0022] Figure 2E This is an explanatory diagram of another example of arrangement of the connection structure in the solid-state imaging device within the horizontal plane.

[0023] Figure 2F It is an explanatory diagram of another example of arrangement of the connection structure in the solid-state imaging device in the horizontal plane.

[0024] Figure 3A It is a vertical sectional view of a schematic configuration of a solid-state imaging device in which a first substrate and a second substrate are bonded to each other in a face-to-face manner.

[0025] Figure 3B It is a vertical sectional view of a schematic configuration of a solid-state imaging device in which a first substrate and a second substrate are bonded to each other in a face-to-back manner.

[0026] Figure 4A yes Figure 3A An explanatory diagram of parasitic capacitance between PWELL and a power supply line in the solid-state imaging device shown.

[0027] Figure 4B yes Figure 3B An explanatory diagram of parasitic capacitance between PWELL and a power supply line in the solid-state imaging device shown.

[0028] Figure 5A yes Figure 3A Schematic arrangement diagram of power supply wiring and GND wiring in the solid-state imaging device shown.

[0029] Figure 5B yes Figure 3B Schematic arrangement diagram of power supply wiring and GND wiring in the solid-state imaging device shown.

[0030] Figure 5C The diagram shows the Figure 5A An example of a configuration in which impedance is reduced in a solid-state imaging device is shown.

[0031] Figure 6A is a vertical sectional view of a schematic configuration of a solid-state imaging device according to a first configuration example of the present embodiment.

[0032] Figure 6B is a vertical sectional view of a schematic configuration of a solid-state imaging device according to a first configuration example of the present embodiment.

[0033] Figure 6C is a vertical sectional view of a schematic configuration of a solid-state imaging device according to a first configuration example of the present embodiment.

[0034] Figure 6D is a vertical sectional view of a schematic configuration of a solid-state imaging device according to a first configuration example of the present embodiment.

[0035] Figure 6E is a vertical sectional view of a schematic configuration of a solid-state imaging device according to a first configuration example of the present embodiment.

[0036] Figure 7A is a vertical sectional view of a schematic configuration of a solid-state imaging device according to a second configuration example of the present embodiment.

[0037] Figure 7B is a vertical sectional view of a schematic configuration of a solid-state imaging device according to a second configuration example of the present embodiment.

[0038] Figure 7C is a vertical sectional view of a schematic configuration of a solid-state imaging device according to a second configuration example of the present embodiment.

[0039] Figure 7D is a vertical sectional view of a schematic configuration of a solid-state imaging device according to a second configuration example of the present embodiment.

[0040] Figure 7E is a vertical sectional view of a schematic configuration of a solid-state imaging device according to a second configuration example of the present embodiment.

[0041] Figure 7F is a vertical sectional view of a schematic configuration of a solid-state imaging device according to a second configuration example of the present embodiment.

[0042] Figure 7G is a vertical sectional view of a schematic configuration of a solid-state imaging device according to a second configuration example of the present embodiment.

[0043] Figure 7H is a vertical sectional view of a schematic configuration of a solid-state imaging device according to a second configuration example of the present embodiment.

[0044] Figure 7I is a vertical sectional view of a schematic configuration of a solid-state imaging device according to a second configuration example of the present embodiment.

[0045] Figure 7J is a vertical sectional view of a schematic configuration of a solid-state imaging device according to a second configuration example of the present embodiment.

[0046] Figure 7K is a vertical sectional view of a schematic configuration of a solid-state imaging device according to a second configuration example of the present embodiment.

[0047] Figure 8A is a vertical sectional view of a schematic configuration of a solid-state imaging device according to a third configuration example of the present embodiment.

[0048] Figure 8B is a vertical sectional view of a schematic configuration of a solid-state imaging device according to a third configuration example of the present embodiment.

[0049] Figure 8C is a vertical sectional view of a schematic configuration of a solid-state imaging device according to a third configuration example of the present embodiment.

[0050] Figure 8D is a vertical sectional view of a schematic configuration of a solid-state imaging device according to a third configuration example of the present embodiment.

[0051] Figure 8E is a vertical sectional view of a schematic configuration of a solid-state imaging device according to a third configuration example of the present embodiment.

[0052] Figure 8F is a vertical sectional view of a schematic configuration of a solid-state imaging device according to a third configuration example of the present embodiment.

[0053] Figure 8G is a vertical sectional view of a schematic configuration of a solid-state imaging device according to a third configuration example of the present embodiment.

[0054] Figure 9A is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a fourth configuration example of the present embodiment.

[0055] Figure 9B is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a fourth configuration example of the present embodiment.

[0056] Figure 9C is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a fourth configuration example of the present embodiment.

[0057] Figure 9D is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a fourth configuration example of the present embodiment.

[0058] Figure 9E is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a fourth configuration example of the present embodiment.

[0059] Figure 9F is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a fourth configuration example of the present embodiment.

[0060] Figure 9G is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a fourth configuration example of the present embodiment.

[0061] Figure 9His a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a fourth configuration example of the present embodiment.

[0062] Figure 9I is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a fourth configuration example of the present embodiment.

[0063] Figure 9J is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a fourth configuration example of the present embodiment.

[0064] Figure 9K is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a fourth configuration example of the present embodiment.

[0065] Figure 10A is a vertical sectional view of a schematic configuration of a solid-state imaging device according to a fifth configuration example of the present embodiment.

[0066] Figure 10B is a vertical sectional view of a schematic configuration of a solid-state imaging device according to a fifth configuration example of the present embodiment.

[0067] Figure 10C is a vertical sectional view of a schematic configuration of a solid-state imaging device according to a fifth configuration example of the present embodiment.

[0068] Figure 10D is a vertical sectional view of a schematic configuration of a solid-state imaging device according to a fifth configuration example of the present embodiment.

[0069] Figure 10E is a vertical sectional view of a schematic configuration of a solid-state imaging device according to a fifth configuration example of the present embodiment.

[0070] Figure 10F is a vertical sectional view of a schematic configuration of a solid-state imaging device according to a fifth configuration example of the present embodiment.

[0071] Figure 10G is a vertical sectional view of a schematic configuration of a solid-state imaging device according to a fifth configuration example of the present embodiment.

[0072] Figure 11A is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a sixth configuration example of the present embodiment.

[0073] Figure 11B is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a sixth configuration example of the present embodiment.

[0074] Figure 11C is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a sixth configuration example of the present embodiment.

[0075] Figure 11D is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a sixth configuration example of the present embodiment.

[0076] Figure 11E is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a sixth configuration example of the present embodiment.

[0077] Figure 11F is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a sixth configuration example of the present embodiment.

[0078] Figure 12A is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a seventh configuration example of the present embodiment.

[0079] Figure 12B is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a seventh configuration example of the present embodiment.

[0080] Figure 12C is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a seventh configuration example of the present embodiment.

[0081] Figure 12D is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a seventh configuration example of the present embodiment.

[0082] Figure 12E is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a seventh configuration example of the present embodiment.

[0083] Figure 12F is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a seventh configuration example of the present embodiment.

[0084] Figure 12G is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a seventh configuration example of the present embodiment.

[0085] Figure 12H is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a seventh configuration example of the present embodiment.

[0086] Figure 12I is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a seventh configuration example of the present embodiment.

[0087] Figure 12J is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a seventh configuration example of the present embodiment.

[0088] Figure 12Kis a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a seventh configuration example of the present embodiment.

[0089] Figure 12L is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a seventh configuration example of the present embodiment.

[0090] Figure 13A is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to an eighth configuration example of the present embodiment.

[0091] Figure 13B is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to an eighth configuration example of the present embodiment.

[0092] Figure 13C is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to an eighth configuration example of the present embodiment.

[0093] Figure 13D is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to an eighth configuration example of the present embodiment.

[0094] Figure 13E is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to an eighth configuration example of the present embodiment.

[0095] Figure 13F is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to an eighth configuration example of the present embodiment.

[0096] Figure 13G is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to an eighth configuration example of the present embodiment.

[0097] Figure 13H is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to an eighth configuration example of the present embodiment.

[0098] Figure 14A is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a ninth configuration example of the present embodiment.

[0099] Figure 14B is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a ninth configuration example of the present embodiment.

[0100] Figure 14C is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a ninth configuration example of the present embodiment.

[0101] Figure 14D is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a ninth configuration example of the present embodiment.

[0102] Figure 14E is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a ninth configuration example of the present embodiment.

[0103] Figure 14F is a vertical sectional view of a schematic configuration of a solid-state imaging device according to a ninth configuration example of the present embodiment.

[0104] Figure 14G is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a ninth configuration example of the present embodiment.

[0105] Figure 14H is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a ninth configuration example of the present embodiment.

[0106] Figure 14I is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a ninth configuration example of the present embodiment.

[0107] Figure 14J is a vertical sectional view of a schematic configuration of a solid-state imaging device according to a ninth configuration example of the present embodiment.

[0108] Figure 14K is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a ninth configuration example of the present embodiment.

[0109] Figure 15A is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a tenth configuration example of the present embodiment.

[0110] Figure 15B is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a tenth configuration example of the present embodiment.

[0111] Figure 15C is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a tenth configuration example of the present embodiment.

[0112] Figure 15D is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a tenth configuration example of the present embodiment.

[0113] Figure 15E is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a tenth configuration example of the present embodiment.

[0114] Figure 15F is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a tenth configuration example of the present embodiment.

[0115] Figure 15Gis a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a tenth configuration example of the present embodiment.

[0116] Figure 16A is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to an eleventh configuration example of the present embodiment.

[0117] Figure 16B is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to an eleventh configuration example of the present embodiment.

[0118] Figure 16C is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to an eleventh configuration example of the present embodiment.

[0119] Figure 16D is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to an eleventh configuration example of the present embodiment.

[0120] Figure 16E is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to an eleventh configuration example of the present embodiment.

[0121] Figure 16F is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to an eleventh configuration example of the present embodiment.

[0122] Figure 16G is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to an eleventh configuration example of the present embodiment.

[0123] Figure 17A is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a twelfth configuration example of the present embodiment.

[0124] Figure 17B is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a twelfth configuration example of the present embodiment.

[0125] Figure 17C is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a twelfth configuration example of the present embodiment.

[0126] Figure 17D is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a twelfth configuration example of the present embodiment.

[0127] Figure 17E is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a twelfth configuration example of the present embodiment.

[0128] Figure 17F is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a twelfth configuration example of the present embodiment.

[0129] Figure 17G is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a twelfth configuration example of the present embodiment.

[0130] Figure 17H is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a twelfth configuration example of the present embodiment.

[0131] Figure 17I is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a twelfth configuration example of the present embodiment.

[0132] Figure 17J is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a twelfth configuration example of the present embodiment.

[0133] Figure 18A is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a thirteenth configuration example of the present embodiment.

[0134] Figure 18B is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a thirteenth configuration example of the present embodiment.

[0135] Figure 18C is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a thirteenth configuration example of the present embodiment.

[0136] Figure 18D is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a thirteenth configuration example of the present embodiment.

[0137] Figure 18E is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a thirteenth configuration example of the present embodiment.

[0138] Figure 18F is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a thirteenth configuration example of the present embodiment.

[0139] Figure 18G is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a thirteenth configuration example of the present embodiment.

[0140] Figure 19A is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a fourteenth configuration example of the present embodiment.

[0141] Figure 19B is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a fourteenth configuration example of the present embodiment.

[0142] Figure 19Cis a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a fourteenth configuration example of the present embodiment.

[0143] Figure 19D is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a fourteenth configuration example of the present embodiment.

[0144] Figure 19E is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a fourteenth configuration example of the present embodiment.

[0145] Figure 19F is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a fourteenth configuration example of the present embodiment.

[0146] Figure 19G is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a fourteenth configuration example of the present embodiment.

[0147] Figure 19H is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a fourteenth configuration example of the present embodiment.

[0148] Figure 19I is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a fourteenth configuration example of the present embodiment.

[0149] Figure 19J is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a fourteenth configuration example of the present embodiment.

[0150] Figure 19K is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a fourteenth configuration example of the present embodiment.

[0151] Figure 20A is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a fifteenth configuration example of the present embodiment.

[0152] Figure 20B is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a fifteenth configuration example of the present embodiment.

[0153] Figure 20C is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a fifteenth configuration example of the present embodiment.

[0154] Figure 20D is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a fifteenth configuration example of the present embodiment.

[0155] Figure 20E is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a fifteenth configuration example of the present embodiment.

[0156] Figure 20F is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a fifteenth configuration example of the present embodiment.

[0157] Figure 20G is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a fifteenth configuration example of the present embodiment.

[0158] Figure 21A is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a sixteenth configuration example of the present embodiment.

[0159] Figure 21B is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a sixteenth configuration example of the present embodiment.

[0160] Figure 21C is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a sixteenth configuration example of the present embodiment.

[0161] Figure 21D is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a sixteenth configuration example of the present embodiment.

[0162] Figure 21E is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a sixteenth configuration example of the present embodiment.

[0163] Figure 21F is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a sixteenth configuration example of the present embodiment.

[0164] Figure 21G is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a sixteenth configuration example of the present embodiment.

[0165] Figure 21H is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a sixteenth configuration example of the present embodiment.

[0166] Figure 21I is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a sixteenth configuration example of the present embodiment.

[0167] Figure 21J is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a sixteenth configuration example of the present embodiment.

[0168] Figure 21K is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a sixteenth configuration example of the present embodiment.

[0169] Figure 21Lis a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a sixteenth configuration example of the present embodiment.

[0170] Figure 21M is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a sixteenth configuration example of the present embodiment.

[0171] Figure 22A is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a seventeenth configuration example of the present embodiment.

[0172] Figure 22B is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a seventeenth configuration example of the present embodiment.

[0173] Figure 22C is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a seventeenth configuration example of the present embodiment.

[0174] Figure 22D is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a seventeenth configuration example of the present embodiment.

[0175] Figure 22E is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a seventeenth configuration example of the present embodiment.

[0176] Figure 22F is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a seventeenth configuration example of the present embodiment.

[0177] Figure 22G is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a seventeenth configuration example of the present embodiment.

[0178] Figure 22H is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a seventeenth configuration example of the present embodiment.

[0179] Figure 22I is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a seventeenth configuration example of the present embodiment.

[0180] Figure 22J is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a seventeenth configuration example of the present embodiment.

[0181] Figure 22K is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a seventeenth configuration example of the present embodiment.

[0182] Figure 22L is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a seventeenth configuration example of the present embodiment.

[0183] Figure 22M is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a seventeenth configuration example of the present embodiment.

[0184] Figure 23A is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to an eighteenth configuration example of the present embodiment.

[0185] Figure 23B is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to an eighteenth configuration example of the present embodiment.

[0186] Figure 23C is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to an eighteenth configuration example of the present embodiment.

[0187] Figure 23D is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to an eighteenth configuration example of the present embodiment.

[0188] Figure 23E is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to an eighteenth configuration example of the present embodiment.

[0189] Figure 23F is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to an eighteenth configuration example of the present embodiment.

[0190] Figure 23G is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to an eighteenth configuration example of the present embodiment.

[0191] Figure 23H is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to an eighteenth configuration example of the present embodiment.

[0192] Figure 23I is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to an eighteenth configuration example of the present embodiment.

[0193] Figure 23J is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to an eighteenth configuration example of the present embodiment.

[0194] Figure 23K is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to an eighteenth configuration example of the present embodiment.

[0195] Figure 24A is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a nineteenth configuration example of the present embodiment.

[0196] Figure 24Bis a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a nineteenth configuration example of the present embodiment.

[0197] Figure 24C is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a nineteenth configuration example of the present embodiment.

[0198] Figure 24D is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a nineteenth configuration example of the present embodiment.

[0199] Figure 24E is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a nineteenth configuration example of the present embodiment.

[0200] Figure 24F is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a nineteenth configuration example of the present embodiment.

[0201] Figure 24G is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a nineteenth configuration example of the present embodiment.

[0202] Figure 24H is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a nineteenth configuration example of the present embodiment.

[0203] Figure 24I is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a nineteenth configuration example of the present embodiment.

[0204] Figure 24J is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a nineteenth configuration example of the present embodiment.

[0205] Figure 24K is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a nineteenth configuration example of the present embodiment.

[0206] Figure 24L is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a nineteenth configuration example of the present embodiment.

[0207] Figure 24M is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a nineteenth configuration example of the present embodiment.

[0208] Figure 25A is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a twentieth configuration example of the present embodiment.

[0209] Figure 25B is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a twentieth configuration example of the present embodiment.

[0210] Figure 25C is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a twentieth configuration example of the present embodiment.

[0211] Figure 25D is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a twentieth configuration example of the present embodiment.

[0212] Figure 25E is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a twentieth configuration example of the present embodiment.

[0213] Figure 25F is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a twentieth configuration example of the present embodiment.

[0214] Figure 25G is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a twentieth configuration example of the present embodiment.

[0215] Figure 25H is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a twentieth configuration example of the present embodiment.

[0216] Figure 25I is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a twentieth configuration example of the present embodiment.

[0217] Figure 25J is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a twentieth configuration example of the present embodiment.

[0218] Figure 25K is a vertical sectional view showing a schematic configuration of a solid-state imaging device according to a twentieth configuration example of the present embodiment.

[0219] Figure 26A The appearance of a smartphone as an example of an electronic device to which the solid-state imaging device according to the present embodiment can be applied is illustrated.

[0220] Figure 26B The external appearance of a digital camera as another example of an electronic device to which the solid-state imaging device according to the present embodiment can be applied is illustrated.

[0221] Figure 26C The external appearance of a digital camera as another example of an electronic device to which the solid-state imaging device according to the present embodiment can be applied is illustrated.

[0222] Figure 27A is a cross-sectional view of a configuration example of a solid-state imaging device to which the technology according to the present invention can be applied.

[0223] Figure 27B is an explanatory diagram illustrating a schematic configuration example of a solid-state imaging device to which the technology according to the present invention can be applied.

[0224] Figure 27C is an explanatory diagram illustrating a schematic configuration example of a video camera to which the technology according to the present invention can be applied.

[0225] Figure 27D is a diagram illustrating a schematic configuration example of an endoscopic surgery system.

[0226] Figure 27E is a block diagram illustrating an example of a functional configuration of a camera head and a camera control unit (CCU).

[0227] Figure 27F is a block diagram illustrating a schematic configuration example of a vehicle control system.

[0228] Figure 27G This is an auxiliary explanatory diagram showing an example of the installation positions of the vehicle exterior information detection unit and the camera unit. DETAILED DESCRIPTION

[0229] Hereinafter, a description will be given of preferred embodiments of the present invention in detail with reference to the accompanying drawings. Note that in this specification and the accompanying drawings, repeated description of components having substantially the same functional configuration will be omitted by assigning the same reference numerals.

[0230] In the drawings described below, the sizes of some components may be exaggerated for illustration in some cases for the sake of explanation. The relative sizes of components shown in the drawings are not necessarily accurate representations of the size relationships between actual components.

[0231] Note that the description is given in the following order.

[0232] 1. Overall Structure of a Solid-State Imaging Device

[0233] 2. About the setting of connection structure

[0234] 3. About the direction of the second substrate

[0235] 3-1. Considerations based on PWELL area

[0236] 3-2. Consideration Based on Power Consumption and GND Wiring Arrangement 4. Variations in the Configuration of the Solid-State Imaging Device

[0237] 4-1. First Configuration Example

[0238] 4-2. Second Configuration Example

[0239] 4-3. Third structural example

[0240] 4-4. Fourth Configuration Example

[0241] 4-5. Fifth Configuration Example

[0242] 4-6. Sixth Configuration Example

[0243] 4-7. Seventh structural example

[0244] 4-8. Eighth Construction Example

[0245] 4-9. Ninth construction example

[0246] 4-10. Tenth construction example

[0247] 4-11. Eleventh construction example

[0248] 4-12. Twelfth Construction Example

[0249] 4-13. Thirteenth Construction Example

[0250] 4-14. Fourteenth Construction Example

[0251] 4-15. Fifteenth construction example

[0252] 4-16. Sixteenth Construction Example

[0253] 4-17. Seventeenth construction example

[0254] 4-18. Eighteenth Construction Example

[0255] 4-19. Nineteenth construction example

[0256] 4-20. Twentieth construction example

[0257] 4-21. Summary

[0258] 5. Application Examples

[0259] 6. Supplement

[0260] (1. Overall Structure of Solid-State Imaging Device)

[0261] Figure 1 : is a vertical cross-sectional view showing a schematic configuration of a solid-state imaging device according to an embodiment of the present invention. Figure 1As shown, the solid-state imaging device 1 according to the present embodiment is a three-layer stacked solid-state imaging device, which includes a stacked first substrate 110A, a second substrate 110B, and a third substrate 110C. In the figure, the dotted line AA represents the bonding surface of the first substrate 110A and the second substrate 110B, and the dotted line BB represents the bonding surface of the second substrate 110B and the third substrate 110C. The first substrate 110A is a pixel substrate provided with a pixel unit. The second substrate 110B and the third substrate 110C are provided with circuits for performing various signal processing related to the operation of the solid-state imaging device 1. The second substrate 110B and the third substrate 110C are, for example, a logic substrate provided with a logic circuit or a storage substrate provided with a storage circuit. The solid-state imaging device 1 is a back-illuminated CMOS (Complementary Metal-Oxide-Semiconductor) image sensor, which photoelectrically converts light incident from the back side of the first substrate 110A in the pixel unit, which will be described below. Note that for the purpose of illustration, Figure 1 In the following, a case where the second substrate 110B is a logic substrate and the third substrate 110C is a memory substrate is described as an example.

[0262] In the stacked solid-state imaging device 1, circuits can be more appropriately configured to suit the functions of each substrate. Consequently, it is easier to achieve higher performance in the solid-state imaging device 1. In the illustrated configuration example, the pixel cells in the first substrate 110A and the logic circuits or memory circuits in the second substrate 110B and third substrate 110C can be appropriately configured to suit the functions of each substrate. This allows for a high-performance solid-state imaging device 1.

[0263] In the following, the direction in which the first substrate 110A, the second substrate 110B, and the third substrate 110C are stacked is also referred to as the z-axis direction. In addition, the direction in which the first substrate 110A is placed in the z-axis direction is defined as the positive direction of the z-axis. In addition, the two directions perpendicular to each other on the surface (horizontal surface) perpendicular to the z-axis direction are also referred to as the x-axis direction and the y-axis direction, respectively. In addition, in the following, in each substrate, of the two surfaces opposite to the main surface direction of the semiconductor substrates 101, 121, and 131 described later, the surface on the side where functional components such as transistors are provided or the surface on the side where the multilayer wiring layers 105, 125, and 135 that enable the functional components to operate, which will be described later, are provided is also referred to as the front side (front side surface), and the other surface opposite to this surface is also referred to as the back side (back side surface). In each substrate, the side where the front side is provided is referred to as the front side (front side), and the side where the back side is provided is also referred to as the back side (back side).

[0264] The first substrate 110A primarily comprises a semiconductor substrate 101 formed of, for example, silicon (Si) and a multilayer wiring layer 105 formed on the semiconductor substrate 101. A pixel unit, in which pixels are arranged two-dimensionally, and a pixel signal processing circuit that processes pixel signals are primarily formed on the semiconductor substrate 101. Each pixel primarily comprises a photodiode (PD) that receives light from an observation target (observation light) and performs photoelectric conversion, and a driver circuit, which includes transistors and the like that read out an electrical signal (pixel signal) corresponding to the observation light captured by the PD. The pixel signal processing circuit performs various types of signal processing, such as analog-to-digital conversion (AD conversion), on the pixel signal. Note that in this embodiment, the pixel unit is not limited to one in which pixels are arranged two-dimensionally; pixels may be arranged three-dimensionally. Furthermore, in this embodiment, a substrate composed of a material other than semiconductors may be used in place of the semiconductor substrate 101. For example, a sapphire substrate may be used in place of the semiconductor substrate 101. In this case, a mode may be employed in which a film that performs photoelectric conversion (e.g., an organic photoelectric conversion film) is deposited on the sapphire substrate to form the pixels.

[0265] The insulating film 103 is stacked on the front side of the semiconductor substrate 101 on which the pixel unit and the pixel signal processing circuit are formed. Within the insulating film 103, a multilayer wiring layer 105 is formed, which includes signal line wiring for transmitting various signals, such as pixel signals and drive signals for driving the transistors of the drive circuit. The multilayer wiring layer 105 also includes power wiring, ground wiring (GND wiring), etc. Note that hereinafter, for simplicity, the signal line wiring may be referred to as signal line in some cases. In addition, the power wiring and the GND wiring are collectively referred to as power lines in some cases. The lowermost wiring of the multilayer wiring layer 105 can be electrically connected to the pixel unit or the pixel signal processing circuit through a contact portion 107 in which a conductive material such as tungsten (W) is buried. In fact, a plurality of wiring layers can be formed by repeatedly forming an interlayer insulating film having a predetermined thickness and forming a wiring layer. However, in Figure 1 In the drawings, for simplicity, these multi-layer interlayer insulating films are collectively referred to as insulating films 103 , and the plurality of wiring layers are collectively referred to as multi-layer wiring layers 105 .

[0266] Note that pads 151 functioning as external input / output units (I / O units) for exchanging various signals with the outside may be formed in the multilayer wiring layer 105. The pads 151 may be provided along the outer periphery of the chip.

[0267] The second substrate 110B is, for example, a logic substrate. The second substrate 110B mainly includes a semiconductor substrate 121 formed of, for example, Si and a multilayer wiring layer 125 formed on the semiconductor substrate 121. A logic circuit is formed on the semiconductor substrate 121. In the logic circuit, various types of signal processing related to the operation of the solid-state imaging device 1 are performed. For example, in the logic circuit, control of a drive signal for driving the pixel unit of the first substrate 110A (that is, drive control of the pixel unit) and signal exchange with the outside can be controlled. Note that in this embodiment, a substrate including a material other than a semiconductor can be used instead of the semiconductor substrate 121. For example, a sapphire substrate can be used instead of the semiconductor substrate 121. In this case, a mode can be used in which a semiconductor film (for example, a Si film) is deposited on a sapphire substrate and a logic circuit is formed in the semiconductor film.

[0268] An insulating film 123 is stacked on the front side of the semiconductor substrate 121 on which the logic circuit is formed. A multilayer wiring layer 125 for transmitting various signals related to the operation of the logic circuit is formed within the insulating film 123. The multilayer wiring layer 125 also includes power wiring, GND wiring, etc. The lowermost wiring of the multilayer wiring layer 125 can be electrically connected to the logic circuit through, for example, a contact portion 127 in which a conductive material such as W is embedded. Note that, similar to the insulating film 103 and the multilayer wiring layer 105 of the first substrate 110A, the insulating film 123 of the second substrate 110B can also be a general term for an interlayer insulating film in a multilayer form, and the multilayer wiring layer 125 can be a general term for a wiring layer in a multilayer form.

[0269] The third substrate 110C is, for example, a storage substrate. The third substrate 110C mainly includes a semiconductor substrate 131 formed of, for example, Si and a multilayer wiring layer 135 formed on the semiconductor substrate 131. A storage circuit is formed on the semiconductor substrate 131. The storage circuit temporarily stores the pixel signal acquired by the pixel unit of the first substrate 110A and AD-converted by the pixel signal processing circuit. Temporarily storing the pixel signal in the storage circuit makes a global shutter possible and allows the pixel signal to be read out from the solid-state imaging device 1 to the outside at a higher speed. Therefore, even when shooting at high speed, it is possible to capture a higher quality image with suppressed distortion. Note that in this embodiment, a substrate including a material other than a semiconductor can be used instead of the semiconductor substrate 131. For example, a sapphire substrate can be used instead of the semiconductor substrate 131. In this case, the following mode can be used: a film for forming a storage element (for example, a phase change material film) is deposited on a sapphire substrate, and a storage circuit is formed using the film.

[0270] An insulating film 133 is stacked on the front surface of the semiconductor substrate 131 on which the memory circuit is formed. A multilayer wiring layer 135 for transmitting various signals related to the operation of the memory circuit is formed within the insulating film 133. The multilayer wiring layer 135 also includes power wiring, GND wiring, etc. The lowermost wiring of the multilayer wiring layer 135 can be electrically connected to the memory circuit, for example, via a contact portion 137 in which a conductive material such as W is embedded. Note that, similar to the insulating film 103 and the multilayer wiring layer 105 of the first substrate 110A, the insulating film 133 of the third substrate 110C can also be a general term for an interlayer insulating film in a multilayer form, and the multilayer wiring layer 135 can be a general term for a wiring layer in a multilayer form.

[0271] In the multi-layer wiring layer 135, pads 151 functioning as I / O units for exchanging various signals with the outside may be formed. The pads 151 may be provided along the outer periphery of the chip.

[0272] The first substrate 110A, the second substrate 110B, and the third substrate 110C are each manufactured in a wafer state, and then these substrates are bonded together and subjected to a process for electrically connecting the respective signal lines provided in the substrates to each other and the respective power supply lines provided in the respective substrates to each other.

[0273] Specifically, first, the first substrate 110A in a wafer state and the second substrate 110B in a wafer state are bonded together so that the front surface of the semiconductor substrate 101 of the first substrate 110A (the surface on which the multilayer wiring layer 105 is provided) and the front surface of the semiconductor substrate 121 of the second substrate 110B (the surface on which the multilayer wiring layer 125 is provided) face each other. Hereinafter, the state in which these two substrates are bonded together and the surfaces of the semiconductor substrates face each other is also referred to as F-TO-F (face-to-face).

[0274] Subsequently, the third substrate 110C in a wafer state is further bonded to the multilayer structure of the first substrate 110A and the second substrate 110B in a wafer state, with the back surface of the semiconductor substrate 121 of the second substrate 110B (the surface on the side opposite to the side on which the multilayer wiring layer 125 is provided) and the front surface of the semiconductor substrate 131 of the third substrate 110C (the surface on the side on which the multilayer wiring layer 135 is provided) facing each other. At this time, the semiconductor substrate 121 is thinned before this bonding step, and an insulating film 129 having a predetermined thickness is formed on the back side of the semiconductor substrate 121. Hereinafter, the state in which the two substrates are bonded and the respective front and back surfaces of the semiconductor substrates face each other is also referred to as F-TO-B (face-to-back).

[0275] Subsequently, the semiconductor substrate 101 of the first substrate 110A is thinned, and an insulating film 109 is formed on the back side of the semiconductor substrate 101. TSV 157 is formed to electrically connect the signal line in the first substrate 110A and the signal line in the second substrate 110B to each other, and to electrically connect the power line in the first substrate 110A and the power line in the second substrate 110B to each other. Note that in this specification, for simplicity, the wiring in one substrate and the wiring in another substrate are electrically connected to each other can be simplified to the term "one substrate and another substrate are electrically connected to each other". At this time, when it is stated that "the substrates are electrically connected to each other", the wiring that is actually electrically connected can be a signal line or a power line. In this specification, TSV represents a via provided from one surface of any one of the first substrate 110A, the second substrate 110B and the third substrate 110C for penetrating at least one of the semiconductor substrates 101, 121 or 131. In this embodiment, as described above, a substrate including a material other than semiconductor may be used instead of the semiconductor substrates 101 , 121 , and 131 ; however, in this specification, for convenience, a via provided to penetrate a substrate including such a material other than semiconductor is also referred to as a TSV.

[0276] TSVs 157 are formed from the back side of first substrate 110A toward second substrate 110B and are configured to electrically connect signal lines provided in first substrate 110A and signal lines provided in second substrate 110B, as well as to electrically connect power lines provided in first substrate 110A and power lines provided in second substrate 110B. Specifically, TSVs 157 are formed by forming a first through-hole that exposes a predetermined wiring line in multilayer wiring layer 105 of first substrate 110A and a second through-hole, different from the first through-hole, that exposes a predetermined wiring line in multilayer wiring layer 125 of second substrate 110B from the back side of first substrate 110A, and embedding a conductive material in the first through-hole and the second through-hole. TSVs 157 allow electrical connection between the predetermined wiring line in multilayer wiring layer 105 of first substrate 110A and the predetermined wiring line in multilayer wiring layer 125 of second substrate 110B. Note that TSVs that electrically connect wirings of a plurality of substrates through two different through-holes (openings passing through at least one semiconductor substrate) in this manner are also referred to as twin contacts.

[0277] exist Figure 1 In the configuration example shown in , TSV 157 is formed by embedding a first metal (e.g., copper (Cu)) contained in the multilayer wiring layers 105, 125, and 135 described later in the through-hole. However, the conductive material contained in TSV 157 does not necessarily need to be the same as the first metal, and any material can be used as the conductive material.

[0278] After forming the TSVs 157 , a color filter layer 111 (CF layer 111 ) and a microlens array 113 (ML array 113 ) are formed on the back side of the semiconductor substrate 101 of the first substrate 110A with an insulating film 109 interposed therebetween.

[0279] The CF layer 111 is constructed by arranging a plurality of CFs two-dimensionally. The ML array 113 is constructed by arranging a plurality of MLs two-dimensionally. The CF layer 111 and the ML array 113 are formed directly above the pixel unit, and one CF and one ML are arranged for the PD of one pixel.

[0280] Each CF in the CF layer 111 has, for example, any one of red, green, and blue. The observation light through the CF enters the PD of the pixel, and a pixel signal is acquired, thereby acquiring a pixel signal of the color component of the color filter for the observation target (that is, imaging in terms of color becomes possible). In fact, a pixel corresponding to a CF plays the role of a sub-pixel, and a pixel may include multiple sub-pixels. For example, in the solid-state imaging device 1, a pixel may include four-color sub-pixels: a pixel with a red CF (that is, a red pixel), a pixel with a green CF (that is, a green pixel), a pixel with a blue CF (that is, a blue pixel), and a pixel without a CF (that is, a white pixel). However, in this specification, for the sake of convenience, the structure corresponding to a sub-pixel will also be referred to as a pixel, without distinguishing between sub-pixels and pixels. Note that the arrangement method of CF is not particularly limited, and for example, it can be various arrangements, such as a delta arrangement, a stripe arrangement, a diagonal arrangement, or a rectangular arrangement.

[0281] The ML array 113 is formed to allow each ML to be placed directly above each CF. Providing the ML array 113 allows observation light collected by the ML to enter the PD of the pixel through the CF, which can improve the light collection efficiency of the observation light and thus achieve the effect of improving the sensitivity of the solid-state imaging device 1.

[0282] After forming the CF layer 111 and the ML array 113, pad openings 153a and 153b are formed, respectively, to expose the pads 151 provided in the multilayer wiring layer 105 of the first substrate 110A and the multilayer wiring layer 135 of the third substrate 110C. The pad opening 153a is formed to extend from the back side of the first substrate 110A to the metal surface of the pads 151 provided in the multilayer wiring layer 105 of the first substrate 110A. The pad opening 153b is formed to pass through the first and second substrates 110A and 110B from the back side of the first substrate 110A to the metal surface of the pads 151 provided in the multilayer wiring layer 135 of the third substrate 110C. The pads 151 and other external circuits are electrically connected to each other through the pad openings 153a and 153b, for example, by wire bonding. That is, the corresponding signal lines included in the first substrate 110A and the corresponding signal lines included in the third substrate 110C can be electrically connected to each other through other external circuits, and the corresponding power lines included in the first substrate 110A and the corresponding power lines included in the third substrate 110C can be electrically connected to each other through other external circuits.

[0283] In this manual, Figure 1 In the case where there are a plurality of pad openings 153 as shown in the drawing, the pad openings 153 are distinguished from one another by assigning different letters to the respective ends of the reference numerals for convenience, as in pad openings 153a, 153b, . . . .

[0284] Thereafter, the stacked wafer structure stacked and processed in a wafer state is diced for each individual solid-state imaging device 1 , thereby completing the solid-state imaging device 1 .

[0285] The schematic configuration of the solid-state imaging device 1 has been described above. As described above, in the solid-state imaging device 1, the corresponding signal lines provided in the first substrate 110A and the second substrate 110B are electrically connected to each other via the TSVs 157, and the corresponding power supply lines provided in the first substrate 110A and the second substrate 110B are electrically connected to each other via the TSVs 157. The pads 151 exposed by the pad openings 153a and 153b are connected to each other by means of electrical connection means (e.g., wiring arranged outside the solid-state imaging device 1), thereby enabling the corresponding signal lines provided in the second substrate 110B and the third substrate 110C to be electrically connected to each other, and the corresponding power supply lines provided in the second substrate 110B and the third substrate 110C to be electrically connected to each other. That is, the corresponding signal lines provided in the first substrate 110A, the second substrate 110B, and the third substrate 110C can be electrically connected together through the TSV 157, the pad 151, and the pad openings 153a and 153b, and the corresponding power lines provided in the first substrate 110A, the second substrate 110B, and the third substrate 110C can be electrically connected together through the TSV 157, the pad 151, and the pad openings 153a and 153b. Note that in this specification, the structure in which the corresponding signal lines and the corresponding power lines provided in the substrates are electrically connected to each other (for example, in Figure 1 The TSV 157, pad 151 and pad openings 153a and 153b shown in FIG are collectively referred to as a coupling structure. Figure 1 , an electrode bonding structure 159 (a structure that exists on bonding surfaces between substrates and is bonded in a state where electrodes respectively formed on the bonding surfaces are in direct contact with each other) described later is also included in the connection structure.

[0286] Note that the multilayer wiring layer 105 of the first substrate 110A, the multilayer wiring layer 125 of the second substrate 110B, and the multilayer wiring layer 135 of the third substrate 110C can be constructed by stacking a plurality of first metal wiring layers 141 including a first metal with relatively low resistance. The first metal is, for example, copper (Cu). Using Cu wiring can exchange signals at a higher speed. However, considering the bonding adhesion between the wiring and the wiring, the pad 151 can be formed by a second metal different from the first metal. Therefore, in the illustrated construction example, the multilayer wiring layer 105 of the first substrate 110A and the multilayer wiring layer 135 of the third substrate 110C, each provided with a pad 151, respectively includes a second metal wiring layer 143 formed by a second metal in the same layer as the pad 151. The second metal is, for example, aluminum (Al). In addition to the pad 151, the Al wiring can be used as, for example, a power supply wiring or a GND wiring that is usually formed as a wide wiring.

[0287] In addition, the first metal and the second metal are not limited to Cu and Al as exemplified above. As the first metal and the second metal, various types of metals can be used. Alternatively, each of the multilayer wiring layers 105, 125, and 135 can be formed of a conductive material other than a metal. It is sufficient that the wiring layer is formed of a conductive material, and its material is not limited. Instead of using two types of conductive materials, all wiring layers of the multilayer wiring layers 105, 125, and 135 including the pad 151 can be formed of the same conductive material.

[0288] In this embodiment, the TSV 157, the electrode and the via included in the electrode bonding structure 159 described later can also be formed by a first metal (e.g., Cu). For example, when the first metal is Cu, these structures can be formed by a single damascene method or a dual damascene method. However, this embodiment is not limited to this example, and part or all of these structures can be formed by a second metal, other metals different from either the first metal and the second metal, or other non-metallic conductive materials. For example, the via included in the TSV 157 and the electrode bonding structure 159 can be formed by embedding a metal material (e.g., W) with good embeddability in the opening. In the case where the via diameter is relatively small, considering the embeddability, a structure using W can be preferably applied. TSV 157 does not have to be formed by embedding a conductive material in a through hole, but can include a film of conductive material formed on the inner wall (side wall and bottom) of the through hole.

[0289] although Figure 1 Although illustration is omitted in the following figures, in the solid-state imaging device 1, an insulating material is present that electrically insulates the first metal from the second metal at the portion where the conductive material, such as the first metal and the second metal, is in contact with the semiconductor substrates 101, 121, and 131. The insulating material may be, for example, any of various known materials, such as silicon oxide (SiO2) or silicon nitride (SiN). The insulating material may be inserted between the conductive material and each of the semiconductor substrates 101, 121, and 131, or may be inside each of the semiconductor substrates 101, 121, and 131 and away from the portion where the conductive material and the semiconductor substrates 101, 121, and 131 are in contact with each other. For example, in the case of the TSV 157, the insulating material may be present between the inner wall of the through hole provided in the semiconductor substrates 101, 121, and 131 and the conductive material embedded in the through hole (that is, a film of the insulating material may be formed on the inner wall of the through hole). Alternatively, for the TSV 157, the insulating material may be present in a portion of the semiconductor substrates 101, 121, and 131 that is away from the through-hole provided in the semiconductor substrates 101, 121, and 131 by a predetermined distance in the horizontal plane direction. Figure 1 Although illustration is omitted in the following figures, when the first metal is Cu, a barrier metal is present to prevent Cu from diffusing in portions where Cu is in contact with the semiconductor substrates 101, 121, and 131 or the insulating films 103, 109, 123, 129, and 133. As the barrier metal, various known materials such as titanium nitride (TiN) or tantalum nitride (TaN) can be used.

[0290] Furthermore, the specific configurations and formation methods of the components formed on the semiconductor substrates 101, 121, and 131 of each substrate (the pixel unit and pixel signal processing circuit provided in the first substrate 110A, the logic circuit provided in the second substrate 110B, and the memory circuit provided in the third substrate 110C), the multilayer wiring layers 105, 125, and 135, and the insulating films 103, 109, 123, 129, and 133) can be similar to various known configurations and methods. Therefore, the specific configurations and formation methods will not be described in detail here.

[0291] For example, it is sufficient for the insulating films 103, 109, 123, 129 and 133 to be formed of a material having insulating properties. Their materials are not limited. The insulating films 103, 109, 123, 129 and 133 can be formed of, for example, SiO2 or SiN. In addition, the insulating films 103, 109, 123, 129 and 133 are not necessarily formed of one type of insulating material, but can be formed of a plurality of types of stacked insulating materials. In addition, for example, for the formation area of ​​the wiring required for transmitting signals at a higher speed in the insulating films 103, 123 and 133, a low-k material having insulating properties can be used. The use of low-k materials allows the parasitic capacitance between the wiring to be reduced, which can further contribute to higher-speed signal transmission.

[0292] As another specific structure of the components formed in the semiconductor substrates 101, 121 and 131 of each substrate, the multilayer wiring layers 105, 125 and 135 and the insulating films 103, 109, 123, 129 and 133 and another formation method thereof, for example, those structures and methods such as those described in Patent Document 1, which is a prior application filed by the applicant of the present application, can be appropriately applied.

[0293] In addition, in the above-mentioned construction example, the first substrate 110A is equipped with a pixel signal processing circuit that performs signal processing such as AD conversion on the pixel signal, but the present embodiment is not limited to this example. Part or all of the functions of the pixel signal processing circuit can be set to the second substrate 110B. This case can realize a solid-state imaging device 1 that performs so-called pixel-by-pixel analog-to-digital conversion (pixel ADC). In the pixel ADC, the pixel signal acquired by the PD set to each pixel is transmitted to the pixel signal processing circuit of the second substrate 110B in units of pixels, and in a pixel array in which a plurality of pixels are arranged in both the column direction and the row direction, AD conversion is performed, for example, in units of pixels. Compared with the solid-state imaging device 1 that includes an AD conversion circuit in each column of the pixel array and performs conventional column-by-column analog-to-digital conversion (column ADC), this allows the pixel signal to undergo AD conversion and readout at a higher speed. In the column ADC, the plurality of pixels included in the column undergo AD conversion sequentially. Note that, when the solid-state imaging device 1 is configured to be capable of performing pixel ADC, each pixel is provided with a connection structure electrically connecting each signal line provided in the first substrate 110A and each signal line provided in the second substrate 110B to each other.

[0294] Furthermore, in the above-described construction example, a case is described in which the second substrate 110B is a logic substrate and the third substrate 110C is a storage substrate. However, the present embodiment is not limited to this example. It is sufficient for the second substrate 110B and the third substrate 110C to be substrates having functions other than the functions of a pixel substrate, and the functions may be determined optionally. For example, the solid-state imaging device 1 does not necessarily include any storage circuit. In this case, for example, both the second substrate 110B and the third substrate 110C may function as a logic substrate. Alternatively, the logic circuit and the storage circuit may be distributed in the second substrate 110B and the third substrate 110C, and these substrates may cooperate to realize the functions of the logic substrate and the storage substrate. Alternatively, the second substrate 110B may be a storage substrate, and the third substrate 110C may be a logic substrate.

[0295] In addition, in the above-described configuration example, a Si substrate is used as the semiconductor substrates 101, 121, and 131 of each substrate, but the present embodiment is not limited to this example. As the semiconductor substrates 101, 121, and 131, for example, other types of semiconductor substrates such as gallium arsenide (GaAs) substrates or silicon carbide (SiC) substrates can be used. Alternatively, as described above, instead of the semiconductor substrates 101, 121, and 131, for example, substrates each formed of a material other than a semiconductor, such as a sapphire substrate, etc. can be used.

[0296] (2. About the connection structure setting)

[0297] As reference Figure 1As described above, in the solid-state imaging device 1, the signal lines included in the substrate can be electrically connected to each other via a connection structure, and / or the power lines included in the substrate can be electrically connected to each other across multiple substrates via a connection structure. By taking into account the configuration and performance of each substrate (chip), the arrangement of the connection structure within the horizontal plane can be appropriately determined to improve the performance of the entire solid-state imaging device 1. Several variations of the arrangement of the connection structure within the horizontal plane in the solid-state imaging device 1 will be described.

[0298] Figure 2A and Figure 2B Each is an explanatory diagram of an example of arrangement of a connection structure in a horizontal plane in the solid-state imaging device 1. For example, Figure 2A and Figure 2B Each illustrates the arrangement of the connection structure in the solid-state imaging device 1 in the case where a pixel signal processing circuit that performs processing such as AD conversion on a pixel signal is mounted on the first substrate 110A.

[0299] Figure 2A The diagram schematically illustrates a first substrate 110A, a second substrate 110B, and a third substrate 110C included in the solid-state imaging device 1. The electrical connection between the lower surface of the first substrate 110A (the surface opposing the second substrate 110B) and the upper surface of the second substrate 110B (the surface opposing the first substrate 110A) via a connection structure is indicated by a dashed line in a simulated manner, and the electrical connection between the lower surface of the second substrate 110B (the surface opposing the third substrate 110C) and the upper surface of the third substrate 110C (the surface opposing the second substrate 110B) via a connection structure is indicated by a solid line in a simulated manner.

[0300] On the upper surface of the first substrate 110A, the positions of the pixel unit 206 and the connection structure 201 are shown. The connection structure 201 plays the role of an external input / output unit (I / O unit), which is used to exchange various signals such as power signals and GND signals with the outside. Specifically, the connection structure 201 can be a pad 151 provided on the upper surface of the first substrate 110A. Alternatively, as shown in FIG. Figure 1 As shown, in the case where the pads 151 are provided in the multilayer wiring layer 105 of the first substrate 110A, the multilayer wiring layer 125 of the second substrate 110B, or the multilayer wiring layer 135 of the third substrate 110C, the connection structure 201 may be a pad opening 153 provided to expose the pads 151. Alternatively, the connection structure 201 may be a lead opening 155 described later. Figure 2AAs shown, the first substrate 110A is provided with a pixel unit 206 in the middle of the chip, and the connection structure 201 included in the I / O unit is provided around the pixel unit 206 (i.e., along the outer periphery of the chip). In addition, although not shown, the pixel signal processing circuit can also be provided around the pixel unit 206.

[0301] Figure 2B The schematic diagram shows the position of the connection structure 202 on the lower surface of the first substrate 110A, the position of the connection structure 203 on the upper surface of the second substrate 110B, the position of the connection structure 204 on the lower surface of the second substrate 110B, and the position of the connection structure 205 on the upper surface of the third substrate 110C. The connection structures 202 to 205 can be TSVs 157 provided between the substrates or electrode bonding structures 159 described later. Alternatively, as Figure 1 As shown, in the case where the pad 151 is provided in the multilayer wiring layer 125 of the second substrate 110B or the multilayer wiring layer 135 of the third substrate 110C, the pad opening 153 provided to expose the pad 151 among the connection structures 202 to 205 may be located directly below the connection structure 201. Alternatively, the connection structures 202 to 205 may be the lead opening 155 described later. Note that Figure 2B With Figure 2A The connection structures 202 to 205 are uniformly illustrated in the form of straight lines representing electrical connections. That is, the connection structure 202 on the lower surface of the first substrate 110A and the connection structure 203 on the upper surface of the second substrate 110B are represented by dotted lines, and the connection structure 204 on the lower surface of the second substrate 110B and the connection structure 205 on the upper surface of the third substrate 110C are represented by solid lines.

[0302] As described above, in the illustrated configuration example, the pixel signal processing circuit is mounted around the pixel unit 206 of the first substrate 110A. Therefore, the pixel signal acquired by the pixel unit 206 undergoes processing such as AD conversion by the pixel signal processing circuit on the first substrate 110A and is then transmitted to the circuit provided on the second substrate 110B. In addition, as described above, the connection structure 201 included in the I / O unit is also provided around the pixel unit 206 of the first substrate 110A. Therefore, as described above, Figure 2B As shown, in order to electrically connect the pixel signal processing circuit and the I / O unit to the circuit provided on the second substrate 110B, the connection structure 202 on the lower surface of the first substrate 110A is provided along the outer periphery of the chip in association with the area where the pixel signal processing circuit and the I / O unit are located. In addition, the connection structure 203 on the upper surface of the second substrate 110B is also provided along the outer periphery of the chip.

[0303] At the same time, the logic circuit or memory circuit mounted on the second substrate 110B and the third substrate 110C can be formed on the entire surface of the chip. The connection structure 204 on the lower surface of the second substrate 110B and the connection structure 205 on the upper surface of the third substrate 110C are thus provided over the entire surface of the chip in association with the positions where the logic circuit or memory circuit is mounted, such as Figure 2B shown.

[0304] Figure 2C and Figure 2D Each is an explanatory diagram of another example of the arrangement of the connection structure in the solid-state imaging device 1 within the horizontal plane. Figure 2C and Figure 2D Each illustrates a configuration of a connection structure in the case where, for example, the solid-state imaging device 1 is configured to be capable of performing pixel ADC. In this case, the pixel signal processing circuit is not mounted on the first substrate 110A but on the second substrate 110B.

[0305] Similar to Figure 2A , Figure 2C The first substrate 110A, the second substrate 110B, and the third substrate 110C included in the solid-state imaging device 1 are schematically illustrated. The electrical connection between the lower surface of the first substrate 110A (the surface opposite to the second substrate 110B) and the upper surface of the second substrate 110B (the surface opposite to the first substrate 110A) through the connection structure is represented by a dashed line or a dotted line in a simulated manner, and the electrical connection between the lower surface of the second substrate 110B (the surface opposite to the third substrate 110C) and the upper surface of the third substrate 110C (the surface opposite to the second substrate 110B) through the connection structure is represented by a solid line in a simulated manner. Among the lines representing the electrical connection between the lower surface of the first substrate 110A and the upper surface of the second substrate 110B, the dashed line represents, for example, also present Figure 2A The electrical connections related to the I / O unit are shown in the figure, while the dotted lines indicate that they do not exist. Figure 2A The electrical connections associated with the pixel ADC in.

[0306] Similar to Figure 2B , Figure 2D The diagram schematically illustrates the position of the connection structure 202 on the lower surface of the first substrate 110A, the position of the connection structure 203 on the upper surface of the second substrate 110B, the position of the connection structure 204 on the lower surface of the second substrate 110B, and the position of the connection structure 205 on the upper surface of the third substrate 110C. Figure 2D With Figure 2C The connection structures 202 to 205 are shown in the form of straight lines that represent electrical connections. That is, in the connection structure 202 on the lower surface of the first substrate 110A or the connection structure 203 on the upper surface of the second substrate 110B, for example, Figure 2A The electrical connections corresponding to the I / O units are represented by dashed lines, and the electrical connections related to the pixel ADCs are represented by dotted lines. In contrast, the connection structure 204 on the lower surface of the second substrate 110B and the connection structure 205 on the upper surface of the third substrate 110C are represented by solid lines.

[0307] As described above, in the illustrated configuration example, the pixel signal processing circuit is mounted on the second substrate 110B, and the pixel signal processing circuit is configured to be able to perform pixel ADC. That is, the pixel signal acquired by each pixel of the pixel unit 206 is transmitted to the pixel signal processing circuit mounted on the second substrate 110B directly below on a pixel basis, and the pixel signal processing circuit performs processing such as AD conversion. Figure 2C and Figure 2D As shown, in the construction example, therefore, the connection structure 202 on the lower surface of the first substrate 110A is set along the outer periphery of the chip in a manner associated with the area where the I / O unit exists (the connection structure 202 represented by the dotted line in the figure) so as to transmit the signal from the I / O unit to the circuit provided on the second substrate 110B, and is set throughout the entire area where the pixel unit 206 exists (the connection structure 202 represented by the dotted line in the figure) so as to transmit the pixel signal from each pixel of the pixel unit 206 to the circuit provided on the second substrate 110B.

[0308] The signal lines of the second substrate 110B and the third substrate 110C are electrically connected to each other, and the power lines of the second substrate 110B and the third substrate 110C are electrically connected to each other, similar to Figure 2A and Figure 2B The construction example shown. Therefore, Figure 2C and Figure 2D As shown, the connection structure 204 on the lower surface of the second substrate 110B and the connection structure 205 on the upper surface of the third substrate 110C are arranged over the entire surface of the chip.

[0309] Figure 2E and Figure 2F Each of them is an explanatory diagram of still another example of the arrangement of the connection structure in the solid-state imaging device 1 within the horizontal plane. Figure 2E and Figure 2F Each illustrates the configuration of a connection structure in the case where, for example, a memory circuit is mounted on the second substrate 110B.

[0310] Similar to Figure 2A , Figure 2EThe first substrate 110A, the second substrate 110B, and the third substrate 110C included in the solid-state imaging device 1 are schematically illustrated. The electrical connection between the lower surface of the first substrate 110A (the surface opposite to the second substrate 110B) and the upper surface of the second substrate 110B (the surface opposite to the first substrate 110A) through the connection structure is represented by a dashed line or a dotted line in a simulated manner, and the electrical connection between the lower surface of the second substrate 110B (the surface opposite to the third substrate 110C) and the upper surface of the third substrate 110C (the surface opposite to the second substrate 110B) through the connection structure is represented by a solid line or a dotted line in a simulated manner. Among the lines representing the electrical connection between the lower surface of the first substrate 110A and the upper surface of the second substrate 110B, the dashed line represents, for example, also present Figure 2A The electrical connections related to the I / O unit are shown in the figure, while the dotted lines indicate that they do not exist. Figure 2A Furthermore, among the lines representing electrical connections between the lower surface of the second substrate 110B and the upper surface of the third substrate 110C, the solid lines represent lines that also exist, for example. Figure 2A The electrical connections in FIG. 1 are related to signals not directly related to the operation of the memory circuit, and the dotted lines represent electrical connections not present in FIG. Figure 2A The electrical connections associated with the storage circuit.

[0311] Similar to Figure 2B , Figure 2F The diagram schematically illustrates the position of the connection structure 202 on the lower surface of the first substrate 110A, the position of the connection structure 203 on the upper surface of the second substrate 110B, the position of the connection structure 204 on the lower surface of the second substrate 110B, and the position of the connection structure 205 on the upper surface of the third substrate 110C. Figure 2F With Figure 2E The connection structures 202 to 205 are shown in the form of straight lines that represent electrical connections. That is, in the connection structure 202 on the lower surface of the first substrate 110A or the connection structure 203 on the upper surface of the second substrate 110B, for example, Figure 2A The connection structures corresponding to the electrical connections related to the I / O cells are indicated by dashed lines, and the connection structures corresponding to the electrical connections related to the storage circuits are indicated by dotted lines. In addition, in the connection structures 204 on the lower surface of the second substrate 110B and the connection structures 205 on the upper surface of the third substrate 110C, for example, Figure 2A Those connection structures in FIG. 1 that correspond to electrical connections related to signals not directly related to the operation of the memory circuit are represented by solid lines, while those connection structures that may correspond to electrical connections related to the memory circuit are represented by dotted lines.

[0312] As described above, in the illustrated configuration example, the memory circuit is mounted on the second substrate 110B. In this case, the pixel signal processing circuit is mounted on the first substrate 110A, and the pixel signals acquired by the pixel cells 206 on the first substrate 110A and subjected to A / D conversion by the pixel signal processing circuit can be transmitted to and stored in the memory circuit on the second substrate 110B. To externally read the pixel signals stored in the memory circuit on the second substrate 110B, for example, the signals are then transmitted between the memory circuit on the second substrate 110B and the logic circuit on the third substrate 110C.

[0313] Therefore, in the construction example, as the connection structure 202 on the lower surface of the first substrate 110A, the connection structure 202 is provided along the outer periphery of the chip in association with the area where the I / O unit and the pixel signal processing circuit are installed (the connection structure 202 indicated by the dotted line in the figure) so as to transmit the signal from the I / O unit and the pixel signal processing circuit to the wiring provided in the second substrate 110B, and the connection structure 202 is provided for transmitting the pixel signal that has undergone AD conversion to the storage circuit of the second substrate 110B (the connection structure 202 indicated by the dotted line in the figure). At this time, in order to make the delay time equal, it is desired that the wiring length of the transmission path of the pixel signal from the circuit of the first substrate 110A to the storage circuit of the second substrate 110B and the wiring length of the transmission path of the signal between the storage circuit of the second substrate 110B and the logic circuit of the third substrate 110C are as equal as possible. Therefore, for example, as Figure 2F As shown, the connection structures 202 to 205 for exchanging signals between the circuit of the first substrate 110A and the memory circuit of the second substrate 110B, and between the memory circuit of the second substrate 110B and the circuit of the third substrate 110C, can be arranged to be concentrated near the middle of the horizontal plane. However, as long as the wiring length can be made substantially uniform, the connection structures 202 to 205 do not necessarily need to be arranged near the middle of the horizontal plane as in the example shown.

[0314] Several examples of the configuration of the connection structure in the solid-state imaging device 1 in the horizontal plane have been described above. Note that this embodiment is not limited to the above-mentioned examples. The components mounted on each substrate of the solid-state imaging device 1 can be appropriately determined, and the configuration of the connection structure in the horizontal plane of the solid-state imaging device 1 can also be appropriately determined based on the components. As the components mounted on each substrate and the configuration of the corresponding connection structure in the horizontal plane, various known components and configurations can be applied. In addition, in Figures 2A to 2FIn the example shown, the connection structure 201 included in the I / O cell is arranged along three sides of the outer periphery of the chip, but the present embodiment is not limited to these examples. Various known configurations can also be applied as the configuration of the I / O cell. For example, the connection structure 201 included in the I / O cell can be arranged along one side, two sides, or four sides of the outer periphery of the chip.

[0315] (3. Regarding the direction of the second substrate)

[0316] exist Figure 1 In the illustrated configuration example, in the solid-state imaging device 1, a first substrate 110A and a second substrate 110B are bonded together in a face-to-face manner (i.e., the front side of the second substrate 110B faces the first substrate 110A). Alternatively, the solid-state imaging device 1 may include a first substrate 110A and a second substrate 110B bonded together in a face-to-back manner (i.e., the front side of the second substrate 110B may face the third substrate 110C).

[0317] The direction of the second substrate 110B can be appropriately determined to improve the performance of the entire solid-state imaging device 1 by considering, for example, the configuration and performance of each substrate (each chip). Here, two concepts for determining the direction of the second substrate 110B are described as examples.

[0318] (3-1. Consideration based on PWELL area)

[0319] Similar to Figure 1 The construction example shown, Figure 3A 1 is a vertical cross-sectional view showing a schematic configuration of the solid-state imaging device 1 in which a first substrate 110A and a second substrate 110B are bonded together in a face-to-face manner. Figure 1 The construction example shown, Figure 3B 1 is a vertical cross-sectional view of a schematic configuration of a solid-state imaging device 1a in which a first substrate 110A and a second substrate 110B are bonded together in a face-to-back manner. The configuration of the solid-state imaging device 1a is similar to that of the solid-state imaging device 1a except that the direction of the second substrate 110B is opposite. Figure 1 The configuration of the solid-state imaging device 1 is shown.

[0320] like Figure 3A and 3B As shown, the function of each wiring (signal line, GND wiring or power supply wiring) included in the multi-layer wiring layers 105, 105 and 135 is represented by assigning superimposed different hatching lines to these wirings (that is, the hatching line of each wiring is represented by Figure 3A and Figure 3B The legend shown in the figure shows the wiring function superimposed on the Figure 1 The hatched lines on the hatched lines of the wiring shown (for the later described Figure 4A and4B As shown in the figure, in solid-state imaging devices 1 and 1a, terminals for leading signal wiring, GND wiring, and power wiring to the outside (corresponding to the aforementioned pads 151) are arranged along the outer periphery of the chip. These corresponding terminals are paired in a horizontal plane and arranged at a position sandwiching the pixel unit 206. Therefore, in solid-state imaging devices 1 and 1a, the signal lines, GND wiring, and power wiring extend to connect these terminals to each other and spread out in the horizontal plane.

[0321] exist Figure 3A and Figure 3B In the example, "P" is attached to the PWELL (P-well) provided in the first, second, and third substrates 110A, 110B, and 110C, and "N" is attached to the NWELL (N-well) provided in the first, second, and third substrates 110A, 110B, and 110C. For example, in the illustrated configuration, the photodiode (PD) included in each pixel of the pixel cell is a PD with an N-type diffusion region formed in the PWELL to read out electrons generated by photoelectric conversion. Furthermore, the transistors of the driver circuit included in each pixel to read out the electrons generated in the PD are N-type MOS transistors. Therefore, the well (well) of the pixel cell is a PWELL. In contrast, the logic circuits and memory circuits provided in the second and third substrates 110B, 110C include CMOS circuits, and therefore, a mixture of PMOS and NMOS circuits. This makes the area of ​​the existing PWELL and the area of ​​the existing NWELL, for example, approximately the same. Therefore, in the illustrated configuration example, the first substrate 110A has a larger PWELL area than the second and third substrates 110B, 110C.

[0322] Here, in the solid-state imaging devices 1 and 1a, the GND potential can be applied to PWELL. Any configuration in which PWELL and the power supply wiring face each other with an insulator interposed therebetween causes parasitic capacitance to be formed therebetween.

[0323] Reference Figure 4A and Figure 4B The parasitic capacitance formed between PWELL and the power supply wiring is described. Figure 4A yes Figure 3A 1 is an explanatory diagram of parasitic capacitance between PWELL and the power supply wiring in the solid-state imaging device 1 shown. Figure 4A The parasitic capacitance between PWELL and the power supply wiring is shown in a simulated manner by a double-dashed line. Figure 4AAs shown, in the solid-state imaging device 1, a first substrate 110A and a second substrate 110B are bonded together in a face-to-face manner. Therefore, the power supply wiring PWELL of the pixel unit of the first substrate 110A and the power supply wiring in the multilayer wiring layer 125 of the second substrate 110B face each other with an insulator interposed therebetween. This insulator is included in the insulating films 103 and 123, as shown in the figure. This results in parasitic capacitance being formed between the two in this region.

[0324] at the same time, Figure 4B yes Figure 3B FIG. 1 is an explanatory diagram of parasitic capacitance between PWELL and a power supply line in the solid-state imaging device 1 a shown. Figure 4B The parasitic capacitance between PWELL and the power supply wiring is shown in a simulated manner by a double-dashed line. Figure 4B As shown, in the solid-state imaging device 1a, the second substrate 110B and the third substrate 110C are bonded together in a face-to-face manner. Therefore, the PWELL of the logic circuit or memory circuit on the third substrate 110C and the power supply line in the multilayer wiring layer 125 of the second substrate 110B face each other with an insulator interposed between them. This insulator is included in the insulating films 123 and 133, as shown in the figure. This results in parasitic capacitance being formed between the two in this region.

[0325] It is known that the parasitic capacitance mentioned above increases as the area of ​​PWELL increases. Figure 4A and Figure 4B In the construction example shown, this Figure 4A In the illustrated configuration in which the first substrate 110A and the second substrate 110B are joined together in a face-to-face manner, the Figure 4B The illustrated configuration in which the first substrate 110A and the second substrate 110B are bonded together in a face-to-back manner results in greater parasitic capacitance.

[0326] When the parasitic capacitance associated with the power supply wiring in the second substrate 110B is large, the impedance of the current path between the power supply and GND in the second substrate 110B is reduced. Consequently, the power supply system in the second substrate 110B can be further stabilized. Specifically, for example, even if power consumption fluctuates due to fluctuations in the operation of the circuits on the second substrate 110B, fluctuations in the power supply level caused by fluctuations in power consumption can be suppressed. This further stabilizes operation, even when the circuits associated with the second substrate 110B operate at high speeds, and improves the performance of the entire solid-state imaging device 1.

[0327] Thus, when focusing on the PWELL area, Figures 3A to 4BIn the illustrated configuration example, the solid-state imaging device 1 in which the first substrate 110A and the second substrate 110B are joined together in an FF configuration forms a larger parasitic capacitance with respect to the power supply wiring of the second substrate 110B than the solid-state imaging device 1a in which the first substrate 110A and the second substrate 110B are joined together in an FB configuration. This allows for greater stability during high-speed operation. In other words, it can be said that the solid-state imaging device 1 has a more preferred configuration.

[0328] However, some designs of the substrates may allow the third substrate 110C to have a larger PWELL area than the PWELL area of ​​the first substrate 110A. In this case, it is believed that the configuration of the solid-state imaging device 1a, in which a larger parasitic capacitance is formed between the power supply wiring of the second substrate 110B and the PWELL of the third substrate 110C, can achieve higher stability than the solid-state imaging device 1 during high-speed operation.

[0329] In summary, when considering the orientation of the second substrate 110B based on the PWELL area, if the PWELL area of ​​the first substrate 110A is larger than the PWELL area of ​​the third substrate 110C, it is preferable that the solid-state imaging device 1 is constructed so that the front side of the second substrate 110B faces the first substrate 110A. In other words, it is preferable that the solid-state imaging device 1 is constructed so that the first substrate 110A and the second substrate 110B are joined together in a face-to-face manner. Conversely, if the PWELL area of ​​the third substrate 110C is larger than the PWELL area of ​​the first substrate 110A, it is preferable that the solid-state imaging device 1a is constructed so that the front side of the second substrate 110B faces the third substrate 110C. In other words, it is preferable that the solid-state imaging device 1a is constructed so that the first substrate 110A and the second substrate 110B are joined together in a face-to-back manner.

[0330] In this embodiment, the direction of the second substrate 110B can be determined from the perspective of the PWELL area. For example, Figure 1 and described later Figures 6A to 25K The solid-state imaging devices 1 to 21K according to the present embodiment are each configured such that the PWELL area of ​​the first substrate 110A is larger than the PWELL area of ​​the third substrate 110C, and the first and second substrates 110A and 110B are bonded together in a face-to-face manner. Therefore, the solid-state imaging devices 1 to 21K can achieve high operational stability even during high-speed operation.

[0331] Note that examples of cases where the PWELL area of ​​the first substrate 110A is larger than the PWELL area of ​​the third substrate 110C include a case where a pixel unit including only a PD for reading out electrons generated by photoelectric conversion and an NMOS transistor for reading out electrons from the PD is mounted on the first substrate 110A, while various circuits (such as a pixel signal processing circuit, a logic circuit, and a memory circuit) are mounted on the second substrate 110B and the third substrate 110C. Meanwhile, examples of cases where the PWELL area of ​​the third substrate 110C is larger than the PWELL area of ​​the first substrate 110A include a case where a pixel unit and various circuits are mounted together on the first substrate 110A, and the area of ​​the first substrate 110A occupied by the various circuits is relatively large.

[0332] (3-2. Considerations for power consumption and GND wiring settings)

[0333] The above mainly describes the Figure 3A The solid-state imaging device 1 shown and Figure 3B The PWELL area of ​​the solid-state imaging device 1 a is shown, but now attention is paid to the power consumption and GND wiring arrangement in each substrate.

[0334] Figure 5A yes Figure 3A Schematic diagram of arrangement of power supply wiring and GND wiring in the solid-state imaging device 1 shown. Figure 5B yes Figure 3B FIG. 1 is a schematic diagram showing the arrangement of power supply wiring and GND wiring in the solid-state imaging device 1 a shown in FIG. Figure 5A and Figure 5B The structure of the solid-state imaging devices 1 and 1a is simplified, and the schematic arrangement of the power supply wiring and the GND wiring is shown by illustrating the power supply wiring with a two-dot chain line and the GND wiring with a single-dot chain line. In addition, the size of the arrow in the figure represents the amount of current flowing through the power supply wiring and the GND wiring in a simulated manner.

[0335] like Figure 5A and Figure 5BAs shown, it can be considered that the power wiring mainly includes a vertical power wiring 303 and a horizontal power wiring 304, and the vertical power wiring 303 extends in the z-axis direction from the power terminal (VCC) provided on the upper surface of the first substrate 110A (that is, the upper surface of the solid-state imaging device 1 and 1a), and the horizontal power wiring 304 extends in the horizontal direction in the multi-layer wiring layer 105 of the first substrate 110A, the multi-layer wiring layer 125 of the second substrate 110B, and the multi-layer wiring layer 135 of the third substrate 110C. The vertical power wiring 303 and the horizontal power wiring 304 are also collectively referred to as power wirings 303 and 304 below. Note that the horizontal power wiring 304 can actually also exist in the multi-layer wiring layer 105 of the first substrate 110A and the multi-layer wiring layer 125 of the second substrate 110B, but for simplicity, it is shown in FIG. Figure 5A and Figure 5B Not shown in the figure. Figure 5A and Figure 5B In each diagram, only the horizontal power supply wiring 304 in the multilayer wiring layer 135 of the third substrate 110C is shown.

[0336] Furthermore, it can be considered that the GND wiring mainly includes vertical GND wiring 305 and horizontal GND wiring 306. The vertical GND wiring 305 extends in the z-axis direction from the GND terminal provided on the upper surface of the first substrate 110A, while the horizontal GND wiring 306 extends in the horizontal direction through the multilayer wiring layer 105 of the first substrate 110A, the multilayer wiring layer 125 of the second substrate 110B, and the multilayer wiring layer 135 of the third substrate 110C. Hereinafter, the vertical GND wiring 305 and the horizontal GND wiring 306 are collectively referred to as GND wiring 305 and 306. Note that the horizontal GND wiring 306 of the first substrate 110A is also referred to as horizontal GND wiring 306a, the horizontal GND wiring 306 of the second substrate 110B is also referred to as horizontal GND wiring 306b, and the horizontal GND wiring 306 of the third substrate 110C is also referred to as horizontal GND wiring 306c to distinguish them.

[0337] Here, as an example, a case where the power consumption of the third substrate 110C is greater than the power consumption of the first substrate 110A is considered. For example, it is assumed that the third substrate 110C is a logic substrate. The logic circuit is divided into a plurality of circuit blocks, and the circuit block to be operated can be changed according to the processing content. That is, during a series of operations in the solid-state imaging devices 1 and 1a, the position of the logic circuit that mainly operates can be changed. Therefore, the position of the logic circuit through which the power supply current flows is biased (for example, the power supply current is generated due to the charging and discharging of the transistor gate capacitance and the wiring capacitance associated with the operation of the circuit), and therefore, the position can be changed.

[0338] like Figure 5A and Figure 5BAs shown, attention is now focused on the circuit blocks 301 and 302 in the logic circuit of the third substrate 110C. When these two circuit blocks 301 and 302 operate, a current path is formed through the power supply terminal, power supply wiring 303 and 304, circuit blocks 301 and 302, GND wiring 305 and 306, and GND terminal.

[0339] Here, it is assumed that the power consumption of the circuit block 301 is greater than the power consumption of the circuit block 302 at a certain time. In this case, as Figure 5A and Figure 5B As shown, at this time, the current supplied from power supply wirings 303 and 304 to circuit block 301 is larger than the current supplied to circuit block 302. Due to this difference in power consumption, a larger amount of current flows through circuit blocks 301 and 302 to vertical GND wiring 305 (also referred to as vertical GND wiring 305a to distinguish it from vertical GND wiring 305) near circuit block 301 than to vertical GND wiring 305 (also referred to as vertical GND wiring 305b to distinguish it from vertical GND wiring 305) near circuit block 302.

[0340] The first substrate 110A and the second substrate 110B have horizontal GND wirings 306a and 306b, and therefore, the imbalance in the amount of current between the vertical GND wirings 305a and 305b is corrected by the horizontal GND wirings 306a and 306b of the first substrate 110A and the second substrate 110B on the way to the GND terminal on the upper surface of the first substrate 110A. That is, current flows to the horizontal GND wirings 306a and 306b of the first substrate 110A and the second substrate 110B to correct the imbalance in the amount of current between the vertical GND wirings 305a and 305b. Therefore, as Figure 5A and Figure 5B As shown by solid arrows therein, a circular current path passing through the horizontal power wiring 304, circuit blocks 301 and 302, horizontal GND wiring 306c, vertical GND wiring 305a, and horizontal GND wirings 306a and 306b is formed in each of the solid-state imaging devices 1 and 1a.

[0341] At this time, if Figure 5A As shown, in the solid-state imaging device 1 in which the first substrate 110A and the second substrate 110B are joined together in a face-to-face manner, the horizontal GND wirings 306a and 306b of the first substrate 110A and the second substrate 110B are arranged relatively far from the horizontal power wiring 304 of the third substrate 110C. Therefore, in the aforementioned circular current path, the opening width of the loop increases. This increases the inductance of the circular current path. In other words, the impedance becomes higher. This can reduce the stability of the power supply current, and the performance of the entire solid-state imaging device 1 may be reduced.

[0342] At the same time, if Figure 5B As shown, in a solid-state imaging device 1a in which a first substrate 110A and a second substrate 110B are joined together in a face-to-back manner, the horizontal GND wiring 306a of the first substrate 110A is arranged relatively far from the horizontal power wiring 304 of the third substrate 110C, but the horizontal GND wiring 306b of the second substrate 110B is arranged relatively close to the horizontal power wiring 304 of the third substrate 110C. Therefore, in the aforementioned circular current path, the opening width of the loop is reduced. This reduces the inductance of the circular current path. In other words, the impedance becomes lower. Therefore, the power supply current can be further stabilized, and the performance of the entire solid-state imaging device 1 can be further improved.

[0343] Thus, when focusing on power consumption and GND wiring arrangement, if the power consumption of the third substrate 110C is greater than that of the first substrate 110A, it is believed that the solid-state imaging device 1a, in which the first substrate 110A and the second substrate 110B are joined together in a face-to-back manner, can achieve more stable operation than the solid-state imaging device 1 in which the first substrate 110A and the second substrate 110B are joined together in a face-to-face manner. The solid-state imaging device 1a arranges the horizontal GND wiring 306b of the second substrate 110B closer to the horizontal power supply wiring 304 of the third substrate 110C. In other words, it can be said that the solid-state imaging device 1a has a more preferred configuration.

[0344] However, some designs of the substrates may cause the first substrate 110A to consume more power than the third substrate 110C. In this case, it is considered that more stable operation can be expected by configuring the solid-state imaging device 1 in which the distance between the horizontal power supply wiring 306b of the first substrate 110A and the horizontal GND wiring 306b of the second substrate 110B is reduced, rather than configuring the solid-state imaging device 1a.

[0345] In summary, when considering the orientation of the second substrate 110B based on power consumption and GND wiring arrangement, if the power consumption of the first substrate 110A is greater than that of the third substrate 110C, it is preferable to configure the solid-state imaging device 1 so that the front side of the second substrate 110B faces the first substrate 110A. In other words, it is preferable to configure the solid-state imaging device 1 so that the first substrate 110A and the second substrate 110B are joined together face to face. Conversely, if the power consumption of the third substrate 110C is greater than that of the first substrate 110A, it is preferable to configure the solid-state imaging device 1a so that the front side of the second substrate 110B faces the third substrate 110C. In other words, it is preferable to configure the solid-state imaging device 1 so that the first substrate 110A and the second substrate 110B are joined together face to face.

[0346] In this embodiment, the direction of the second substrate 110B can be determined from the viewpoint of power consumption and GND wiring arrangement. For example, Figure 1 and the following Figures 6A to 25K The solid-state imaging devices 1 to 21K according to the present embodiment are each configured such that the power consumption of the first substrate 110A is greater than that of the third substrate 110C, and the first substrate 110A and the second substrate 110B are bonded together in a face-to-face manner. Therefore, the solid-state imaging devices 1 to 21K can achieve more stable operation.

[0347] Note that examples of situations where the power consumption of the third substrate 110C is greater than that of the first substrate 110A include a case where only the pixel cells are mounted on the first substrate 110A, and many circuits (e.g., such as pixel signal processing circuits, logic circuits, and memory circuits) are mounted on the second substrate 110B and the third substrate 110C. A specific example of this configuration includes a case where only the pixel cells are mounted on the first substrate 110A, the pixel signal processing circuits and memory circuits are mounted on the second substrate 110B, and the logic circuits are mounted on the third substrate 110C. In this case, digital circuits in the pixel signal processing circuits (such as those that generate reference voltages for A / D conversion) can be mounted on the third substrate 110C. Alternatively, if a more frequently accessed memory circuit (e.g., a memory circuit that writes or reads pixel signals multiple times per frame) is mounted on the third substrate 110C, it is also considered that the third substrate 110C consumes more power.

[0348] Meanwhile, examples of cases where the power consumption of the first substrate 110A is greater than the power consumption of the third substrate 110C include a case where pixel cells and various circuits are mounted together on the first substrate 110A, and the area of ​​the first substrate 110A occupied by the various circuits is relatively large. Alternatively, in the case where a memory circuit that is less frequently accessed (e.g., a memory circuit that writes or reads pixel signals only once per frame) is mounted on the third substrate 110C, it is also considered that the third substrate 110C consumes less power while the first substrate 110A consumes relatively more power.

[0349] Note that when comparing the power consumption of the first substrate 110A and the power consumption of the third substrate 110C, the power consumption itself may be compared, or other indicators that can represent the magnitude of the power consumption may be compared. Examples of other indicators include the number of gates mounted on the circuits of each substrate (e.g., 100 gates vs. 1,000,000 gates), the operating frequency of the circuits of each substrate (e.g., 100 MHz vs. 1 GHz), and the like.

[0350] Here, as a Figure 5A The method for reducing the impedance of the circular current path in the solid-state imaging device 1 in which the first substrate 110A and the second substrate 110B are bonded together in a face-to-face manner is as shown. Figure 5C As shown, a method for connecting the horizontal GND wiring 306 a of the first substrate 110A and the horizontal GND wiring 306 b of the second substrate 110B to each other by using a plurality of wirings (ie, vertical GND wirings) extending in the z-axis direction is possible. Figure 5C The diagram shows the Figure 5A The solid-state imaging device 1 shown here is an example of a structure in which the impedance is reduced. Figure 5C The solid-state imaging device 1b shown corresponds to Figure 5A The solid-state imaging device 1 shown, in the solid-state imaging device 1b: the horizontal GND wiring 306a of the first substrate 110A and the horizontal GND wiring 306b of the second substrate 110B are connected to each other by using a plurality of vertical GND wirings, and the other components are similar to those of the solid-state imaging device 1.

[0351] use Figure 5C The structure shown strengthens the horizontal GND wiring 306a and 306b and reduces the impedance of the loop current path. Therefore, it can be considered that the overall performance of the solid-state imaging device 1b is further improved. Note that, as an example, Figure 5C The diagram illustrates a configuration that can reduce the impedance of the looping current path when the power consumption of the third substrate 110C is greater than that of the first substrate 110A and the first and second substrates 110A, 110B are joined face-to-face. Furthermore, when the power consumption of the first substrate 110A is greater than that of the third substrate 110C and the first and second substrates 110A, 110B are joined face-to-back, it is sufficient to reduce the impedance of the looping current path by connecting the horizontal GND wiring 306b of the second substrate 110B and the horizontal GND wiring 306c of the third substrate 110C to each other using a plurality of vertical GND wirings.

[0352] However, in order to achieve Figure 5C In the configuration shown, the multilayer wiring layer 105 of the first substrate 110A and the multilayer wiring layer 125 of the second substrate 110B need to be provided with a connection structure for connecting their GND wirings to each other. This imposes a constraint on the arrangement of the GND wirings and other wirings in the multilayer wiring layers 105 and 125, such that the connection structure to be provided must be considered. Specifically, Figure 5CIn the illustrated configuration, the vertical GND wiring and the connection structure connecting the vertical GND wiring between the substrates on first substrate 110A and second substrate 110B are distributed horizontally not only on the chip's periphery but also, more so, in the chip's center. Therefore, the wiring layout must take this distribution into account. This reduces the design flexibility of the wiring within multilayer wiring layers 105 and 125.

[0353] In contrast, as described above, in this embodiment, the impedance of the loop current path is reduced by adjusting the orientation of the second substrate 110B. Figure 5C Unlike the configuration shown, vertical GND wiring is arranged so that more vertical GND wiring is distributed horizontally around the periphery of the chip. This reduces the impedance of the current path without reducing the design flexibility of the wiring in the multilayer wiring layers 105 and 125. This stabilizes the operation of the solid-state imaging devices 1 and 1a.

[0354] Note that, for example, the density of vertical GND wirings provided in the peripheral portion of the chip and the middle portion of the chip in the horizontal plane can be determined as follows. For example, in a case where the number of vertical GND wirings present in one middle region among nine regions obtained by equally dividing the chip into 3×3 regions in the horizontal plane is greater than the number of vertical GND wirings present in the eight peripheral regions, it can be determined that the number of vertical GND wirings in the middle portion of the chip is large (that is, it can be determined that it is possible to apply Figure 5C In contrast, when the number of vertical GND wirings in one middle region is smaller than the number of vertical GND wirings in eight peripheral regions, it can be determined that the number of vertical GND wirings in the peripheral portion of the chip is large (i.e., it can be determined that it is possible to apply Figure 5A and Figure 5B 1 and 1a shown in FIG).

[0355] Here, as an example, the case of dividing the chip equally into nine areas in the horizontal plane has been described, but the number of areas obtained by dividing the chip is not limited to this example. The number of areas obtained by dividing the chip can be appropriately changed to 16 areas of 4×4 areas, 25 areas of 5×5 areas, or the like. For example, when the chip is divided into 16 areas of 4×4 areas, it is sufficient to determine the density from the number of vertical GND wirings in 4 middle areas and 12 peripheral areas. Alternatively, when the chip is divided into 25 areas of 5×5 areas, it is sufficient to determine the density from the number of vertical GND wirings in 1 middle area and 24 peripheral areas, or 9 middle areas and 16 peripheral areas.

[0356] (4. Modification of Configuration of Solid-State Imaging Device)

[0357] Figure 1 The configuration of the solid-state imaging device 1 shown is an example of a solid-state imaging device according to the present embodiment. The solid-state imaging device according to the present embodiment may include Figure 1 The following describes another example of the configuration of the solid-state imaging device according to the present embodiment, which includes a different connection structure. Note that the components of each solid-state imaging device described below correspond to Figure 1 The components of the solid-state imaging device 1 shown in FIG. 1 are shown in FIG. 1 , but the components of each solid-state imaging device described below are Figure 1 A part of the components of the solid-state imaging device 1 shown is changed. Therefore, the details of the components already described with reference to FIG. Figure 1 In addition, the corresponding drawings illustrating the schematic configuration of each solid-state imaging device described below omit the components attached to the Figure 1 In order to avoid complicating the drawings, some of the reference numerals are used. Figure 1 And the respective figures that follow indicate that components having the same type of hatching are formed of the same material.

[0358] In any configuration of the solid-state imaging device according to the present embodiment, at least Figure 1 As in the solid-state imaging device 1 shown in FIG. 1 , a double-contact type TSV 157 is provided. Here, the double-contact refers to a via having a structure in which a conductive material is buried in a first through-hole exposing a predetermined wiring and a second through-hole different from the first through-hole exposing another wiring different from the predetermined wiring, or in which a film including a conductive material is formed on the inner walls of the first and second through-holes.

[0359] Meanwhile, in the solid-state imaging device, all corresponding signal lines and all corresponding power supply lines provided in the first substrate 110A, the second substrate 110B, and the third substrate 110C need to be electrically connected together. Therefore, in addition to the TSVs 157, the solid-state imaging device may further include another connection structure for electrically connecting the signal lines to each other and the power supply lines to each other between the substrates provided with corresponding signal lines and corresponding power supply lines that are not electrically connected to each other via the TSVs 157.

[0360] In this embodiment, solid-state imaging devices are classified into 20 categories according to the specific configurations of these connection structures.

[0361] First construction example ( Figures 6A to 6E) is a configuration example in which a dual-contact type TSV 157 between two layers is provided as a connection structure for electrically connecting respective signal lines provided in the first substrate 110A and the second substrate 110B to each other and electrically connecting respective power supply lines provided in the first substrate 110A and the second substrate 110B to each other, but in which, in addition to the TSV 157, there are no dual-contact type TSV 157 or a shared contact type TSV 157 described later and an electrode bonding structure 159 described later. As used herein, the TSV between two layers refers to a TSV provided to electrically connect respective signal lines and respective power supply lines provided in two adjacent substrates among the first substrate 110A, the second substrate 110B, and the third substrate 110C to each other.

[0362] As described above, in addition to the TSVs 157 that electrically connect the respective signal lines provided in the first substrate 110A and the second substrate 110B to each other and the respective power lines provided in the first substrate 110A and the second substrate 110B to each other, no other TSVs 157 and electrode bonding structures 159 are provided. Therefore, in the solid-state imaging device according to the first construction example, electrical connections between the respective signal lines provided in the first substrate 110A and the third substrate 110C and between the respective power lines provided in the first substrate 110A and the third substrate 110C and / or electrical connections between the respective signal lines provided in the second substrate 110B and the third substrate 110C and between the respective power lines provided in the second substrate 110B and the third substrate 110C are realized through the I / O units. That is, in the solid-state imaging device according to the first configuration example, together with the TSVs 157 that electrically connect the respective signal lines provided in the first substrate 110A and the second substrate 110B to each other and the respective power supply lines provided in the first substrate 110A and the second substrate 110B to each other, the pads 151 that electrically connect the respective signal lines provided in the first substrate 110A and the third substrate 110C to each other and the respective power supply lines provided in the first substrate 110A and the third substrate 110C to each other, and / or the pads 151 that electrically connect the respective signal lines provided in the second substrate 110B and the third substrate 110C to each other and the respective power supply lines provided in the second substrate 110B and the third substrate 110C to each other may be provided as other connection structures. Note that, Figure 1 The solid-state imaging device 1 shown in is also included in the first configuration example.

[0363] Second Configuration Example ( Figures 7A to 7K) is a configuration example in which, together with the dual-contact type TSV 157 between two layers that electrically connects the respective signal lines provided in the first substrate 110A and the second substrate 110B to each other and electrically connects the respective power lines provided in the first substrate 110A and the second substrate 110B to each other, the dual-contact type TSV 157 between at least two layers is further provided as a connection structure for electrically connecting the respective signal lines provided in the second substrate 110B and the third substrate 110C to each other and electrically connecting the respective power lines provided in the second substrate 110B and the third substrate 110C to each other.

[0364] The third construction example ( Figures 8A to 8G ) is a configuration example in which, together with the dual-contact type TSV 157 between the two layers that electrically connects the respective signal lines provided in the first substrate 110A and the second substrate 110B to each other and the respective power lines provided in the first substrate 110A and the second substrate 110B to each other, at least the dual-contact type TSV 157 between the three layers described later is provided as a connection structure. As used herein, the TSV between the three layers means that the TSV 157 extends through all of the first substrate 110A, the second substrate 110B, and the third substrate 110C. The dual-contact TSV 157 between three layers formed from the back side of the first substrate 110A toward the third substrate 110C can electrically connect the various signal lines set in the first substrate 110A and the third substrate 110C to each other and electrically connect the various power lines set in the first substrate 110A and the third substrate 110C to each other through its structure, or electrically connect the various signal lines set in the second substrate 110B and the third substrate 110C to each other and electrically connect the various power lines set in the second substrate 110B and the third substrate 110C to each other. In addition, the dual-contact TSV 157 between the three layers formed from the back side of the third substrate 110C toward the first substrate 110A can electrically connect the respective signal lines provided in the first substrate 110A and the second substrate 110B to each other and electrically connect the respective power lines provided in the first substrate 110A and the second substrate 110B to each other, or electrically connect the respective signal lines provided in the first substrate 110A and the third substrate 110C to each other and electrically connect the respective power lines provided in the first substrate 110A and the third substrate 110C to each other through its structure.

[0365] Fourth Configuration Example ( Figures 9A to 9K) is a configuration example in which, along with dual-contact TSVs 157 between the two layers for electrically connecting the respective signal lines provided in the first substrate 110A and the second substrate 110B and the respective power supply lines provided in the first substrate 110A and the second substrate 110B, at least a shared contact TSV 157 between the two layers, described later, is provided as a connection structure for electrically connecting the respective signal lines provided in the second substrate 110B and the third substrate 110C and the respective power supply lines provided in the second substrate 110B and the third substrate 110C. Here, the shared contact refers to a via having a structure in which a conductive material is embedded in a through-hole provided so as to expose a portion of a predetermined wiring in one substrate while simultaneously exposing a predetermined wiring in the other substrate; or in which a film including a conductive material is formed on the inner wall of the through-hole.

[0366] For example, when forming a common contact-type TSV 157 from the back side of the first substrate 110A for electrically connecting the respective signal lines provided in the first substrate 110A and the second substrate 110B to each other and electrically connecting the corresponding power lines provided in the first substrate 110A and the second substrate 110B to each other, a through-hole having a diameter larger than the space between two wirings of the same potential is first formed by dry etching from the back side of the first substrate 110A, from directly above the two wirings of the same potential, with respect to the two wirings of the same potential arranged at a predetermined interval in the multilayer wiring layer 105 of the first substrate 110A, and with respect to the wiring directly below the space between the two wirings of the same potential in the multilayer wiring layer 105 within the first substrate 110A within the multilayer wiring layer 125 of the second substrate 110B. At this time, the through-hole having a large diameter is formed so as not to expose the two wirings of the same potential. Next, through photolithography and dry etching, a through-hole having a smaller diameter than the space between the two wirings at the same potential is formed to expose the wiring in the multilayer wiring layer 125 of the second substrate 110B located directly below the space between the two wirings at the same potential. Next, a through-hole having a larger diameter is grown by etching back, thereby exposing a portion of the two wirings at the same potential in the multilayer wiring layer 105 of the first substrate 110A. As a result of the above process, the through-hole has a shape that exposes a portion of the two wirings at the same potential in the multilayer wiring layer 105 of the first substrate 110A and exposes the wiring directly below the space between the two wirings in the multilayer wiring layer 125 of the second substrate 110B. The shared contact TSV 157 can be formed by embedding a conductive material in the through-hole or by forming a film of conductive material on the inner wall of the through-hole. According to this method, when forming a through hole with a large diameter and a through hole with a small diameter, dry etching is not performed on two wirings with the same potential, thereby suppressing the corners of the two wirings with the same potential from being scraped and contaminated. Therefore, a solid-state imaging device 1 with higher reliability can be realized.

[0367] Note that in the above example, the case where the shared contact-type TSVs 157 for electrically connecting the various signal lines and power lines provided in the first and second substrates 110A and 110B have been formed from the back side of the first substrate 110A has been described. However, the same applies to the case where the shared contact-type TSVs 157 for electrically connecting the various signal lines and power lines provided in the second and third substrates 110B and 110C have been formed from the front side of the second substrate 110B or from the back side of the third substrate 110C. Furthermore, the same applies to the case where the shared contact-type TSVs 157 between the three layers described later are formed from the back side of the first substrate 110A or from the back side of the third substrate 110C. Furthermore, in the above example, the through-holes are provided so as to pass through the space between two wirings arranged side by side at a predetermined interval. However, for example, the wirings may be formed in a ring shape with an opening, and the through-holes may be provided so as to pass through the wiring openings.

[0368] Alternatively, the shared contact type TSV 157 may be formed by a method different from the above-described method. For example, in the same manner as described above, in the case of forming the shared contact type TSV 157 for electrically connecting the various signal lines and the various power lines provided in the first substrate 110A and the second substrate 110B from the back side of the first substrate 110A, when a through hole having a diameter larger than the space between the two wirings of the same potential in the multilayer wiring layer 105 of the first substrate 110A is formed from directly above the two wirings of the same potential by dry etching, the dry etching can be continued while a portion of the two wirings of the same potential is exposed, rather than stopping the dry etching in the middle so as not to expose the two wirings of the same potential. In this case, due to the etching selectivity of the conductive material (e.g., Cu) included in the two wirings and the insulating material (e.g., SiO2) included in the insulating film 103, etching of the two wirings of the same potential is almost difficult to proceed, while etching of the insulating film 103 can proceed in the space between the two wirings of the same potential. Thus, the through-hole has a shape that exposes a portion of two wirings in the multilayer wiring layer 105 of the first substrate 110A and exposes the wiring located directly below the space between the two wirings in the multilayer wiring layer 125 of the second substrate 110B. The shared contact type TSV 157 can be formed by embedding a conductive material in the through-hole formed in this manner or by forming a film of a conductive material on the inner wall of the through-hole.

[0369] The shared contact type TSV 157 is not necessarily provided as an opening that passes through the space between two wirings of the same potential or the ring wiring. For example, when forming a through hole, the wiring located in the upper layer (in the above example, the wiring in the multilayer wiring layer 105 of the first substrate 110A) can be a single wiring. Specifically, for example, in the same manner as described above, in the case of forming a shared contact type TSV 157 for electrically connecting the various signal lines provided in the first substrate 110A and the second substrate 110B to each other and electrically connecting the various power lines provided in the first substrate 110A and the second substrate 110B to each other from the back side of the first substrate 110A, the through hole can be formed to expose a portion of the single wiring in the multilayer wiring layer 105 of the first substrate 110A and expose the wiring in the multilayer wiring layer 125 of the second substrate 110B. The shared contact type TSV 157 can be formed by embedding a conductive material in the through hole or by forming a film of conductive material on the inner wall of the through hole. However, compared to the case where the number of the above-mentioned wirings in the upper layer is two or the case where the above-mentioned wirings in the upper layer have a ring shape with an opening, in this embodiment, the single wiring in the upper layer causes the through-hole to be formed so that the wiring in the upper layer is not exposed due to, for example, misalignment, etc., resulting in the possibility of contact failure. Therefore, it is preferable that the single wiring pattern be applied to a case where a sufficient margin is provided for the overlap between the through-hole and the single wiring in a manner that can ensure contact characteristics between the TSV 157 and the single wiring.

[0370] Fifth construction example ( Figures 10A to 10G ) is a configuration example in which, together with the dual-contact-type TSVs 157 between two layers for electrically connecting the respective signal lines provided in the first substrate 110A and the second substrate 110B to each other and the respective power supply lines provided in the first substrate 110A and the second substrate 110B to each other, a shared contact-type TSV 157 between at least three layers, which will be described later, is provided as a connection structure. The shared contact-type TSV 157 between the three layers can, by its structure, electrically connect the respective signal lines provided in at least two of the first substrate 110A, the second substrate 110B, or the third substrate 110C to each other and electrically connect the respective power supply lines provided in at least two of the first substrate 110A, the second substrate 110B, or the third substrate 110C to each other.

[0371] Note that in the descriptions of the second to fifth configuration examples, as well as the seventh to tenth configuration examples, the twelfth to fifteenth configuration examples, and the seventeenth to twentieth configuration examples described later, there may be a case where a plurality of dual-contact type or shared-contact type TSVs 157 are present in the drawings. In this case, for convenience, the TSVs 157 are distinguished from each other by assigning different letters to the ends of the corresponding reference numerals, such as TSV 157a, TSV 157b, ..., etc.

[0372] Sixth Construction Example ( Figures 11A to 11F ) is a configuration example in which, together with a dual-contact type TSV 157 between two layers for electrically connecting respective signal lines provided in the first substrate 110A and the second substrate 110B to each other and respective power supply lines provided in the first substrate 110A and the second substrate 110B to each other, at least an electrode bonding structure 159, described later, is provided between the second substrate 110B and the third substrate 110C as a connection structure for electrically connecting respective signal lines provided in the second substrate 110B and the third substrate 110C to each other and respective power supply lines provided in the second substrate 110B and the third substrate 110C to each other. As used herein, the electrode bonding structure 159 means a structure in which electrodes formed on respective bonding surfaces of two substrates are bonded to each other in a state in which they are in direct contact with each other.

[0373] Seventh construction example ( Figures 12A to 12L ) is a construction example in which, together with a dual-contact type TSV 157 between two layers for electrically connecting the respective signal lines provided in the first substrate 110A and the second substrate 110B to each other and for electrically connecting the respective power lines provided in the first substrate 110A and the second substrate 110B to each other, at least an electrode bonding structure 159 described later between the second substrate 110B and the third substrate 110C is provided as a connection structure and a dual-contact type TSV 157 between two layers for electrically connecting the respective signal lines provided in the second substrate 110B and the third substrate 110C to each other and for electrically connecting the respective power lines provided in the second substrate 110B and the second substrate 110B to each other is further provided.

[0374] Eighth Construction Example ( Figures 13A to 13H ) is a construction example in which, together with a dual-contact type TSV 157 between two layers for electrically connecting respective signal lines provided in the first substrate 110A and the second substrate 110B to each other and electrically connecting respective power lines provided in the first substrate 110A and the second substrate 110B to each other, at least an electrode bonding structure 159 between the second substrate 110B and the third substrate 110C described later and a dual-contact type TSV 157 between three layers described later are provided as a connection structure.

[0375] Ninth Construction Example ( Figures 14A to 14K ) is a construction example in which, together with a dual-contact TSV 157 between two layers for electrically connecting respective signal lines provided in the first substrate 110A and the second substrate 110B to each other and for electrically connecting respective power lines provided in the first substrate 110A and the second substrate 110B to each other, at least an electrode bonding structure 159 between a second substrate 110B and a third substrate 110C to be described later and a common contact TSV 157 between two layers to be described later for electrically connecting respective signal lines provided in the second substrate 110B and the third substrate 110C to each other are provided as a connection structure.

[0376] Tenth construction example ( Figures 15A to 15G ) is a construction example in which, together with a dual-contact TSV 157 between two layers for electrically connecting respective signal lines provided in the first substrate 110A and the second substrate 110B to each other and electrically connecting respective power lines provided in the first substrate 110A and the second substrate 110B to each other, at least an electrode bonding structure 159 between the second substrate 110B and the third substrate 110C described later and a common contact TSV 157 between three layers described later are provided as a connection structure.

[0377] Eleventh Construction Example ( Figures 16A to 16G ) is a configuration example in which dual-contact TSVs 157 between three layers are provided as a connection structure, but neither dual-contact or common-contact TSVs 157 nor electrode bonding structures 159 described later are provided in addition to the TSVs 157. In the solid-state imaging device according to the eleventh configuration, the respective signal lines and the respective power supply lines are electrically connected to each other through I / O cells in the substrate provided with the respective signal lines and the respective power supply lines that are not electrically connected to each other through the TSVs 157. That is, in the solid-state imaging device according to the eleventh configuration, for each substrate including the signal lines and the power supply lines that are not electrically connected to each other through the TSVs 157, a pad 151 is provided as another connection structure together with the TSVs 157.

[0378] Twelfth Construction Example ( Figures 17A to 17J ) is a construction example in which, together with the dual-contact TSV 157 between three layers, the dual-contact TSV 157 between at least two layers is provided as a connection structure for electrically connecting the respective signal lines provided in the second substrate 110B and the third substrate 110C to each other and electrically connecting the respective power lines provided in the second substrate 110B and the third substrate 110C to each other.

[0379] Thirteenth Construction Example ( Figures 18A to 18G ) is a configuration example in which at least the dual-contact type TSV 157 between three layers is provided as a connection structure together with the dual-contact type TSV 157 between three layers.

[0380] Fourteenth Construction Example ( Figures 19A to 19K ) is a construction example in which, together with the dual contact type TSV 157 between the three layers, as a connection structure for electrically connecting the respective signal lines provided in the second substrate 110B and the third substrate 110C to each other and electrically connecting the respective power supply lines provided in the second substrate 110B and the third substrate 110C to each other, at least a common contact type TSV 157 between two layers described later is provided.

[0381] Fifteenth Construction Example ( Figures 20A to 20G ) is a configuration example in which at least a shared contact type TSV 157 between three layers described later is provided as a connection structure together with a dual contact type TSV 157 between three layers.

[0382] Sixteenth Construction Example ( Figures 21A to 21M ) is a construction example in which, together with a dual-contact TSV 157 between three layers, as a connection structure for electrically connecting the respective signal lines provided in the second substrate 110B and the third substrate 110C to each other and electrically connecting the respective power lines provided in the second substrate 110B and the third substrate 110C to each other, an electrode bonding structure 159 to be described later is provided at least between the second substrate 110B and the third substrate 110C.

[0383] Seventeenth Construction Example ( Figures 22A to 22M ) is a construction example in which, together with a dual-contact TSV 157 between three layers, at least an electrode bonding structure 159 between a second substrate 110B and a third substrate 110C described later and a dual-contact TSV 157 between two layers for electrically connecting the respective signal lines provided in the second substrate 110B and the third substrate 110C to each other and electrically connecting the respective power lines provided in the second substrate 110B and the third substrate 110C to each other are provided as a connection structure.

[0384] Eighteenth Construction Example ( Figures 23A to 23K ) is a configuration example in which at least an electrode bonding structure 159 between a second substrate 110B and a third substrate 110C described later and the dual contact type TSV 157 between three layers are provided as a connection structure together with the dual contact type TSV 157 between three layers.

[0385] Nineteenth Construction Example ( Figures 24A to 24M) is a construction example in which, together with a dual contact type TSV 157 between three layers, at least an electrode bonding structure 159 between a second substrate 110B and a third substrate 110C described later and a common contact type TSV 157 between two layers for electrically connecting the respective signal lines provided in the second substrate 110B and the third substrate 110C to each other and for electrically connecting the respective power lines provided in the second substrate 110B and the third substrate 110C are provided as a connection structure.

[0386] Twentieth construction example ( Figures 25A to 25K ) is a configuration example in which, together with the dual contact type TSV 157 between the three layers, at least an electrode bonding structure 159 between the second substrate 110B and the third substrate 110C described later and a shared contact type TSV 157 between the three layers described later are provided as a connection structure.

[0387] Below, the first through twentieth configuration examples are described in order. Note that the following figures illustrate examples of connection structures included in at least the solid-state imaging device according to this embodiment. The configurations shown in the following figures do not necessarily mean that the solid-state imaging device according to this embodiment includes only the illustrated connection structures; rather, the solid-state imaging device may have connection structures other than the illustrated ones, as appropriate. In the following description of the figures, the first metal wiring layer is, for example, a Cu wiring layer, and the second metal wiring layer is, for example, an Al wiring layer.

[0388] (4-1. First Configuration Example)

[0389] Figures 6A to 6E are vertical cross-sectional views of schematic configurations of a solid-state imaging device according to a first configuration example of the present embodiment. The solid-state imaging device according to the present embodiment may have Figures 6A to 6E Each of the constructs shown in .

[0390] Figure 6A The solid-state imaging device 2a shown in includes: a double-contact type TSV 157 between two layers as a connection structure, a pad 151 provided in the multilayer wiring layer 105 of the first substrate 110A, a pad opening 153a exposing the pad 151, a pad 151 provided in the multilayer wiring layer 135 of the third substrate 110C, and a pad opening 153b exposing the pad 151. The TSV 157 is formed from the back side of the second substrate 110B toward the first substrate 110A, and is provided to electrically connect the respective signal lines provided in the first substrate 110A and the second substrate 110B to each other and to electrically connect the respective power supply lines provided in the first substrate 110A and the second substrate 110B to each other. Figure 6AIn the configuration shown in , predetermined wirings of the second metal wiring layer in the multi-layer wiring layer 105 of the first substrate 110A and predetermined wirings of the first metal wiring layer in the multi-layer wiring layer 125 of the second substrate 110B are electrically connected to each other through TSVs 157. Respective signal lines provided in the first substrate 110A and the third substrate 110C and respective power supply lines provided in the first substrate 110A and the third substrate 110C can be electrically connected to each other through pads 151 and pad openings 153a and 153b.

[0391] Figure 6B The solid-state imaging device 2b shown in the includes: a double-contact type TSV 157 between two layers as a connection structure, a lead opening 155a for leading out a predetermined wiring in the multilayer wiring layer 125 of the second substrate 110B, a lead opening 155b for leading out a predetermined wiring in the multilayer wiring layer 135 of the third substrate 110C, and a pad 151 provided on the surface of the back side of the first substrate 110A and electrically connected to the predetermined wiring through the conductive material included in the lead openings 155a and 155b. The TSV 157 is formed from the back side of the first substrate 110A toward the second substrate 110B and is provided to electrically connect the respective signal lines provided in the first substrate 110A and the second substrate 110B to each other and to electrically connect the respective power lines provided in the first substrate 110A and the second substrate 110B to each other. Figure 6B In the configuration shown in , predetermined wirings of the first metal wiring layer in the multilayer wiring layer 105 of the first substrate 110A and predetermined wirings of the first metal wiring layer in the multilayer wiring layer 125 of the second substrate 110B are electrically connected to each other through TSVs 157 .

[0392] Here, the lead openings 155a and 155b are openings for leading predetermined wiring in the substrates 110A, 110B and 110C (in the example shown, predetermined wiring in the second substrate 110B and the third substrate 110C) to the outside. Each of the lead openings 155a and 155b has a structure in which a conductive material (e.g., W) is formed on the inner wall of the opening so as to be formed to expose the wiring to be guided. As shown in the figure, a film including a conductive material extends from the inside of the lead openings 155a and 155b to the surface on the back side of the first substrate 110A. The pad 151 is formed on the extended film including the conductive material and is electrically connected to the wiring in the substrate led out by the lead openings 155a and 155b through the film including the conductive material. Figure 6BIn the configuration shown in , the lead opening 155a is configured to lead out predetermined wiring of the first metal wiring layer in the multilayer wiring layer 125 of the second substrate 110B, and the lead opening 155b is configured to lead out predetermined wiring of the first metal wiring layer in the multilayer wiring layer 135 of the third substrate 110C. Note that the conductive material formed on the inner wall of the opening in each of the lead openings 155a and 155b is not limited to W; various known conductive materials can be used as the conductive material.

[0393] In this manual, if Figure 6B As shown, the structure in which the pads 151 provided on the back side of the first substrate 110A are electrically connected to the wirings led out from the lead openings 155a and 155b is also referred to as a lead pad structure. Figure 6A As shown, the structure corresponding to the lead-out pad structure providing pad openings 153a and 153b for the pad 151 formed in the substrate is also referred to as a buried pad structure ( Figure 1 The structure shown in is also a buried pad structure.) The lead-out pad structure can be said to be a structure in which the pad 151 formed in the substrate in the buried pad structure is led out to the outside of the substrate (on the surface on the back side of the first substrate 110A).

[0394] In addition, Figure 6B In the illustrated configuration, the wirings drawn from the two lead openings 155a and 155b are electrically connected to the same pad 151 via a film comprising a conductive material. That is, one pad 151 is shared by the two lead openings 155a and 155b. However, the present embodiment is not limited to such an example. Figure 6B As shown in , in the case where there are a plurality of lead openings 155a and 155b, a pad 151 may be provided for each of the lead openings 155a and 155b. In this case, a film including a conductive material contained in the lead opening 155a and a film including a conductive material contained in the lead opening 155b extend to the surface on the back side of the first substrate 110A and are isolated from each other (i.e., both are non-conductive), and a pad 151 may be provided on each film.

[0395] In this manual, Figure 6B In the case where there are a plurality of lead openings 155 in the illustrated figures, for convenience, the lead openings 155 are distinguished from each other by assigning different letters to the ends of corresponding reference numerals, such as lead opening 155a, lead opening 155b, . . . , and so on.

[0396] Figure 6C The solid-state imaging device 2c shown in FIG. 6 corresponds to the solid-state imaging device 2b shown in FIG. 6 , in which the configuration of the lead-out pad structure is changed. Specifically, Figure 6CIn the illustrated structure, the lead pad structure has a structure in which the film made of a conductive material contained in the lead openings 155a and 155b and the pad 151 formed on the film are buried in the insulating film 109 at a portion where the pad 151 is provided.

[0397] Note that in this manual, Figure 6C The lead pad structure in which the pad 151 on the back surface of the first substrate 110A is buried in the insulating film 109 is also referred to as a buried lead pad structure. Figure 6B The lead pad structure in which the pads 151 on the back surface of the first substrate 110A are not buried in the insulating film 109 is also referred to as a non-buried lead pad structure.

[0398] exist Figure 6C In the construction shown in , similar to Figure 6B In the configuration shown in , one pad 151 is shared by two lead openings 155a and 155b. However, the present embodiment is not limited to such an example. Figure 6B , a plurality of pads 151 may be provided to correspond to the two lead openings 155 a and 155 b in the buried type lead pad structure.

[0399] Figure 6D The solid-state imaging device 2d shown in the figure includes: a dual-contact type TSV 157 between two layers as a connection structure, a lead pad structure for the third substrate 110C (i.e., a lead opening 155c for a predetermined wiring in the multi-layer wiring layer 135 of the third substrate 110C and a pad 151 on the surface of the back side of the first substrate 110A). The TSV 157 is formed from the back side of the first substrate 110A toward the second substrate 110B, and is configured to electrically connect the various signal lines provided in the first substrate 110A and the second substrate 110B to each other and to electrically connect the various power lines provided in the first substrate 110A and the second substrate 110B to each other. Figure 6D In the configuration shown in , predetermined wirings of the first metal wiring layer in the multilayer wiring layer 105 of the first substrate 110A and predetermined wirings 110B of the first metal wiring layer in the multilayer wiring layer 125 of the second substrate are electrically connected to each other through TSVs 157 .

[0400] Here, with Figures 6A to 6C The construction shown in Figure 6D The TSV 157 shown in FIG is constructed by forming a film of a conductive material on the inner wall of the through hole rather than by embedding the first metal into the through hole. In the example shown, the conductive material is formed of the same material (e.g., W) as the conductive material included in the lead opening 155. As described above, in this embodiment, a conductive material such as Figures 6A to 6C The TSV 157 shown has a structure in which a conductive material is buried in the through hole, or a structure such as Figure 6D The TSV 157 shown has a structure in which a film of a conductive material is formed on the inner wall of the through hole. Note that in TSV 157, the film of conductive material formed on the inner wall of the through hole is not limited to W; various known conductive materials can be used as the conductive material. The conductive material included in TSV 157 can be a material different from the conductive material included in lead opening 155.

[0401] Note that in this manual, Figures 6A to 6C As shown in FIG, the TSV 157 having a structure in which a conductive material is buried in a through hole is also referred to as a buried TSV 157. Figure 6D As shown in FIG. 1 , the TSV 157 having a structure in which a film including a conductive material is formed on the inner wall of the through hole is also referred to as a non-buried TSV 157 .

[0402] Here, in Figure 6D In the structure shown in FIG, the film made of a conductive material formed on the inner wall of the through hole in TSV 157 and the film made of a conductive material formed on the inner wall of the opening in the lead opening 155c are formed integrally, and the film made of a conductive material extends to the surface on the back side of the first substrate 110A. The pad 151 is formed on the film made of a conductive material extending to the surface on the back side of the first substrate 110A. That is, in Figure 6D In the configuration shown in , TSV 157 and pad 151 are electrically connected to each other; furthermore, predetermined wiring in the multilayer wiring layer 105 of the first substrate 110A and predetermined wiring in the multilayer wiring layer 125 of the second substrate 110B, which are electrically connected to each other through TSV 157 , are also electrically connected to pad 151 .

[0403] As described, in Figure 6D In the configuration shown in , the dual-contact TSV 157 and the non-buried TSV 157 respectively function as TSVs for electrically connecting the respective signal lines provided in the first substrate 110A and the second substrate 110B to each other and for electrically connecting the respective power lines provided in the first substrate 110A and the second substrate 110B to each other, and each has the function of two lead openings 155a and 155b corresponding to the two through holes (i.e., the lead opening 155a for leading out predetermined wiring in the multilayer wiring layer 105 of the first substrate 110A to the pad 151 on the surface on the back side of the first substrate 110A, and the lead opening 155b for leading out predetermined wiring in the multilayer wiring layer 125 of the second substrate 110B to the pad 151 on the surface on the back side of the first substrate 110A).

[0404] In the following, as in Figure 6D As in the TSV 157 shown in FIG, a structure combining the function of the TSV 157 and the function of the lead openings 155a and 155b is also described as a TSV dual-purpose lead opening. Figure 6D The configuration shown in FIG can be said to be a structure having TSV dual-purpose lead openings 155a and 155b (i.e., TSV 157) and lead opening 155c as a connection structure. Note that in the following figures, to avoid complicating the figures, the TSV dual-purpose lead openings are omitted from the description of the symbol "157" representing the TSV, and only the symbol "155" representing the lead opening is assigned to the TSV dual-purpose lead opening.

[0405] Figure 6E The solid-state imaging device 2e shown in FIG. Figure 6D A solid-state imaging device 2d is shown in FIG. 2 , in which a buried type lead pad structure is provided instead of a non-buried type lead pad structure.

[0406] The type of wiring connected by the double-contact type TSV 157 between two layers is not limited to Figures 6A to 6E . TSV 157 may be connected to a predetermined wiring of the first metal wiring layer or may be connected to a predetermined wiring of the second metal wiring layer. In addition, each of the multilayer wiring layers 105, 125, and 135 may include only the first metal wiring layer, may include only the second metal wiring layer, or may include both the first metal wiring layer and the second metal wiring layer so as to coexist.

[0407] exist Figure 6A In the configuration shown in , in the example shown, the pad 151 is provided in each of the first substrate 110A and the third substrate 110C, but the present embodiment is not limited to such an example. In the first configuration example, the respective signal lines provided in the first substrate 110A and the second substrate 110B are electrically connected to each other through the TSV 157, and the respective power lines provided in the first substrate 110A and the second substrate 110B are electrically connected to each other through the TSV 157. Therefore, the second substrate 110B and the third substrate 110C, which are respectively provided with respective signal lines and respective power lines that are not electrically connected to each other through the TSV 157, or the first substrate 110A and the third substrate 110C, are respectively provided with pads 151 for electrically connecting the respective signal lines to each other and the respective power lines to each other. That is, in Figure 6A In the configuration shown in , the pad 151 may be provided on each of the second substrate 110B and the third substrate 110C, instead of the illustrated configuration example of the pad 151. Similarly, in Figure 6B and Figure 6CIn each configuration shown in , in the example shown, the pad 151 may be provided on each of the second substrate 110B and the third substrate 110C, but the pad 151 may be provided in the first substrate 110A and the third substrate 110C instead.

[0408] exist Figure 6D and 6E In each of the configurations shown in FIG, in the example shown, one pad 151 is shared by the TSV dual-purpose lead openings 155a and 155b and the lead opening 155c, but the present embodiment is not limited to such an example. In each of these configurations, one pad 151 may be provided for each of the TSV dual-purpose lead openings 155a and 155b (i.e., for the TSV 157) and the lead opening 155c. In this case, the film made of a conductive material contained in the TSV dual-purpose lead openings 155a and 155b and the film made of a conductive material contained in the lead opening 155c may extend to the surface on the back side of the first substrate 110A and be isolated from each other (i.e., the two are not conductive).

[0409] (4-2. Second Configuration Example)

[0410] Figures 7A to 7K are vertical cross-sectional views of schematic configurations of a solid-state imaging device according to a second configuration example of the present embodiment. The solid-state imaging device according to the present embodiment may have Figures 7A to 7K The construction shown in .

[0411] Figure 7A The solid-state imaging device 3a shown in the figure includes: dual-contact TSV157a and 157b between two layers as a connection structure, and an embedded pad structure for the first substrate 110A (i.e., a pad 151 arranged in the multi-layer wiring layer 105 of the first substrate 110A and a pad opening 153 exposing the pad 151).

[0412] The TSV 157b is formed from the front surface side of the second substrate 110B toward the third substrate 110C and is provided to electrically connect the respective signal lines provided in the second substrate 110B and the third substrate 110C to each other and to electrically connect the respective power lines provided in the second substrate 110B and the third substrate 110C to each other. Figure 7A In the configuration shown in , predetermined wirings of the second metal wiring layer in the multilayer wiring layer 125 of the second substrate 110B and predetermined wirings of the second metal wiring layer in the multilayer wiring layer 135 of the third substrate 110C are electrically connected to each other through TSVs 157b.

[0413] The TSVs 157a are formed from the back side of the first substrate 110A toward the second substrate 110B and are provided to electrically connect the respective signal lines provided in the first substrate 110A and the second substrate 110B to each other and to electrically connect the respective power lines provided in the first substrate 110A and the second substrate 110B to each other. Figure 7A In the configuration shown in FIG, one via of TSV 157a contacts a predetermined wiring of the first metal wiring layer in the multilayer wiring layer 105 of the first substrate 110A, and the other via contacts the upper end of TSV 157b. That is, TSV 157a is formed to electrically connect the predetermined wiring in the multilayer wiring layer 105 of the first substrate 110A and TSV 157b to each other. Furthermore, TSV 157a electrically connects the predetermined wiring in the multilayer wiring layer 105 of the first substrate 110A to the predetermined wiring in the multilayer wiring layer 125 of the second substrate 110B and the predetermined wiring in the multilayer wiring layer 135 of the third substrate 110C, which are electrically connected by TSV 157b.

[0414] Figure 7B The solid-state imaging device 3b shown in FIG corresponds to Figure 7A The solid-state imaging device 3a shown in FIG. 1 is a device in which the type (material) of the wiring electrically connected through the TSV 157b is changed. Specifically, in FIG. Figure 7B In the illustrated configuration, predetermined wirings of the first metal wiring layer in the multilayer wiring layer 125 of the second substrate 110B and predetermined wirings of the first metal wiring layer in the multilayer wiring layer 135 of the third substrate 110C are electrically connected to each other through TSVs 157 b .

[0415] Figure 7C The solid-state imaging device 3c shown in FIG. Figure 7A The solid-state imaging device 3a shown in FIG. 1 has a different TSV 157a structure. Specifically, Figure 7A In the illustrated configuration, the TSV 157a is provided so as to electrically connect predetermined wirings in the multi-layer wiring layer 105 of the first substrate 110A and the TSV 157b to each other. Figure 7C In the configuration shown in , the TSV 157a is provided to electrically connect a predetermined wiring in the multilayer wiring layer 105 of the first substrate 110A and a predetermined wiring in the multilayer wiring layer 125 of the second substrate 110B to each other. Figure 7C In the configuration shown in , predetermined wirings of the first metal wiring layer in the multilayer wiring layer 105 of the first substrate 110A and predetermined wirings of the second metal wiring layer in the multilayer wiring layer 125 of the second substrate 110B are electrically connected to each other through the TSV 157 a .

[0416] Figure 7D The solid-state imaging device 3d shown in FIG corresponds to Figure 7CThe solid-state imaging device 3c shown in FIG. 1 is a device in which the type of wiring electrically connected by TSVs 157a and 157b is changed. Specifically, in FIG. Figure 7D In the illustrated configuration, predetermined wiring lines of the first metal wiring layer in the multilayer wiring layer 105 of the first substrate 110A and predetermined wiring lines of the first metal wiring layer in the multilayer wiring layer 125 of the second substrate 110B are electrically connected to each other via TSVs 157 a. Predetermined wiring lines of the first metal wiring layer in the multilayer wiring layer 125 of the second substrate 110B and predetermined wiring lines of the first metal wiring layer in the multilayer wiring layer 135 of the third substrate 110C are electrically connected to each other via TSVs 157 b.

[0417] Figure 7E The solid-state imaging device 3e shown in FIG. Figure 7D The solid-state imaging device 3d shown in FIG. 1 has a changed TSV 157b structure. Specifically, in FIG. Figure 7E In the illustrated configuration, the TSVs 157b are formed from the back side of the third substrate 110C toward the second substrate 110B, and are provided to electrically connect the respective signal lines provided in the second substrate 110B and the third substrate 110C to each other and to electrically connect the respective power lines provided in the second substrate 110B and the third substrate 110C to each other. Figure 7E In the configuration shown in , predetermined wirings of the first metal wiring layer in the multilayer wiring layer 125 of the second substrate 110B and predetermined wirings of the first metal wiring layer in the multilayer wiring layer 135 of the third substrate 110C are electrically connected to each other through TSVs 157b.

[0418] Figure 7F The solid-state imaging device 3f shown in FIG. Figure 7B The solid-state imaging device 3b shown in FIG. 3B has a modified buried pad structure. Specifically, Figure 7F In the illustrated configuration, a non-buried lead pad structure for the second substrate 110B (i.e., lead openings 155 for predetermined wiring in the multilayer wiring layer 125 of the second substrate 110B and pads 151 on the surface on the back side of the first substrate 110A) is provided instead of a buried pad structure.

[0419] Figure 7G The solid-state imaging device 3g shown in FIG corresponds to Figure 7F The solid-state imaging device 3f shown in FIG. 3 is a device in which the lead pad structure is changed. Specifically, Figure 7GIn the structure shown, an embedded lead-out pad structure is provided for the third substrate 110C (i.e., a lead opening 155 for a predetermined wiring in the multi-layer wiring layer 135 of the third substrate 110C and a pad 151 formed by embedding in the insulating film 109 on the surface on the back side of the first substrate 110A), rather than a non-embedded lead-out pad structure for the second substrate 110B.

[0420] Figure 7H The solid-state imaging device 3h shown in FIG corresponds to Figure 7B The solid-state imaging device 3b shown in the figure is configured such that a non-buried lead pad structure using TSV dual-purpose lead openings 155a and 155b (i.e., TSV dual-purpose lead openings 155a and 155b and the pad 151 on the surface on the back side of the first substrate 110A) is provided by changing the buried TSV 157a into a non-buried TSV, instead of the TSV 157a and the buried pad structure.

[0421] Figure 7I The solid-state imaging device 3i shown in FIG corresponds to Figure 7D The solid-state imaging device 3d shown in the figure is configured such that a non-buried lead pad structure using TSV dual-purpose lead openings 155a and 155b (i.e., TSV dual-purpose lead openings 155a and 155b and the pad 151 on the surface of the back side of the first substrate 110A) is provided by changing the buried TSV 157a into a non-buried TSV, instead of the TSV 157a and the buried pad structure.

[0422] Figure 7J The solid-state imaging device 3j shown in FIG. Figure 7H In the solid-state imaging device 3h shown in FIG, the non-buried lead pad structure of the TSV dual-purpose lead openings 155a and 155b is changed to a buried lead pad structure.

[0423] Figure 7K The solid-state imaging device 3k shown in FIG corresponds to Figure 7I In the solid-state imaging device 3i shown in FIG, the non-buried type lead pad structure of the TSV dual-purpose lead openings 155a and 155b is changed to a buried type lead pad structure.

[0424] Note that the type of wiring connection of the dual-contact TSV 157 between the two layers is not limited to each of the configurations shown in 7A to 7K. TSV 157 can be connected to a predetermined wiring of the first metal wiring layer, or can be connected to a predetermined wiring of the second metal wiring layer. In addition, each of the multi-layer wiring layers 105, 125, and 135 can include only the first metal wiring layer, can include only the second metal wiring layer, or can include both of them to coexist.

[0425] exist Figures 7A to 7G In each of the configurations shown in , the substrate on which the pad 151 is provided is not limited to the illustrated example. In the second configuration example, the respective signal lines provided in the first substrate 110A and the second substrate 110B and the respective power supply lines provided in the first substrate 110A and the second substrate 110B are electrically connected to each other through one TSV 157a. The respective signal lines provided in the second substrate 110B and the third substrate 110C and the respective power supply lines provided in the second substrate 110B and the third substrate 110C are electrically connected to each other through another TSV 157b. Therefore, the pad 151 as a connection structure may not be provided. Therefore, for example, in Figures 7A to 7G In each of the configurations shown in FIG, the pad 151 may be provided on any one of the substrates 110A, 110B, and 110C to obtain a desired signal.

[0426] In the case of providing a lead pad structure, the lead pad structure may be a non-buried type or a buried type. Figure 7F In the configuration shown in , a buried lead pad structure may be provided instead of a non-buried lead pad structure. Figure 7G In the illustrated configuration, a non-buried type lead pad structure may be provided instead of the buried type lead pad structure.

[0427] (4-3. Third structural example)

[0428] Figures 8A to 8G are vertical cross-sectional views of schematic configurations of a solid-state imaging device according to a third configuration example of the present embodiment. The solid-state imaging device according to the present embodiment may have Figures 8A to 8G Each of the constructs shown in .

[0429] Figure 8A The solid-state imaging device 4a shown in the figure includes: a double-contact type and buried TSV 157a between two layers as a connection structure, a double-contact type and buried TSV 157b between three layers, and a buried pad structure for the first substrate 110A (i.e., a pad 151 provided in the multi-layer wiring layer 105 of the first substrate 110A and a pad opening 153 exposing the pad 151).

[0430] The TSVs 157a are formed from the back side of the first substrate 110A toward the second substrate 110B and are provided to electrically connect the respective signal lines provided in the first substrate 110A and the second substrate 110B to each other and to electrically connect the respective power lines provided in the first substrate 110A and the second substrate 110B to each other. Figure 8AIn the configuration shown in , predetermined wiring of the first metal wiring layer in the multilayer wiring layer 105 of the first substrate 110A and predetermined wiring 110B of the second metal wiring layer in the multilayer wiring layer 125 of the second substrate are electrically connected to each other through TSV 157a. In addition, TSV 157b is formed from the back side of the third substrate 110C toward the first substrate 110A, and is provided to electrically connect the respective signal lines provided in the first substrate 110A and the third substrate 110C to each other and to electrically connect the respective power supply lines provided in the first substrate 110A and the third substrate 110C to each other. Figure 8A In the configuration shown in , predetermined wirings of the second metal wiring layer in the multilayer wiring layer 105 of the first substrate 110A and predetermined wirings of the first metal wiring layer in the multilayer wiring layer 135 of the third substrate 110C are electrically connected to each other through TSVs 157b.

[0431] Figure 8B The solid-state imaging device 4b shown in FIG8 corresponds to the solid-state imaging device 4a shown in FIG8A, wherein the type of wiring electrically connected by the TSV 157a is changed. Specifically, in FIG8A Figure 8B In the illustrated configuration, predetermined wirings of the first metal wiring layer in the multilayer wiring layer 105 of the first substrate 110A and predetermined wirings 110B of the first metal wiring layer in the multilayer wiring layer 125 of the second substrate are electrically connected to each other through TSVs 157 a .

[0432] Figure 8C The solid-state imaging device 4c shown in the figure includes: a double-contact type and buried TSV 157a between two layers as a connection structure, a double-contact type and buried TSV 157b between three layers, a buried pad structure for the second substrate 110B (i.e., a pad 151 provided in the multi-layer wiring layer 125 of the second substrate 110B and a pad opening 153a exposing the pad 151), and a buried pad structure substrate for the third substrate 110C (i.e., a pad 151 provided in the multi-layer wiring layer 135 of the third substrate 110C and a pad opening 153b exposing the pad 151).

[0433] The TSVs 157a are formed from the back side of the first substrate 110A toward the second substrate 110B and are provided to electrically connect the respective signal lines provided in the first substrate 110A and the second substrate 110B to each other and to electrically connect the respective power lines provided in the first substrate 110A and the second substrate 110B to each other. Figure 8CIn the configuration shown in , predetermined wiring of the first metal wiring layer in the multilayer wiring layer 105 of the first substrate 110A and predetermined wiring 110B of the second metal wiring layer in the multilayer wiring layer 125 of the second substrate are electrically connected to each other through TSV 157a. TSV 157b is formed from the back side of the third substrate 110C toward the first substrate 110A, and is provided to electrically connect the respective signal lines provided in the first substrate 110A and the second substrate 110B to each other and to electrically connect the respective power supply lines provided in the first substrate 110A and the second substrate 110B to each other. Figure 8C In the configuration shown in FIG, a predetermined wiring of the first metal wiring layer in the multi-layer wiring layer 105 of the first substrate 110A and a predetermined wiring 110B of the first metal wiring layer in the multi-layer wiring layer 125 of the second substrate are electrically connected to each other through TSVs 157b. In addition, the respective signal lines provided in the second substrate 110B and the third substrate 110C and the respective power supply lines provided in the second substrate 110B and the third substrate 110C can be electrically connected to each other through two buried pad structures.

[0434] Figure 8D The solid-state imaging device 4d shown in FIG. Figure 8B The solid-state imaging device 4b shown in FIG. 4B has a changed buried pad structure and a changed type of wiring electrically connected by TSV 157b. Specifically, in FIG. Figure 8D In the illustrated configuration, a non-buried lead pad structure for the second substrate 110B (i.e., lead openings 155 for predetermined wiring in the multilayer wiring layer 125 of the second substrate 110B and pads 151 on the surface on the back side of the first substrate 110A) is provided instead of a buried pad structure. Figure 8D In the illustrated configuration, predetermined wirings of the first metal wiring layer in the multilayer wiring layer 105 of the first substrate 110A and predetermined wirings of the first metal wiring layer in the multilayer wiring layer 135 of the third substrate 110C are electrically connected to each other through TSVs 157 b .

[0435] Figure 8E The solid-state imaging device 4e shown in FIG. Figure 8D The solid-state imaging device 4d shown in FIG. 4 is a device in which the structure of the lead-out pad structure is changed. Specifically, Figure 8E In the structure shown, an embedded lead-out pad structure is provided for the third substrate 110C (i.e., a lead opening 155 for a predetermined wiring in the multi-layer wiring layer 135 of the third substrate 110C and a pad 151 formed by embedding in the insulating film 109 on the surface on the back side of the first substrate 110A), rather than a non-embedded lead-out pad structure for the second substrate 110B.

[0436] Figure 8FThe solid-state imaging device 4f shown in FIG. Figure 8E The solid-state imaging device 4e shown in the figure is configured so that a non-buried lead pad structure using TSV dual-purpose lead openings 155a and 155b (i.e., TSV dual-purpose lead openings 155a and 155b and the pad 151 on the surface of the back side of the first substrate 110A) is provided by changing the buried TSV 157a into a non-buried TSV, instead of the TSV 157a and the buried lead pad structure.

[0437] Figure 8G The solid-state imaging device 4g shown in FIG. Figure 8F In the solid-state imaging device 4f shown in FIG, the non-buried lead pad structure of the TSV dual-purpose lead openings 155a and 155b is changed to a buried lead pad structure.

[0438] Note that the type of wiring connected by the double-contact type TSV 157 between two and three layers is not limited to Figures 8A to 8G . These TSVs 157 may be connected to predetermined wirings of the first metal wiring layer, or may be connected to predetermined wirings of the second metal wiring layer. In addition, each of the multilayer wiring layers 105, 125, and 135 may include only the first metal wiring layer, may include only the second metal wiring layer, or may include both of them to coexist.

[0439] exist Figure 8C In the configuration shown in , in the example shown, the pad 151 is provided on each of the second substrate 110B and the third substrate 110C. However, the present embodiment is not limited to such an example. In this configuration, the respective signal lines provided in the first substrate 110A and the second substrate 110B and the respective power supply lines provided in the first substrate 110A and the second substrate 110B are electrically connected to each other through TSVs 157a and 157b. Therefore, the second substrate 110B and the third substrate 110C or the first substrate 110A and the third substrate 110C, which are respectively provided with signal lines and power supply lines that are not electrically connected to each other through TSVs 157a or TSVs 157b, may be respectively provided with pads 151 for electrically connecting the respective signal lines to each other and the respective power supply lines to each other. That is, in Figure 8C In the respective configurations shown in , the pads 151 may be provided in the first substrate 110A and the third substrate 110C, instead of the illustrated configuration example of the pads 151 .

[0440] In addition, Figure 8A 、 Figure 8B 、 Figure 8D and Figure 8EIn each of the configurations shown in , the substrate on which the pad 151 is provided is not limited to the illustrated example. In each of these configurations, the respective signal lines provided in the first substrate 110A and the second substrate 110B and the respective power supply lines provided in the first substrate 110A and the second substrate 110B are electrically connected to each other through one TSV 157a. The respective signal lines provided in the first substrate 110A and the third substrate 110C are electrically connected to each other and the respective power supply lines provided in the first substrate 110A and the third substrate 110C are electrically connected to each other through another TSV 157b. Therefore, the pad 151 as a connection structure may not be provided. Therefore, for example, in Figure 8A 、 Figure 8B 、 Figure 8D and Figure 8E In each of the configurations shown in FIG, the pad 151 may be provided on any one of the substrates 110A, 110B, and 110C to obtain a desired signal.

[0441] In the case of setting a lead pad structure, the lead pad structure can be a non-buried type or a buried type. Figure 8D In the configuration shown in , a buried lead pad structure may be provided instead of a non-buried lead pad structure. Figure 8E In the illustrated configuration, a non-buried type lead pad structure may be provided instead of the buried type lead pad structure.

[0442] exist Figures 8A to 8G In each configuration shown in FIG, double contact type and buried type TSVs 157 between three layers are formed from the back side of the third substrate 110C toward the first substrate 110A, but the present embodiment is not limited to this example. TSVs 157 may be formed from the back side of the first substrate 110A toward the third substrate 110C.

[0443] Furthermore, the double-contact type TSVs 157 between the three layers are sufficient to electrically connect the respective signal lines and the respective power supply lines provided in two of the first substrate 110A, the second substrate 110B, and the third substrate 110C to one another according to the direction in which the TSVs 157 are formed. The substrates provided with the respective signal lines and the respective power supply lines to be electrically connected to one another through the TSVs 157 may be optionally changed.

[0444] (4-4. Fourth Configuration Example)

[0445] Figures 9A to 9K are vertical cross-sectional views of schematic configurations of a solid-state imaging device according to a fourth configuration example of the present embodiment. The solid-state imaging device according to the present embodiment may have Figures 9A to 9K Each of the constructs shown in .

[0446] Figure 9AThe solid-state imaging device 5a shown in the figure includes: a dual-contact and buried TSV 157a between two layers as a connection structure, a shared contact and buried TSV 157b between the two layers, and a buried pad structure for the first substrate 110A (i.e., a pad 151 provided in the multi-layer wiring layer 105 of the first substrate 110A and a pad opening 153 exposing the pad 151).

[0447] The TSV 157b is formed from the front surface side of the second substrate 110B toward the third substrate 110C and is provided to electrically connect the respective signal lines provided in the second substrate 110B and the third substrate 110C to each other and to electrically connect the respective power lines provided in the second substrate 110B and the third substrate 110C to each other. Figure 9A In the configuration shown in , predetermined wirings of the second metal wiring layer in the multilayer wiring layer 125 of the second substrate 110B and predetermined wirings of the second metal wiring layer in the multilayer wiring layer 135 of the third substrate 110C are electrically connected to each other through TSVs 157b.

[0448] The TSVs 157a are formed from the back side of the first substrate 110A toward the second substrate 110B and are provided to electrically connect the respective signal lines provided in the first substrate 110A and the second substrate 110B to each other and to electrically connect the respective power lines provided in the first substrate 110A and the second substrate 110B to each other. Figure 9A In the configuration shown in FIG, one via of TSV 157a contacts a predetermined wiring of the first metal wiring layer in the multilayer wiring layer 105 of the first substrate 110A, and the other via contacts the upper end of TSV 157b. That is, TSV 157a is formed to electrically connect the predetermined wiring in the multilayer wiring layer 105 of the first substrate 110A and TSV 157b to each other. Furthermore, TSV 157a electrically connects the predetermined wiring in the multilayer wiring layer 105 of the first substrate 110A to the predetermined wiring in the multilayer wiring layer 125 of the second substrate 110B and the predetermined wiring in the multilayer wiring layer 135 of the third substrate 110C, which are electrically connected by TSV 157b.

[0449] Figure 9B The solid-state imaging device 5b shown in FIG. Figure 9A The solid-state imaging device 5a shown in FIG. 1 is a device in which the type of wiring electrically connected by the TSV 157b is changed. Specifically, in FIG. Figure 9B In the illustrated configuration, predetermined wirings of the first metal wiring layer in the multilayer wiring layer 125 of the second substrate 110B and predetermined wirings of the first metal wiring layer in the multilayer wiring layer 135 of the third substrate 110C are electrically connected to each other through TSVs 157 b .

[0450] Figure 9CThe solid-state imaging device 5c shown in FIG. Figure 9A The solid-state imaging device 5a shown in FIG. 1 is a device in which the TSV 157a structure is changed. Specifically, in FIG. Figure 9A In the illustrated configuration, the TSV 157a is provided so as to electrically connect predetermined wirings in the multi-layer wiring layer 105 of the first substrate 110A and the TSV 157b to each other. Figure 9C In the illustrated configuration, the TSV 157a is provided to electrically connect predetermined wiring in the multilayer wiring layer 105 of the first substrate 110A and predetermined wiring in the multilayer wiring layer 125 of the second substrate 110B to each other. Figure 9C In the configuration shown in , predetermined wirings of the first metal wiring layer in the multilayer wiring layer 105 of the first substrate 110A and predetermined wirings of the second metal wiring layer in the multilayer wiring layer 125 of the second substrate 110B are electrically connected to each other through the TSV 157 a .

[0451] Figure 9D The solid-state imaging device 5d shown in FIG. Figure 9C The solid-state imaging device 5c shown in FIG. 1 is a device in which the type of wiring electrically connected by TSVs 157a and 157b is changed. Specifically, in FIG. Figure 9D In the illustrated configuration, a predetermined wiring line of the first metal wiring layer in the multilayer wiring layer 105 of the first substrate 110A and a predetermined wiring line 110B of the first metal wiring layer in the multilayer wiring layer 125 of the second substrate are electrically connected to each other via TSVs 157 a. Furthermore, a predetermined wiring line of the first metal wiring layer in the multilayer wiring layer 125 of the second substrate 110B and a predetermined wiring line of the first metal wiring layer in the multilayer wiring layer 135 of the third substrate 110C are electrically connected to each other via TSVs 157 b.

[0452] Figure 9E The solid-state imaging device 5e shown in FIG. Figure 9D The solid-state imaging device 5d shown in FIG. 5 is a device in which the structure of the TSV 157b is changed. Specifically, in FIG. Figure 9E In the illustrated configuration, the TSV 157b is formed from the back side of the third substrate 110C toward the second substrate 110B and is provided to electrically connect the respective signal lines provided in the second substrate 110B and the third substrate 110C to each other and to electrically connect the respective power lines provided in the second substrate 110B and the third substrate 110C to each other. Figure 9E In the configuration shown in , predetermined wirings of the first metal wiring layer in the multilayer wiring layer 125 of the second substrate 110B and predetermined wirings of the first metal wiring layer in the multilayer wiring layer 135 of the third substrate 110C are electrically connected to each other through TSVs 157b.

[0453] Figure 9FThe solid-state imaging device 5f shown in FIG. Figure 9B The solid-state imaging device 5b shown in FIG. 5 is a device in which the buried pad structure is changed. Specifically, in FIG. Figure 9F In the illustrated configuration, a non-buried lead pad structure for the second substrate 110B (i.e., lead openings 155 for predetermined wiring in the multilayer wiring layer 125 of the second substrate 110B and pads 151 on the surface on the back side of the first substrate 110A) is provided instead of a buried pad structure.

[0454] Figure 9G The solid-state imaging device 5g shown in FIG. Figure 9F The solid-state imaging device 5f shown in FIG. 5 is a device in which the structure of the lead-out pad structure is changed. Specifically, in FIG. Figure 9G In the structure shown, an embedded lead-out pad structure is provided for the third substrate 110C (i.e., a lead opening 155 for a predetermined wiring in the multi-layer wiring layer 135 of the third substrate 110C and a pad 151 formed by embedding in the insulating film 109 on the surface on the back side of the first substrate 110A), rather than a non-embedded lead-out pad structure for the second substrate 110B.

[0455] Figure 9H The solid-state imaging device 5h shown in FIG. Figure 9B The solid-state imaging device 5b shown in the figure is configured such that a non-buried lead pad structure using TSV dual-purpose lead openings 155a and 155b (i.e., TSV dual-purpose lead openings 155a and 155b and the pad 151 on the surface on the back side of the first substrate 110A) is provided by changing the buried TSV 157a into a non-buried TSV, instead of the TSV 157a and the buried pad structure.

[0456] Figure 9I The solid-state imaging device 5i shown in FIG. Figure 9D The solid-state imaging device 5d shown in the figure is configured such that a non-buried lead pad structure using TSV dual-purpose lead openings 155a and 155b (i.e., TSV dual-purpose lead openings 155a and 155b and the pad 151 on the surface on the back side of the first substrate 110A) is provided by changing the buried TSV 157a into a non-buried TSV, instead of the TSV 157a and the buried pad structure.

[0457] Figure 9J The solid-state imaging device 5j shown in FIG. Figure 9H In the solid-state imaging device 5h shown in FIG, the non-buried lead pad structure of the TSV dual-purpose lead openings 155a and 155b is changed to a buried lead pad structure.

[0458] Figure 9KThe solid-state imaging device 5k shown in FIG. Figure 9I In the solid-state imaging device 5i shown in FIG, the non-buried type lead pad structure of the TSV dual-purpose lead openings 155a and 155b is changed to a buried type lead pad structure.

[0459] The types of wiring connections through the double contact type TSV 157 between two layers and the shared contact type TSV 157 between two layers are not limited to Figures 9A to 9K Each configuration shown in . These TSVs 157 can be connected to predetermined wirings of the first metal wiring layer, or can be connected to predetermined wirings of the second metal wiring layer. In addition, each of the multilayer wiring layers 105, 125, and 135 can include only the first metal wiring layer, can include only the second metal wiring layer, or can include both of them to coexist.

[0460] exist Figures 9A to 9G In each of the configurations shown in , the substrate on which the pad 151 is provided is not limited to the illustrated example. In the fourth configuration example, the respective signal lines provided in the first substrate 110A and the second substrate 110B and the respective power supply lines provided in the first substrate 110A and the second substrate 110B are electrically connected to each other through one TSV 157a. The respective signal lines provided in the second substrate 110B and the third substrate 110C and the respective power supply lines provided in the second substrate 110B and the third substrate 110C are electrically connected to each other through another TSV 157b. Therefore, the pad 151 as a connection structure may not be provided. Therefore, for example, in Figures 9A to 9G In each of the configurations shown in FIG. 1 , the pad 151 may be provided on any one of the substrates 110A, 110B, and 110C to obtain a desired signal.

[0461] In the case of providing a lead pad structure, the lead pad structure may be a non-buried type or a buried type. Figure 9F In the configuration shown in , a buried lead pad structure may be provided instead of a non-buried lead pad structure. Figure 9G In the illustrated configuration, a non-buried type lead pad structure may be provided instead of the buried type lead pad structure.

[0462] (4-5. Fifth Configuration Example)

[0463] Figures 10A to 10G are vertical cross-sectional views of schematic configurations of a solid-state imaging device according to a fifth configuration example of the present embodiment. The solid-state imaging device according to the present embodiment may have Figures 10A to 10G Each of the constructs shown in .

[0464] Figure 10AThe solid-state imaging device 6a shown in the figure includes: a double contact type and buried TSV 157a between two layers as a connection structure, a shared contact type and buried TSV 157b between three layers, and a buried pad structure for the first substrate 110A (i.e., a pad 151 provided in the multi-layer wiring layer 105 of the first substrate 110A and a pad opening 153 exposing the pad 151).

[0465] The TSVs 157a are formed from the back side of the first substrate 110A toward the second substrate 110B and are provided to electrically connect the respective signal lines provided in the first substrate 110A and the second substrate 110B to each other and to electrically connect the respective power lines provided in the first substrate 110A and the second substrate 110B to each other. Figure 10A In the configuration shown in , predetermined wiring of the first metal wiring layer in the multilayer wiring layer 105 of the first substrate 110A and predetermined wiring of the second metal wiring layer in the multilayer wiring layer 125 of the second substrate 110B are electrically connected to each other through TSV 157a. In addition, TSV 157b is formed from the back side of the third substrate 110C toward the first substrate 110A, and is provided to electrically connect the respective signal lines provided in the first substrate 110A and the third substrate 110C to each other and to electrically connect the respective power supply lines provided in the first substrate 110A and the third substrate 110C to each other. Figure 10A In the configuration shown in , predetermined wirings of the second metal wiring layer in the multilayer wiring layer 105 of the first substrate 110A and predetermined wirings of the first metal wiring layer in the multilayer wiring layer 135 of the third substrate 110C are electrically connected to each other through TSVs 157b.

[0466] Figure 10B The solid-state imaging device 6b shown in FIG. Figure 10A The solid-state imaging device 6a shown in FIG. 1 is a device in which the type of wiring electrically connected by the TSV 157a is changed. Specifically, in FIG. Figure 10B In the illustrated configuration, predetermined wirings of the first metal wiring layer in the multilayer wiring layer 105 of the first substrate 110A and predetermined wirings of the first metal wiring layer in the multilayer wiring layer 125 of the second substrate 110B are electrically connected to each other through TSVs 157 a .

[0467] Figure 10C The solid-state imaging device 6c shown in FIG includes: a double-contact type and buried TSV 157a between two layers as a connection structure, a shared contact type and buried TSV 157b between three layers, and a buried pad structure for the second substrate 110B (i.e., a pad 151 provided in the multi-layer wiring layer 125 of the second substrate 110B and a pad opening 153 exposing the pad 151).

[0468] The TSVs 157a are formed from the back side of the first substrate 110A toward the second substrate 110B and are provided to electrically connect the respective signal lines provided in the first substrate 110A and the second substrate 110B to each other and to electrically connect the respective power lines provided in the first substrate 110A and the second substrate 110B to each other. Figure 10C In the configuration shown in , predetermined wiring of the first metal wiring layer in the multilayer wiring layer 105 of the first substrate 110A and predetermined wiring of the second metal wiring layer in the multilayer wiring layer 125 of the second substrate 110B are electrically connected to each other through TSV 157a. In addition, TSV 157b is formed from the back side of the third substrate 110C toward the first substrate 110A, and is provided to electrically connect the respective signal lines provided in the first substrate 110A, the second substrate 110B, and the third substrate 110C together and to electrically connect the respective power supply lines included in the first substrate 110A, the second substrate 110B, and the third substrate 110C together. Figure 10C In the configuration shown in , predetermined wirings of the first metal wiring layer in the multilayer wiring layer 105 of the first substrate 110A, predetermined wirings of the first metal wiring layer in the multilayer wiring layer 125 of the second substrate 110B, and predetermined wirings of the first metal wiring layer in the multilayer wiring layer 135 of the third substrate 110C are electrically connected together by TSVs 157b.

[0469] Figure 10D The solid-state imaging device 6d shown in FIG. Figure 10B The solid-state imaging device 6b shown in FIG. 1 has a changed buried pad structure and a changed type of wiring electrically connected by TSV 157b. Specifically, in FIG. Figure 10D In the illustrated configuration, a non-buried lead pad structure for the second substrate 110B (i.e., lead openings 155 for predetermined wiring in the multilayer wiring layer 125 of the second substrate 110B and pads 151 on the surface on the back side of the first substrate 110A) is provided instead of a buried pad structure. Figure 10D In the illustrated configuration, predetermined wirings of the first metal wiring layer in the multilayer wiring layer 105 of the first substrate 110A and predetermined wirings of the first metal wiring layer in the multilayer wiring layer 135 of the third substrate 110C are electrically connected to each other through TSVs 157 b .

[0470] Figure 10E The solid-state imaging device 6e shown in FIG. Figure 10D The solid-state imaging device 6d shown in FIG. 6d has a different structure of the lead pad structure. Specifically, Figure 10EIn the structure shown, an embedded lead-out pad structure is provided for the third substrate 110C (i.e., a lead opening 155 for a predetermined wiring in the multi-layer wiring layer 135 of the third substrate 110C and a pad 151 formed by embedding in the insulating film 109 on the surface on the back side of the first substrate 110A), rather than a non-embedded lead-out pad structure for the second substrate 110B.

[0471] Figure 10F The solid-state imaging device 6f shown in FIG. Figure 10E The solid-state imaging device 6e shown in the figure is configured so that a non-buried lead pad structure using TSV dual-purpose lead openings 155a and 155b (i.e., TSV dual-purpose lead openings 155a and 155b and the pad 151 on the surface of the back side of the first substrate 110A) is provided by changing the buried TSV 157a into a non-buried TSV, instead of the TSV 157a and the buried lead pad structure.

[0472] Figure 10G The solid-state imaging device 6g shown in FIG. Figure 10F In the solid-state imaging device 6f shown in FIG, the non-buried lead pad structure of the TSV dual-purpose lead openings 155a and 155b is changed to a buried lead pad structure.

[0473] The types of wiring connected by the dual-contact TSVs 157 between two layers and the shared-contact TSVs 157 between three layers are not limited to each of the configurations shown in 10A to 10G. These TSVs 157 can be connected to predetermined wiring of the first metal wiring layer, or can be connected to predetermined wiring of the second metal wiring layer. In addition, each of the multi-layer wiring layers 105, 125, and 135 can include only the first metal wiring layer, can include only the second metal wiring layer, or can include both of them to coexist.

[0474] exist Figures 10A to 10E In each of the configurations shown in , the substrate on which the pad 151 is provided is not limited to the illustrated example. In each of these configurations, the respective signal lines provided in the first substrate 110A and the second substrate 110B and the respective power supply lines provided in the first substrate 110A and the second substrate 110B are electrically connected to each other through one TSV 157a. The respective signal lines provided in the first substrate 110A and the third substrate 110C and the respective power supply lines provided in the first substrate 110A and the third substrate 110C are electrically connected to each other through at least another TSV 157b. Therefore, the pad 151 as a connection structure may not be provided. Therefore, for example, in Figures 10A to 10E In each of the configurations shown in FIG. 1 , the pad 151 may be provided on any one of the substrates 110A, 110B, and 110C to obtain a desired signal.

[0475] In the case of providing a lead pad structure, the lead pad structure may be a non-buried type or a buried type. Figure 10D In the configuration shown in , a buried lead pad structure may be provided instead of a non-buried lead pad structure. Figure 10E In the illustrated configuration, a non-buried type lead pad structure may be provided instead of the buried type lead pad structure.

[0476] exist Figures 10A to 10G In each configuration shown in FIG, shared contact type and buried type TSVs 157 between the three layers are formed from the back side of the third substrate 110C toward the first substrate 110A, but the present embodiment is not limited to this example. TSVs 157 may be formed from the back side of the first substrate 110A toward the third substrate 110C.

[0477] In addition, it is sufficient that the common contact type TSV 157 between the three layers electrically connects the respective signal lines and the respective power supply lines provided in at least two of the first substrate 110A, the second substrate 110B, and the third substrate 110C. The substrates provided with the respective signal lines and the respective power supply lines electrically connected to each other through the TSV 157 may be optionally changed.

[0478] (4-6. Sixth Configuration Example)

[0479] Figures 11A to 11F are vertical cross-sectional views of schematic configurations of a solid-state imaging device according to a sixth configuration example of the present embodiment. The solid-state imaging device according to the present embodiment may have Figures 11A to 11F Each of the constructs shown in .

[0480] Figure 11A The solid-state imaging device 7a shown in the figure includes: a dual-contact type and buried TSV 157 between two layers as a connection structure, an electrode bonding structure 159 arranged between the second substrate 110B and the third substrate 110C, and a buried pad structure for the first substrate 110A (i.e., a pad 151 arranged in the multi-layer wiring layer 105 of the first substrate 110A and a pad opening 153 exposing the pad 151).

[0481] The TSVs 157 are formed from the back side of the first substrate 110A toward the second substrate 110B and are provided to electrically connect the respective signal lines provided in the first substrate 110A and the second substrate 110B to each other and to electrically connect the respective power lines provided in the first substrate 110A and the second substrate 110B to each other. Figure 11AIn the configuration shown in FIG, predetermined wirings of the first metal wiring layer in the multi-layer wiring layer 105 of the first substrate 110A and predetermined wirings of the second metal wiring layer in the multi-layer wiring layer 125 of the second substrate 110B are electrically connected to each other through TSVs 157. In addition, respective signal lines provided in the second substrate 110B and the third substrate 110C and respective power supply lines provided in the second substrate 110B and the third substrate 110C are electrically connected to each other through electrode bonding structures 159.

[0482] Here, specifically, the electrode contact structure 159 can be formed by performing heat treatment in a state where the second substrate 110B and the third substrate 110C are bonded to each other in a manner that the electrodes provided on the bonding surface of the second substrate 110B and the electrodes provided on the bonding surface of the third substrate 110C are in contact with each other, and bonding the electrodes together. The electrode bonding structure 159 includes an electrode formed on the bonding surface of the second substrate 110B, a via for electrically connecting the electrode to a predetermined wiring in the multilayer wiring layer 125, an electrode formed on the bonding surface of the third substrate 110C, and a via for electrically connecting the electrode to a predetermined wiring in the multilayer wiring layer 135. Note that at this time, the second substrate 110B and the third substrate 110C are bonded face to back, so the via provided on the second substrate 110B side is formed as a via (i.e., TSV) that penetrates the semiconductor substrate 121.

[0483] Figure 11B The solid-state imaging device 7b shown in FIG. Figure 11A The solid-state imaging device 7a shown in FIG. 1 is a device in which the type of wiring electrically connected by the TSV 157 is changed. Specifically, in FIG. Figure 11B In the illustrated configuration, predetermined wirings of the first metal wiring layer in the multilayer wiring layer 105 of the first substrate 110A and predetermined wirings of the first metal wiring layer in the multilayer wiring layer 125 of the second substrate 110B are electrically connected to each other through TSVs 157 .

[0484] Figure 11C The solid-state imaging device 7c shown in FIG. Figure 11B The solid-state imaging device 7b shown in FIG. 7B has a modified buried pad structure. Specifically, Figure 11C In the illustrated configuration, a non-buried lead pad structure for the second substrate 110B (i.e., lead openings 155 for predetermined wiring in the multilayer wiring layer 125 of the second substrate 110B and pads 151 on the surface on the back side of the first substrate 110A) is provided instead of a buried pad structure.

[0485] Figure 11D The solid-state imaging device 7d shown in FIG. Figure 11CThe solid-state imaging device 7c shown in FIG. 7 is a device in which the structure of the lead-out pad is changed. Specifically, Figure 11D In the structure shown, an embedded lead-out pad structure is provided for the third substrate 110C (i.e., a lead opening 155 for a predetermined wiring in the multi-layer wiring layer 135 of the third substrate 110C and a pad 151 formed by embedding in the insulating film 109 on the surface on the back side of the first substrate 110A), rather than a non-embedded lead-out pad structure for the second substrate 110B.

[0486] Figure 11E The solid-state imaging device 7e shown in FIG. Figure 11D The solid-state imaging device 7d shown in the figure is configured such that a non-buried lead pad structure using TSV dual-purpose lead openings 155a and 155b (i.e., TSV dual-purpose lead openings 155a and 155b and the pad 151 on the surface of the back side of the first substrate 110A) is provided by changing the buried TSV 157 into a non-buried TSV, instead of the TSV 157 and the buried lead pad structure.

[0487] Figure 11F The solid-state imaging device 7f shown in FIG corresponds to Figure 11E In the solid-state imaging device 7e shown in FIG, the non-buried lead pad structure of the TSV dual-purpose lead openings 155a and 155b is changed to a buried lead pad structure.

[0488] Note that in Figures 11A to 11F In each of the configurations shown in FIG, the type of wiring connected by the dual-contact TSV 157 between the two layers is not limited. TSV 157 can be connected to a predetermined wiring of the first metal wiring layer, or can be connected to a predetermined wiring of the second metal wiring layer. In addition, each of the multilayer wiring layers 105, 125, and 135 can include only the first metal wiring layer, can include only the second metal wiring layer, or can include both of them to coexist.

[0489] exist Figures 11A to 11D In each of the configurations shown in , the substrate on which the pad 151 is provided is not limited to the illustrated example. In the sixth configuration example, the respective signal lines provided in the first substrate 110A and the second substrate 110B and the respective power supply lines provided in the first substrate 110A and the second substrate 110B are electrically connected to each other through TSV 157. The respective signal lines provided in the second substrate 110B and the third substrate 110C and the respective power supply lines provided in the second substrate 110B and the third substrate 110C are electrically connected to each other through the electrode bonding structure 159. Therefore, the pad 151 as a connection structure may not be provided. Therefore, for example, in Figures 11A to 11DIn each of the configurations shown in FIG. 1 , the pad 151 may be provided on any one of the substrates 110A, 110B, and 110C to obtain a desired signal.

[0490] In addition, in the case where a lead pad structure is provided, the lead pad structure may be a non-buried type or a buried type. Figure 11C In the configuration shown in , a buried lead pad structure may be provided instead of a non-buried lead pad structure. Figure 11D In the illustrated configuration, a non-buried type lead pad structure may be provided instead of the buried type lead pad structure.

[0491] (4-7. Seventh structural example)

[0492] Figures 12A to 12L 12A to 12L are vertical cross-sectional views of schematic configurations of a solid-state imaging device according to a seventh configuration example of the present embodiment. The solid-state imaging device according to the present embodiment can have each configuration shown in FIG.

[0493] Figure 12A The solid-state imaging device 8a shown in the figure includes: dual-contact and buried TSVs 157a, 157b and 157c between two layers as a connection structure, an electrode bonding structure 159 arranged between the second substrate 110B and the third substrate 110C, and a buried pad structure for the first substrate 110A (i.e., a pad 151 arranged in the multi-layer wiring layer 105 of the first substrate 110A and a pad opening 153 exposing the pad 151).

[0494] TSVs 157a are formed from the back side of the first substrate 110A toward the second substrate 110B and are provided to electrically connect the respective signal lines provided in the first and second substrates 110A, 110B, and to electrically connect the respective power lines provided in the first and second substrates 110A, 110B. TSVs 157b and 157c are formed from the front side of the second substrate 110B toward the third substrate 110C and are provided to electrically connect the respective signal lines provided in the second and third substrates 110B, 110B, and to electrically connect the respective power lines provided in the second and third substrates 110B, 110C. Furthermore, the respective signal lines provided in the second and third substrates 110B, 110C, and the respective power lines provided in the second and third substrates 110B, 110C, are electrically connected to each other via electrode bonding structures 159.

[0495] As for TSVs 157b and 157c, TSV 157b of one of the two TSVs is provided to electrically connect a predetermined wiring of the second metal wiring layer in the multilayer wiring layer 125 of the second substrate 110B and an electrode in the multilayer wiring layer 135 of the third substrate 110C to each other. The electrode in the multilayer wiring layer 135 is formed so as to expose the metal surface from the insulating film 133. That is, the electrode is formed in the same manner as the electrode included in the electrode bonding structure 159. In this specification, for the sake of convenience, the following electrodes (such as the above-mentioned electrodes) are also referred to as single-sided electrodes: the electrodes are formed so as to expose the metal surface from each of the insulating films 103, 123 and 133 in each of the multilayer wiring layers 105, 125 and 135 in the same manner as the electrodes included in the electrode contact structure 159, but the electrodes are not included in the electrode contact structure 159. Accordingly, for convenience, an electrode formed in the multilayer wiring layers 105, 125, and 135 to expose a metal surface from the insulating films 103, 123, and 133 and included in the electrode bonding structure 159 is also referred to as a double-sided electrode. Figure 12A In the configuration shown in , the TSV 157 b is provided to electrically connect a predetermined wiring in the multilayer wiring layer 125 of the second substrate 110B and a single-sided electrode in the multilayer wiring layer 135 of the third substrate 110C.

[0496] Furthermore, the other of the two TSVs, TSV 157 c is provided to electrically connect predetermined wiring of the second metal wiring layer in the multilayer wiring layer 125 of the second substrate 110B and predetermined wiring of the second metal wiring layer in the multilayer wiring layer 135 of the third substrate 110C to each other.

[0497] Furthermore, TSVs 157a are arranged so that one via contacts a predetermined wiring line of the first metal wiring layer in the multilayer wiring layer 105 of the first substrate 110A, while the other via contacts the upper end of TSV 157b. In other words, TSVs 157a are formed to electrically connect the predetermined wiring line in the multilayer wiring layer 105 of the first substrate 110A and TSVs 157b. Furthermore, TSVs 157a electrically connect the predetermined wiring line in the multilayer wiring layer 105 of the first substrate 110A to the predetermined wiring line in the multilayer wiring layer 125 of the second substrate 110B, which are electrically connected by TSVs 157b, and to the single-sided electrodes in the multilayer wiring layer 135 of the third substrate 110C.

[0498] Figure 12B The solid-state imaging device 8b shown in FIG corresponds to Figure 12A The solid-state imaging device 8a shown in FIG. 8a has a different TSV 157b structure. Specifically, Figure 12BIn the illustrated configuration, the TSV 157b is provided to electrically connect predetermined wirings of the second metal wiring layer in the multilayer wiring layer 125 of the second substrate 110B and the double-sided electrodes included in the electrode contact structure 159 to each other. Figure 12B In the configuration shown in , the TSV 157 b also functions as a via included in the electrode bonding structure 159 .

[0499] Figure 12C The solid-state imaging device 8c shown in FIG corresponds to Figure 12A The solid-state imaging device 8a shown in FIG. 1 is a device in which the type of wiring electrically connected by TSVs 157b and 157c is changed. Specifically, in FIG. Figure 12C In the illustrated configuration, a predetermined wiring line of the first metal wiring layer in the multilayer wiring layer 125 of the second substrate 110B and a single-sided electrode in the multilayer wiring layer 135 of the third substrate 110C are electrically connected to each other via TSVs 157b. Furthermore, a predetermined wiring line of the first metal wiring layer in the multilayer wiring layer 125 of the second substrate 110B and a predetermined wiring line of the first metal wiring layer in the multilayer wiring layer 135 of the third substrate 110C are electrically connected to each other via TSVs 157c.

[0500] Figure 12D The solid-state imaging device 8d shown in FIG. Figure 12A The solid-state imaging device 8a shown in FIG. 1 is a device in which the TSV 157a structure is changed. Specifically, in FIG. Figure 12A In the illustrated configuration, the TSV 157a is provided to electrically connect a predetermined wiring in the multi-layer wiring layer 105 of the first substrate 110A and the TSV 157b to each other. Figure 12D In the configuration shown in , the TSV 157a is provided to electrically connect a predetermined wiring in the multilayer wiring layer 105 of the first substrate 110A and a predetermined wiring in the multilayer wiring layer 125 of the second substrate 110B to each other. Figure 12D In the configuration shown in , predetermined wirings of the first metal wiring layer in the multilayer wiring layer 105 of the first substrate 110A and predetermined wirings of the second metal wiring layer in the multilayer wiring layer 125 of the second substrate 110B are electrically connected to each other through the TSV 157 a .

[0501] Figure 12E The solid-state imaging device 8e shown in FIG. Figure 12D The solid-state imaging device 8d shown in FIG. 1 is a device in which the type of wiring electrically connected by TSVs 157a, 157b, and 157c is changed. Specifically, Figure 12EIn the illustrated configuration, predetermined wiring lines of the first metal wiring layer in the multilayer wiring layer 105 of the first substrate 110A and predetermined wiring lines of the first metal wiring layer in the multilayer wiring layer 125 of the second substrate 110B are electrically connected to each other via TSVs 157a. Furthermore, predetermined wiring lines of the first metal wiring layer in the multilayer wiring layer 125 of the second substrate 110B and single-sided electrodes in the multilayer wiring layer 135 of the third substrate 110C are electrically connected to each other via TSVs 157b. Furthermore, predetermined wiring lines of the first metal wiring layer in the multilayer wiring layer 125 of the second substrate 110B and predetermined wiring lines of the first metal wiring layer in the multilayer wiring layer 135 of the third substrate 110C are electrically connected to each other via TSVs 157c.

[0502] Figure 12F The solid-state imaging device 8f shown corresponds to Figure 12E The solid-state imaging device 8e shown in FIG. 8 is a device in which the configuration of the TSVs 157b and 157c is changed. Specifically, Figure 12F In the illustrated configuration, the TSV 157b is formed from the back side of the third substrate 110C toward the second substrate 110B and is provided to electrically connect the respective signal lines provided in the second substrate 110B and the third substrate 110C to each other and to electrically connect the respective power lines provided in the second substrate 110B and the third substrate 110C to each other. Figure 12F In the configuration shown in , a single-sided electrode in the insulating film 129 provided on the back side of the second substrate 110B and a predetermined wiring of the first metal wiring layer in the multilayer wiring layer 135 of the third substrate 110C are electrically connected to each other through TSV 157b. In addition, TSV 157c is formed from the back side of the third substrate 110C toward the second substrate 110B, and is provided to electrically connect the respective signal lines provided in the second substrate 110B and the third substrate 110C to each other and to electrically connect the respective power supply lines provided in the second substrate 110B and the third substrate 110C to each other. Figure 12F In the configuration shown in , predetermined wirings of the first metal wiring layer in the multilayer wiring layer 125 of the second substrate 110B and predetermined wirings of the first metal wiring layer in the multilayer wiring layer 135 of the third substrate 110C are electrically connected to each other through the TSV 157 c.

[0503] Figure 12G The solid-state imaging device 8g shown in FIG. Figure 12C The solid-state imaging device 8c shown in FIG. 8 has a modified buried pad structure. Specifically, Figure 12GIn the structure shown, a non-buried lead pad structure for the second substrate 110B (i.e., a lead opening 155 for a predetermined wiring in the multilayer wiring layer 125 of the second substrate 110B and a pad 151 on the surface on the back side of the first substrate 110A) is provided instead of a buried pad structure.

[0504] Figure 12H The solid-state imaging device 8h shown in FIG. Figure 12G The solid-state imaging device 8g shown in FIG. 8 is a device in which the structure of the lead-out pad structure is changed. Specifically, in FIG. Figure 12H In the structure shown, an embedded lead-out pad structure is provided for the third substrate 110C (i.e., a lead opening 155 for a predetermined wiring in the multi-layer wiring layer 135 of the third substrate 110C and a pad 151 formed by embedding in the insulating film 109 on the surface on the back side of the first substrate 110A), rather than a non-embedded lead-out pad structure for the second substrate 110B.

[0505] Figure 12I The solid-state imaging device 8i shown in FIG corresponds to Figure 12C The solid-state imaging device 8c shown in the figure is configured so that a non-buried lead pad structure using TSV dual-purpose lead openings 155a and 155b (i.e., TSV dual-purpose lead openings 155a and 155b and the pad 151 on the surface on the back side of the first substrate 110A) is provided by changing the buried TSV 157a into a non-buried TSV, instead of the TSV 157a and the buried pad structure.

[0506] Figure 12J The solid-state imaging device 8j shown in FIG. Figure 12E The solid-state imaging device 8e shown in the figure is configured so that a non-buried lead pad structure using TSV dual-purpose lead openings 155a and 155b (i.e., TSV dual-purpose lead openings 155a and 155b and the pad 151 on the surface on the back side of the first substrate 110A) is provided by changing the buried TSV 157a into a non-buried TSV, instead of the TSV 157a and the buried pad structure.

[0507] Figure 12K The solid-state imaging device 8k shown in FIG. Figure 12I In the solid-state imaging device 8i shown in FIG, the non-buried type lead pad structure of the TSV dual-purpose lead openings 155a and 155b is changed to a buried type lead pad structure.

[0508] Figure 12L The solid-state imaging device 81 shown in FIG corresponds to Figure 12JIn the solid-state imaging device 8j shown in FIG, the non-buried lead pad structure of the TSV dual-purpose lead openings 155a and 155b is changed to a buried lead pad structure.

[0509] Note that in Figures 12A to 12L In each of the configurations shown in FIG, the type of wiring connected by the dual-contact TSV 157 between the two layers is not limited. TSV 157 can be connected to a predetermined wiring of the first metal wiring layer, or can be connected to a predetermined wiring of the second metal wiring layer. In addition, each of the multi-layer wiring layers 105, 125, and 135 can include only the first metal wiring layer, can include only the second metal wiring layer, or can include both of them to coexist.

[0510] In addition, Figures 12A to 12H In each of the configurations shown in , the substrate on which the pad 151 is provided is not limited to the illustrated example. In the seventh configuration example, the respective signal lines provided in the first substrate 110A and the second substrate 110B and the respective power supply lines provided in the first substrate 110A and the second substrate 110B are electrically connected to each other on one side through the TSV 157a. The respective signal lines provided in the second substrate 110B and the third substrate 110C and the respective power supply lines provided in the second substrate 110B and the third substrate 110C are electrically connected to each other on the other side through the electrode bonding structure 159 and the TSVs 157b and 157c. Therefore, the pad 151 as a connection structure may not be provided. Therefore, for example, in Figures 12A to 12H In each of the configurations shown in FIG, the pad 151 may be provided on any one of the substrates 110A, 110B, and 110C to obtain a desired signal.

[0511] In the case of providing a lead pad structure, the lead pad structure may be a non-buried type or a buried type. Figure 12G In the configuration shown in , a buried lead pad structure may be provided instead of a non-buried lead pad structure. Figure 12H In the illustrated configuration, a non-buried type lead pad structure may be provided instead of the buried type lead pad structure.

[0512] exist Figure 12A and 12C In each of the configurations shown in FIG. 12L , in the example shown, the TSV 157 b is in contact with a single-sided electrode, but the present embodiment is not limited to such an example. Figure 12B In the same manner as the configuration shown in , the TSV 157 b may be configured to contact the double-sided electrodes. In the case where the TSV 157 b is configured to contact the double-sided electrodes, the TSV 157 b serves as a via included in the electrode bonding structure 159 .

[0513] (4-8. Eighth Configuration Example)

[0514] Figures 13A to 13H are vertical cross-sectional views of schematic configurations of a solid-state imaging device according to an eighth configuration example of the present embodiment. The solid-state imaging device according to the present embodiment may have Figures 13A to 13H Each of the constructs shown in .

[0515] Figure 13A The solid-state imaging device 9a shown in the figure includes: a double-contact type and buried TSV 157a between two layers as a connection structure, a double-contact type and buried TSV 157b between three layers, an electrode bonding structure 159 arranged between the second substrate 110B and the third substrate 110C, and a buried pad structure for the first substrate 110A (i.e., a pad 151 arranged in the multi-layer wiring layer 105 of the first substrate 110A and a pad opening 153 exposing the pad 151).

[0516] The TSVs 157a are formed from the back side of the first substrate 110A toward the second substrate 110B and are provided to electrically connect the respective signal lines provided in the first substrate 110A and the second substrate 110B to each other and to electrically connect the respective power lines provided in the first substrate 110A and the second substrate 110B to each other. Figure 13A In the configuration shown in , predetermined wiring of the first metal wiring layer in the multilayer wiring layer 105 of the first substrate 110A and predetermined wiring of the second metal wiring layer in the multilayer wiring layer 125 of the second substrate 110B are electrically connected to each other through TSV 157a. In addition, TSV 157b is formed from the back side of the third substrate 110C toward the first substrate 110A, and is provided to electrically connect the respective signal lines provided in the first substrate 110A and the third substrate 110C to each other and to electrically connect the respective power supply lines provided in the first substrate 110A and the third substrate 110C to each other. Figure 13A In the configuration shown in FIG, predetermined wiring of the second metal wiring layer in the multilayer wiring layer 105 of the first substrate 110A and predetermined wiring of the first metal wiring layer in the multilayer wiring layer 135 of the third substrate 110C are electrically connected to each other via TSVs 157b. In addition, the respective signal lines provided in the second substrate 110B and the third substrate 110C and the respective power supply lines provided in the second substrate 110B and the third substrate 110C are electrically connected to each other via electrode bonding structures 159.

[0517] Figure 13B The solid-state imaging device 9b shown in FIG. Figure 13A The solid-state imaging device 9a shown in FIG. 1 is a device in which the type of wiring electrically connected by the TSV 157a is changed. Specifically, Figure 13BIn the illustrated configuration, predetermined wirings of the first metal wiring layer in the multilayer wiring layer 105 of the first substrate 110A and predetermined wirings of the first metal wiring layer in the multilayer wiring layer 125 of the second substrate 110B are electrically connected to each other through TSVs 157 a .

[0518] Figure 13C The solid-state imaging device 9c shown in FIG. Figure 13A The solid-state imaging device 9a shown in FIG. 1 has a different TSV 157b structure. Specifically, Figure 13C In the illustrated configuration, the TSVs 157b are formed from the back side of the third substrate 110C toward the first substrate 110A and are provided to electrically connect the respective signal lines provided in the first substrate 110A and the second substrate 110B to each other and to electrically connect the respective power lines provided in the first substrate 110A and the second substrate 110B to each other. Figure 13C In the configuration shown in , predetermined wirings of the first metal wiring layer in the multilayer wiring layer 105 of the first substrate 110A and predetermined wirings of the first metal wiring layer in the multilayer wiring layer 125 of the second substrate 110B are electrically connected to each other through the TSV 157 b .

[0519] Figure 13D The solid-state imaging device 9d shown in FIG. Figure 13C The solid-state imaging device 9c shown in FIG. 1 has a changed TSV 157b structure. Specifically, Figure 13D In the illustrated configuration, the TSVs 157b are formed from the back side of the third substrate 110C toward the first substrate 110A and are provided to electrically connect the respective signal lines provided in the first substrate 110A and the second substrate 110B to each other and to electrically connect the respective power lines provided in the first substrate 110A and the second substrate 110B to each other. Figure 13D In the configuration shown in , predetermined wiring of the first metal wiring layer in the multilayer wiring layer 105 of the first substrate 110A and a one-sided electrode in the insulating film 129 provided on the back surface side of the second substrate 110B are electrically connected to each other through the TSV 157b.

[0520] Figure 13E The solid-state imaging device 9e shown in FIG. Figure 13B The solid-state imaging device 9b shown in FIG. 1 is a device in which the buried pad structure is changed and the type of wiring electrically connected by the TSV 157b is changed. Specifically, in FIG. Figure 13E In the illustrated configuration, a non-buried lead pad structure for the second substrate 110B (i.e., lead openings 155 for predetermined wiring in the multilayer wiring layer 125 of the second substrate 110B and pads 151 on the surface on the back side of the first substrate 110A) is provided instead of a buried pad structure. Figure 13EIn the illustrated configuration, predetermined wirings of the first metal wiring layer in the multilayer wiring layer 105 of the first substrate 110A and predetermined wirings of the first metal wiring layer in the multilayer wiring layer 135 of the third substrate 110C are electrically connected to each other through TSVs 157 b .

[0521] Figure 13F The solid-state imaging device 9f shown in FIG. Figure 13E The solid-state imaging device 9e shown in FIG. 1 is a device in which the structure of the lead pad structure is changed. Specifically, Figure 13F In the structure shown, an embedded lead-out pad structure is provided for the third substrate 110C (i.e., a lead opening 155 for a predetermined wiring in the multi-layer wiring layer 135 of the third substrate 110C and a pad 151 formed by embedding in the insulating film 109 on the surface on the back side of the first substrate 110A), rather than a non-embedded lead-out pad structure for the second substrate 110B.

[0522] Figure 13G The solid-state imaging device 9g shown in FIG. Figure 13F The solid-state imaging device 9f shown in the figure is configured so that a non-buried lead pad structure using TSV dual-purpose lead openings 155a and 155b (i.e., TSV dual-purpose lead openings 155a and 155b and the pad 151 on the surface of the back side of the first substrate 110A) is provided by changing the buried TSV 157a into a non-buried TSV, instead of the TSV 157a and the buried lead pad structure.

[0523] Figure 13H The solid-state imaging device 9h shown in FIG. Figure 13G In the solid-state imaging device 9g shown in FIG, the non-buried lead pad structure of the TSV dual-purpose lead openings 155a and 155b is changed to a buried lead pad structure.

[0524] Note that in Figures 13A to 13H In each of the configurations shown in FIG, the type of wiring connected by the dual-contact TSVs 157 between two and three layers is not limited. These TSVs 157 can be connected to predetermined wirings of the first metal wiring layer, or can be connected to predetermined wirings of the second metal wiring layer. In addition, each of the multilayer wiring layers 105, 125, and 135 can include only the first metal wiring layer, can include only the second metal wiring layer, or can include both of them to coexist.

[0525] exist Figures 13A to 13FIn each of the configurations shown in , the substrate on which the pad 151 is provided is not limited to the illustrated example. In each of these configurations, the respective signal lines provided in the first substrate 110A and the second substrate 110B and the respective power lines provided in the first substrate 110A and the second substrate 110B are electrically connected to each other through TSV 157a. The respective signal lines provided in the second substrate 110B and the third substrate 110C and the respective power lines provided in the second substrate 110B and the third substrate 110C are electrically connected to each other through the electrode bonding structure 159. Therefore, the pad 151 as a connecting structure may not be provided. Therefore, for example, in each of the configurations shown in 13A to 13F, the pad 151 may be provided on any one of the substrates 110A, 110B, and 110C to obtain the desired signal.

[0526] In the case of providing a lead pad structure, the lead pad structure may be a non-buried type or a buried type. Figure 13E In the configuration shown in , a buried lead pad structure may be provided instead of a non-buried lead pad structure. Figure 13F In the illustrated configuration, a non-buried type lead pad structure may be provided instead of the buried type lead pad structure.

[0527] exist Figures 13A to 13H In each configuration shown in FIG, double contact type and buried type TSVs 157 between three layers are formed from the back side of the third substrate 110C toward the first substrate 110A, but the present embodiment is not limited to this example. TSVs 157 may be formed from the back side of the first substrate 110A toward the third substrate 110C.

[0528] Furthermore, it is sufficient that the dual-contact TSVs 157 between the three layers electrically connect the respective power supply lines and the respective signal lines provided in two of the first substrate 110A, the second substrate 110B, and the third substrate 110C to one another according to the direction in which the TSVs 157 are formed. The substrates provided with the respective signal lines and the respective power supply lines electrically connected to one another through the TSVs 157 may be optionally changed.

[0529] exist Figure 13D In the configuration shown in , in the example shown, TSV 157b is in contact with a single-sided electrode, but the present embodiment is not limited to such an example. In such a configuration, TSV 157b may be configured to be in contact with a double-sided electrode. In the case where TSV 157b is configured to be in contact with a double-sided electrode, TSV 157b functions as a via included in electrode bonding structure 159.

[0530] (4-9. Ninth Construction Example)

[0531] Figures 14A to 14Kare vertical cross-sectional views of schematic configurations of a solid-state imaging device according to a ninth configuration example of the present embodiment. The solid-state imaging device according to the present embodiment may have Figures 14A to 14K Each of the constructs shown in .

[0532] Figure 14A The solid-state imaging device 10a shown in FIG includes: a dual-contact type and buried TSV 157a between two layers as a connection structure, a shared contact type and buried TSV 157b, TSV 157c between the two layers, an electrode bonding structure provided between the second substrate 110B and the third substrate 110C, and a buried pad structure for the first substrate 110A (i.e., a pad 151 provided in the multi-layer wiring layer 105 of the first substrate 110A and a pad opening 153 exposing the pad 151).

[0533] TSVs 157a are formed from the back side of the first substrate 110A toward the second substrate 110B and are provided to electrically connect the respective signal lines provided in the first and second substrates 110A, 110B, and to electrically connect the respective power lines provided in the first and second substrates 110A, 110B. TSVs 157b and 157c are each formed from the front side of the second substrate 110B toward the third substrate 110C and are each provided to electrically connect the respective signal lines provided in the second and third substrates 110B, 110C, and to electrically connect the respective power lines provided in the second and third substrates 110B, 110C. Furthermore, the respective signal lines provided in the second and third substrates 110B, 110C, and the respective power lines provided in the second and third substrates 110B, 110C, are electrically connected to each other via electrode bonding structures 159.

[0534] Of the TSVs 157b and 157c, TSV 157b, one of the two TSVs, is provided to electrically connect a predetermined wiring of the second metal wiring layer in the multilayer wiring layer 125 of the second substrate 110B and a single-sided electrode in the multilayer wiring layer 135 of the third substrate 110C. Furthermore, TSV 157c, the other of the two TSVs, is provided to electrically connect a predetermined wiring of the second metal wiring layer in the multilayer wiring layer 125 of the second substrate 110B and a predetermined wiring of the second metal wiring layer in the multilayer wiring layer 135 of the third substrate 110C.

[0535] TSVs 157a are arranged so that one via contacts a predetermined wiring line of the first metal wiring layer in the multilayer wiring layer 105 of the first substrate 110A, and the other via contacts the upper end of TSV 157b. In other words, TSV 157a is formed to electrically connect the predetermined wiring line in the multilayer wiring layer 105 of the first substrate 110A to TSV 157b. Furthermore, the predetermined wiring line in the multilayer wiring layer 105 of the first substrate 110A, the predetermined wiring line in the multilayer wiring layer 125 of the second substrate 110B electrically connected by TSV 157b, and the single-sided electrode in the multilayer wiring layer 135 of the third substrate 110C are electrically connected together through TSV 157a.

[0536] Figure 14B The solid-state imaging device 10b shown in FIG. Figure 14A The solid-state imaging device 10a shown in FIG. 1 is a device in which the type of wiring electrically connected by TSVs 157b and 157c is changed. Specifically, in FIG. Figure 14B In the illustrated configuration, a predetermined wiring of the first metal wiring layer in the multilayer wiring layer 125 of the second substrate 110B and a single-sided electrode in the multilayer wiring layer 135 of the third substrate 110C are electrically connected to each other via TSVs 157b. Furthermore, a predetermined wiring of the first metal wiring layer in the multilayer wiring layer 125 of the second substrate 110B and a predetermined wiring of the first metal wiring layer in the multilayer wiring layer 135 of the third substrate 110C are electrically connected to each other via TSVs 157c.

[0537] Figure 14C The solid-state imaging device 10c shown in FIG. Figure 14A The solid-state imaging device 10a shown in FIG. 1 is a device in which the TSV 157a structure is changed. Specifically, in FIG. Figure 14A In the illustrated configuration, the TSV 157a is provided to electrically connect a predetermined wiring in the multi-layer wiring layer 105 of the first substrate 110A and the TSV 157b to each other. Figure 14C In the configuration shown in FIG, TSVs 157 a are provided to electrically connect predetermined wirings in the multilayer wiring layer 105 of the first substrate 110A and predetermined wirings in the multilayer wiring layer 125 of the second substrate 110B. Figure 14C In the configuration shown in , predetermined wirings of the first metal wiring layer in the multilayer wiring layer 105 of the first substrate 110A and predetermined wirings 110B of the second metal wiring layer in the multilayer wiring layer 125 of the second substrate are electrically connected to each other through TSVs 157a.

[0538] Figure 14D The solid-state imaging device 10d shown in FIG. Figure 14CThe solid-state imaging device 10c shown in FIG. 1 is a device in which the type of wiring electrically connected by TSVs 157a, 157b, and 157c is changed. Specifically, in FIG. Figure 14D In the illustrated configuration, a predetermined wiring line of the first metal wiring layer in the multilayer wiring layer 105 of the first substrate 110A and a predetermined wiring line of the first metal wiring layer in the multilayer wiring layer 125 of the second substrate 110B are electrically connected to each other via TSVs 157a. Furthermore, a predetermined wiring line of the first metal wiring layer in the multilayer wiring layer 125 of the second substrate 110B and a single-sided electrode in the multilayer wiring layer 135 of the third substrate 110C are electrically connected to each other via TSVs 157b. Furthermore, a predetermined wiring line of the first metal wiring layer in the multilayer wiring layer 125 of the second substrate 110B and a predetermined wiring line of the first metal wiring layer in the multilayer wiring layer 135 of the third substrate 110C are electrically connected to each other via TSVs 157c.

[0539] Figure 14E The solid-state imaging device 10e shown in FIG. Figure 14D The solid-state imaging device 10d shown in FIG. 1 is a device in which the configurations of the TSVs 157b and 157c are changed. Specifically, Figure 14E In the illustrated configuration, the TSV 157b is formed from the back side of the third substrate 110C toward the second substrate 110B and is provided to electrically connect the respective signal lines provided in the second substrate 110B and the third substrate 110C to each other and to electrically connect the respective power lines provided in the second substrate 110B and the third substrate 110C to each other. Figure 14E In the configuration shown in , the single-sided electrode provided in the insulating film 129 on the back surface side of the second substrate 110B and the predetermined wiring of the first metal wiring layer in the multilayer wiring layer 135 of the third substrate 110C are electrically connected to each other through the TSV 157b. Figure 14E In the illustrated configuration, the TSV 157c is formed from the back side of the third substrate 110C toward the second substrate 110B and is provided to electrically connect the respective signal lines provided in the second substrate 110B and the third substrate 110C to each other and to electrically connect the respective power lines provided in the second substrate 110B and the third substrate 110C to each other. Figure 14E In the configuration shown in , predetermined wirings of the first metal wiring layer in the multilayer wiring layer 125 of the second substrate 110B and predetermined wirings of the first metal wiring layer in the multilayer wiring layer 135 of the third substrate 110C are electrically connected to each other through the TSV 157 c.

[0540] Figure 14F The solid-state imaging device 10f shown in FIG. Figure 14B The solid-state imaging device 10b shown in FIG. 1 has a modified buried pad structure. Specifically, Figure 14FIn the structure shown, a non-buried lead pad structure for the second substrate 110B (i.e., a lead opening 155 for a predetermined wiring in the multilayer wiring layer 125 of the second substrate 110B and a pad 151 on the surface on the back side of the first substrate 110A) is provided instead of a buried pad structure.

[0541] Figure 14G The solid-state imaging device 10g shown in FIG. Figure 14F The solid-state imaging device 10f shown in FIG. 1 is a device in which the structure of the lead-out pad structure is changed. Specifically, Figure 14G In the structure shown, an embedded lead-out pad structure is provided for the third substrate 110C (i.e., a lead opening 155 for a predetermined wiring in the multi-layer wiring layer 135 of the third substrate 110C and a pad 151 formed by embedding in the insulating film 109 on the surface on the back side of the first substrate 110A), rather than a non-embedded lead-out pad structure for the second substrate 110B.

[0542] Figure 14H The solid-state imaging device 10h shown in FIG. Figure 14B The solid-state imaging device 10b shown in the figure, in which a non-buried lead pad structure using TSV dual-purpose lead openings 155a and 155b (i.e., TSV dual-purpose lead openings 155a and 155b and the pad 151 on the surface on the back side of the first substrate 110A) is set by changing the buried TSV 157a into a non-buried TSV, instead of the TSV 157a and the buried pad structure.

[0543] Figure 14I The solid-state imaging device 10i shown in FIG corresponds to Figure 14D , a solid-state imaging device 10d is shown in the figure, wherein a non-buried lead pad structure using TSV dual-purpose lead openings 155a and 155b (i.e., TSV dual-purpose lead openings 155a and 155b and the pad 151 on the surface on the back side of the first substrate 110A) is provided by changing the buried TSV 157a into a non-buried TSV, instead of the TSV 157a and the buried pad structure.

[0544] Figure 14J The solid-state imaging device 10j shown in FIG. Figure 14H In the solid-state imaging device 10h shown in FIG, the non-buried lead pad structure of the TSV dual-purpose lead openings 155a and 155b is changed to a buried lead pad structure.

[0545] Figure 14K The solid-state imaging device 10k shown in FIG. Figure 14IIn the solid-state imaging device 10i shown in FIG, the non-buried lead pad structure of the TSV dual-purpose lead openings 155a and 155b is changed to a buried lead pad structure.

[0546] Note that in Figures 14A to 14K In each of the configurations shown in FIG, the types of wiring connected by the dual-contact TSVs 157 between the two layers and the shared-contact TSVs 157 between the two layers are not limited. These TSVs 157 can each be connected to a predetermined wiring of the first metal wiring layer, or can be connected to a predetermined wiring of the second metal wiring layer. In addition, each of the multi-layer wiring layers 105, 125, and 135 can include only the first metal wiring layer, can include only the second metal wiring layer, or can include both of them so as to coexist.

[0547] exist Figures 14A to 14G In each of the configurations shown in , the substrate on which the pad 151 is provided is not limited to the example shown. In the ninth configuration example, the respective signal lines provided in the first substrate 110A and the second substrate 110B and the respective power supply lines provided in the first substrate 110A and the second substrate 110B are electrically connected to each other through TSV 157a. The respective signal lines provided in the second substrate 110B and the third substrate 110C and the respective power supply lines provided in the second substrate 110B and the third substrate 110C are electrically connected to each other through TSV 157b and 157c. Therefore, the pad 151 as a connection structure may not be provided. Therefore, for example, in Figures 14A to 14G In each of the configurations shown in FIG, the pad 151 may be provided on any one of the substrates 110A, 110B, and 110C to obtain a desired signal.

[0548] In the case of providing a lead pad structure, the lead pad structure may be a non-buried type or a buried type. Figure 14F In the configuration shown in , a buried lead pad structure may be provided instead of a non-buried lead pad structure. Figure 14G In the illustrated configuration, a non-buried type lead pad structure may be provided instead of the buried type lead pad structure.

[0549] exist Figures 14A to 14K In each of the configurations shown in , in the example shown, TSV 157b is in contact with a single-sided electrode, but the present embodiment is not limited to such an example. In each of these configurations, TSV 157b may be configured to be in contact with a double-sided electrode. In the case where TSV 157b is configured to be in contact with a double-sided electrode, TSV 157b functions as a via included in electrode bonding structure 159.

[0550] (4-10. Tenth structural example)

[0551] Figures 15A to 15G are vertical cross-sectional views of schematic configurations of a solid-state imaging device according to a tenth configuration example of the present embodiment. The solid-state imaging device according to the present embodiment may have Figures 15A to 15G Each of the constructs shown in .

[0552] Figure 15A The solid-state imaging device 11a shown in the figure includes: a double-contact type and buried TSV 157a between two layers as a connection structure, a common contact type and buried TSV 157b between three layers, an electrode bonding structure 159 arranged between the second substrate 110B and the third substrate 110C, and a buried pad structure for the first substrate 110A (i.e., a pad 151 arranged in the multi-layer wiring layer 105 of the first substrate 110A and a pad opening 153 exposing the pad 151).

[0553] The TSVs 157a are formed from the back side of the first substrate 110A toward the second substrate 110B and are provided to electrically connect the respective signal lines provided in the first substrate 110A and the second substrate 110B to each other and to electrically connect the respective power lines provided in the first substrate 110A and the second substrate 110B to each other. Figure 15A In the configuration shown in , predetermined wiring of the first metal wiring layer in the multilayer wiring layer 105 of the first substrate 110A and predetermined wiring of the second metal wiring layer in the multilayer wiring layer 125 of the second substrate 110B are electrically connected to each other through TSV 157a. In addition, TSV 157b is formed from the back side of the third substrate 110C toward the first substrate 110A, and is provided to electrically connect the respective signal lines provided in the first substrate 110A and the third substrate 110C to each other and to electrically connect the respective power supply lines provided in the first substrate 110A and the third substrate 110C to each other. Figure 10A In the configuration shown in FIG, predetermined wiring of the second metal wiring layer in the multilayer wiring layer 105 of the first substrate 110A and predetermined wiring of the first metal wiring layer in the multilayer wiring layer 135 of the third substrate 110C are electrically connected to each other via TSVs 157b. In addition, the respective signal lines provided in the second substrate 110B and the third substrate 110C and the respective power supply lines provided in the second substrate 110B and the third substrate 110C are electrically connected to each other via electrode bonding structures 159.

[0554] Figure 15B The solid-state imaging device 11b shown in FIG corresponds to Figure 15A The solid-state imaging device 11a shown in FIG. 1 is a device in which the type of wiring electrically connected by the TSV 157a is changed. Specifically, Figure 15BIn the illustrated configuration, predetermined wirings of the first metal wiring layer in the multilayer wiring layer 105 of the first substrate 110A and predetermined wirings of the first metal wiring layer in the multilayer wiring layer 125 of the second substrate 110B are electrically connected to each other through TSVs 157 a .

[0555] Figure 15C The solid-state imaging device 11c shown in the figure includes: a double-contact type and buried TSV 157a between two layers as a connection structure, a shared contact type and buried TSV 157b between three layers, an electrode bonding structure 159 arranged between the second substrate 110B and the third substrate 110C, and a buried pad structure for the second substrate 110B (i.e., a pad 151 arranged in the multi-layer wiring layer 125 of the second substrate 110B and a pad opening 153 exposing the pad 151).

[0556] The TSVs 157a are formed from the back side of the first substrate 110A toward the second substrate 110B and are provided to electrically connect the respective signal lines provided in the first substrate 110A and the second substrate 110B to each other and to electrically connect the respective power lines provided in the first substrate 110A and the second substrate 110B to each other. Figure 15C In the configuration shown in , predetermined wiring of the first metal wiring layer in the multilayer wiring layer 105 of the first substrate 110A and predetermined wiring of the second metal wiring layer in the multilayer wiring layer 125 of the second substrate 110B are electrically connected to each other through TSV 157a. In addition, TSV 157b is formed from the back side of the third substrate 110C toward the first substrate 110A, and is provided to electrically connect the respective signal lines provided in the first substrate 110A, the second substrate 110B, and the third substrate 110C together and to electrically connect the respective power supply lines included in the first substrate 110A, the second substrate 110B, and the third substrate 110C together. Figure 15C In the configuration shown in FIG, predetermined wiring lines of the first metal wiring layer in the multilayer wiring layer 105 of the first substrate 110A, predetermined wiring lines of the first metal wiring layer in the multilayer wiring layer 125 of the second substrate 110B, and predetermined wiring lines of the first metal wiring layer in the multilayer wiring layer 135 of the third substrate 110C are electrically connected together by TSVs 157b. In addition, the respective signal lines provided in the second substrate 110B and the third substrate 110C, as well as the respective power supply lines provided in the second substrate 110B and the third substrate 110C, are electrically connected to each other via electrode bonding structures 159.

[0557] Figure 15D The solid-state imaging device 11d shown in FIG. Figure 15B The solid-state imaging device 11b shown in FIG. 1 has a changed buried pad structure and a changed type of wiring electrically connected by TSV 157b. Specifically, in FIG. Figure 15D In the illustrated configuration, a non-buried lead pad structure for the second substrate 110B (i.e., lead openings 155 for predetermined wiring in the multilayer wiring layer 125 of the second substrate 110B and pads 151 on the surface on the back side of the first substrate 110A) is provided instead of a buried pad structure. Figure 15D In the illustrated configuration, predetermined wirings of the first metal wiring layer in the multilayer wiring layer 105 of the first substrate 110A and predetermined wirings of the first metal wiring layer in the multilayer wiring layer 135 of the third substrate 110C are electrically connected to each other through TSVs 157 b .

[0558] Figure 15E The solid-state imaging device 11e shown in FIG. Figure 15D The solid-state imaging device 11d shown in FIG. 1 is a device in which the structure of the lead pad structure is changed. Specifically, in FIG. Figure 15E In the structure shown, an embedded lead-out pad structure is provided for the third substrate 110C (i.e., a lead opening 155 for a predetermined wiring in the multi-layer wiring layer 135 of the third substrate 110C and a pad 151 formed by embedding in the insulating film 109 on the surface on the back side of the first substrate 110A), rather than a non-embedded lead-out pad structure for the second substrate 110B.

[0559] Figure 15F The solid-state imaging device 11f shown in FIG corresponds to Figure 15E The solid-state imaging device 11e shown in the figure is configured so that a non-buried lead pad structure using TSV dual-purpose lead openings 155a and 155b (i.e., TSV dual-purpose lead openings 155a and 155b and the pad 151 on the surface of the back side of the first substrate 110A) is provided by changing the buried TSV 157a into a non-buried TSV, instead of the TSV 157a and the buried lead pad structure.

[0560] Figure 15G The solid-state imaging device 11g shown in FIG. Figure 15F In the solid-state imaging device 11f shown in FIG, the non-buried lead pad structure of the TSV dual-purpose lead openings 155a and 155b is changed to a buried lead pad structure.

[0561] Note that in Figures 15A to 15GIn each of the configurations shown in FIG, the types of wiring connected by the dual-contact TSVs 157 between two layers and the shared-contact TSVs 157 between three layers are not limited. These TSVs 157 can each be connected to a predetermined wiring of the first metal wiring layer, or can be connected to a predetermined wiring of the second metal wiring layer. In addition, each of the multilayer wiring layers 105, 125, and 135 can include only the first metal wiring layer, can include only the second metal wiring layer, or can include both of them so as to coexist.

[0562] exist Figures 15A to 15E In each of the configurations shown in , the substrate on which the pad 151 is provided is not limited to the illustrated example. In each of these configurations, the respective signal lines provided in the first substrate 110A and the second substrate 110B and the respective power supply lines provided in the first substrate 110A and the second substrate 110B are electrically connected to each other through one TSV 157a. The respective signal lines provided in the first substrate 110A and the third substrate 110C and the respective power supply lines provided in the first substrate 110A and the third substrate 110C are electrically connected to each other through another TSV 157b. The respective signal lines provided in the second substrate 110B and the third substrate 110C and the respective power supply lines provided in the second substrate 110B and the third substrate 110C are electrically connected to each other through the electrode bonding structure 159. Therefore, the pad 151 as a connection structure may not be provided. Therefore, for example, in Figures 15A to 15E In each of the configurations shown in FIG, the pad 151 may be provided on any one of the substrates 110A, 110B, and 110C to obtain a desired signal.

[0563] In the case of providing a lead pad structure, the lead pad structure may be a non-buried type or a buried type. Figure 15D In the configuration shown in , a buried lead pad structure may be provided instead of a non-buried lead pad structure. Figure 15E In the illustrated configuration, a non-buried lead pad structure may be provided instead of the buried lead pad structure.

[0564] exist Figures 15A to 15G In each configuration shown in FIG, shared contact type and buried type TSVs 157 between the three layers are formed from the back side of the third substrate 110C toward the first substrate 110A, but the present embodiment is not limited to this example. TSVs 157 may be formed from the back side of the first substrate 110A toward the third substrate 110C.

[0565] In addition, it is sufficient that the common contact type TSV 157 between the three layers electrically connects the signal lines and the power supply lines included in at least two of the first substrate 110A, the second substrate 110B, or the third substrate 110C. The substrates provided with the signal lines and the power supply lines electrically connected to each other through the TSV 157 may be optionally changed.

[0566] (4-11. Eleventh Construction Example)

[0567] Figures 16A to 16G 16A to 16G are vertical cross-sectional views of schematic configurations of a solid-state imaging device according to an eleventh configuration example of the present embodiment. The solid-state imaging device according to the present embodiment can have each configuration shown in FIG.

[0568] Figure 16A The solid-state imaging device 12a shown in includes: a double-contact type and buried type TSV 157 between three layers as a connection structure, a buried pad structure for the first substrate 110A (i.e., a pad 151 provided in the multi-layer wiring layer 105 of the first substrate 110A and a pad opening 153a exposing the pad 151), and a buried pad structure for the second substrate 110B (i.e., a pad 151 provided in the multi-layer wiring layer 125 of the second substrate 110B and a pad opening 153b exposing the pad 151). The TSV 157 is formed from the back side of the first substrate 110A toward the third substrate 110C, and is provided to electrically connect the respective signal lines provided in the first substrate 110A and the third substrate 110C to each other and to electrically connect the respective power supply lines provided in the first substrate 110A and the third substrate 110C to each other. In Figure 16A In the illustrated configuration, predetermined wirings of the first metal wiring layer in the multilayer wiring layer 105 of the first substrate 110A and predetermined wirings of the first metal wiring layer in the multilayer wiring layer 135 of the third substrate 110C are electrically connected to each other via TSVs 157. In addition, the respective signal lines provided in the first substrate 110A and the second substrate 110B and the respective power supply lines provided in the first substrate 110A and the second substrate 110B can be electrically connected to each other via two buried pad structures.

[0569] Figure 16B The solid-state imaging device 12b shown in FIG corresponds to Figure 16A The solid-state imaging device 12a shown in FIG. 1 is a device in which the TSV 157 structure is changed. Specifically, Figure 16B In the illustrated configuration, the TSV 157 is formed from the back side of the third substrate 110C toward the first substrate 110A, and is provided to electrically connect the respective signal lines provided in the first substrate 110A and the third substrate 110C to each other and to connect the respective power lines provided in the first substrate 110A and the third substrate 110C to each other. Figure 16B In the illustrated configuration, predetermined wirings of the second metal wiring layer in the multilayer wiring layer 105 of the first substrate 110A and predetermined wirings of the first metal wiring layer in the multilayer wiring layer 135 of the third substrate 110C are electrically connected to each other through TSVs 157 .

[0570] Figure 16C The solid-state imaging device 12c shown in FIG corresponds to Figure 16A The solid-state imaging device 12a shown in FIG. 1 is a device in which the TSV 157 structure is changed. Specifically, Figure 16C In the illustrated configuration, the TSV 157 is formed from the back side of the first substrate 110A toward the third substrate 110C and is provided to electrically connect the respective signal lines provided in the second substrate 110B and the third substrate 110C to each other and to electrically connect the respective power lines provided in the second substrate 110B and the third substrate 110C to each other. Figure 16C In the illustrated configuration, predetermined wirings of the second metal wiring layer in the multilayer wiring layer 125 of the second substrate 110B and predetermined wirings of the first metal wiring layer in the multilayer wiring layer 135 of the third substrate 110C are electrically connected to each other through TSVs 157 .

[0571] Figure 16D The solid-state imaging device 12d shown in FIG corresponds to Figure 16A The solid-state imaging device 12a shown in FIG. 1 has a modified buried pad structure. Specifically, Figure 16D In the illustrated configuration, a non-buried type pad structure for the first substrate 110A (i.e., a lead opening 155a for a predetermined wiring in the multilayer wiring layer 105 of the first substrate 110A and a pad 151 on the surface of the back side of the first substrate 110A) and a non-buried type lead pad structure for the second substrate 110B (i.e., a lead opening 155b for a predetermined wiring in the multilayer wiring layer 125 of the second substrate 110B and a pad 151 on the surface of the back side of the first substrate 110A) are provided instead of a buried pad structure. Note that in Figure 16D In the illustrated configuration, lead openings 155 a and 155 b share a common pad 151 .

[0572] Figure 16E The solid-state imaging device 12e shown in FIG corresponds to Figure 16D The solid-state imaging device 12d shown in FIG. 1 is a device in which the structure of the lead-out pad structure is changed. Specifically, Figure 16EIn the illustrated configuration, an embedded lead pad structure for the second substrate 110B (i.e., lead openings 155a for predetermined wiring in the multilayer wiring layer 125 of the second substrate 110B and pads 151 formed by embedding in the insulating film 109 on the surface on the back side of the first substrate 110A) and an embedded lead pad structure for the third substrate 110C (i.e., lead openings 155b for predetermined wiring in the multilayer wiring layer 135 of the third substrate 110C and pads 151 formed by embedding in the insulating film 109 on the surface on the back side of the first substrate 110A) are provided, instead of a non-embedded lead pad structure for the first substrate 110A and a non-embedded lead pad structure for the second substrate 110B. Note that in Figure 16E In the illustrated configuration, lead openings 155 a and 155 b share a common pad 151 .

[0573] Figure 16F The solid-state imaging device 12f shown in FIG corresponds to Figure 16E The solid-state imaging device 12e shown in FIG, wherein, instead of the TSV 157 and the lead pad structure for the second substrate 110B and the third substrate 110C, a non-buried type lead pad structure using TSV dual-purpose lead openings 155a and 155b and a lead opening 155c for predetermined wiring in the multi-layer wiring layer 125 of the second substrate 110B is provided (i.e., TSV dual-purpose lead openings 155a and 155b, lead opening 155c, and pads 151 provided on the surface on the back side of the first substrate 110A) is provided by changing the buried type TSV 157 to a non-buried type TSV and by providing TSV dual-purpose lead openings 155a and 155b and a lead opening 155c for predetermined wiring in the multi-layer wiring layer 125 of the second substrate 110B. Note that in Figure 16F In the illustrated configuration, the TSV dual-purpose lead openings 155 a and 155 b and the lead opening 155 c share one pad 151 .

[0574] Figure 16G The solid-state imaging device 12g shown in FIG corresponds to Figure 16F The solid-state imaging device 12f shown in FIG. 1 is provided with a buried lead pad structure instead of a non-buried lead pad structure. Figure 16G In the illustrated configuration, the TSV dual-purpose lead openings 155 a and 155 b and the lead opening 155 c share one pad 151 .

[0575] Note that in Figures 16A to 16GIn each of the configurations shown in FIG, the type of wiring connected by the dual-contact TSV 157 between the three layers is not limited. TSV 157 can be connected to a predetermined wiring of the first metal wiring layer, or can be connected to a predetermined wiring of the second metal wiring layer. In addition, each of the multilayer wiring layers 105, 125, and 135 can include only the first metal wiring layer, can include only the second metal wiring layer, or can include both of them to coexist.

[0576] exist 16A to 16D In each of the configurations shown in , in the example shown, a pad 151 is provided on each of the first substrate 110A and the second substrate 110B, but the present embodiment is not limited to such an example. In each of these configurations, the respective signal lines provided in the first substrate 110A and the third substrate 110C and the respective power supply lines provided in the first substrate 110A and the third substrate 110C are electrically connected to each other through TSVs 157. Therefore, the first substrate 110A and the second substrate 110B or the second substrate 110B and the third substrate 110C, which are respectively provided with respective signal lines and respective power supply lines that are not electrically connected to each other through TSVs 157, may be respectively provided with pads 151 for electrically connecting the respective signal lines and the respective power supply lines to each other. That is, in 16A to 16D In each of the configurations shown, the pads 151 may be provided on each of the second substrate 110B and the third substrate 110C, instead of the illustrated configuration example of the pads 151. Figure 16E In the configuration shown in , in the illustrated example, the pads 151 are provided on each of the second substrate 110B and the third substrate 110C, but the pads 151 may be provided on each of the first substrate 110A and the second substrate 110B instead.

[0577] exist Figure 16D and Figure 16E In each of the illustrated configurations, in the illustrated example, the lead openings 155a and 155b share a single pad 151, but the present embodiment is not limited to such an example. In each of these configurations, one pad 151 may be provided for each of the two lead openings 155a and 155b. In this case, the film comprising the conductive material contained in the two lead openings 155a and 155b may extend on the surface of the back side of the first substrate 110A and be isolated from each other (i.e., so that the two are not conductive).

[0578] exist Figure 16F and Figure 16GIn each of the illustrated configurations, in the example shown, the TSV dual-purpose lead openings 155a and 155b and the lead opening 155c share a single pad 151, but the present embodiment is not limited to such an example. In each of these configurations, one pad 151 may be provided for each of the TSV dual-purpose lead openings 155a and 155b (i.e., for the TSV 157) and the lead opening 155c. In this case, the film including the conductive material contained in the TSV dual-purpose lead openings 155a and 155b and the film including the conductive material contained in the lead opening 155c may extend on the surface of the back side of the first substrate 110A and be isolated from each other (i.e., both are non-conductive).

[0579] In addition, in the case where a lead pad structure is provided, the lead pad structure may be a non-buried type or a buried type. Figure 16D In the configuration shown, a buried lead pad structure may be provided instead of a non-buried lead pad structure. Figure 16E In the illustrated configuration, a non-buried type lead pad structure may be provided instead of the buried type lead pad structure.

[0580] In addition, it is sufficient that the double-contact type TSVs 157 between the three layers electrically connect the respective signal lines and the respective power supply lines provided in two of the first substrate 110A, the second substrate 110B, and the third substrate 110C to one another according to the direction in which the TSVs 157 are formed. The substrates provided with the respective signal lines and the respective power supply lines electrically connected to one another through the TSVs 157 may be optionally changed.

[0581] (4-12. Twelfth structural example)

[0582] Figures 17A to 17J are vertical cross-sectional views of schematic configurations of a solid-state imaging device according to a twelfth configuration example of the present embodiment. The solid-state imaging device according to the present embodiment may have Figures 17A to 17J Each construction shown.

[0583] Figure 17A The solid-state imaging device 13a shown in the figure includes: double-contact and buried TSV 157a between three layers as a connection structure, double-contact and buried TSV 157b between two layers, and a buried pad structure for the first substrate 110A (i.e., a pad 151 provided in the multi-layer wiring layer 105 of the first substrate 110A and a pad opening 153 exposing the pad 151).

[0584] The TSVs 157a are formed from the back side of the first substrate 110A toward the third substrate 110C and are provided to electrically connect the respective signal lines provided in the first substrate 110A and the third substrate 110C to each other and to electrically connect the respective power lines provided in the first substrate 110A and the third substrate 110C to each other. Figure 17A In the configuration shown in , predetermined wiring of the first metal wiring layer in the multilayer wiring layer 105 of the first substrate 110A and predetermined wiring of the second metal wiring layer in the multilayer wiring layer 135 of the third substrate 110C are electrically connected to each other through TSV 157a. In addition, TSV 157b is formed from the front side of the second substrate 110B toward the third substrate 110C, and is provided to electrically connect the respective signal lines provided in the second substrate 110B and the third substrate 110C to each other and to electrically connect the respective power supply lines provided in the second substrate 110B and the third substrate 110C to each other. Figure 17A In the configuration shown in , predetermined wirings of the second metal wiring layer in the multilayer wiring layer 125 of the second substrate 110B and predetermined wirings of the second metal wiring layer in the multilayer wiring layer 135 of the third substrate 110C are electrically connected to each other through TSVs 157b.

[0585] Figure 17B The solid-state imaging device 13b shown corresponds to Figure 17A The solid-state imaging device 13a shown in FIG. 1 is a device in which the type of wiring electrically connected by TSVs 157a and 157b is changed. Specifically, Figure 17B In the configuration shown in , predetermined wirings of the first metal wiring layer in the multilayer wiring layer 105 of the first substrate 110A and predetermined wirings of the first metal wiring layer in the multilayer wiring layer 135 of the third substrate 110C are electrically connected to each other through TSVs 157a. Figure 17B In the configuration shown in , predetermined wirings of the first metal wiring layer in the multilayer wiring layer 125 of the second substrate 110B and predetermined wirings of the first metal wiring layer in the multilayer wiring layer 135 of the third substrate 110C are electrically connected to each other through TSVs 157b.

[0586] Figure 17C The solid-state imaging device 13c shown includes: dual-contact and buried TSVs 157a between three layers as a connection structure, dual-contact and buried TSVs 157b between two layers, a buried pad structure for the first substrate 110A (i.e., a pad 151 provided in the multi-layer wiring layer 105 of the first substrate 110A and a pad opening 153a exposing the pad 151), and a buried pad structure for the second substrate 110B (i.e., a pad 151 provided in the multi-layer wiring layer 125 of the second substrate 110B and a pad opening 153b exposing the pad 151).

[0587] The TSVs 157a are formed from the back side of the first substrate 110A toward the third substrate 110C and are provided to electrically connect the respective signal lines provided in the second substrate 110B and the third substrate 110C to each other and to electrically connect the respective power lines provided in the second substrate 110B and the third substrate 110C to each other. Figure 17C In the configuration shown in , predetermined wiring of the second metal wiring layer in the multilayer wiring layer 125 of the second substrate 110B and predetermined wiring of the first metal wiring layer in the multilayer wiring layer 135 of the third substrate 110C are electrically connected to each other through TSV 157a. In addition, TSV 157b is formed from the front side of the second substrate 110B toward the third substrate 110C, and is provided to electrically connect the respective signal lines provided in the second substrate 110B and the third substrate 110C to each other and to electrically connect the respective power supply lines provided in the second substrate 110B and the third substrate 110C to each other. Figure 17C In the configuration shown in FIG, predetermined wiring of the second metal wiring layer in the multilayer wiring layer 125 of the second substrate 110B and predetermined wiring of the first metal wiring layer in the multilayer wiring layer 135 of the third substrate 110C are electrically connected to each other via TSVs 157b. In addition, the respective signal lines provided in the first substrate 110A and the second substrate 110B and the respective power supply lines provided in the first substrate 110A and the second substrate 110B are electrically connected to each other via two buried pad structures.

[0588] Figure 17D The solid-state imaging device 13d shown in FIG corresponds to Figure 17B The solid-state imaging device 13b shown in FIG. 1 is a device in which the structure of the TSV 157b is changed. Specifically, Figure 17D In the configuration shown in , TSV 157b is formed from the back side of the third substrate 110C toward the second substrate 110B, and is provided to electrically connect the respective signal lines provided in the second substrate 110B and the third substrate 110C to each other and to electrically connect the respective power lines provided in the second substrate 110B and the third substrate 110C to each other. Figure 17D In the configuration shown in , predetermined wirings of the first metal wiring layer in the multilayer wiring layer 125 of the second substrate 110B and predetermined wirings of the first metal wiring layer in the multilayer wiring layer 135 of the third substrate 110C are electrically connected to each other through TSVs 157b.

[0589] Figure 17E The solid-state imaging device 13e shown in FIG corresponds to Figure 17B The solid-state imaging device 13b shown in FIG. 1 has a modified buried pad structure. Specifically, Figure 17EIn the configuration shown in , a non-buried lead pad structure for the second substrate 110B (i.e., a lead opening 155 for a predetermined wiring in the multilayer wiring layer 125 of the second substrate 110B and a pad 151 on the surface on the back side of the first substrate 110A) is provided instead of a buried pad structure.

[0590] Figure 17F The solid-state imaging device 13f shown in FIG corresponds to Figure 17E The solid-state imaging device 13e shown in FIG. 1 has a different structure of the lead pad. Specifically, Figure 17F In the structure shown, an embedded lead-out pad structure is provided for the third substrate 110C (i.e., a lead opening 155 for a predetermined wiring in the multi-layer wiring layer 135 of the third substrate 110C and a pad 151 formed by embedding in the insulating film 109 on the surface on the back side of the first substrate 110A), rather than a non-embedded lead-out pad structure for the second substrate 110B.

[0591] Figure 17G The solid-state imaging device 13g shown corresponds to Figure 17B The solid-state imaging device 13b shown in the figure is configured such that a non-buried lead pad structure using TSV dual-purpose lead openings 155a and 155b (i.e., TSV dual-purpose lead openings 155a and 155b and the pad 151 on the surface on the back side of the first substrate 110A) is provided by changing the buried TSV 157a into a non-buried TSV, instead of the TSV 157a and the buried pad structure.

[0592] Figure 17H The solid-state imaging device 13h shown in FIG corresponds to Figure ...

Claims

1. A solid-state imaging device, comprising: A first substrate, the first substrate comprising a first semiconductor substrate and a first multi-layer wiring layer stacked on the first semiconductor substrate, a pixel unit is formed on the first semiconductor substrate, and pixels are arranged on the pixel unit; a second substrate including a second semiconductor substrate and a second multi-layer wiring layer stacked on the second semiconductor substrate, a circuit having a predetermined function being formed on the second semiconductor substrate; and a third substrate including a third semiconductor substrate and a third multi-layer wiring layer stacked on the third semiconductor substrate, a circuit having a predetermined function being formed on the third semiconductor substrate, The first substrate, the second substrate and the third substrate are stacked in sequence, The first substrate and the second substrate are bonded together in such a manner that the first multilayer wiring layer and the second multilayer wiring layer face each other, The solid-state imaging device includes a first connection structure for electrically connecting two of the first substrate, the second substrate, and the third substrate to each other, the first connection structure including a via hole, The via has a structure in which a conductive material is buried in one through hole and another through hole, or has a structure in which a film made of a conductive material is formed on the inner wall of the through hole, the one through hole is configured to expose a first wiring included in one of the first multilayer wiring layer, the second multilayer wiring layer, and the third multilayer wiring layer, and the other through hole is configured to expose a second wiring included in one of the first multilayer wiring layer, the second multilayer wiring layer, and the third multilayer wiring layer except the multilayer wiring layer containing the first wiring.

2. The solid-state imaging device according to claim 1, further comprising a second connection structure for electrically connecting the second substrate and the third substrate to each other, wherein The second connection structure includes: a first opening set by at least passing through the first substrate from the back side of the first substrate to expose predetermined wiring in the second multi-layer wiring layer, and a second opening set by at least passing through the first substrate and the second substrate from the back side of the first substrate to expose predetermined wiring in the third multi-layer wiring layer.

3. The solid-state imaging device according to claim 2, wherein: The predetermined wiring in the second multi-layer wiring layer exposed through the first opening and the predetermined wiring in the third multi-layer wiring layer exposed through the second opening include pads functioning as I / O cells.

4. The solid-state imaging device according to claim 2, wherein A pad serving as an I / O unit is present on the surface of the back side of the first substrate, A film made of a conductive material is formed on inner walls of the first opening and the second opening, and The predetermined wiring in the second multi-layer wiring layer exposed through the first opening and the predetermined wiring in the third multi-layer wiring layer exposed through the second opening are electrically connected to the pad through the conductive material.

5. The solid-state imaging device according to claim 4, wherein The predetermined wiring in the second multi-layer wiring layer and the predetermined wiring in the third multi-layer wiring layer are electrically connected to the same pad through the conductive material.

6. The solid-state imaging device according to claim 4, wherein The predetermined wiring in the second multi-layer wiring layer and the predetermined wiring in the third multi-layer wiring layer are electrically connected to the pads different from each other through the conductive material.

7. The solid-state imaging device according to claim 1, further comprising a second connection structure for electrically connecting the second substrate and the third substrate to each other, wherein The second substrate and the third substrate are bonded together in such a manner that the second semiconductor substrate and the third multi-layer wiring layer face each other, and The second connection structure includes a via hole set by at least passing through the second substrate from the front side of the second substrate, and the via hole electrically connects the predetermined wiring in the second multi-layer wiring layer with the predetermined wiring in the third multi-layer wiring layer, or includes a via hole set by at least passing through the third substrate from the back side of the third substrate, and the via hole electrically connects the predetermined wiring in the second multi-layer wiring layer with the predetermined wiring in the third multi-layer wiring layer.

8. The solid-state imaging device according to claim 7, wherein The via hole of the second connection structure has a structure in which a conductive material is embedded in a third through hole that exposes the predetermined wiring in the second multilayer wiring layer and in a fourth through hole that exposes the predetermined wiring in the third multilayer wiring layer and is different from the third through hole; or, the via hole of the second connection structure has a structure in which a film made of a conductive material is formed on the inner walls of the third through hole and the fourth through hole.

9. The solid-state imaging device according to claim 7, wherein: The via of the second connection structure has a structure in which a conductive material is embedded in a through hole configured to expose a portion of the predetermined wiring in the second multilayer wiring layer and the predetermined wiring in the third multilayer wiring layer, or is embedded in a through hole configured to expose a portion of the predetermined wiring in the third multilayer wiring layer and the predetermined wiring in the second multilayer wiring layer; or, the via of the second connection structure has a structure in which a film made of a conductive material is formed on the inner wall of the through hole.

10. An electronic device comprising a solid-state imaging device for electronically photographing an observation object, The solid-state imaging device is the solid-state imaging device according to any one of claims 1 to 9.

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