Battery piece with suede structure and preparation method and application thereof
By designing a new suede structure in HJT cells, changing the light path, improving the light energy absorption and utilization rate, solving the problem of low light conversion efficiency of existing suede structures, and achieving more efficient photovoltaic cell performance.
Patent Information
- Application Number
- CN202411374441.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-29
- Publication Date
- 2025-01-07
AI Technical Summary
The suede structure of existing HJT batteries leads to low light utilization and poor light conversion efficiency. The suede structure needs to be optimized to improve light energy absorption and battery performance.
Design a new suede structure, by reducing the angle between the inclined surface of one side of the pyramid-like unit and the plane of the macroscopic surface of the silicon wafer, α<β, changing the path of incident light and reflected light, enhancing the trapping light effect, and maximizing The degree of absorption of light energy and reduces the influence of functional layer deposition.
The photoconversion efficiency of photovoltaic cells is improved, the utilization rate of light is enhanced, and the preparation method of cell is simplified, solving the reflection loss and low trapped light problems of pyramid morphology in vertical and horizontal placement environments.
Smart Images
Figure CN119277858A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of solar photovoltaics, and in particular relates to a solar cell with a velvet structure, a preparation method thereof, and an application thereof. Background Art
[0002] Crystalline silicon solar photovoltaic cell technology has advanced rapidly in recent years, particularly HJT (Hereto junction with Intrinsic Thin Layer), a leading next-generation high-efficiency photovoltaic cell. Heterojunction HJT cells, with their multiple advantages, including high conversion efficiency, significant potential for efficiency improvement, robust power generation capabilities, and a streamlined process, are currently attracting significant attention from industry investors. Assuming a 27.0% conversion efficiency, 8% power degradation over 25 years, and a 4% power gain, the critical non-silicon cost range for HJT cells is estimated to be approximately 0.4-0.5 yuan / W. As the cost-performance advantages of heterojunction cells become increasingly apparent, they are expected to replace mainstream alternatives. In the HJT heterojunction cell structure, the heterojunction interface determines the cell's ultimate properties. The silicon substrate, a component of this interface, is a key factor in determining cell performance.
[0003] Therefore, creating a textured surface on the silicon substrate can help to re-reflect sunlight or other light that strikes the surface of the HJT cell, allowing it to be absorbed and utilized, thereby improving the solar cell's light conversion efficiency. However, current textured surfaces still prevent a significant portion of light from being utilized, resulting in poor light conversion efficiency for HJT cells made with silicon wafers that incorporate this textured surface.
[0004] In summary, how to optimize the light trapping performance of the velvet structure to maximize the absorption of light energy, extend the optical path, increase the photogenerated carriers, and improve the light conversion efficiency of HJT cells is a technical problem that needs to be solved urgently. Summary of the Invention
[0005] In response to the shortcomings of the prior art, the present invention aims to provide a solar cell with a velvet structure, as well as its preparation method and application. The present invention designs a novel velvet structure. By reducing the angle between the inclined surface of one side of the pyramid-like unit and the plane of the silicon wafer's macroscopic surface, such that α is less than β, the path of incident and reflected light entering the silicon wafer is changed. This not only enhances the silicon wafer's light trapping effect in horizontal or vertical scenarios, maximizing light energy absorption, extending the optical path, increasing photogenerated carriers, and improving light utilization, but also reduces the impact on the deposition of functional layers in the solar cell. Solar cells prepared based on this velvet structure have excellent light conversion efficiency.
[0006] In order to achieve the purpose of the invention, the present invention adopts the following technical solutions:
[0007] In a first aspect, the present invention provides a battery cell with a velvet structure, the battery cell comprising a silicon wafer, a velvet structure being provided on one surface of the silicon wafer, the velvet structure having a plurality of pyramid-like units, an angle between an inclined surface on one side of the pyramid-like units and a plane of the macroscopic surface of the silicon wafer being denoted as α, an angle between an inclined surface on the other opposite side and the plane of the macroscopic surface of the silicon wafer being denoted as β, β ≥ 90°, α < β.
[0008] The inclined surface of the pyramid-like unit is a plane formed by the top of the pyramid-like unit and the bottom edge of the bottom of the pyramid-like unit.
[0009] This invention designs a novel velvet structure. By reducing the angle between the inclined surface of one pyramid-like unit and the plane of the silicon wafer's macroscopic surface to α < β, the path of incident and reflected light entering the wafer is altered. This not only enhances the wafer's light trapping effect in horizontal or vertical scenarios, maximizing light energy absorption, extending the optical path, increasing photogenerated carriers, and improving light utilization, but also reduces the impact on the deposition of functional layers in the cell. Cells fabricated using this velvet structure exhibit excellent light conversion efficiency.
[0010] It should be noted that the macroscopic surface of the silicon wafer refers to the plane of the silicon wafer where the velvet structure is grown.
[0011] In the present invention, β≥90°, for example, it can be 90°, 100° or 110°, and α<β, for example, it can be 90°, 80°, 70°, 60°, 50°, 40°, 30°, 20° or 10°.
[0012] In the present invention, if α=β, when the module is placed vertically or horizontally, sunlight is almost perpendicular to the silicon wafer surface, resulting in increased reflection loss and a significant loss of efficiency.
[0013] Preferably, the silicon wafer is an n-type silicon wafer.
[0014] Preferably, the value range of β is 90°-180°, and α<β.
[0015] Preferably, the angle α is less than 90°.
[0016] Preferably, the value range of α is 20°-90°, for example, 20°, 30°, 45°, 50°, 30°, 70° or 80°, etc. The present invention prefers α within this range, which can more fully absorb light energy, extend the optical path, increase photogenerated carriers, and improve light utilization.
[0017] Preferably, the cross-section of the top of the pyramid-like unit is an arc-shaped rounded corner.
[0018] In the present invention, when depositing an amorphous silicon layer, the silicon wafer with the arc-shaped rounded corner tower top can improve the deposition uniformity of the amorphous silicon layer on the velvet surface, reduce the defect state density, and achieve a good passivation effect.
[0019] Preferably, the radius of curvature of the fillet of the pyramid-like unit top is 30-500 nm, for example, 30 nm, 50 nm, 100 nm, 200 nm, 300 nm, 400 nm or 500 nm, and preferably 100-400 nm.
[0020] Preferably, the cross section of the tower valley of the velvet structure is an arc-shaped rounded corner.
[0021] In the present invention, when depositing an amorphous silicon layer, the silicon wafer with the arc-shaped rounded corner valley can improve the deposition uniformity of the amorphous silicon layer on the velvet surface, reduce the defect state density, and achieve a good passivation effect.
[0022] Preferably, the radius of curvature of the fillet of the pyramid-like unit is 30-500 nm, for example, 30 nm, 50 nm, 100 nm, 200 nm, 300 nm, 400 nm or 500 nm, and preferably 100-400 nm.
[0023] Preferably, the cell comprises a heterojunction cell.
[0024] Preferably, the heterojunction cell includes the silicon wafer, and the non-texture surface of the silicon wafer is sequentially stacked with an intrinsic amorphous silicon layer, an n-type amorphous silicon layer, a transparent oxide layer and a back electrode along the direction away from the silicon wafer, and the texture surface of the silicon wafer is sequentially stacked with an intrinsic amorphous silicon layer, a p-type amorphous silicon layer, a transparent oxide layer and a positive electrode along the direction away from the silicon wafer.
[0025] Preferably, the material of the transparent oxide layer includes ITO (indium tin oxide).
[0026] Preferably, the back electrode and the positive electrode are prepared by screen printing.
[0027] Preferably, the steps of the screen printing method include: printing the positive electrode and the back electrode on the transparent oxide layer on both sides by screen printing, and then drying at 80-90°C (for example, it can be 80°C, 85°C, 90°C, 95°C or 100°C, etc.) for 120-150s (for example, it can be 120s, 130s, 140s or 150s, etc.).
[0028] In a second aspect, the present invention provides a method for preparing a cell having a velvet structure as described in the first aspect, wherein the cell comprises a silicon wafer having a velvet structure provided on one side of the surface of the silicon wafer, and the method for preparing the silicon wafer comprises the following steps:
[0029] One side of the silicon wafer is textured to form a pyramid structure.
[0030] One side slope of the pyramid structure is laser etched so that the angle between the laser etched surface and the plane of the silicon wafer's macroscopic surface is reduced, that is, α<β, where β is the angle between the other side slope and the plane of the silicon wafer's macroscopic surface, thereby obtaining a silicon wafer with a velvet structure.
[0031] The preparation method provided by the present invention has a simple process and can effectively solve the problems of large reflection loss and low light trapping in the pyramid morphology of HJT cells when they are actually used in vertical and horizontal placement environments.
[0032] Preferably, the texturing is alkali texturing, and the alkali solution used in the alkali texturing includes potassium hydroxide solution and / or sodium hydroxide solution.
[0033] It should be noted that in the process of alkali texturing, the silicon wafer is anisotropically corroded by alkali solution, so that the Si(100) crystal plane is corroded into a tetragonal pyramid structure (i.e., a pyramid structure) of the Si(111) crystal plane, forming a velvet surface, which can reduce the surface reflectivity of the silicon wafer to below 12.5%, thereby generating more photogenerated carriers.
[0034] Preferably, the concentration of the alkali solution is 1-20 wt%, for example, 1 wt%, 5 wt%, 10 wt%, 15 wt% or 20 wt%, etc., preferably 10-20 wt%.
[0035] Preferably, the side length of the base of the pyramid structure is 1-4 μm, for example, 1 μm, 2 μm, 3 μm or 4 μm.
[0036] Preferably, during the laser etching process on one side slope of the pyramid structure, the textured silicon wafer and the laser source maintain a certain angle, and the angle between the textured silicon wafer and the laser source is 1°-90°, for example, it can be 1°, 5°, 10°, 30°, 50°, 60° or 90°, etc., preferably 20-80°.
[0037] Preferably, during the laser etching process in step (2), specific process parameters include:
[0038] The laser spot scanning interval is 1-500μm, for example, it can be 1μm, 20μm, 50μm, 100μm, 200μm, 300μm, 400μm or 500μm, etc. The laser scanning speed is 1-10mm / s, for example, it can be 1mm / s, 1mm / s, 3mm / s, 5mm / s, 7mm / s or 9mm / s, etc. The frequency is 1-1000kHz, for example, it can be 50kHz, 100kHz, 200kHz, 300kHz, 400kHz or 500kHz, etc.
[0039] Preferably, after the laser etching process, the top and valley of the pyramid-like unit are further rounded, and the specific steps of the rounding process include:
[0040] The laser-etched silicon wafer is cleaned using a corrosive medium.
[0041] In the present invention, by using a corrosive medium for cleaning, isotropic etching of the silicon wafer is achieved, thereby rounding the top and valley of the pyramid-like unit, which is beneficial to improving the deposition uniformity of the amorphous silicon layer on the velvet surface, reducing the defect state density, and achieving a good passivation effect.
[0042] Preferably, the cleaning temperature is 20-30°C, for example, 20°C, 25°C or 30°C, and the cleaning time is 90-120s, for example, 90s, 100s, 110s or 120s.
[0043] Preferably, the corrosive medium comprises ozone and / or hydrofluoric acid.
[0044] Preferably, the ozone concentration is 1-45 ppm, for example, 1 ppm, 5 ppm, 10 ppm, 20 ppm, 30 ppm, 40 ppm or 45 ppm.
[0045] Preferably, the concentration of the hydrofluoric acid is 1-40 wt%, for example, 1 wt%, 5 wt%, 10 wt%, 20 wt%, 30 wt% or 40 wt%.
[0046] Preferably, the method for preparing the silicon wafer comprises the following steps:
[0047] Pre-clean the silicon wafer: clean the silicon wafer with a cleaning solution at 60-90°C (for example, 60°C, 70°C, 80°C or 90°C, etc., preferably 80-90°C) for 100-600s (exemplarily, for example, 100s, 200s, 300s, 400s, 500s or 600s, etc., preferably 100-150s); the cleaning solution comprises sodium hydroxide, hydrogen peroxide and water in a volume ratio of 1:5:(5-15) (for example, 1:5:5, 1:5:10 or 1:5:15, etc., preferably 1:1:(6-8)).
[0048] Alkali texturing of the silicon wafer: using an alkali solution with a concentration of 1-20 wt % to texturize the silicon wafer pre-cleaned in step (1), forming a pyramid structure with a bottom side length of 1-4 μm.
[0049] The textured surface of the silicon wafer after texturing is placed under a laser source, and the silicon wafer and the laser source are kept at a certain angle. One side of the pyramid structure is laser etched, so that the angle α between the laser etched surface formed by etching and the plane of the silicon wafer's macroscopic surface is reduced, that is, α<β, β is the angle between the other side of the slope and the plane of the silicon wafer's macroscopic surface, forming a pyramid-like unit; during the laser etching process, specific process parameters include: laser spot scanning spacing of 1-500μm, laser scanning speed of 1-10mm / s, and frequency of 1-1000kHz.
[0050] A corrosive medium is used to clean a silicon wafer having pyramid-like units, and the tops and valleys of the pyramid-like units are rounded to obtain a silicon wafer having a velvet structure. The cleaning temperature is 20-30°C, the cleaning time is 90-120s, and the corrosive medium includes ozone with a concentration of 1-45ppm and hydrofluoric acid with a concentration of 1-40wt%.
[0051] In the present invention, the purpose of pre-cleaning is to form a clean silicon wafer surface and avoid carrier recombination at the interface caused by defects and impurities introduced by uncleanness.
[0052] In a third aspect, the present invention provides a photovoltaic module, comprising the solar cell according to the first aspect.
[0053] The numerical range described in the present invention includes not only the point values listed above, but also any point values between the above numerical ranges that are not listed. Due to space limitations and for the sake of simplicity, the present invention no longer exhaustively lists the specific point values included in the range.
[0054] Compared with the prior art, the present invention has the following beneficial effects:
[0055] (1) The present invention designs a novel velvet structure. By reducing the angle between the inclined surface of one side of the pyramid-like unit and the plane of the macroscopic surface of the silicon wafer so that α is less than β, the path of incident and reflected light entering the silicon wafer is changed. This not only enhances the light trapping effect of the silicon wafer in horizontal or vertical scenes, maximizes light energy absorption, extends the optical path, increases photogenerated carriers, and improves light utilization, but also reduces the impact on the deposition of functional layers in the cell. The cell prepared based on this velvet structure has excellent light conversion efficiency.
[0056] (2) The preparation method provided by the present invention is simple in process and can effectively solve the problem of large reflection loss and low light trapping in the pyramid morphology of HJT cells when they are actually used in vertical and horizontal placement environments. BRIEF DESCRIPTION OF THE DRAWINGS
[0057] Figure 1 This is a schematic cross-sectional view of the textured surface in a silicon wafer having a textured surface structure provided in Example 3 of the present invention.
[0058] Figure 2 This is a schematic diagram of the process for suede modification in the preparation method provided in Example 3 of the present invention.
[0059] Figure 3 This is a schematic cross-sectional view of the textured surface in the silicon wafer with a textured surface structure provided in Comparative Example 1 of the present invention.
[0060] Figure 4 This is a comparison diagram of the reflection path of incident light when the silicon wafer with a textured structure provided by Example 3 of the present invention and Comparative Example 1 is placed vertically.
[0061] Figure 5 This is a comparison diagram of the reflection path of incident light when the silicon wafer with a textured structure provided by Example 3 of the present invention and Comparative Example 1 is placed horizontally. DETAILED DESCRIPTION
[0062] The technical solution of the present invention is further described below by way of specific embodiments. It should be understood by those skilled in the art that the embodiments are merely to help understand the present invention and should not be regarded as specific limitations of the present invention.
[0063] Example 1
[0064] This embodiment provides a heterojunction cell with a velvet structure, the heterojunction cell including a silicon wafer, a velvet structure provided on one surface of the silicon wafer, the velvet structure having a plurality of pyramid-like units, the angle between the inclined surface of one side of the pyramid-like unit and the plane of the macroscopic surface of the silicon wafer being denoted as α, α being 90°, and the angle between the inclined surface of the other opposite side and the plane of the macroscopic surface of the silicon wafer being denoted as β, β being 120°; the inclined surface of the pyramid-like unit being a plane formed by the top of the pyramid-like unit and the bottom edge of the bottom of the pyramid-like unit.
[0065] The silicon wafer is an n-type silicon wafer.
[0066] The cross section of the pyramid-like unit's top is an arc-shaped fillet, and the fillet curvature radius of the pyramid-like unit's top is 90nm; the cross section of the valley of the velvet structure is an arc-shaped fillet, and the fillet curvature radius of the valley of the pyramid-like unit is 90nm.
[0067] The non-textured surface of the silicon wafer includes a stacked intrinsic hydrogenated amorphous silicon layer, an n-type amorphous silicon layer, an ITO (indium tin oxide) layer and a back electrode along the direction away from the silicon wafer, and the velvet surface of the silicon wafer includes a stacked intrinsic hydrogenated amorphous silicon layer, a p-type amorphous silicon layer, an ITO layer and a positive electrode along the direction away from the silicon wafer; the materials of the positive electrode and the negative electrode are both silver.
[0068] This embodiment also provides a method for preparing the above-mentioned silicon wafer, comprising the following steps:
[0069] (1) Pre-clean the silicon wafer:
[0070] The silicon wafer was cleaned at 80° C. for 120 seconds using a cleaning solution comprising sodium hydroxide, hydrogen peroxide, and water in a volume ratio of 1:5:6.
[0071] (2) Alkali texturing of silicon wafers:
[0072] The silicon wafer pre-cleaned in step (1) is textured using an alkaline solution with a concentration of 15 wt % to form a pyramid structure with a bottom side length of 3 μm.
[0073] Wherein, the alkali solution is potassium hydroxide solution.
[0074] (3) Suede modification:
[0075] The textured surface of the silicon wafer after texturing is placed under a laser source, and the silicon wafer and the laser source are kept at a certain angle of 45°. One side of the pyramid structure is laser etched so that the angle α between the laser etched surface and the plane of the silicon wafer's macroscopic surface is 90°, and β is the angle between the other side's slope and the plane of the silicon wafer's macroscopic surface, forming a pyramid-like unit.
[0076] During the laser etching process, specific process parameters include: laser spot scanning spacing of 20 μm, laser scanning speed of 5 mm / s, and frequency of 100 kHz.
[0077] (4) Cleaning the silicon wafer after the treatment in step (3) with a corrosive medium, completing the rounding of the top and valley of the pyramid-like unit, and obtaining a silicon wafer with a velvet structure.
[0078] The cleaning temperature is 25° C., the cleaning time is 100 s, and the corrosive medium includes ozone with a concentration of 45 ppm and hydrofluoric acid with a concentration of 40 wt %.
[0079] This embodiment also provides a method for preparing the above-mentioned heterojunction solar cell, the method comprising the following steps:
[0080] (a) Plasma-enhanced chemical vapor deposition (PECVD) is used to sequentially deposit an intrinsic hydrogenated amorphous silicon layer and a p-type amorphous silicon layer on the textured surface of the silicon wafer prepared above.
[0081] (b) Using the PECVD method, an intrinsic hydrogenated amorphous silicon layer and an n-type amorphous silicon layer are sequentially deposited on the non-textured surface of the silicon wafer.
[0082] (c) Using a CVD method, an ITO layer is deposited on the p-type amorphous silicon layer and the n-type amorphous silicon layer, and then silver paste is printed on the ITO layers on different sides of the silicon wafer by screen printing, and then dried at 85° C. for 120 seconds to obtain the heterojunction solar cell.
[0083] Example 2
[0084] This embodiment provides a heterojunction cell with a velvet structure, the heterojunction cell including a silicon wafer, a velvet structure provided on one surface of the silicon wafer, the velvet structure having a plurality of pyramid-like units, the angle between the inclined surface of one side of the pyramid-like unit and the plane of the macroscopic surface of the silicon wafer being denoted as α, α being 60°, and the angle between the inclined surface of the other opposite side and the plane of the macroscopic surface of the silicon wafer being denoted as β, β being 120°; the inclined surface of the pyramid-like unit being a plane formed by the top of the pyramid-like unit and the bottom edge of the bottom of the pyramid-like unit.
[0085] The silicon wafer is an n-type silicon wafer.
[0086] The cross section of the pyramid-like unit's top is an arc-shaped fillet, and the fillet curvature radius of the pyramid-like unit's top is 60nm; the cross section of the valley of the velvet structure is an arc-shaped fillet, and the fillet curvature radius of the valley of the pyramid-like unit is 60nm.
[0087] The non-textured surface of the silicon wafer includes a stacked intrinsic hydrogenated amorphous silicon layer, an n-type amorphous silicon layer, an ITO (indium tin oxide) layer and a back electrode along the direction away from the silicon wafer, and the velvet surface of the silicon wafer includes a stacked intrinsic hydrogenated amorphous silicon layer, a p-type amorphous silicon layer, an ITO layer and a positive electrode along the direction away from the silicon wafer; the materials of the positive electrode and the negative electrode are both silver.
[0088] This embodiment also provides a method for preparing the above-mentioned silicon wafer, comprising the following steps:
[0089] (1) Pre-clean the silicon wafer:
[0090] The silicon wafer was cleaned at 60° C. for 600 s using a cleaning solution comprising sodium hydroxide, hydrogen peroxide, and water in a volume ratio of 1:5:10.
[0091] (2) Alkali texturing of silicon wafers:
[0092] The silicon wafer pre-cleaned in step (1) is textured using an alkaline solution with a concentration of 10 wt % to form a pyramid structure with a bottom side length of 2 μm.
[0093] Wherein, the alkali solution is potassium hydroxide solution or sodium hydroxide solution.
[0094] (3) Suede modification:
[0095] The textured surface of the silicon wafer after texturing is placed under a laser source, and the silicon wafer and the laser source are kept at a certain angle of 30°. The inclined surface of one side of the pyramid structure is laser etched so that the angle α between the laser etched surface and the plane of the silicon wafer's macroscopic surface is 60°, forming a pyramid-like unit.
[0096] During the laser etching process, specific process parameters include: laser spot scanning spacing of 20 μm, laser scanning speed of 5 mm / s, and frequency of 100 kHz.
[0097] (4) Cleaning the silicon wafer after the treatment in step (3) with a corrosive medium, completing the rounding of the top and valley of the pyramid-like unit, and obtaining a silicon wafer with a velvet structure.
[0098] The cleaning temperature is 20° C., the cleaning time is 120 seconds, and the corrosive medium includes ozone with a concentration of 20 ppm and hydrofluoric acid with a concentration of 20 wt %.
[0099] This embodiment also provides a method for preparing the above-mentioned heterojunction solar cell, the method comprising the following steps:
[0100] (a) Using PECVD (chemical vapor deposition) method, an intrinsic hydrogenated amorphous silicon layer and a p-type amorphous silicon layer are sequentially deposited on the textured surface of a silicon wafer.
[0101] (b) Using the PECVD method, an intrinsic hydrogenated amorphous silicon layer and an n-type amorphous silicon layer are sequentially deposited on the non-textured surface of the silicon wafer.
[0102] (c) Using a CVD method, an ITO layer is deposited on the p-type amorphous silicon layer and the n-type amorphous silicon layer, and then silver paste is printed on the ITO layers on different sides of the silicon wafer by screen printing, and then dried at 85° C. for 120 seconds to obtain the heterojunction solar cell.
[0103] Example 3
[0104] This embodiment provides a cell with a velvet structure, the cell comprising a silicon wafer, a velvet structure being provided on one side of the silicon wafer, the velvet structure having a plurality of pyramid-like units, and a cross-sectional schematic diagram thereof as shown in FIG. Figure 1 As shown, the angle between the inclined surface of one side of the pyramid-like unit and the plane of the macroscopic surface of the silicon wafer is recorded as α, which is 30°, and the angle between the inclined surface of the other side and the plane of the macroscopic surface of the silicon wafer is recorded as β, which is 120°; the inclined surface of the pyramid-like unit is the plane formed by the top of the pyramid-like unit and the bottom edge of the bottom of the pyramid-like unit.
[0105] The silicon wafer is an n-type silicon wafer.
[0106] The cross section of the pyramid-like unit's top is an arc-shaped fillet, and the fillet curvature radius of the pyramid-like unit's top is 40nm; the cross section of the valley of the velvet structure is an arc-shaped fillet, and the fillet curvature radius of the valley of the pyramid-like unit is 40nm.
[0107] The non-textured surface of the silicon wafer includes a stacked intrinsic hydrogenated amorphous silicon layer, an n-type amorphous silicon layer, an ITO (indium tin oxide) layer and a back electrode along the direction away from the silicon wafer, and the velvet surface of the silicon wafer includes a stacked intrinsic hydrogenated amorphous silicon layer, a p-type amorphous silicon layer, an ITO layer and a positive electrode along the direction away from the silicon wafer; the materials of the positive electrode and the negative electrode are both silver.
[0108] This embodiment also provides a method for preparing the above-mentioned silicon wafer, comprising the following steps:
[0109] (1) Pre-clean the silicon wafer:
[0110] The silicon wafer was cleaned at 90° C. for 100 s using a cleaning solution comprising sodium hydroxide, hydrogen peroxide, and water in a volume ratio of 1:5:15.
[0111] (2) Alkali texturing of silicon wafers:
[0112] The silicon wafer pre-cleaned in step (1) is textured using an alkaline solution with a concentration of 5 wt % to form a pyramid structure with a bottom side length of 1 μm.
[0113] Wherein, the alkali solution is potassium hydroxide solution or sodium hydroxide solution.
[0114] (3) Suede modification, the process diagram is as follows Figure 2 As shown:
[0115] The textured surface of the silicon wafer after texturing is placed under a laser source, and the silicon wafer and the laser source are kept at a certain angle of 20°. The inclined surface of one side of the pyramid structure is laser etched so that the angle α between the laser etched surface and the plane of the silicon wafer's macroscopic surface is 30°, forming a pyramid-like unit.
[0116] During the laser etching process, specific process parameters include: laser spot scanning spacing of 20 μm, laser scanning speed of 5 mm / s, and frequency of 100 kHz.
[0117] (4) Cleaning the silicon wafer after the treatment in step (3) with a corrosive medium, completing the rounding of the top and valley of the pyramid-like unit, and obtaining a silicon wafer with a velvet structure.
[0118] The cleaning temperature is 30° C., the cleaning time is 90 seconds, and the corrosive medium includes ozone with a concentration of 15 ppm and hydrofluoric acid with a concentration of 10 wt %.
[0119] This embodiment also provides a method for preparing the above-mentioned heterojunction solar cell, comprising the following steps:
[0120] (a) Using the PECVD method, an intrinsic hydrogenated amorphous silicon layer and a p-type amorphous silicon layer are sequentially deposited on the textured surface of a silicon wafer.
[0121] (b) Using the PECVD method, an intrinsic hydrogenated amorphous silicon layer and an n-type amorphous silicon layer are sequentially deposited on the non-textured surface of the silicon wafer.
[0122] (c) Using a CVD method, an ITO layer is deposited on the p-type amorphous silicon layer and the n-type amorphous silicon layer, and then silver paste is printed on the ITO layers on different sides of the silicon wafer by screen printing, and then dried at 85° C. for 120 seconds to obtain the heterojunction solar cell.
[0123] Example 4
[0124] The difference between this embodiment and embodiment 1 is that the cross-section of the top of the pyramid-like unit and the cross-section of the valley of the velvet structure are both non-rounded, that is, step (4) is not performed.
[0125] The rest of the preparation methods and parameters remained the same as in Example 1.
[0126] Comparative Example 1
[0127] The difference between this comparative example and Example 1 is that α and β are the same, both 120°, that is, step (3) is not performed.
[0128] The rest of the preparation methods and parameters remained the same as in Example 1.
[0129] Figure 3 The cross-sectional schematic diagram of the texture in the silicon wafer with a texture structure provided in this comparative example is shown.
[0130] Figure 4 and Figure 5 Comparisons of incident light reflection paths for silicon wafers with textured surfaces, provided in Example 3 and Comparative Example 1, when placed vertically or horizontally, are shown. The comparison shows that incident sunlight reflected from the modified textured surface passes through the main cell body, enhancing absorption. Light reflected from conventional textured surfaces does not pass through the main cell body, resulting in poor absorption.
[0131] Performance Testing
[0132] Photoelectric performance tests were conducted on the heterojunction cells prepared in the above examples and comparative examples. The test parameters included open circuit voltage (Voc), short circuit current (Jsc), fill factor (FF) and photoelectric conversion efficiency (PCE).
[0133] The test results are shown in Table 1.
[0134] Table 1
[0135]
[0136] analyze:
[0137] The present invention reduces the angle between the inclined surface of one side of the pyramid-like unit and the plane of the silicon wafer's macroscopic surface, changing the path of incident and reflected light entering the silicon wafer. This not only enhances the silicon wafer's light trapping effect, maximizing light energy absorption, extending the optical path, increasing photogenerated carriers, and improving light utilization, but also reduces the impact on the subsequent deposition of the amorphous silicon layer in heterojunction cells. The resulting heterojunction cell exhibits excellent light conversion efficiency.
[0138] From the comparison between Example 1 and Example 4, it can be seen that if the cross-section of the top of the pyramid-like unit and the cross-section of the valley of the velvet structure are both non-rounded, it is not conducive to improving the fill factor, resulting in low efficiency of the heterojunction cell.
[0139] From the comparison between Example 1 and Comparative Example 1, it can be seen that if step (3) is not performed, that is, the velvet surface is not laser modified, α and β are the same, both 120°, then the heterojunction cell will not absorb enough incident sunlight, the short-circuit current will be low, and the efficiency of the heterojunction cell will be low.
[0140] The applicant states that while the above-described embodiments illustrate the process of the present invention, the present invention is not limited to the above-described process steps, nor does it imply that the present invention must rely on the above-described process steps for implementation. Those skilled in the art will appreciate that any improvements to the present invention, equivalent substitutions for the raw materials used, additions of auxiliary components, and selection of specific methods, etc., fall within the scope of protection and disclosure of the present invention.
Claims
1. A battery cell with a velvet structure, characterized in that: The cell comprises a silicon wafer, a velvet structure is arranged on one side surface of the silicon wafer, the velvet structure has a plurality of pyramid-like units, an angle between an inclined surface on one side of the pyramid-like unit and a plane of a macroscopic surface of the silicon wafer is denoted as α, and an angle between an inclined surface on the other side opposite to the plane of the macroscopic surface of the silicon wafer is denoted as β, β≥90°, α<β; The inclined surface of the pyramid-like unit is a plane formed by the top of the pyramid-like unit and the bottom edge of the bottom of the pyramid-like unit.
2. The battery cell according to claim 1, characterized in that: The value range of β is 90°-180°, α<β; Preferably, the angle α is less than 90°.
3. The battery cell according to claim 1 or 2, characterized in that: The cross section of the top of the pyramid-like unit is an arc-shaped rounded corner; Preferably, the radius of curvature of the fillet of the top of the pyramid-like unit is 30-500 nm; Preferably, the cross section of the tower valley of the velvet structure is an arc-shaped rounded corner; Preferably, the radius of curvature of the rounded corners of the pyramid-like units is 30-500 nm.
4. The battery cell according to any one of claims 1 to 3, characterized in that: The battery cell comprises a heterojunction battery cell; Preferably, the heterojunction cell comprises the silicon wafer, the non-texture surface of the silicon wafer being stacked with an intrinsic amorphous silicon layer, an n-type amorphous silicon layer, a transparent oxide layer and a back electrode in sequence along a direction away from the silicon wafer, and the texture surface of the silicon wafer being stacked with an intrinsic amorphous silicon layer, a p-type amorphous silicon layer, a transparent oxide layer and a positive electrode in sequence along a direction away from the silicon wafer.
5. A method for preparing a battery cell with a suede structure according to any one of claims 1 to 4, characterized in that: The cell comprises a silicon wafer, a velvet structure is arranged on one side surface of the silicon wafer, and the method for preparing the silicon wafer comprises the following steps: Texturing is performed on one side of the silicon wafer to form a pyramid structure; One side slope of the pyramid structure is laser etched so that the angle α between the laser etched surface and the plane of the macroscopic surface of the silicon wafer is reduced, that is, α<β, β is the angle between the other side slope and the plane of the macroscopic surface of the silicon wafer, thereby obtaining a silicon wafer with a velvet structure.
6. The preparation method according to claim 5, characterized in that: The texturing is alkali texturing, and the alkali solution used in the alkali texturing includes potassium hydroxide solution and / or sodium hydroxide solution; Preferably, the concentration of the alkali solution is 1-20wt%, preferably 10-20wt%; Preferably, the length of the base side of the pyramid structure is 1-4 μm.
7. The preparation method according to claim 5 or 6, characterized in that: During the laser etching process, specific process parameters include: The laser spot scanning interval is 1-500μm, the laser scanning speed is 1-10mm / s, and the frequency is 1-1000kHz.
8. The preparation method according to any one of claims 5 to 7, characterized in that: After the laser etching process, the top and valley of the pyramid-like unit are further rounded, and the specific steps of the rounding process include: Using corrosive media to clean the silicon wafer after laser etching; Preferably, the cleaning temperature is 20-30°C and the cleaning time is 90-120s; Preferably, the corrosive medium comprises ozone and / or hydrofluoric acid; Preferably, the concentration of ozone is 1-45 ppm; Preferably, the concentration of the hydrofluoric acid is 1-40 wt %.
9. The preparation method according to any one of claims 5 to 8, characterized in that: The method for preparing the silicon wafer comprises the following steps: Pre-cleaning the silicon wafer: cleaning the silicon wafer with a cleaning solution at 60-90° C. for 100-600 seconds; the cleaning solution includes sodium hydroxide, hydrogen peroxide and water in a volume ratio of 1:5:(5-15); Alkali texturing of silicon wafers: using 1-20wt% alkali solution to texturing the pre-cleaned silicon wafers to form a pyramid structure with a bottom side length of 1-4μm; The textured surface of the silicon wafer after texture processing is placed under a laser source, and the silicon wafer and the laser source are kept at a certain angle, and the inclined surface on one side of the pyramid structure is laser etched, so that the angle α between the laser etched surface formed by etching and the plane of the macroscopic surface of the silicon wafer is reduced, that is, α<β, β is the angle between the inclined surface on the other side and the plane of the macroscopic surface of the silicon wafer, so as to form a pyramid-like unit; During the laser etching process, specific process parameters include: laser spot scanning spacing 1-500μm, laser scanning speed 1-10mm / s, frequency 1-1000kHz; A corrosive medium is used to clean a silicon wafer having pyramid-like units, and the top and valley of the pyramid-like units are rounded to obtain a silicon wafer having a velvet structure; wherein the cleaning temperature is 20-30°C, the cleaning time is 90-120s, and the corrosive medium includes ozone with a concentration of 1-45ppm and hydrofluoric acid with a concentration of 1-40wt%.
10. A photovoltaic module, characterized in that: The photovoltaic module comprises the solar cell according to any one of claims 1 to 4.