SRAM awakening method and device

Abstract

The invention discloses an SRAM (Static Random Access Memory) awakening method and device, and the method comprises the following steps: determining the number of split blocks according to PPA performance parameters of an SRAM; according to the depth of the SRAM and the number of the split blocks, splitting is carried out after splitting granularity is obtained, and a plurality of SRAM sub-blocks are formed; awakening the currently accessed SRAM sub-block according to the current access address of the access pointer, and enabling other SRAM sub-blocks to be in dormancy; and when the current access address is consistent with the preset wake-up address of the currently accessed SRAM sub-block, waking up the next SRAM sub-block. According to the invention, the SRAM is divided into a plurality of small sub-blocks (SRAM sub-blocks), and the sub-blocks are divided into a plurality of sub-blocks (SRAM sub-blocks). Only the currently accessed sub-block is awakened, and other sub-blocks are kept in a dormant state. In this way, the power consumption can be effectively reduced even in an application scenario with a high access rate.

Description

Technical Field

[0001] The present invention relates to the technical field of cache control, and in particular to an SRAM wake-up method and device. Background Art

[0002] In some large cache application designs, SRAM power consumption may account for a large part of the entire design. In some power-sensitive applications (such as consumer electronics), reducing SRAM power consumption will become the key to optimizing the power consumption of the entire design.

[0003] The existing solution is generally to control the low-power port (such as SLP) of SRAM, control SRAM to be in SLP state (low power) when SRAM is not accessed, and dynamically turn on SRAM (SLP) when access comes, and enter SLP state again after access ends. In the above solution, the non-access time slot of SRAM is actually used to obtain power consumption benefits. This solution has two main disadvantages:

[0004] (a) In some stream processing cache applications, SRAM is in a frequently accessed state, and there is no non-access time window or the non-access time window is very small, that is, there is a lack of sufficient low-power time, which makes the power saving benefits limited. (b) Based on the overall control of the SRAM low-power state of the logical cache, for some large cache applications, when only a small space in the SRAM is accessed, the entire SRAM also needs to be in a working state. Most of the non-accessed space also brings a large power consumption overhead because the entire SRAM is in a non-low-power state. Summary of the invention

[0005] The SRAM wake-up method and device provided by the embodiment of the present invention divide the SRAM into multiple SRAM sub-blocks, and simultaneously control the wake-up and sleep of the multiple SRAM sub-blocks based on the access address, thereby reducing the energy consumption of the SRAM.

[0006] To achieve the above object, a first aspect of an embodiment of the present application provides an SRAM wake-up method, comprising:

[0007] Determine the number of split blocks according to the PPA performance parameter of SRAM;

[0008] According to the depth of the SRAM and the number of split blocks, a split granularity is obtained and then split to form a plurality of SRAM sub-blocks;

[0009] The SRAM sub-block currently being accessed is awakened according to the current access address of the access pointer, and other SRAM sub-blocks are put into sleep mode; when the current access address is consistent with the preset wake-up address of the SRAM sub-block currently being accessed, the next SRAM sub-block is awakened.

[0010] In a possible implementation manner of the first aspect, before waking up the SRAM sub-block currently accessed according to the current access address of the access pointer, the method includes:

[0011] According to the split granularity and the wake-up time, a plurality of preset wake-up addresses are determined; each of the SRAM sub-blocks corresponds to a preset wake-up address, and the address difference between adjacent preset wake-up addresses is equal to the split granularity.

[0012] In a possible implementation manner of the first aspect, determining a plurality of preset wake-up addresses according to the split granularity and the wake-up time specifically includes:

[0013] Determine the maximum depth corresponding to each of the SRAM sub-blocks according to the split granularity;

[0014] The difference between the maximum depth and the wake-up time is used as a preset wake-up address of the SRAM sub-block.

[0015] In a possible implementation manner of the first aspect, before determining the plurality of preset wake-up addresses, the method includes:

[0016] Determining a minimum wake-up time according to the sleep mode of the SRAM sub-block;

[0017] A natural number that is less than or equal to the minimum wake-up time is selected as the wake-up time.

[0018] In a possible implementation manner of the first aspect, determining the number of split blocks according to the PPA performance parameter of the SRAM specifically includes:

[0019] According to the PPA performance parameter of the SRAM, an area function of the SRAM area with respect to the number of split blocks and a power consumption function of the SRAM power consumption with respect to the number of split blocks are determined;

[0020] The number of split blocks is determined according to the intersection of the area function and the power consumption function.

[0021] A second aspect of an embodiment of the present application provides an SRAM wake-up device, including:

[0022] A determination module, used for determining the number of split blocks according to the PPA performance parameter of the SRAM;

[0023] A splitting module, used for splitting after obtaining a splitting granularity according to the depth of the SRAM and the number of split blocks, to form a plurality of SRAM sub-blocks;

[0024] The wake-up module is used to wake up the SRAM sub-block currently being accessed according to the current access address of the access pointer, so that other SRAM sub-blocks are in sleep mode; when the current access address is consistent with the preset wake-up address of the SRAM sub-block currently being accessed, wake up the next SRAM sub-block.

[0025] In a possible implementation of the second aspect, a preset module is also included, which is used to determine a number of preset wake-up addresses according to the split granularity and the wake-up time; each of the SRAM sub-blocks corresponds to a preset wake-up address, and the address difference between adjacent preset wake-up addresses is equal to the split granularity.

[0026] In a possible implementation of the second aspect, the preset module includes a first preset unit, which is used to determine the maximum depth corresponding to each of the SRAM sub-blocks according to the split granularity; and use the difference between the maximum depth and the wake-up time as the preset wake-up address of the SRAM sub-block.

[0027] In a possible implementation of the second aspect, the preset module also includes: a second preset unit, used to: determine the minimum wake-up time according to the sleep mode of the SRAM sub-block; and select a natural number less than or equal to the minimum wake-up time as the wake-up time.

[0028] In a possible implementation manner of the second aspect, the confirmation module includes a confirmation unit, configured to:

[0029] According to the PPA performance parameter of the SRAM, an area function of the SRAM area with respect to the number of split blocks and a power consumption function of the SRAM power consumption with respect to the number of split blocks are determined;

[0030] The number of split blocks is determined according to the intersection of the area function and the power consumption function.

[0031] Compared with the prior art, the embodiments of the present invention provide an SRAM wake-up method and device, which determines the optimal number of splits based on the PPA (performance, power consumption, area) performance parameters of the SRAM, calculates the size of each sub-block according to the total depth of the SRAM and the number of split blocks, and splits them. When the access pointer points to a sub-block, only the sub-block is woken up; after the access is completed, the sub-block re-enters the dormant state. The correct sub-block is ensured to be woken up by presetting the wake-up address.

[0032] This application greatly reduces unnecessary power consumption by waking up only the part that needs to be accessed currently. Since the wakeup and sleep of the sub-blocks are dynamic, the impact on performance is minimized. In practice, the split granularity and wakeup strategy can be adjusted according to the needs of the application. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1It is a flowchart of an SRAM wake-up method provided by an embodiment of the present invention;

[0034] Figure 2 An embodiment of the present invention provides a schematic diagram of SRAM control based on access address. DETAILED DESCRIPTION

[0035] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0036] In applications with large caches that need to be accessed frequently, there are two main problems: one is how to effectively use low-power modes when accessing continuously; the other is how to avoid wasting power when accessing only a small part of the data while the entire SRAM is active.

[0037] To solve the above problems, see Figure 1 , an embodiment of the present invention provides an SRAM wake-up method, comprising:

[0038] S10. Determine the number of split blocks according to the PPA performance parameter of the SRAM.

[0039] S11 . According to the depth of the SRAM and the number of split blocks, a split granularity is obtained and then split to form a plurality of SRAM sub-blocks.

[0040] S12, waking up the SRAM sub-block currently being accessed according to the current access address of the access pointer, and putting the other SRAM sub-blocks into sleep mode; when the current access address is consistent with the preset wake-up address of the SRAM sub-block currently being accessed, waking up the next SRAM sub-block.

[0041] In S10-S11, the SRAM is logically regarded as a large cache as a whole, split into multiple physical sub-SRAMs of the same size, and each physical SRAM sub-block has an independent low-power control port (such as SLP, SD, etc.). In S12, according to the access prediction (such as address), the currently accessed physical SRAM is in the awake (normal activity) state; the unaccessed physical SRAM blocks are controlled in the dormant state, that is, the low-power state (such as SLP, SD).

[0042] Historical access patterns can be used to predict future access behaviors, allowing for more accurate decisions about when to wake up or sleep a sub-block. The preset wake-up address should be close enough to the sub-block boundary, but also leave some margin to avoid the extra power consumption caused by frequent wake-up and sleep.

[0043] In practical applications, an efficient controller can be designed to manage the status of all sub-blocks to ensure fast response to access requests and timely switching of sub-block states. Each sub-block needs to be equipped with a low-power control port (such as SLP, SD, etc.) for fast entry or exit of low-power states.

[0044] Through the above wake-up method, power consumption can be significantly reduced while maintaining reasonable performance, especially in application scenarios that are very sensitive to power consumption.

[0045] See also Figure 2 Exemplarily, before waking up the SRAM sub-block currently being accessed according to the current access address of the access pointer, the method includes:

[0046] According to the split granularity and the wake-up time, a plurality of preset wake-up addresses are determined; each of the SRAM sub-blocks corresponds to a preset wake-up address, and the address difference between adjacent preset wake-up addresses is equal to the split granularity.

[0047] The split granularity is obtained by dividing the total depth of the SRAM by the number of split blocks, that is, the depth of each sub-block; and the wake-up time refers to the time required from detecting the need to wake up the next sub-block to actually completing the wake-up operation. This time needs to be short enough to ensure that it does not affect performance, but it cannot be too short to avoid frequent wake-up and sleep resulting in additional power consumption.

[0048] The preset wake-up address is an address set to wake up the next sub-block in advance. Each SRAM sub-block has a preset wake-up address, which indicates the location of the next sub-block that should be woken up when the access is about to exceed the range of the current sub-block.

[0049] For applications based on fifo or frame buffer, the access address changes continuously and incrementally. Assuming that the total depth of SRAM is 1024 address units, it is divided into 4 sub-blocks, then the depth of each sub-block is 256 address units. If we set the wake-up time to 10 address units, then: the preset wake-up address of the first sub-block (0 to 255 addresses) is 246 (i.e. 256-10). The preset wake-up address of the second sub-block (256 to 511 addresses) is 506 (i.e. 512-10). And so on, determine the preset wake-up address for subsequent sub-blocks.

[0050] In this embodiment, it is necessary to monitor the current access address of the access pointer. When the access address is close to the preset wake-up address of a sub-block, preparations for waking up the next sub-block begin. When the access address reaches the preset wake-up address, the next sub-block is woken up. At the same time, if the current sub-block is no longer accessed, it is put into a dormant state. In this way, it can be ensured that the next sub-block is woken up in time when the access is about to exceed the range of the current sub-block, while reducing power consumption as much as possible. This method is particularly suitable for application scenarios that are sensitive to power consumption, such as mobile devices and embedded systems.

[0051] Exemplarily, the determining of a plurality of preset wake-up addresses according to the split granularity and the wake-up time specifically includes:

[0052] According to the split granularity, a maximum depth corresponding to each of the SRAM sub-blocks is determined.

[0053] The difference between the maximum depth and the wake-up time is used as a preset wake-up address of the SRAM sub-block.

[0054] If the depth N of a single SRAM sub-block is used as the split granularity, then the next SRAM block can be woken up in advance when the access address is Nm, 2N-m, 3N-m, etc. The wake-up time m can be selected to meet the preset minimum wake-up time. In particular, m=1, that is, wake up one cycle in advance.

[0055] A deeper low power state (such as SD relative to SLP) saves more power but also requires a longer wake-up time. Therefore, when the pointer switches across areas, the area to be accessed needs to be woken up in advance.

[0056] Exemplarily, before determining a plurality of preset wake-up addresses, the method includes:

[0057] The minimum wake-up time is determined according to the sleep mode of the SRAM sub-block.

[0058] A natural number that is less than or equal to the minimum wake-up time is selected as the wake-up time.

[0059] The wake-up time is the time from detecting the need to wake up the next sub-block to actually completing the wake-up operation. This time needs to be short enough to ensure that performance is not affected, but not too short to avoid frequent wake-up and sleep resulting in additional power consumption. Determine the minimum wake-up time based on how the SRAM sub-block sleeps. This may involve reading the technical specification document of the SRAM to understand the time required to go from the sleep state to the active state. Choose a natural number less than or equal to the minimum wake-up time as the wake-up time. This step ensures that the wake-up time is fast enough while minimizing unnecessary wake-up operations.

[0060] Exemplarily, determining the number of split blocks according to the PPA performance parameter of the SRAM specifically includes:

[0061] According to the PPA performance parameter of the SRAM, an area function of the SRAM area with respect to the number of split blocks and a power consumption function of the SRAM power consumption with respect to the number of split blocks are determined.

[0062] The number of split blocks is determined according to the intersection of the area function and the power consumption function.

[0063] The more physical split blocks, the better. PPA performance needs to be considered comprehensively. Generally speaking, the higher the integration, the smaller the area. For example, a sram with a depth of 8192 can be implemented with 128x64, that is, 64 srams with a depth of 128. Usually, no splitting is done, that is, the area of ​​a whole sram of 8192 is smaller than the sum of the areas of 64 srams with a depth of 128 (because it can achieve a higher integration). Although from the perspective of power consumption, the more split blocks there are, the higher the power consumption benefit, but when the area overhead caused by this is greater than the power consumption benefit, it will no longer be cost-effective to make a finer-grained split. Therefore, the granularity of the split is a trade-off choice of the overall PPA performance that comprehensively considers the area and power consumption. From a mathematical point of view, the area benefit is a decreasing function of the number of split blocks, and the power consumption benefit is an increasing function of the number of split blocks. A simple splitting principle is that the split granularity corresponding to the intersection of these two function curves is the maximum split granularity that can be selected in the application. The number of split blocks determined in the end is not greater than the maximum split granularity.

[0064] The area function describes how the total area of ​​the SRAM changes with the number of blocks. This function may not be linear because it is affected by many factors, such as the increase in the area of ​​the control circuitry for each sub-block.

[0065] The power consumption function describes how the total power consumption of the SRAM changes with the number of sub-blocks. This function usually decreases as the number of sub-blocks increases, because more sub-blocks can reduce unnecessary power consumption.

[0066] Then determine the area function and power consumption function: Based on the PPA performance parameters of SRAM, construct the area function A(N)A(N)A(N) and the power consumption function P(N)P(N)P(N), where N represents the number of split blocks.

[0067] Solve the intersection of the area function and the power consumption function: Find the intersection of the area function A(N)A(N)A(N) and the power consumption function P(N)P(N)P(N), that is, the value of N that satisfies A(N)=P(N). This intersection indicates that a balance point has been reached between area and power consumption, making the total area and power consumption of the SRAM at a relatively ideal level.

[0068] The number of split blocks N that makes the area function and the power consumption function equal is selected as the optimal number of split blocks.

[0069] Through the above steps, we can determine the optimal number of split blocks based on the SRAM PPA performance parameter, thereby minimizing power consumption and area while ensuring performance. This method is very suitable for application scenarios that are sensitive to power consumption and area, such as mobile devices and high-performance computing systems.

[0070] Compared with the prior art, the embodiment of the present invention provides an SRAM wake-up method, which determines the optimal number of splits based on the PPA (performance, power consumption, area) performance parameters of the SRAM, calculates the size of each sub-block according to the total depth of the SRAM and the number of split blocks, and splits them. When the access pointer points to a sub-block, only the sub-block is woken up; after the access is completed, the sub-block re-enters the sleep state. The correct sub-block is ensured to be woken up by presetting the wake-up address.

[0071] This application greatly reduces unnecessary power consumption by waking up only the part that needs to be accessed currently. Since the wakeup and sleep of the sub-blocks are dynamic, the impact on performance is minimized. In practice, the split granularity and wakeup strategy can be adjusted according to the needs of the application.

[0072] An embodiment of the present application provides an SRAM wake-up device, including: a determination module, a splitting module and a wake-up module.

[0073] The determination module is used to determine the number of split blocks according to the PPA performance parameter of the SRAM.

[0074] The splitting module is used to obtain the splitting granularity according to the depth of the SRAM and the number of split blocks, and then split the blocks to form a plurality of SRAM sub-blocks.

[0075] The wake-up module is used to wake up the SRAM sub-block currently being accessed according to the current access address of the access pointer, so that other SRAM sub-blocks are in sleep mode; when the current access address is consistent with the preset wake-up address of the SRAM sub-block currently being accessed, wake up the next SRAM sub-block.

[0076] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the system described above can refer to the corresponding process in the aforementioned method embodiment and will not be described again here.

[0077] Exemplarily, a preset module is also included, which is used to determine several preset wake-up addresses according to the split granularity and the wake-up time; each SRAM sub-block corresponds to a preset wake-up address, and the address difference between adjacent preset wake-up addresses is equal to the split granularity.

[0078] Exemplarily, the preset module includes a first preset unit, configured to determine a maximum depth corresponding to each of the SRAM sub-blocks according to the split granularity; and use a difference between the maximum depth and the wake-up time as a preset wake-up address of the SRAM sub-block.

[0079] Exemplarily, the preset module further includes: a second preset unit, configured to: determine a minimum wake-up time according to the sleep mode of the SRAM sub-block; and select a natural number less than or equal to the minimum wake-up time as the wake-up time.

[0080] Exemplarily, the confirmation module includes a confirmation unit, which is used to:

[0081] According to the PPA performance parameter of the SRAM, an area function of the SRAM area with respect to the number of split blocks and a power consumption function of the SRAM power consumption with respect to the number of split blocks are determined;

[0082] The number of split blocks is determined according to the intersection of the area function and the power consumption function.

[0083] Compared with the prior art, the embodiment of the present invention provides an SRAM wake-up device, which determines the optimal number of splits based on the PPA (performance, power consumption, area) performance parameters of the SRAM, calculates the size of each sub-block according to the total depth of the SRAM and the number of split blocks, and splits them. When the access pointer points to a sub-block, only the sub-block is woken up; after the access is completed, the sub-block re-enters the dormant state. The correct sub-block is ensured to be woken up by presetting the wake-up address.

[0084] This application greatly reduces unnecessary power consumption by waking up only the part that needs to be accessed currently. Since the wakeup and sleep of the sub-blocks are dynamic, the impact on performance is minimized. In practice, the split granularity and wakeup strategy can be adjusted according to the needs of the application.

[0085] An embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium includes a stored computer program, wherein when the computer program is executed, the device where the computer-readable storage medium is located is controlled to execute the SRAM wake-up method as described above.

[0086] The computer device may be a computing device such as a smart phone, a tablet computer, a desktop computer, and a cloud server. The computer device may include, but is not limited to, a processor and a memory. Those skilled in the art will appreciate that the figure is merely an example of a computer device and does not constitute a limitation on the computer device, and may include more or fewer components than shown in the figure, or a combination of certain components, or different components, such as input and output devices, network access devices, etc.

[0087] The processor may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor, etc.

[0088] In some embodiments, the memory may be an internal storage unit of the computer device, such as a hard disk or memory of the computer device. In other embodiments, the memory may also be an external storage device of the computer device, such as a plug-in hard disk, a smart memory card (Smart Media Card, SMC), a secure digital (Secure Digital, SD) card, a flash card (Flash Card), etc. equipped on the computer device. Further, the memory may also include both an internal storage unit of the computer device and an external storage device. The memory is used to store an operating system, an application program, a boot loader (BootLoader), data, and other programs, such as the program code of the computer program, etc. The memory may also be used to temporarily store data that has been output or is to be output.

[0089] An embodiment of the present application provides a computer program product. When the computer program product is run on a computer device, the computer device implements the steps in the above-mentioned method embodiments when executing the computer device.

[0090] In several embodiments provided in the present application, it is understood that each box in the flow chart or block diagram can represent a module, a program segment or a part of a code, and the module, a program segment or a part of a code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from that marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved.

[0091] If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product is stored in a storage medium and includes several instructions for a computer device to perform all or part of the steps of the methods described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0092] The above is a preferred embodiment of the present invention. It should be pointed out that a person skilled in the art can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications are also considered to be within the scope of protection of the present invention.

Claims

1. SRAM wake-up method, characterized in that, include: Determine the number of split blocks according to the PPA performance parameter of SRAM; According to the depth of the SRAM and the number of split blocks, a split granularity is obtained and then split to form a plurality of SRAM sub-blocks; Waking up the SRAM sub-block currently being accessed according to the current access address of the access pointer, and putting the other SRAM sub-blocks into sleep; When the current access address is consistent with the preset wake-up address of the SRAM sub-block currently accessed, the next SRAM sub-block is woken up.

2. The SRAM wake-up method according to claim 1, characterized in that: Before waking up the SRAM sub-block currently being accessed according to the current access address of the access pointer, the method includes: According to the split granularity and the wake-up time, a plurality of preset wake-up addresses are determined; each of the SRAM sub-blocks corresponds to a preset wake-up address, and the address difference between adjacent preset wake-up addresses is equal to the split granularity.

3. The SRAM wake-up method as claimed in claim 2, characterized in that: The determining of a plurality of preset wake-up addresses according to the split granularity and the wake-up time specifically includes: Determine the maximum depth corresponding to each of the SRAM sub-blocks according to the split granularity; The difference between the maximum depth and the wake-up time is used as a preset wake-up address of the SRAM sub-block.

4. The SRAM wake-up method as claimed in claim 2, characterized in that: Before determining a plurality of preset wake-up addresses, the method includes: Determining a minimum wake-up time according to the sleep mode of the SRAM sub-block; A natural number that is less than or equal to the minimum wake-up time is selected as the wake-up time.

5. The SRAM wake-up method according to claim 1, characterized in that: Determining the number of split blocks according to the PPA performance parameter of the SRAM specifically includes: According to the PPA performance parameter of the SRAM, an area function of the SRAM area with respect to the number of split blocks and a power consumption function of the SRAM power consumption with respect to the number of split blocks are determined; The number of split blocks is determined according to the intersection of the area function and the power consumption function. 6.SRAM wake-up device, characterized in that, include: A determination module, used for determining the number of split blocks according to the PPA performance parameter of the SRAM; A splitting module, used for performing splitting after obtaining a splitting granularity according to the depth of the SRAM and the number of split blocks, to form a plurality of SRAM sub-blocks; A wake-up module, used for waking up the SRAM sub-block currently being accessed according to the current access address of the access pointer, so that the other SRAM sub-blocks are in dormancy; When the current access address is consistent with the preset wake-up address of the SRAM sub-block currently accessed, the next SRAM sub-block is woken up.

7. The SRAM wake-up device as claimed in claim 6, characterized in that: It also includes a preset module, which is used to determine a number of preset wake-up addresses according to the split granularity and the wake-up time; each SRAM sub-block corresponds to a preset wake-up address, and the address difference between adjacent preset wake-up addresses is equal to the split granularity.

8. The SRAM wake-up device as claimed in claim 7, characterized in that: The preset module includes a first preset unit, which is used to determine the maximum depth corresponding to each of the SRAM sub-blocks according to the split granularity; and use the difference between the maximum depth and the wake-up time as the preset wake-up address of the SRAM sub-block.

9. The SRAM wake-up device as claimed in claim 6, characterized in that: The preset module also includes: a second preset unit, which is used to: determine a minimum wake-up time according to the sleep mode of the SRAM sub-block; and select a natural number less than or equal to the minimum wake-up time as the wake-up time.

10. The SRAM wake-up device as claimed in claim 6, characterized in that: The confirmation module includes a confirmation unit, which is used to: According to the PPA performance parameter of the SRAM, an area function of the SRAM area with respect to the number of split blocks and a power consumption function of the SRAM power consumption with respect to the number of split blocks are determined; The number of split blocks is determined according to the intersection of the area function and the power consumption function.

Images