Instruction compiling method of graphics processor, electronic equipment and storage medium

Abstract

The invention discloses an instruction compiling method of a graphics processor, electronic equipment and a storage medium, and the method comprises the steps: receiving a kernel function registered by an application program and a submitted instruction code file when the application program initializes an interface under a programming model architecture for the first time; generating a first function handle in real time, and sending the first function handle to the application program to complete initialization of an interface under the programming model architecture; compiling the instruction code file into an instruction code set offline; storing the instruction code set and compiling information generated during offline compiling of the instruction code file in a preset cache library; uploading the instruction code set to a graphics processor under a non-programming model architecture to obtain a second function handle; and recording a mapping relationship between the first function handle and the second function handle in a preset interface management module. According to the method, the interface is quickly initialized, and the compiling instruction code file is fully compiled in an offline state to obtain better compiling information, so that the compiling efficiency and quality are improved.

Description

Technical Field

[0001] The present invention relates to the field of heterogeneous conversion technology, and in particular to an instruction compilation method for a graphics processor, an electronic device and a storage medium. Background Art

[0002] When the upper-level application and the lower-level GPU (graphics processing unit) are not of the same architecture, instruction compilation is required when the two interact. For example, CUDA is a parallel programming framework. Currently, only one company's GPU supports this framework. Therefore, heterogeneous instruction compilation is required between GPUs of different architectures to implement heterogeneous instruction calls.

[0003] In the traditional heterogeneous instruction compilation and execution system, the most widely implemented architecture conversion in the industry, CUDA program conversion to DTK instructions, is used as an example to illustrate. As shown in the figure below, CUDA calls are divided into two types. The first type is API calls, which do not contain instruction code files. This is the form of most calls. When processing, you only need to consider the correspondence between API functions, data structures, pointer types, and main entities. The second type is the compilation of instruction code files, which basically uses the LLVM framework system to compile instruction code files into instruction code sets supported by another framework system.

[0004] The biggest problem with this is that the instruction code file is compiled in real time, and the real-time compilation time is short, which makes it impossible to fully run the optimized compilation method, that is, the optimal instruction code file cannot be obtained, resulting in slow running of the system after the final compilation. Summary of the invention

[0005] In order to solve the above technical problem, the present invention provides an instruction compilation method for a graphics processor, an electronic device and a storage medium.

[0006] A first aspect of the present invention provides an instruction compiling method for a graphics processor, comprising:

[0007] When the application program initializes the interface under the programming model architecture for the first time, receiving the kernel function registered by the application program and the instruction code file submitted;

[0008] Generating a first function handle in real time, and sending the first function handle to the application program to complete initialization of the interface under the programming model architecture;

[0009] Offline compiling the instruction code file into an instruction code set;

[0010] Storing the instruction code set and compilation information generated when the instruction code file is compiled offline in a preset cache library;

[0011] Uploading the instruction code set to a graphics processor that is not under the programming model architecture to obtain a second function handle;

[0012] The mapping relationship between the first function handle and the second function handle is recorded in a preset interface management module.

[0013] A second aspect of the present invention provides an instruction compiling device for a graphics processor, the device comprising:

[0014] An information acquisition module, used to receive the kernel function registered by the application and the instruction code file submitted when the application initializes the interface under the programming model architecture for the first time;

[0015] An interface initialization module, used for generating a first function handle in real time, and sending the first function handle to the application program to complete initialization of the interface under the programming model architecture;

[0016] An offline compiling module, used for compiling the instruction code file into an instruction code set offline;

[0017] A storage module, used for storing the instruction code set and compilation information generated when the instruction code file is compiled offline in a preset cache library;

[0018] A function handle acquisition module, used for uploading the instruction code set to a graphics processor under a non-programming model architecture to obtain a second function handle;

[0019] A mapping relationship recording module is used to record the mapping relationship between the first function handle and the second function handle in a preset interface management module.

[0020] A third aspect of the present invention provides an electronic device, the electronic device comprising:

[0021] at least one processor; and

[0022] a memory communicatively connected to the at least one processor; wherein,

[0023] The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can execute the instruction compilation method of the graphics processor as described in the first aspect above.

[0024] A fourth aspect of the present invention provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the instruction compiling method for a graphics processor as described in the first aspect above is implemented.

[0025] In the instruction compilation method of the above-mentioned graphics processor, when the application program initializes the interface under the programming model architecture for the first time, the kernel function registered by the application program and the instruction code file submitted are received, and the first function handle generated in real time is sent to the application program to complete the initialization of the interface under the programming model architecture, so that the interface can be initialized quickly, saving the time of interface initialization. The instruction code file is compiled into an instruction code set offline; the instruction code set and the compilation information generated when the instruction code file is compiled offline are stored in a preset cache library; there is sufficient time to compile the compiled instruction code file offline, and better compilation information can be obtained, thereby improving the compilation efficiency and quality. The instruction code set is uploaded to the graphics processor under the non-programming model architecture to obtain the second function handle; the mapping relationship between the first function handle and the second function handle is recorded in the preset interface management module, and heterogeneous instruction calls can be made based on the mapping relationship.

[0026] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0028] Figure 1 The invention provides a heterogeneous instruction compilation and execution system in the prior art.

[0029] Figure 2 The invention is a flowchart of a method for compiling instructions for a graphics processor provided by an embodiment of the present invention.

[0030] Figure 3 It is a structural diagram of a heterogeneous compilation execution system in the present invention provided by an embodiment of the present invention.

[0031] Figure 4 The invention is a flowchart of a method for compiling instructions for a graphics processor provided by an embodiment of the present invention.

[0032] Figure 5 It is a structural diagram of an instruction compiling device for a graphics processor provided by an embodiment of the present invention.

[0033] Figure 6 It is a structural schematic diagram of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0034] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0035] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present invention described herein can cover sequential implementations other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0036] The CUDA programming model allows programmers to define kernels as C functions, and compile using new syntax each time a function is called. The runtime is introduced in the compilation workflow, which provides C functions executed on the host to allocate and release device memory, transfer data between host memory and device memory, manage systems with multiple devices, etc. In the prior art, reference Figure 1 , Figure 1 A heterogeneous instruction compilation and execution system in the prior art is described below. Figure 1 , take the architecture conversion of a single framework CUDA program into DTK instructions as an example to illustrate, Figure 1 As shown, CUDA calls are divided into two cases:

[0037] One is through the driver API call (CUDA API), which is built on the API module and does not contain the instruction code file (PTX). This is the vast majority of calling forms. When processing, you only need to consider the API function correspondence, data structure correspondence, pointer type correspondence, and main entity correspondence. Most applications do not use the driver API because they do not require an additional level of control, and when using the runtime, context and module management are implicit, resulting in more concise code.

[0038] The other is the real-time compilation of instruction code files (PTX), which basically uses LLVM (such as gfx9 or gfx10 series) to compile the instruction code files into instruction code sets supported by the DTK framework, and then upload the instruction code sets to the graphics processor (DCU) under the DTK framework. Kernel functions can be written in the CUDA instruction set structure, which is called an instruction code file and is usually compiled in C language.

[0039] In both cases, nvcc must be used to compile the kernel function into binary code before it can be executed on the device. Since the instruction code file is compiled in real time, the time taken is short and the optimized compilation cannot be fully executed, resulting in a slow running speed of the system after the final compilation.

[0040] In order to solve the problem that the optimization compilation of the real-time compilation instruction code file in the prior art cannot be fully executed, the present invention provides an instruction compilation method for a graphics processor. Figure 2 , showing a flow chart of an instruction compilation method for a graphics processor provided by an embodiment of the present invention. This embodiment is applicable to the case of converting instruction code files for different architectures. The method can be executed by an instruction compilation device for a graphics processor. The instruction compilation device for the graphics processor can be implemented in the form of hardware and / or software. The instruction compilation device for the graphics processor can be configured in an electronic device.

[0041] like Figure 2 As shown, the method includes:

[0042] S201. When the application program initializes the interface under the programming model architecture for the first time, the kernel function registered by the application program and the instruction code file submitted are received.

[0043] S202: Generate a first function handle in real time, and send the first function handle to the application program to complete the initialization of the interface under the programming model architecture.

[0044] The application is an application under the CUDA architecture. The compilation process of the instruction code file is optimized to improve the binary code generated after the kernel function PTX is compiled. The PTX is submitted in the API interface to be compiled into binary code for upload, and the function handle is obtained. Then, the function handle is used to call and execute, with a sufficient interval in between. In addition, in order to achieve a certain compilation optimization effect, it is usually necessary to call and execute the function handle multiple times. In particular, in commercial CUDA programs, kernel functions, especially key kernel functions, are often executed multiple times, but this takes up more execution time, making the interface initialization efficiency low.

[0045] Therefore, in this embodiment, the initialization of the application usually occurs in scenarios such as application installation and porting. Considering that the user usually does not need to use the application immediately during initialization, when the interface of the CUDA application needs to be initialized, the first function handle is generated in real time. The first function handle can also be a pre-set default function handle. Then, the first function handle is sent to the application first to quickly complete the interface initialization and improve the initialization efficiency.

[0046] S203 , compile the instruction code file into an instruction code set offline.

[0047] Figure 3 Schematic diagram of the structure of the heterogeneous compilation execution system in the present invention. Figure 3 As shown, in the heterogeneous compilation and execution system of the present invention, a vGPU (virtual graphics processor) is added. The vGPU is used to buffer and record the CUDA API. A cache library of kernel functions is also added. The cache library caches the compilation information, execution information, etc. of the PTX (instruction code file) to perform offline compilation optimization.

[0048] Compile the instruction code file into an instruction code set offline. Specifically, the operating status of the central processing unit can be queried; if the operating status is idle, the central processing unit is called offline to compile the instruction code file into an instruction code set. During the idle period of the CPU (central processing unit), start the PTX real-time compilation work, perform fully optimized offline compilation on the real-time compiled PTX function, compile the instruction code file into a code form that can be recognized by the target model architecture (i.e., the model architecture corresponding to the graphics processor of the non-programming model architecture in S205), and obtain the instruction code set. The instruction code set is in the form of binary code.

[0049] S204: Storing the instruction code set and the compilation information generated when the instruction code file is compiled offline in a preset cache library.

[0050] Among them, the compilation information includes function name, PTX source code, etc.

[0051] S205 , uploading the instruction code set to a graphics processor under the non-programming model architecture to obtain a second function handle.

[0052] Assume that the programming model architecture is the first end, and the non-programming model architecture is the second end opposite to the programming model architecture. Initially, the instruction code set uploads the instruction code set to the graphics processor under the non-programming model architecture to obtain a second function handle.

[0053] S206: Record a mapping relationship between the first function handle and the second function handle in a preset interface management module.

[0054] The first function handle is a false function handle, and the second function handle is a true function handle. By mapping the relationship between the two, the initialization phase of real-time compilation and the offline optimization phase can be independent of each other and associated with each other. This can not only quickly complete the interface initialization, but also make full use of the offline time to fully compile the instruction code file and obtain a higher quality instruction code set.

[0055] In an optional embodiment, the compilation information includes a priority, the priority of the instruction code set compiled offline is the first level, the priority of the instruction code set compiled in real-time is the second level, and the first level is the highest level. Since offline compilation usually has sufficient time to compile a binary code file with a certain quality, the quality of the instruction code set obtained after offline compilation is usually higher than the quality of the instruction code set obtained during real-time compilation. Therefore, the priority of the instruction code set compiled offline is set higher than the priority of the instruction code set compiled in real-time.

[0056] In an optional embodiment, if Figure 4 As shown, the instruction compilation method of the graphics processor also includes the following steps:

[0057] S401. When an application calls an interface under a programming model architecture, a first function handle submitted by the application is received, and a compilation status of an instruction code file is queried in a cache library according to compilation information.

[0058] The application uses the basic calling method of the kernel function (lanuchkernel) to call the interface under the programming model architecture. The kernel function can be written in the CUDA instruction set structure called PTX (instruction code file). It is usually more efficient to use C language. The instruction code set obtained after compiling the instruction code file is the kernel function. To call the interface under the programming model architecture, you must first obtain the corresponding kernel function.

[0059] The compilation status of the instruction code file represents the compilation quality of the instruction code file. In this embodiment, the compilation quality corresponding to the compilation status is arranged from high to low as follows: compiled and uploaded, compiled and not uploaded, and not compiled and not uploaded.

[0060] S402: If the compilation status is compiled and uploaded, convert the first function handle into a second function handle according to the mapping relationship in the interface management module.

[0061] If the compilation status is compiled and uploaded, it means that the instruction code file has been fully compiled, and the compiled instruction code set has been uploaded to the graphics processor under the non-programming model architecture. In this case, the second function handle already exists in the cache library and there is a mapping relationship between the first function handle and the second function handle. Therefore, the interface can be called based on this information, and the first function handle can be converted into the corresponding second function handle in the interface management module based on the mapping relationship.

[0062] S403: Run the kernel function according to the second function handle to call the graphics processor under the non-programming model architecture.

[0063] When the second function handle is obtained, the kernel function can be run according to the second function handle to call the graphics processor under the non-programming model architecture to complete the interface call.

[0064] S404: If the compilation status is compiled and not uploaded, read one of the instruction code sets in the cache library according to the compilation information.

[0065] After executing S404, execute S407-S408.

[0066] Specifically, if the number of instruction code sets in the cache library is 1, the instruction code set is selected for subsequent operations. If the number of instruction code sets in the cache library is multiple, the instruction code sets are selected according to their priorities, and the instruction code set with the highest priority is selected for subsequent operations.

[0067] S405: If the compilation status is not compiled and not uploaded, compile the instruction code file into an instruction code set in real time.

[0068] If the compilation status is not compiled and not uploaded, it means that the instruction code file has not been fully compiled. In this case, the second function handle does not exist in the cache library, and there is no mapping relationship between the first function handle and the second function handle. Therefore, it is currently in the application stage and an interface call is required. Therefore, real-time compilation is required to compile the instruction code file into an instruction code set.

[0069] S406: Storing the instruction code set and the compilation information generated when the instruction code file is compiled in real time in a preset cache library.

[0070] After the instruction code set is obtained through real-time compilation, the instruction code set and the compilation information generated when the instruction code file is compiled in real time are stored in the cache library, so that the cache library has a fully compiled instruction code set and a mapping relationship between the first function handle and the second function handle, compilation information, etc.

[0071] S407: Upload the instruction code set to the graphics processor under the non-programming model architecture to obtain a second function handle.

[0072] Before executing this step, the instruction code set in the cache library has not been uploaded, so the instruction code set is uploaded to the graphics processor under the non-programming model architecture to obtain a second function handle.

[0073] S408. Record a mapping relationship between the first function handle and the second function handle in a preset interface management module.

[0074] The instruction code set corresponds to the first function handle and also to the second function handle. Therefore, the mapping relationship between the first function handle and the second function handle can be obtained and recorded in the interface management module (API management module). When the interface management module needs to call the interface, it can quickly determine the second function handle corresponding to the first function handle based on the mapping relationship and perform function conversion, and then start the core function normally.

[0075] The cache library is provided with a fully compiled instruction code set, a mapping relationship between the first function handle and the second function handle, compilation information, etc.

[0076] After executing S408, the process returns to executing S402.

[0077] In this embodiment, when calling an interface in a specific application, whether the instruction code file needs to be compiled in real time is determined by the compilation status of the instruction code file, which can ensure that the instruction code file can be fully compiled, thereby improving the compilation quality and program running speed.

[0078] In order to verify the beneficial effects of the instruction compilation method for a graphics processor of the present invention, a comparative test was conducted on the instruction compilation method for a graphics processor through experiments.

[0079] Hardware setup: Two servers, operating system Kylin Linux V10 (SP2), the server contains four HygonC86 738532-core, 8 DCU Z100L (32G video memory). Each GPU has 3840 computing cores and 32GB GDDR4 video memory. The two servers are connected by Gigabit network.

[0080] Test procedure: In order to ensure the extensiveness and typicality of the test, the ResNET50 and Mask-RCNN models of the TensorFlow framework, the Wensheng graph model Stable Diffusion, and the large model LLaMA2-7B were selected as heterogeneous simulation test cases.

[0081] Test method: The overall test method uses the running result comparison method. The test program uses the CUDA version (CUDA11). The test comparison program uses the HIP version compiled by DTK (version 24.04.1). The compilation target architecture is gfx908. It runs in the DTK environment, and the physical device and network device remain unchanged. The test results are shown in the following table.

[0082] Table 1: Test results data table under different frameworks

[0083]

[0084] As can be seen from the table above, based on the DCU hardware, most of the test results have reached or are close to the performance of native DTK programs. Partly due to significant optimization effects, the execution efficiency exceeds the performance of native applications by 103% or even 150%.

[0085] In one embodiment, see Figure 5 , shows a schematic diagram of the structure of an instruction compilation device for a graphics processor provided by an embodiment of the present invention. Figure 5 As shown, the device comprises:

[0086] The information acquisition module 501 is used to receive the kernel function registered by the application and the instruction code file submitted when the application initializes the interface under the programming model architecture for the first time;

[0087] An interface initialization module 502, used to generate a first function handle in real time, and send the first function handle to the application to complete initialization of the interface under the programming model architecture;

[0088] An offline compiling module 503, used for offline compiling the instruction code file into an instruction code set;

[0089] The storage module 504 is used to store the instruction code set and the compilation information generated when the instruction code file is compiled offline in a preset cache library;

[0090] A function handle acquisition module 505, configured to upload the instruction code set to a graphics processor not under the programming model architecture to obtain a second function handle;

[0091] The mapping relationship recording module 506 is used to record the mapping relationship between the first function handle and the second function handle in a preset interface management module.

[0092] Optionally, the offline compilation module 503 includes:

[0093] The operation status query submodule is used to query the operation status of the central processing unit;

[0094] The offline compiling submodule is used for offline calling the central processing unit to compile the instruction code file into an instruction code set if the running state is idle.

[0095] Optionally, the compilation information includes a priority, and the priority of the instruction code set compiled offline is the first level.

[0096] Optionally, the instruction compiling device of the graphics processor further includes:

[0097] An interface calling module, configured to receive the first function handle submitted by the application when the application calls the interface under the programming model architecture, and query the compilation status of the instruction code file in the cache library according to the compilation information;

[0098] a function handle conversion module, configured to convert the first function handle into the second function handle according to the mapping relationship in the interface management module if the compilation status is compiled and uploaded;

[0099] The graphics processor calling module is used to run the kernel function according to the second function handle to call the graphics processor under a non-programming model architecture.

[0100] Optionally, the instruction compiling device of the graphics processor further includes:

[0101] An instruction code set reading module, configured to read one of the instruction code sets in the cache library according to the compilation information if the compilation status is compiled and not uploaded;

[0102] An instruction code set uploading module, used to upload the instruction code set to a graphics processor not under the programming model architecture, to obtain a second function handle;

[0103] A mapping relationship acquisition module is used to record the mapping relationship between the first function handle and the second function handle in a preset interface management module; and return the content of the execution function handle conversion module.

[0104] Optionally, the instruction code set reading module includes:

[0105] A priority determination submodule, used for reading the priority of each instruction code set recorded in the compilation information in the cache library;

[0106] The instruction code set reading submodule is used to read the instruction code set with the highest current priority from the cache library; wherein the priority includes a first level and a second level, and the first level is higher than the second level.

[0107] Optionally, the instruction compiling device of the graphics processor further includes:

[0108] A real-time compiling module, used for compiling the instruction code file into an instruction code set in real time if the compiling status is not compiled and not uploaded;

[0109] The compilation result storage module is used to store the instruction code set and the compilation information generated when the instruction code file is compiled in real time in a preset cache library; and execute the content of the instruction code set upload module.

[0110] Optionally, the compilation information includes a priority, and the priority of the instruction code set compiled in real time is the second level.

[0111] The instruction compiling device for a graphics processor provided in an embodiment of the present invention can execute the instruction compiling method for a graphics processor provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of executing the instruction compiling method for a graphics processor.

[0112] See also Figure 6 , shows a schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workbenches, personal digital assistants, blade servers, mainframe computers, and other suitable computers. The electronic device may also represent various forms of mobile devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present invention described and / or claimed herein.

[0113] like Figure 6 As shown, the electronic device 10 includes at least one processor 11, and a memory connected to the at least one processor 11, such as a read-only memory (ROM) 12, a random access memory (RAM) 13, etc., wherein the memory stores a computer program that can be executed by at least one processor, and the processor 11 can perform various appropriate actions and processes according to the computer program stored in the read-only memory (ROM) 12 or the computer program loaded from the storage unit 18 to the random access memory (RAM) 13. In the RAM 13, various programs and data required for the operation of the electronic device 10 can also be stored. The processor 11, the ROM 12, and the RAM 13 are connected to each other through a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0114] A number of components in the electronic device 10 are connected to the I / O interface 15, including: an input unit 16, such as a keyboard, a mouse, etc.; an output unit 17, such as various types of displays, speakers, etc.; a storage unit 18, such as a disk, an optical disk, etc.; and a communication unit 19, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 19 allows the electronic device 10 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0115] The processor 11 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. The processor 11 executes the various methods and processes described above, such as the instruction compilation method of the graphics processor.

[0116] In some embodiments, the instruction compilation method of the graphics processor may be implemented as a computer program, which is tangibly contained in a computer-readable storage medium, such as a storage unit 18. In some embodiments, part or all of the computer program may be loaded and / or installed on the electronic device 10 via the ROM 12 and / or the communication unit 19. When the computer program is loaded into the RAM 13 and executed by the processor 11, one or more steps of the instruction compilation method of the graphics processor described above may be performed. Alternatively, in other embodiments, the processor 11 may be configured to execute the instruction compilation method of the graphics processor in any other appropriate manner (e.g., by means of firmware).

[0117] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0118] Computer programs for implementing the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that when the computer program is executed by the processor, the functions / operations specified in the flow chart and / or block diagram are implemented. The computer program may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0119] In the context of the present invention, a computer readable storage medium may be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, device, or equipment. Alternatively, a computer readable storage medium may be a machine readable signal medium. More specific examples of machine readable storage media may include electrical connections based on one or more lines, portable computer disks, hard disks, random access memories (RAM), read-only memories (ROM), erasable programmable read-only memories (EPROM or flash memory), optical fibers, portable compact disk read-only memories (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0120] To provide interaction with a user, the systems and techniques described herein may be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and a pointing device (e.g., a mouse or trackball) through which the user can provide input to the electronic device. Other types of devices may also be used to provide interaction with the user; for example, the feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form (including acoustic input, voice input, or tactile input).

[0121] The systems and techniques described herein may be implemented in a computing system that includes backend components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes frontend components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such backend components, middleware components, or frontend components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), a blockchain network, and the Internet.

[0122] A computing system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The client and server relationship is generated by computer programs running on the corresponding computers and having a client-server relationship with each other. The server may be a cloud server, also known as a cloud computing server or cloud host, which is a host product in the cloud computing service system to solve the defects of difficult management and weak business scalability in traditional physical hosts and VPS services.

[0123] An embodiment of the present invention further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the instruction compilation method of the graphics processor provided by any embodiment of the present invention is implemented.

[0124] In the process of implementation, the computer program product can be written in one or more programming languages ​​or a combination thereof to perform the computer program code of the present invention, including object-oriented programming languages, such as Java, Smalltalk, C++, and conventional procedural programming languages, such as "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a separate software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or can be connected to an external computer (for example, using an Internet service provider to connect through the Internet).

[0125] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0126] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for compiling instructions for a graphics processor, characterized in that: include: When the application program initializes the interface under the programming model architecture for the first time, receiving the kernel function registered by the application program and the instruction code file submitted; Generating a first function handle in real time, and sending the first function handle to the application program to complete initialization of the interface under the programming model architecture; Offline compiling the instruction code file into an instruction code set; Storing the instruction code set and compilation information generated when the instruction code file is compiled offline in a preset cache library; Uploading the instruction code set to a graphics processor that is not under the programming model architecture to obtain a second function handle; The mapping relationship between the first function handle and the second function handle is recorded in a preset interface management module.

2. The method according to claim 1, characterized in that The offline compiling of the instruction code file into an instruction code set includes: Query the operating status of the CPU; If the running state is idle, the central processing unit is called offline to compile the instruction code file into an instruction code set.

3. The method according to claim 1, characterized in that: The compilation information includes a priority, and the priority of the instruction code set compiled offline is the first level.

4. The method according to any one of claims 1 to 3, characterized in that Also includes: When the application calls the interface under the programming model architecture, receiving the first function handle submitted by the application, and querying the compilation status of the instruction code file in the cache library according to the compilation information; If the compilation status is compiled and uploaded, converting the first function handle into the second function handle according to the mapping relationship in the interface management module; The kernel function is executed according to the second function handle to call a graphics processor that is not in the programming model architecture.

5. The method according to claim 4, characterized in that Also includes: If the compilation status is compiled and not uploaded, reading one of the instruction code sets in the cache library according to the compilation information; Uploading the instruction code set to a graphics processor that is not under the programming model architecture to obtain a second function handle; Recording the mapping relationship between the first function handle and the second function handle in a preset interface management module; returning to execute if the compilation status is edited and uploaded, converting the first function handle into the second function handle according to the mapping relationship in the interface management module.

6. The method according to claim 5, characterized in that The step of reading one of the instruction code sets in the cache according to the compilation information comprises: In the cache library, reading the priority of each instruction code set recorded in the compilation information; The instruction code set with the highest current priority is read from the cache library; wherein the priority includes a first level and a second level, and the first level is higher than the second level.

7. The method according to claim 4, characterized in that Also includes: If the compilation status is not compiled and not uploaded, compiling the instruction code file into an instruction code set in real time; Storing the instruction code set and compilation information generated when the instruction code file is compiled in real time in a preset cache library; Uploading the instruction code set to a graphics processor that is not under the programming model architecture to obtain a second function handle; Recording the mapping relationship between the first function handle and the second function handle in a preset interface management module; returning to execute if the compilation status is edited and uploaded, converting the first function handle into the second function handle according to the mapping relationship in the interface management module.

8. The method according to claim 7, characterized in that The compilation information includes a priority, and the priority of the instruction code set compiled in real time is the second level.

9. An electronic device, characterized in that: The electronic device comprises: at least one processor; and a memory communicatively connected to the at least one processor; wherein, The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can execute the instruction compiling method for a graphics processor according to any one of claims 1 to 8.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the instruction compiling method for a graphics processor according to any one of claims 1 to 8 is implemented.

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