Controller and system for processing interrupt request

Abstract

The invention discloses a controller and a system for processing an interrupt request, and belongs to the technical field of computers. Wherein the controller is used for, in response to a detected interrupt request with an interrupt identifier, determining a target processor cluster corresponding to the interrupt request; determining a transmission path of the interrupt request, wherein the transmission path comprises a target processor cluster and a first interrupt node; a first identifier corresponding to the interrupt identifier is stored in a first memory, the first memory is used for the first interrupt node to query the first memory according to the received interrupt identifier to obtain the first identifier corresponding to the interrupt identifier, and forwarding of the interrupt request is realized according to the first identifier, so that the target processor cluster processes the interrupt request. By configuring the first memory, the first interrupt node can quickly and flexibly route the interrupt request according to the first memory, so that the processing efficiency of the interrupt request is improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of computer technology, and in particular to a controller and a system for processing interrupt requests. Background Art

[0002] In the field of computer technology, there is an interrupt mechanism. When an emergency event occurs in a peripheral device, an interrupt request is sent to a processor cluster. The processor cluster interrupts other requests currently being executed according to the interrupt request, and processes the interrupt request with priority, thereby promptly resolving the emergency event that occurred in the peripheral device. As a result, the processor cluster does not need to poll peripheral devices and other components to see if an emergency event occurs, which is conducive to improving the performance of the processor cluster. How to enable the processor cluster to flexibly and efficiently process interrupt requests has become a problem worthy of attention. Summary of the invention

[0003] The embodiment of the present application provides a controller and a system for processing interrupt requests, which can be used to enable a processor cluster to flexibly and efficiently process interrupt requests. The technical solution provided by the embodiment of the present application includes the following aspects.

[0004] In a first aspect, a controller is provided, the controller being used to: in response to detecting an interrupt request, determine a target processor cluster corresponding to the interrupt request in one or more processor clusters included in an integrated circuit, the interrupt request having an interrupt identifier, the integrated circuit also comprising an interrupt circuit coupled to the one or more processor clusters, the interrupt circuit comprising a multi-level interrupt node; determine a transmission path of the interrupt request, the transmission path comprising the target processor cluster and a first interrupt node in the multi-level interrupt nodes; store a first identifier corresponding to the interrupt identifier in a first memory, the first memory being used for the first interrupt node to query the first memory according to the interrupt identifier after receiving the interrupt request, to obtain the first identifier corresponding to the interrupt identifier, and to perform any one of the following processes according to the first identifier: when the first identifier indicates a second interrupt node in the multi-level interrupt nodes, sending the interrupt request to the target processor cluster through the second interrupt node so that the target processor cluster processes the interrupt request; or, when the first identifier indicates the target processor cluster, directly sending the interrupt request to the target processor cluster so that the target processor cluster processes the interrupt request.

[0005] In an exemplary embodiment, the transmission path also includes a third interrupt node in the multi-level interrupt node, and the controller is also used to: store a second identifier corresponding to the interrupt identifier in a second memory, and the second memory is used for the third interrupt node to query the second memory according to the interrupt identifier after receiving the interrupt request, obtain the second identifier corresponding to the interrupt identifier, and send the interrupt request to the first interrupt node indicated by the second identifier.

[0006] In an exemplary embodiment, the controller is also used to: store a third identifier corresponding to the interrupt identifier in a third memory, the third memory is used by the third interrupt node to query the third memory according to the interrupt identifier to obtain the third identifier corresponding to the interrupt identifier, in response to the value of the third identifier indicating that the third interrupt node is authorized to send the interrupt request to the first interrupt node, query the second memory according to the interrupt identifier to obtain the second identifier corresponding to the interrupt identifier.

[0007] In an exemplary embodiment, the controller is also used to: store a fourth identifier corresponding to the second identifier in a fourth memory, the fourth memory is used by the third interrupt node to query the fourth memory according to the second identifier to obtain the fourth identifier corresponding to the second identifier, and in response to the value of the fourth identifier indicating that the first interrupt node is authorized to receive the interrupt request, send the interrupt request to the first interrupt node.

[0008] In an exemplary embodiment, the controller is also used to: in response to the first interrupt node being in an abnormal state, determine that the value of the fourth identifier indicates that the first interrupt node is not authorized to receive the interrupt request; in response to the first interrupt node returning to a normal state within a first time, update the fourth memory so that the value of the fourth identifier indicates that the first interrupt node is authorized to receive the interrupt request; in response to the first interrupt node not returning to a normal state within the first time, update the second memory and the fourth memory to update the first interrupt node and the target processor cluster included in the transmission path.

[0009] In an exemplary embodiment, the controller is also used to: store a fifth identifier corresponding to the interrupt identifier in a fifth memory, and the fifth memory is used by the first interrupt node to query the fifth memory according to the interrupt identifier to obtain the fifth identifier corresponding to the interrupt identifier; wherein, in response to the value of the fifth identifier indicating that the first interrupt node is authorized to send the interrupt request to other interrupt nodes, the first identifier indicates the second interrupt node.

[0010] In an exemplary embodiment, the controller is also used to: store a sixth identifier corresponding to the first identifier in a sixth memory, the sixth memory is used by the first interrupt node to query the sixth memory according to the first identifier to obtain the sixth identifier corresponding to the first identifier, and in response to the value of the sixth identifier indicating that the second interrupt node is authorized to receive the interrupt request, send the interrupt request to the target processor cluster through the second interrupt node.

[0011] In an exemplary embodiment, the controller is also used to: in response to the second interrupt node being in an abnormal state, determine that the value of the sixth identifier indicates that the second interrupt node is not authorized to receive the interrupt request; in response to the second interrupt node returning to a normal state within a second time, update the sixth memory so that the value of the sixth identifier indicates that the second interrupt node is authorized to receive the interrupt request; in response to the second interrupt node not returning to a normal state within the second time, update the first memory and the sixth memory to update the second interrupt node and the target processor cluster included in the transmission path.

[0012] In an exemplary embodiment, the interrupt request is an MSI (message signaled interrupt) type interrupt request, and the controller is also used to: store a fifth identifier corresponding to the interrupt identifier in a fifth memory, and the fifth memory is used by the first interrupt node to query the fifth memory according to the interrupt identifier to obtain the fifth identifier corresponding to the interrupt identifier; wherein, in response to the value of the fifth identifier indicating that the first interrupt node is not authorized to send the interrupt request to the other interrupt nodes, the first identifier indicates the target processor cluster.

[0013] In an exemplary embodiment, the controller is used to: read a seventh memory to obtain topology information, wherein the topology information indicates a topological relationship between the multi-level interrupt nodes and the one or more processor clusters; and determine a transmission path of the interrupt request according to the topology information.

[0014] In a second aspect, a method for processing an interrupt request is provided, the method comprising:

[0015] In response to detecting an interrupt request, determining a target processor cluster corresponding to the interrupt request in one or more processor clusters included in the integrated circuit, the interrupt request having an interrupt identifier, the integrated circuit further comprising an interrupt circuit coupled to the one or more processor clusters, the interrupt circuit comprising a multi-level interrupt node;

[0016] Determining a transmission path of the interrupt request, the transmission path including the target processor cluster and a first interrupt node in the multi-level interrupt nodes;

[0017] A first identifier corresponding to the interrupt identifier is stored in a first memory, and the first memory is used for the first interrupt node to query the first memory according to the interrupt identifier after receiving the interrupt request, to obtain the first identifier corresponding to the interrupt identifier, and to perform any one of the following processes according to the first identifier:

[0018] In a case where the first identifier indicates a second interrupt node in the multi-level interrupt nodes, sending the interrupt request to the target processor cluster through the second interrupt node, so that the target processor cluster processes the interrupt request;

[0019] Alternatively, when the first identifier indicates the target processor cluster, the interrupt request is directly sent to the target processor cluster so that the target processor cluster processes the interrupt request.

[0020] In an exemplary embodiment, the transmission path also includes a third interrupt node in the multi-level interrupt nodes, and the method also includes: storing a second identifier corresponding to the interrupt identifier in a second memory, and the second memory is used for the third interrupt node to query the second memory according to the interrupt identifier after receiving the interrupt request, to obtain the second identifier corresponding to the interrupt identifier, and to send the interrupt request to the first interrupt node indicated by the second identifier.

[0021] In an exemplary embodiment, the method further includes: storing a third identifier corresponding to the interrupt identifier in a third memory, the third memory being used by the third interrupt node to query the third memory according to the interrupt identifier to obtain the third identifier corresponding to the interrupt identifier, in response to the value of the third identifier indicating that the third interrupt node is authorized to send the interrupt request to the first interrupt node, querying the second memory according to the interrupt identifier to obtain the second identifier corresponding to the interrupt identifier.

[0022] In an exemplary embodiment, the method also includes: storing a fourth identifier corresponding to the second identifier in a fourth memory, the fourth memory being used by the third interrupt node to query the fourth memory according to the second identifier to obtain the fourth identifier corresponding to the second identifier, and in response to the value of the fourth identifier indicating that the first interrupt node is authorized to receive the interrupt request, sending the interrupt request to the first interrupt node.

[0023] In an exemplary embodiment, the method also includes: in response to the first interrupt node being in an abnormal state, determining that the value of the fourth identifier indicates that the first interrupt node is not authorized to receive the interrupt request; in response to the first interrupt node returning to a normal state within a first time, updating the fourth memory so that the value of the fourth identifier indicates that the first interrupt node is authorized to receive the interrupt request; in response to the first interrupt node not returning to a normal state within the first time, updating the second memory and the fourth memory to update the first interrupt node and the target processor cluster included in the transmission path.

[0024] In an exemplary embodiment, the method also includes: storing a fifth identifier corresponding to the interrupt identifier in a fifth memory, and the fifth memory is used by the first interrupt node to query the fifth memory according to the interrupt identifier to obtain the fifth identifier corresponding to the interrupt identifier; wherein, in response to the value of the fifth identifier indicating that the first interrupt node is authorized to send the interrupt request to other interrupt nodes, the first identifier indicates the second interrupt node.

[0025] In an exemplary embodiment, the method also includes: storing a sixth identifier corresponding to the first identifier in a sixth memory, the sixth memory being used by the first interrupt node to query the sixth memory according to the first identifier to obtain the sixth identifier corresponding to the first identifier, and in response to the value of the sixth identifier indicating that the second interrupt node is authorized to receive the interrupt request, sending the interrupt request to the target processor cluster through the second interrupt node.

[0026] In an exemplary embodiment, the method also includes: in response to the second interrupt node being in an abnormal state, determining that the value of the sixth identifier indicates that the second interrupt node is not authorized to receive the interrupt request; in response to the second interrupt node returning to a normal state within a second time, updating the sixth memory so that the value of the sixth identifier indicates that the second interrupt node is authorized to receive the interrupt request; in response to the second interrupt node not returning to a normal state within the second time, updating the first memory and the sixth memory to update the second interrupt node and the target processor cluster included in the transmission path.

[0027] In an exemplary embodiment, the interrupt request is an MSI type interrupt request, and the method further includes: storing a fifth identifier corresponding to the interrupt identifier in a fifth memory, and the fifth memory is used by the first interrupt node to query the fifth memory according to the interrupt identifier to obtain the fifth identifier corresponding to the interrupt identifier; wherein, in response to the value of the fifth identifier indicating that the first interrupt node is not authorized to send the interrupt request to the other interrupt nodes, the first identifier indicates the target processor cluster.

[0028] In an exemplary embodiment, determining the transmission path of the interrupt request includes: reading a seventh memory to obtain topology information, wherein the topology information indicates a topological relationship between the multi-level interrupt nodes and the one or more processor clusters; and determining the transmission path of the interrupt request based on the topology information.

[0029] According to a third aspect, a system for processing an interrupt request is provided. The system includes an integrated circuit and a controller provided by the first aspect or any exemplary embodiment of the first aspect.

[0030] The technical solution provided by the embodiments of the present application brings at least the following technical effects.

[0031] In the embodiment of the present application, since the first memory is configured, the first interrupt node can quickly determine the first identifier by querying the first memory after receiving the interrupt request, thereby realizing fast, accurate and flexible routing of the interrupt request according to the first identifier. It only takes a short time for the target processor cluster to receive (directly or through the second interrupt node) and process the interrupt request, thereby improving the processing efficiency of the interrupt request. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0033] Figure 1 is a schematic diagram of the structure of an integrated circuit provided in an embodiment of the present application;

[0034] Figure 2 is a schematic diagram of the structure of another integrated circuit provided in an embodiment of the present application;

[0035] Figure 3 is a schematic diagram of the structure of a seventh memory provided in an embodiment of the present application;

[0036] Figure 4is a schematic diagram of an address value provided in an embodiment of the present application;

[0037] Figure 5 is a schematic diagram of the structure of another integrated circuit provided in an embodiment of the present application;

[0038] Figure 6 is a schematic diagram of the structure of another integrated circuit provided in an embodiment of the present application;

[0039] Figure 7 is a schematic diagram of the structure of another integrated circuit provided in an embodiment of the present application;

[0040] Figure 8 is a schematic diagram of the structure of another integrated circuit provided in an embodiment of the present application;

[0041] Fig. 9 is a schematic diagram of the structure of a multi-chip system provided in an embodiment of the present application;

[0042] Fig.10 is a schematic diagram of a routing table provided in an embodiment of the present application;

[0043] Fig.11 This is a flowchart of a method for processing an interrupt request provided by an embodiment of the present application. DETAILED DESCRIPTION

[0044] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0045] The development of modern processors has brought about tremendous changes in various fields of human society. For example, modern processors have promoted the development of industrial automation, health care, scientific research, and entertainment. Among them, the processor is, for example, a CPU (central processing unit).

[0046] From the perspective of the instruction set architecture of modern processors, it can be divided into complex instruction sets and RISC (reduced instruction set computer). Complex instruction sets have first-mover advantages, such as X86. RISC has lower power consumption and higher frequency, and has gradually replaced complex instruction sets in recent years. RISC is ARM (advanced RISC machine) or RISC-V, etc., where V stands for five.

[0047] In addition, with the in-depth study of semiconductor technology and processor architecture, the performance of processors has also been improved to a certain extent, making it possible to design highly complex processor systems. In such a complex processor system, peripheral devices can be set according to actual needs to expand the functions of the complex processor system. Peripheral devices can be connected to the processor to help users access the complex processor system and use the additional functions of the complex processor system.

[0048] The interrupt system can improve the efficiency of the processor in processing interrupt requests sent by peripheral devices. After the interrupt system receives an interrupt request from a peripheral device, the processor will interrupt the currently executing program flow according to the interrupt request, and then select the appropriate interrupt handler to respond and process the interrupt request according to the source of the interrupt request.

[0049] In the RISC-V architecture, the traditional interrupt system only supports wired interrupt requests, such as processing wired interrupt requests through PLIC (platform level interrupt controller). However, in a complex processor system, the number of peripheral devices that send wired interrupt requests (i.e., the source of interrupt requests) is large, and the number of processors used to process wired interrupt requests is also large, which will make the layout and wiring of the entire interrupt system complex and reduce feasibility.

[0050] AIA (Advanced Interrupt Architecture) is a new interrupt system under the RISC-V architecture. AIA adds support for MSI type interrupt requests. In other words, in AIA, wired type interrupt requests are uniformly converted to MSI type interrupt requests to facilitate the processor to process interrupt requests. This conversion function is completed through APLIC (Advanced Platform Level Interrupt Controller).

[0051] However, when there are a large number of peripheral devices, the number of interrupt requests is also large. It takes a long time for APLIC to process a large number of interrupt requests. Therefore, after the peripheral device sends an interrupt request, the processor needs to wait for a long time to receive the interrupt request to be processed, which affects the processing efficiency of the interrupt request. In addition, in a multi-chip (die, also called bare die) scenario, that is, a complex multi-core scenario, the peripheral device may be located in a distant physical slot, and the die that receives the interrupt request and the die where the processor for processing the interrupt request is located may be different dies, so it is necessary to implement interrupt request processing in this scenario.

[0052] The present application embodiment provides an integrated circuit. Figure 1 As shown, the integrated circuit includes one or more processor clusters, and an interrupt circuit coupled to the one or more processor clusters, wherein the interrupt circuit includes a multi-level interrupt node.

[0053] Among them, multi-level interrupt nodes refer to at least two levels of interrupt nodes. At least two levels of interrupt nodes include interrupt nodes for interrupt control, and the interrupt nodes for interrupt control can have one level. The interrupt nodes for interrupt control are connected to the processor cluster, and the interrupt nodes for interrupt control are, for example, APLIC. At least two levels of interrupt nodes also include interrupt nodes for routing interrupt requests, and the interrupt nodes for routing interrupt requests can have one level or multiple levels. When there is one level of interrupt nodes for routing interrupt requests, the interrupt nodes for routing interrupt requests are connected to the interrupt nodes for interrupt control. When there are multiple levels of interrupt nodes for routing interrupt requests, the multiple levels of interrupt nodes for routing interrupt requests are connected in sequence, and one level of interrupt nodes for routing interrupt requests is connected to the interrupt nodes for interrupt control.

[0054] When a multi-level interrupt node includes two levels of interrupt nodes, the two levels of interrupt nodes are a first interrupt node and a second interrupt node, the first interrupt node is an interrupt node for routing interrupt requests, the first interrupt node includes a first memory, the second interrupt node is an interrupt node for performing interrupt control (e.g., APLIC), the first interrupt node, the second interrupt node, and the processor cluster are connected in sequence, the transmission direction of the interrupt request is, for example, the first interrupt node, the second interrupt node, and the processor cluster, and in the multi-level interrupt node, the second interrupt node is the next-level interrupt node of the first interrupt node.

[0055] When the multi-level interrupt node includes three-level interrupt nodes, the three-level interrupt nodes are the first interrupt node, the second interrupt node and the third interrupt node (also called the dispatcher). The first interrupt node and the third interrupt node are interrupt nodes for routing interrupt requests, and the second interrupt node is an interrupt node for performing interrupt control. Figure 2 As shown, the third interrupt node, the first interrupt node, the second interrupt node and the processor cluster are connected in sequence, and the transmission direction of the interrupt request is, for example, the third interrupt node, the first interrupt node, the second interrupt node and the processor cluster. In the multi-level interrupt node, the first interrupt node is the next-level interrupt node of the third interrupt node.

[0056] Of course, the multi-level interrupt node can also include a fourth interrupt node (for example, the third interrupt node is the next-level interrupt node of the fourth interrupt node), a fifth interrupt node (for example, the fourth interrupt node is the next-level interrupt node of the fifth interrupt node), etc. according to actual needs, and examples are not given one by one here. The integrated circuit provided in the embodiment of the present application has a tree-shaped topology structure of multi-level interrupt nodes and processor clusters. This topology structure has low complexity, strong scalability and strong robustness, which is conducive to realizing hierarchical management and routing of interrupt requests, improving routing efficiency, and thus improving the processing efficiency of interrupt requests.

[0057] The above-mentioned processor cluster may also be referred to as a processor cluster or a processor group. A processor cluster includes a configurable cache and multiple processor cores, and the cache is, for example, a level 3 (L3) cache. In one example, a processor cluster includes 4 cores and 1 L3 cache, that is, 4 cores share one L3 cache, that is, 4 cores and 1 L3 cache are called 1 CPU Cluster. When a CPU die includes 64 cores, it means that the CPU die includes 16 CPU Clusters.

[0058] The embodiment of the present application provides a controller, which is used to control the above integrated circuit, and then process the interrupt request. Exemplarily, an operating system can be run on the controller, and the integrated circuit can be controlled through the operating system.

[0059] The controller is used to determine, in response to detecting an interrupt request, a target processor cluster corresponding to the interrupt request in one or more processor clusters included in the integrated circuit, wherein the interrupt request has an interrupt identifier; determine a transmission path for the interrupt request, the transmission path including the target processor cluster and a first interrupt node in a multi-level interrupt node; store a first identifier corresponding to the interrupt identifier in a first memory, the first memory being used for the first interrupt node to query the first memory according to the interrupt identifier after receiving the interrupt request, to obtain the first identifier corresponding to the interrupt identifier, and to forward the interrupt request according to the first identifier, so that the target processor cluster processes the interrupt request.

[0060] Among them, the peripheral device can generate an interrupt request when an emergency occurs, and the interrupt request is used to request to improve the emergency event that occurred in the peripheral device. Exemplarily, the embodiment of the present application obtains the interrupt request generated by the peripheral device through HMI (hub management interface, HMI), and then performs address conversion on the interrupt request through IOMMU (input / output memory management unit, input and output memory management unit), and sends the interrupt request after address conversion to the first interrupt node, then the interrupt request received by the first interrupt node is the interrupt request after address conversion. Optionally, address conversion refers to converting a virtual address into a physical address.

[0061] In some embodiments, the peripheral device is a wired interrupt device, and the wired interrupt device sends a wired interrupt request. Exemplarily, the IOMMU can send a wired interrupt request to the first interrupt node through the first line, and the wired interrupt request has an interrupt identifier that is a line identifier of the first line.

[0062] In some other embodiments, the peripheral device is a PCI-E (peripheral component interconnect express) device, and the PCI-E device sends an MSI type interrupt request. Exemplarily, the IOMMU sends an MSI type interrupt request to the first interrupt node through a second line (different from the first line mentioned above), and the MSI type interrupt request has an interrupt identifier that is included in the MSI type interrupt request.

[0063] Optionally, an HMI for obtaining wired type interrupt requests is also referred to as wired HMI, and an HMI for obtaining MSI type interrupt requests is also referred to as PCI-E HMI. Wired HMI and PCI-E HMI may be collectively referred to as device HMI.

[0064] It can be seen that no matter what type of interrupt request the first interrupt node receives, the interrupt request has an interrupt identifier, and the interrupt identifier corresponds to the interrupt request one by one. In addition, each peripheral device may also have a device identifier, and the device identifier corresponds to the peripheral device one by one.

[0065] In some implementations, the interrupt request has a bound processor cluster (interrupt binding technology), and the controller uses the processor cluster bound to the interrupt request as the target processor cluster. For example, there is a correspondence between the interrupt identifier and the processor cluster, and the controller queries the correspondence according to the interrupt identifier of the interrupt request to obtain the processor cluster corresponding to the interrupt identifier, so that the queried processor cluster can be used as the target processor cluster.

[0066] In other implementations, the controller determines a target processor cluster based on the load conditions of each processor cluster in the multiple processor clusters. The target processor cluster is, for example, a processor cluster with a lower load rate in the multiple processor clusters. A lower load rate may mean that the load rate is lower than a load rate threshold.

[0067] After determining the target processor cluster, the transmission path of the interrupt request can be determined, and the transmission path is used to transmit the interrupt request from the initiator of the interrupt request (such as the above-mentioned peripheral device) to the target processor cluster, so that the target processor cluster can process the interrupt request. The transmission path includes the target processor cluster and the first interrupt node, that is, after the interrupt request is sent by the initiator, it can be transmitted to the target processor cluster through the route of the first interrupt node.

[0068] Exemplarily, the transmission path may include a third interrupt node in addition to the target processor cluster and the first interrupt node. That is, after the interrupt request is sent by the initiator, it may be first transmitted to the first interrupt node via the route of the third interrupt node, and then transmitted to the target processor cluster via the route of the first interrupt node. Of course, the transmission path may also include the fourth interrupt node, the fifth interrupt node, etc., which are not described in detail here.

[0069] In an exemplary embodiment, the controller is used to read the seventh memory to obtain topology information, where the topology information indicates a topological relationship between multi-level interrupt nodes and one or more processor clusters; and determine a transmission path for the interrupt request according to the topology information.

[0070] Optionally, the seventh memory is a read-only memory, such as a read-only register. In one example, the seventh memory includes: the number of third interrupt nodes, the number of first interrupt nodes corresponding to each third interrupt node, the number of second interrupt nodes corresponding to each first interrupt node, and reserved bits to reflect the above-mentioned topological information, so that the topological information can indicate the topological relationship between the multi-level interrupt nodes and one or more processor clusters, that is, indicate the topology of the above-mentioned integrated circuit.

[0071] See also Figure 3The seventh memory is represented by AIA number control (AIA number control, AIA_NUMCTRL) to control the number of nodes that each routing level can support. In an example, AIA_NUMCTRL is a 32-bit memory. Figure 3 As shown, the meaning of each bit in the 32-bit memory is as follows.

[0072] Bits 31 to 24 are reserved bits, and the values ​​of the reserved bits can all be 0.

[0073] The 23rd to 16th bits are DP_NODENUM, which represents the number of third interrupt nodes Dispatcher that the integrated circuit can support, and the number is 256, for example.

[0074] Bits 15 to 8 are AB_NODENUM, which represents the number of first interruption nodes Arbiter that each third interruption node Dispatcher can support. The number is 256, for example.

[0075] Bits 7 to 0 are AP_NODENUM, which represent the number of second interruption nodes that each first interruption node Arbiter can support. The number is 256, for example.

[0076] Optionally, the transmission path determined by the controller is in a first format, which is a format that the controller can recognize (or understand), and the transmission path includes the identifiers of each element present on the transmission path. The transmission path can also be abstracted into a second format, which is a format that the user can recognize. In one example, the controller can also recognize the second format. For example, the second format is in the format of an interrupt routing address value (IRAV). In an embodiment of the present application, the first interrupt node, the third interrupt node, and the second interrupt node can respectively have address values, and the interrupt routing address value can reflect the various interrupt nodes included in the transmission path. An exemplary structure of the address value can be found in Figure 4 .

[0077] exist Figure 4 In the address value, the address value includes four fields, namely LV.3, LV.2, LV.1 and LV.0 fields, and the levels of these four fields decrease in sequence. The 15th to 12th bits of the address value are the LV.3 field, the 11th to 8th bits are the LV.2 field, the 7th to 4th bits are the LV.1 field, and the 3rd to 0th bits are the LV.0 field. Each field represents a routing level. Figure 4In the example shown, each routing level can accommodate up to 16 child nodes, where the nodes at the last level are called leaf nodes. For example, the routing level represented by LV.3 includes 1 child node (such as 1 Dispatcher, the fourth interrupt node), the routing level represented by LV.2 includes 1 child node (such as 1 Dispatcher, the third interrupt node), the routing level represented by LV.1 includes 16 child nodes (such as 16 Arbiters, the first interrupt node), and the routing level represented by LV.0 includes 16 leaf nodes (such as 16 second interrupt nodes), then the integrated circuit includes a total of 256 leaf nodes.

[0078] It should be understood that Figure 4 The situation shown is only an example. The embodiment of the present application can change the total number of fields and the number of bits occupied by the fields according to the number of leaf nodes to meet actual needs. In the embodiment of the present application, there is no binding relationship between the routing level and the first interruption node or the third interruption node. For example, if the second interruption node is LV.0, the first interruption node directly connected to the second interruption node can be LV.1, or LV.2, etc., and the third interruption node connected to the first interruption node can be LV.2, or LV.3, etc., and so on.

[0079] Next, combine Figures 5 to 8 Give examples to illustrate several topological structures of integrated circuits.

[0080] The first topology, see Figure 5 , Figure 5 A 4-layer tree topology is shown.

[0081] There is only one LV.3 and LV.2, which are node A (the fourth interrupt node Dispatcher) and node B (the third interrupt node Dispatcher), and the interrupt routing address values ​​are 0.xxx and 0.0.xx, respectively, where x means ignore, that is, the routing level where x is located does not need to be considered.

[0082] There are two nodes of LV.1 connected to LV.2 node B, namely node C0 and node C1 (both are first interruption nodes Arbiter), and the interruption routing address values ​​are 0.0.0.x and 0.0.1.x respectively.

[0083] There are four nodes of LV.0 connected to LV.1 node C0, namely leaf nodes D0, D1, D2, and D3 (all APLIC). The interrupt routing address values ​​are 0.0.0.0, 0.0.0.1, 0.0.0.2, and 0.0.0.3 respectively.

[0084] There are three nodes of LV.0 connected to LV.1 node C1, namely leaf nodes D4, D5, and D6 (all APLIC). The interrupt routing address values ​​are 0.0.1.0, 0.0.1.1, and 0.0.1.2 respectively.

[0085] The second topology, see Figure 6 , Figure 6 A 3-layer tree topology is shown.

[0086] LV.3 has only one node, namely, node A (the third interrupt node Dispatcher), and the interrupt routing address value is 0.xxx.

[0087] There are two nodes of LV.2 connected to LV.3 node A, namely node B0 and node B1 (both are first interruption nodes Arbiter), and the interruption routing address values ​​are 0.0.xx and 0.1.xx respectively.

[0088] There are four nodes of LV.0 directly connected to LV.2 node B0, namely leaf nodes D0, D1, D2, and D3 (all APLIC). The interrupt routing address values ​​are 0.0.x.0, 0.0.x.1, 0.0.x.2, and 0.0.x.3 respectively.

[0089] There is only one LV.0 node directly connected to LV.2 node B1, namely leaf node D4 (APLIC), and the interrupt routing address value is 0.1.x.0.

[0090] The third topology, see Figure 7 , Figure 7 A 2-layer tree topology is shown.

[0091] LV.3 has only one node, namely, node A (the first interrupt node Arbiter), and the interrupt routing address value is 0.xxx.

[0092] There are four nodes of LV.0 directly connected to LV.3 node A, namely leaf nodes D0, D1, D2, and D3 (all APLIC). The interrupt routing address values ​​are 0.xx0, 0.xx1, 0.xx2, and 0.xx3 respectively.

[0093] The fourth topology, see Figure 8 , Figure 8 A composite topology is shown.

[0094] LV.3 has only one node, namely, node A (the branch for node B0 is the fourth interrupt node Dispatcher, the branch for node B1 is the third interrupt node Dispatcher, and the branch for node D7 is the first interrupt node Arbiter), and the interrupt routing address value is 0.xxx.

[0095] There are two nodes of LV.2 connected to LV.3 node A, namely node B0 (third interrupt node Dispatcher) and node B1 (first interrupt node Arbiter), and the interrupt routing address values ​​are 0.0.xx and 0.1.xx respectively.

[0096] There are two nodes of LV.1 connected to LV.2 node B0, namely nodes C0 and C1 (both are first interruption nodes Arbiter). The interruption routing address values ​​are 0.0.0.x and 0.0.1.x respectively.

[0097] There are three nodes of LV.0 connected to LV.1 node C1, namely leaf nodes D0, D1, and D2 (all APLIC). The interrupt routing address values ​​are 0.0.0.0, 0.0.0.1, and 0.0.0.2 respectively.

[0098] There are two nodes of LV.0 connected to LV.1 node C1, namely leaf nodes D3 and D4 (both are APLIC). The interrupt routing address values ​​are 0.0.1.0 and 0.0.1.1 respectively.

[0099] There are two nodes of LV.0 directly connected to LV.2 node B1, namely leaf nodes D5 and D6 (both are APLIC), and the interrupt routing address values ​​are 0.1.x.0 and 0.1.x.1 respectively.

[0100] There is only one LV.0 node directly connected to LV.3 node A, namely leaf node D7 (APLIC). The interrupt routing address value is 0.xx0.

[0101] According to the above description, the first memory AB_INTPROUTE[x] is used by the first interrupt node to query the first memory AB_INTPROUTE[x] according to the interrupt identifier after receiving the interrupt request, obtain the first identifier corresponding to the interrupt identifier, and forward the interrupt request according to the first identifier so that the target processor cluster receives and processes the interrupt request.

[0102] Optionally, the first memory may include multiple sub-memories, and the x in AB_INTPROUTE[x] is used to distinguish different sub-memories. The reason is that the storage space of each sub-memory is limited. When the number of interrupt identifiers is large, the storage space of one sub-memory may not be able to accommodate the first identifiers corresponding to all interrupt identifiers. Therefore, the embodiment of the present application may adopt multiple sub-memories to accommodate the first identifiers corresponding to all interrupt identifiers. Regardless of how many sub-memories the first memory includes, the interrupt identifier and the first identifier are in a one-to-one correspondence, and different sub-memories are used to store the first identifiers corresponding to different interrupt identifiers. The other memories mentioned below may also include multiple sub-memories, which will not be repeated in the embodiment of the present application.

[0103] Since the controller has determined the transmission path of the interrupt request in the integrated circuit, the memory used by each interrupt node (such as the first interrupt node and the third interrupt node, etc.) on the transmission path for routing the interrupt request can be configured, so that each interrupt node used to route the interrupt request can query the used memory after receiving the interrupt request to forward the interrupt request according to the transmission path, thereby ensuring that the target processor cluster can receive and process the interrupt request.

[0104] For example, the first interrupt node performs any of the following processes according to the first identifier: when the first identifier indicates the second interrupt node in the multi-level interrupt node, the interrupt request is sent to the target processor cluster through the second interrupt node so that the target processor cluster processes the interrupt request; or, when the first identifier indicates the target processor cluster, the interrupt request is directly sent to the target processor cluster so that the target processor cluster processes the interrupt request. That is, the first identifier satisfies any of the following conditions.

[0105] The first condition is that the first identifier indicates the target processor cluster. For this condition, the first identifier directly indicates the target processor cluster, so the first interrupt node can directly send an interrupt request to the target processor cluster. Wherein, directly sending an interrupt request to the target processor cluster means sending an interrupt request to the target processor cluster without passing through the second interrupt node. Exemplarily, this condition is applicable to the case where the interrupt request is an MSI type interrupt request.

[0106] In an exemplary embodiment, the controller is also used to: store a fifth identifier corresponding to the interrupt identifier in a fifth memory, the fifth memory is used by the first interrupt node to query the fifth memory according to the interrupt identifier to obtain the fifth identifier corresponding to the interrupt identifier, in response to the value of the fifth identifier indicating that the first interrupt node is not authorized to send an interrupt request to other interrupt nodes (for example, the second interrupt node at the next level), the first identifier indicates the target processor cluster.

[0107] Thus, the first interrupt node queries the second part of the first memory according to the interrupt identifier, obtains the first identifier, and directly sends an interrupt request to the target processor cluster indicated by the first identifier. Since the value of the fifth identifier indicates that the first interrupt node is not authorized to send an interrupt request to the second interrupt node at the next level of the first interrupt node, the first interrupt node can directly send an interrupt request to the target processor cluster according to the above description.

[0108] For example, the controller may store a fifth identifier corresponding to the interrupt identifier in the fifth memory AB_INTPCTRL[x], and the fifth identifier indicates that an interrupt request is not allowed to be sent to the second interrupt node at the next level of the first interrupt node. For example, if the interrupt identifier is 1, the fifth identifier corresponding to the interrupt identifier 1 may be stored in the first bit group (corresponding to the interrupt identifier 1) included in the fifth memory. The controller may also store a first identifier in the second part of the first memory, and the first identifier indicates a target processor cluster for processing interrupt requests. For example, if the interrupt identifier is 1 and the target processor cluster is 1, the first identifier indicating the target processor cluster 1 is stored in the first bit group (corresponding to the interrupt identifier 1) included in the second part of the first memory.

[0109] The second condition is that the first identifier indicates the second interrupt node, the second interrupt node corresponds to the target processor cluster, and the transmission path also includes the second interrupt node. For this condition, the first identifier indicates the second interrupt node, so the first interrupt node can send an interrupt request to the second interrupt node, and accordingly, the second interrupt node forwards the interrupt request to the target processor cluster, thereby realizing the sending of the interrupt request to the target processor cluster through the second interrupt node. Exemplarily, this condition can be applicable to the case where the interrupt request is a wired type interrupt request, and can also be applicable to the case where the interrupt request is an MSI type interrupt request.

[0110] In an exemplary embodiment, the controller is also used to: store a fifth identifier corresponding to the interrupt identifier in a fifth memory, the fifth memory is used by the first interrupt node to query the fifth memory according to the interrupt identifier to obtain the fifth identifier corresponding to the interrupt identifier, in response to the value of the fifth identifier indicating that the first interrupt node is authorized to send an interrupt request to other interrupt nodes (for example, the second interrupt node at the next level), and the first identifier indicates the second interrupt node.

[0111] Thus, the first interrupt node queries the first part of the first memory according to the interrupt identifier, thereby obtaining the first identifier, and sends an interrupt request to the target processor cluster through the second interrupt node indicated by the first identifier. Since the value of the fifth identifier indicates that the first interrupt node is authorized to send an interrupt request to the second interrupt node of the next level, the first interrupt node can directly send an interrupt request to the second interrupt node according to the above description, and the second interrupt node forwards the interrupt request to the target processor cluster.

[0112] Among them, if the interrupt request is a wired type interrupt request, the second interrupt node converts the wired type interrupt request into an MSI type interrupt request, and forwards the MSI type interrupt request to the target processor cluster. Alternatively, if the interrupt request is an MIS type interrupt request, the second interrupt node does not need to convert the MSI type interrupt request, and can transparently transmit the MSI type interrupt request to the target processor cluster.

[0113] For example, the controller may store a fifth identifier corresponding to the interrupt identifier in the fifth memory AB_INTPCTRL[x], and the fifth identifier indicates that an interrupt request is allowed to be sent to the second interrupt node at the next level of the first interrupt node. For example, if the interrupt identifier is 1, the fifth identifier corresponding to the interrupt identifier 1 may be stored in the first bit group (corresponding to the interrupt identifier 1) included in the fifth memory. The controller may also store a first identifier corresponding to the interrupt identifier in the first part of the first memory, and the first identifier is used to indicate the second interrupt node at the next level of the first interrupt node. For example, if the interrupt identifier is 1 and the second interrupt node is the second interrupt node 1, the first identifier indicating the second interrupt node 1 is stored in the first bit group (corresponding to the interrupt identifier 1) included in the first part of the first memory.

[0114] In the first condition above, the first identifier (indicating the target processor cluster) is located in the second part of the first memory, and in the second condition here, the first identifier (indicating the second interrupt node) is located in the first part of the first memory, because the two first identifiers indicate different elements. Optionally, the first part and the second part are different storage spaces in the same memory (i.e., the first memory), or the first part and the second part are different memories (i.e., the first memory includes different memories), which is not limited in the embodiment of the present application.

[0115] Exemplarily, the target processor cluster includes at least one processing core, and the target processor cluster can process the interrupt request sent by the second interrupt node through a reference processing core in the at least one processing core to improve emergency events occurring in the peripheral device.

[0116] When there is only one processing core in the target processor cluster, the processing core is the reference processing core. When there are multiple processing cores in the target processor cluster, the reference processing core can be a processing core specified by the controller among the multiple processing cores. For example, when a PCI-E device initiates an interrupt request (wired type or MSI type), the hypervisor (a virtualization controller) will allocate a reference processing core to the interrupt request based on the load of the processors included in the current multiple processor clusters to respond to the interrupt request.

[0117] Optionally, the second interrupt node corresponds to a reference register, which can also be configured by a controller. The reference register includes a processing core identifier corresponding to the interrupt identifier of the interrupt request. After the second interrupt node receives the interrupt request, it queries the reference register according to the interrupt identifier to obtain the processing core identifier corresponding to the interrupt identifier. The processing core indicated by the processing core identifier is the reference processing core used to process the interrupt request. The second interrupt node sends an interrupt request to the target processor cluster where the reference processing core is located, so that the reference processing core processes the interrupt request.

[0118] In an exemplary embodiment, the controller is also used to: store a sixth identifier corresponding to the first identifier in a sixth memory, the sixth memory is used for the first interrupt node to query the sixth memory according to the first identifier to obtain the sixth identifier corresponding to the first identifier, in response to the value of the sixth identifier indicating that the second interrupt node is authorized to receive the interrupt request, the interrupt request is sent to the target processor cluster through the second interrupt node indicated by the first identifier.

[0119] For example, the first interrupt node also uses the sixth memory AB_APCTRL[x], so the controller can store the sixth identifier corresponding to the first identifier (used to indicate the second interrupt node) in the sixth memory, and the sixth identifier is used to indicate whether the second interrupt node is allowed to receive the interrupt request. For example, the first identifier indicating the second interrupt node 1 is the first identifier 1, then the sixth identifier corresponding to the first identifier 1 is stored in the first bit group (corresponding to the first identifier 1) included in the sixth memory.

[0120] In an exemplary embodiment, the controller is also used to: in response to the second interrupt node being in an abnormal state, determine that the value of the sixth identifier indicates that the second interrupt node is not authorized to receive an interrupt request; in response to the second interrupt node returning to a normal state within a second time, update the sixth memory so that the value of the sixth identifier indicates that the second interrupt node is authorized to receive an interrupt request; in response to the second interrupt node not returning to a normal state within the second time, update the first memory and the sixth memory to update the second interrupt node and the target processor cluster included in the transmission path.

[0121] In response to the second interrupt node being in an abnormal state, for example, the occupancy rate of the target processor cluster corresponding to the second interrupt node is higher than a threshold, it is determined that the value of the sixth identifier indicates that the second interrupt node is not authorized to receive an interrupt request. It should be understood that the value of the sixth identifier can be switched according to actual conditions (whether the second interrupt node is in a normal state or an abnormal state), that is, the controller can modify the value of the sixth identifier according to actual conditions.

[0122] For example, if the occupancy rate of the target processor cluster is lower than the threshold within the second time, the second interrupt node recovers to a normal state within the second time, thereby updating the sixth memory so that the value of the sixth identifier indicates that the second interrupt node is authorized to receive interrupt requests.

[0123] For another example, if the occupancy rate of the target processor cluster is not lower than the threshold within the second time, the second interrupt node does not return to normal state within the second time, then the processor cluster that processes the interrupt request can be updated from the target processor cluster to another processor cluster, and the other processor cluster no longer corresponds to the second interrupt node that is not authorized to receive the interrupt request, but corresponds to another second interrupt node. Accordingly, the first memory (to indicate the other second interrupt nodes) and the sixth memory (to indicate whether the other second interrupt nodes are authorized to receive the interrupt request) need to be updated.

[0124] As mentioned above, in addition to the first interrupt node, the integrated circuit may also include a third interrupt node. Then the controller may also configure the memory used by the third interrupt node. See the following description for details.

[0125] In an exemplary embodiment, the controller is also used to: store a second identifier corresponding to the interrupt identifier in a second memory, and the second memory is used for the third interrupt node to query the second memory according to the interrupt identifier after receiving an interrupt request, obtain the second identifier corresponding to the interrupt identifier, and send an interrupt request to the first interrupt node indicated by the second identifier.

[0126] For example, the third interrupt node uses the second memory DP_INTPROUTE[x], so the controller can store the second identifier corresponding to the interrupt identifier in the second memory, and the second identifier is used to indicate the first interrupt node of the next level of the third interrupt node. For example, the interrupt identifier is 1, and the first interrupt node of the next level is the first interrupt node 1, then in the first bit group (corresponding to the interrupt identifier 1) included in the second memory, the second identifier indicating the first interrupt node 1 is stored.

[0127] In an exemplary embodiment, the controller is also used to: store a third identifier corresponding to the interrupt identifier in a third memory, the third memory is used for the third interrupt node to query the third memory according to the interrupt identifier to obtain the third identifier corresponding to the interrupt identifier, in response to the value of the third identifier indicating that the third interrupt node is authorized to send an interrupt request to the first interrupt node, query the second memory according to the interrupt identifier to obtain the second identifier corresponding to the interrupt identifier.

[0128] For example, the third interrupt node also uses the third memory DP_INTPCTRL[x], so the controller can store the third identifier corresponding to the interrupt identifier in the third memory, and the third identifier is used to indicate whether it is allowed to send an interrupt request to the first interrupt node of the next level of the third interrupt node. For example, if the interrupt identifier is 1, the third identifier corresponding to the interrupt identifier 1 is stored in the first bit group (corresponding to the interrupt identifier 1) included in the third memory. The third identifier can be determined according to actual conditions, and the embodiment of the present application does not limit this.

[0129] In an exemplary embodiment, the controller is also used to: store a fourth identifier corresponding to the second identifier in a fourth memory, the fourth memory is used for the third interrupt node to query the fourth memory according to the second identifier to obtain the fourth identifier corresponding to the second identifier, and in response to the value of the fourth identifier indicating that the first interrupt node is authorized to receive the interrupt request, send an interrupt request to the first interrupt node.

[0130] For example, the third interrupt node also uses the fourth memory DP_ABCTRL[x], so the controller can store the fourth identifier corresponding to the second identifier (used to indicate the first interrupt node) in the fourth memory, and the fourth identifier is used to indicate whether the first interrupt node is allowed to receive the interrupt request. For example, the second identifier indicating the first interrupt node 1 is the second identifier 1, then the fourth identifier corresponding to the second identifier 1 is stored in the first bit group (corresponding to the second identifier 1) included in the fourth memory.

[0131] In an exemplary embodiment, the controller is also used to: in response to the first interrupt node being in an abnormal state, determine that the value of the fourth identifier indicates that the first interrupt node is not authorized to receive an interrupt request; in response to the first interrupt node returning to a normal state within a first time, update the fourth memory so that the value of the fourth identifier indicates that the first interrupt node is authorized to receive an interrupt request; in response to the first interrupt node not returning to a normal state within the first time, update the second memory and the fourth memory to update the first interrupt node and the target processor cluster included in the transmission path.

[0132] In response to the first interrupt node being in an abnormal state, for example, the occupancy rate of the target processor cluster corresponding to the second interrupt node corresponding to the first interrupt node is higher than a threshold, it is determined that the value of the fourth identifier indicates that the first interrupt node is not authorized to receive an interrupt request. It should be understood that the value of the fourth identifier can be switched according to the actual situation (whether the first interrupt node is in a normal state or an abnormal state), that is, the controller can modify the value of the fourth identifier according to the actual situation.

[0133] For example, if the occupancy rate of the target processor cluster is lower than the threshold within the first time, the first interrupt node returns to normal state within the first time; or, if other processor clusters different from the target processor cluster are replaced within the first time, the target processor cluster and the other processor clusters correspond to different second interrupt nodes, but correspond to the same first interrupt node, then the first interrupt node also returns to normal state within the first time, and the fourth memory can be updated so that the value of the fourth identifier indicates that the first interrupt node is authorized to receive interrupt requests.

[0134] For another example, if the occupancy rate of the target processor cluster is not lower than the threshold within the first time, the processor cluster that processes the interrupt request may be updated from the target processor cluster to another processor cluster, the target processor cluster and the other processor cluster correspond to different second interrupt nodes, and the corresponding other processor clusters correspond to other first interrupt nodes different from the first interrupt node, and the first interrupt node does not return to normal state within the first time. Accordingly, the second memory (to indicate the other first interrupt nodes) and the fourth memory (to indicate whether the other first interrupt nodes are authorized to receive interrupt requests) need to be updated.

[0135] Next, combine Fig. 9 and Fig.10 The following examples illustrate the process of the controller configuring the memory and the integrated circuit routing the interrupt request. Fig. 9 This is an exemplary multi-DIE architecture that forms a SOC (system on chip). Fig. 9 In the , there are 4 dies, namely IO DIE 0, IO DIE 1, CPU DIE 0 and CPU DIE 0. D2D represents the communication module between different DIEs.

[0136] IO DIE 0 and IO DIE 1 include Device Hub and IOMMU respectively. The functions of Device Hub and IOMMU can be found in the above description and will not be described here.

[0137] CPU DIE 1 includes LV.3, LV.2 and LV.0 nodes, wherein LV.3 node is A node, LV.2 node is B1 node, LV.0 node is D5 node, D6 node and D7 node.

[0138] CPU DIE 0 includes LV.2, LV.1 and LV.0 nodes, wherein LV.2 node is B0 node, LV.1 node is C0 node and C1 node, LV.0 node is D0 node, D1 node, D2 node, D3 node and D4 node.

[0139] See also Fig.10, the peripheral device with device ID 0 sends interrupt request 0, and the address value corresponding to interrupt request 0 is 0.0.0.0, which means that the target processor cluster corresponding to interrupt request 0 is CPU Cluster 0. Based on this, the controller determines that the routing path corresponding to interrupt request 0 is node A, node B0, node C0, and node D0. Therefore, the controller configures the memory used by node A, node B0, and node C0 respectively, so that node A sends interrupt request 0 to node B0, node B0 sends interrupt request 0 to node C0, and node C0 sends interrupt request 0 to node D0. Then, interrupt request 0 can be sent from node D0 to CPUCluster 0, and CPU Cluster 0 processes the interrupt request 0. In this case, the processing of interrupt request 0 across CPUDIEs is realized, which is more flexible.

[0140] Continue to see Fig.10 , the peripheral device with device identification m+1 sends an interrupt request j, and the address corresponding to the interrupt request j is 0.1.x.1, which means that the target processor cluster corresponding to the interrupt request j is CPU Cluster 6. Based on this, the controller determines that the routing path corresponding to the interrupt request j is node A, node B1, and node D6. Therefore, the controller configures the memory used by node A and node B1 respectively, so that node A sends the interrupt request j to node B1, and node B1 sends the interrupt request j to node D6. Then the interrupt request j can be sent by node D6 to CPU Cluster 6, and CPU Cluster 6 processes the interrupt request j.

[0141] To sum up, in the embodiment of the present application, since the first memory is configured, the first interrupt node can quickly determine the first identifier by querying the first memory after receiving the interrupt request, thereby realizing fast, accurate and flexible routing of the interrupt request according to the first identifier. It only takes a short time for the target processor cluster to receive (directly receive, or receive through the second interrupt node) and process the interrupt request, thereby improving the processing efficiency of the interrupt request.

[0142] The present application also provides a method for processing an interrupt request, which can be applied to the controller described above. Fig.11 As shown, the method includes the following steps.

[0143] Step 1101, in response to detecting an interrupt request, determining a target processor cluster corresponding to the interrupt request in one or more processor clusters included in the integrated circuit, the interrupt request having an interrupt identifier, the integrated circuit also including an interrupt circuit coupled to the one or more processor clusters, the interrupt circuit including multiple levels of interrupt nodes.

[0144] Step 1102 , determining a transmission path of the interrupt request, where the transmission path includes a target processor cluster and a first interrupt node in a multi-level interrupt node.

[0145] In an exemplary embodiment, determining a transmission path of an interrupt request includes: reading a seventh memory to obtain topology information, where the topology information indicates a topological relationship between a multi-level interrupt node and one or more processor clusters; and determining the transmission path of the interrupt request according to the topology information.

[0146] Step 1103, storing a first identifier corresponding to the interrupt identifier in a first memory, the first memory is used for the first interrupt node to query the first memory according to the interrupt identifier after receiving the interrupt request, to obtain the first identifier corresponding to the interrupt identifier, and to perform any of the following processes according to the first identifier: when the first identifier indicates a second interrupt node in the multi-level interrupt node, sending an interrupt request to a target processor cluster through the second interrupt node so that the target processor cluster processes the interrupt request; or, when the first identifier indicates a target processor cluster, directly sending an interrupt request to the target processor cluster so that the target processor cluster processes the interrupt request.

[0147] In response to detecting an interrupt request, determining a target processor cluster corresponding to the interrupt request in one or more processor clusters included in the integrated circuit, the interrupt request having an interrupt identifier, the integrated circuit further comprising an interrupt circuit coupled to the one or more processor clusters, the interrupt circuit comprising a plurality of interrupt nodes;

[0148] Determine a transmission path of the interrupt request, the transmission path including a target processor cluster and a first interrupt node in a multi-level interrupt node;

[0149] The first identifier corresponding to the interrupt identifier is stored in the first memory. The first memory is used for the first interrupt node to query the first memory according to the interrupt identifier after receiving the interrupt request, obtain the first identifier corresponding to the interrupt identifier, and perform any one of the following processes according to the first identifier:

[0150] In the case where the first identifier indicates a second interrupt node in the multi-level interrupt node, sending an interrupt request to the target processor cluster through the second interrupt node, so that the target processor cluster processes the interrupt request;

[0151] Alternatively, when the first identifier indicates a target processor cluster, the interrupt request is directly sent to the target processor cluster so that the target processor cluster processes the interrupt request.

[0152] In an exemplary embodiment, the transmission path also includes a third interrupt node in the multi-level interrupt node, and the method also includes: storing a second identifier corresponding to the interrupt identifier in a second memory, and the second memory is used for the third interrupt node to query the second memory according to the interrupt identifier after receiving an interrupt request, obtain the second identifier corresponding to the interrupt identifier, and send an interrupt request to the first interrupt node indicated by the second identifier.

[0153] In an exemplary embodiment, the method also includes: storing a third identifier corresponding to the interrupt identifier in a third memory, the third memory being used by a third interrupt node to query the third memory according to the interrupt identifier to obtain the third identifier corresponding to the interrupt identifier, in response to the value of the third identifier indicating that the third interrupt node is authorized to send an interrupt request to the first interrupt node, querying the second memory according to the interrupt identifier to obtain a second identifier corresponding to the interrupt identifier.

[0154] In an exemplary embodiment, the method also includes: storing a fourth identifier corresponding to the second identifier in a fourth memory, the fourth memory being used by the third interrupt node to query the fourth memory according to the second identifier to obtain the fourth identifier corresponding to the second identifier, and in response to the value of the fourth identifier indicating that the first interrupt node is authorized to receive the interrupt request, sending an interrupt request to the first interrupt node.

[0155] In an exemplary embodiment, the method also includes: in response to the first interrupt node being in an abnormal state, determining that the value of the fourth identifier indicates that the first interrupt node is not authorized to receive an interrupt request; in response to the first interrupt node returning to a normal state within a first time, updating the fourth memory so that the value of the fourth identifier indicates that the first interrupt node is authorized to receive an interrupt request; in response to the first interrupt node not returning to a normal state within the first time, updating the second memory and the fourth memory to update the first interrupt node and the target processor cluster included in the transmission path.

[0156] In an exemplary embodiment, the method also includes: storing a fifth identifier corresponding to the interrupt identifier in a fifth memory, and the fifth memory is used by the first interrupt node to query the fifth memory according to the interrupt identifier to obtain the fifth identifier corresponding to the interrupt identifier; wherein, in response to the value of the fifth identifier indicating that the first interrupt node is authorized to send an interrupt request to other interrupt nodes, the first identifier indicates the second interrupt node.

[0157] In an exemplary embodiment, the method also includes: storing a sixth identifier corresponding to the first identifier in a sixth memory, the sixth memory being used by the first interrupt node to query the sixth memory according to the first identifier to obtain the sixth identifier corresponding to the first identifier, and in response to the value of the sixth identifier indicating that the second interrupt node is authorized to receive the interrupt request, sending the interrupt request to the target processor cluster through the second interrupt node.

[0158] In an exemplary embodiment, the method also includes: in response to the second interrupt node being in an abnormal state, determining that the value of the sixth identifier indicates that the second interrupt node is not authorized to receive an interrupt request; in response to the second interrupt node returning to a normal state within a second time, updating the sixth memory so that the value of the sixth identifier indicates that the second interrupt node is authorized to receive an interrupt request; in response to the second interrupt node not returning to a normal state within the second time, updating the first memory and the sixth memory to update the second interrupt node and the target processor cluster included in the transmission path.

[0159] In an exemplary embodiment, the interrupt request is an MSI type interrupt request, and the method also includes: storing a fifth identifier corresponding to the interrupt identifier in a fifth memory, and the fifth memory is used for the first interrupt node to query the fifth memory according to the interrupt identifier to obtain the fifth identifier corresponding to the interrupt identifier; wherein, in response to the value of the fifth identifier indicating that the first interrupt node is not authorized to send an interrupt request to other interrupt nodes, the first identifier indicates a target processor cluster.

[0160] It should be noted that Fig.11 The method shown belongs to the same concept as the controller embodiment above. Its specific implementation process and technical effects are detailed in the controller embodiment and will not be repeated here.

[0161] Illustratively, an embodiment of the present application further provides a system for processing an interrupt request, the system comprising the controller and integrated circuit described above.

[0162] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. The embodiments described in the above exemplary embodiments do not represent all embodiments consistent with the present application. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0163] It should be understood that the "plurality" mentioned in this article refers to two or more. The character " / " generally indicates that the objects before and after are in an "or" relationship.

[0164] The above description is only an exemplary embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the principles of the present application shall be included in the protection scope of the present application.

Claims

1. A controller, characterized in that: The controller is used to: In response to detecting an interrupt request, determining a target processor cluster corresponding to the interrupt request in one or more processor clusters included in the integrated circuit, the interrupt request having an interrupt identifier, the integrated circuit further comprising an interrupt circuit coupled to the one or more processor clusters, the interrupt circuit comprising a multi-level interrupt node; Determining a transmission path of the interrupt request, the transmission path including the target processor cluster and a first interrupt node in the multi-level interrupt nodes; A first identifier corresponding to the interrupt identifier is stored in a first memory, and the first memory is used for the first interrupt node to query the first memory according to the interrupt identifier after receiving the interrupt request, to obtain the first identifier corresponding to the interrupt identifier, and to perform any one of the following processes according to the first identifier: In a case where the first identifier indicates a second interrupt node in the multi-level interrupt nodes, sending the interrupt request to the target processor cluster through the second interrupt node, so that the target processor cluster processes the interrupt request; Alternatively, when the first identifier indicates the target processor cluster, the interrupt request is directly sent to the target processor cluster so that the target processor cluster processes the interrupt request.

2. The controller according to claim 1, characterized in that: The transmission path further includes a third interrupt node in the multi-level interrupt nodes, and the controller is further configured to: A second identifier corresponding to the interrupt identifier is stored in a second memory, and the second memory is used for the third interrupt node to query the second memory according to the interrupt identifier after receiving the interrupt request, obtain the second identifier corresponding to the interrupt identifier, and send the interrupt request to the first interrupt node indicated by the second identifier.

3. The controller according to claim 2, characterized in that: The controller is also used for: A third identifier corresponding to the interrupt identifier is stored in a third memory, and the third memory is used by the third interrupt node to query the third memory according to the interrupt identifier to obtain the third identifier corresponding to the interrupt identifier. In response to the value of the third identifier indicating that the third interrupt node is authorized to send the interrupt request to the first interrupt node, the second memory is queried according to the interrupt identifier to obtain a second identifier corresponding to the interrupt identifier.

4. The controller according to claim 2, characterized in that: The controller is also used for: A fourth identifier corresponding to the second identifier is stored in a fourth memory, and the fourth memory is used by the third interrupt node to query the fourth memory according to the second identifier to obtain the fourth identifier corresponding to the second identifier, and in response to the value of the fourth identifier indicating that the first interrupt node is authorized to receive the interrupt request, the interrupt request is sent to the first interrupt node.

5. The controller according to claim 4, characterized in that: The controller is also used for: In response to the first interrupt node being in an abnormal state, determining that a value of the fourth identifier indicates that the first interrupt node is not authorized to receive the interrupt request; In response to the first interrupt node recovering to a normal state within a first time, updating the fourth memory so that the value of the fourth identifier indicates that the first interrupt node is authorized to receive the interrupt request; In response to the first interrupt node not returning to a normal state within the first time, the second memory and the fourth memory are updated to update the first interrupt node and the target processor cluster included in the transmission path.

6. The controller according to any one of claims 1 to 5, characterized in that: The controller is also used for: storing a fifth identifier corresponding to the interrupt identifier in a fifth memory, wherein the fifth memory is used by the first interrupt node to query the fifth memory according to the interrupt identifier to obtain the fifth identifier corresponding to the interrupt identifier; In which, in response to the value of the fifth identifier indicating that the first interrupt node is authorized to send the interrupt request to other interrupt nodes, the first identifier indicates the second interrupt node.

7. The controller according to claim 6, characterized in that: The controller is also used for: A sixth identifier corresponding to the first identifier is stored in a sixth memory, and the sixth memory is used by the first interrupt node to query the sixth memory according to the first identifier to obtain the sixth identifier corresponding to the first identifier, and in response to the value of the sixth identifier indicating that the second interrupt node is authorized to receive the interrupt request, the interrupt request is sent to the target processor cluster through the second interrupt node.

8. The controller according to claim 7, characterized in that: The controller is also used for: In response to the second interrupt node being in an abnormal state, determining that a value of the sixth identifier indicates that the second interrupt node is not authorized to receive the interrupt request; In response to the second interrupt node recovering to a normal state within a second time, updating the sixth memory so that the value of the sixth identifier indicates that the second interrupt node is authorized to receive the interrupt request; In response to the second interrupt node not returning to a normal state within the second time, the first memory and the sixth memory are updated to update the second interrupt node and the target processor cluster included in the transmission path.

9. The controller according to any one of claims 1 to 5, characterized in that: The interrupt request is a message signal interrupt (MSI) type interrupt request, and the controller is further used for: storing a fifth identifier corresponding to the interrupt identifier in a fifth memory, wherein the fifth memory is used by the first interrupt node to query the fifth memory according to the interrupt identifier to obtain the fifth identifier corresponding to the interrupt identifier; In response to the value of the fifth identifier indicating that the first interrupt node is not authorized to send the interrupt request to the other interrupt nodes, the first identifier indicates the target processor cluster.

10. The controller according to any one of claims 1-5, 7 or 8, characterized in that: The controller is used to: Reading a seventh memory to obtain topology information, wherein the topology information indicates a topological relationship between the multi-level interrupt node and the one or more processor clusters; A transmission path of the interrupt request is determined according to the topology information.

11. A system for processing an interrupt request, characterized in that: The system comprises an integrated circuit and the controller according to any one of claims 1-10.

Images