Integrated circuit and method and system for processing interrupt request

Abstract

The invention discloses an integrated circuit and a method and system for processing an interrupt request, and belongs to the technical field of computers. An integrated circuit includes one or more processor clusters, and coupled interrupt circuitry. Wherein the interrupt circuit is used for receiving an interrupt request through a first interrupt node in the multiple levels of interrupt nodes, and querying the first memory according to an interrupt identifier of the interrupt request to obtain a first identifier corresponding to the interrupt identifier. And sending an interrupt request to the target processor cluster through the first interrupt node and the second interrupt node under the condition that the first identifier indicates the second interrupt node in the multiple levels of interrupt nodes, or sending the interrupt request to the target processor cluster through the first interrupt node under the condition that the first identifier indicates the target processor cluster, and processing the interrupt request by the target processor cluster. The first interrupt node quickly and flexibly routes the interrupt request according to the first memory, so that the processing efficiency of the interrupt request is improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of computer technology, and in particular to an integrated circuit, a method and a system for processing an interrupt request. Background Art

[0002] In the field of computer technology, there is an interrupt mechanism. In the interrupt mechanism, a peripheral device sends an interrupt request to a processor cluster when an emergency event occurs. After receiving the interrupt request, the processor cluster interrupts other requests currently being executed and processes the interrupt request first, thereby resolving the emergency event in a timely manner. As a result, the processor cluster does not need to poll peripheral devices and other components to see if an emergency event occurs, which is beneficial to improving the performance of the processor cluster. How to enable the processor cluster to handle interrupt requests flexibly and efficiently has become a problem worthy of attention. Summary of the invention

[0003] The embodiment of the present application provides an integrated circuit, a method and a system for processing an interrupt request, which can be used to enable a processor cluster to flexibly and efficiently process interrupt requests. The technical solution provided by the embodiment of the present application includes the following aspects.

[0004] In a first aspect, an integrated circuit is provided, comprising one or more processor clusters, and an interrupt circuit coupled to the one or more processor clusters, the interrupt circuit comprising a multi-level interrupt node, the interrupt circuit being used to: receive an interrupt request through a first interrupt node in the multi-level interrupt nodes, the interrupt request having an interrupt identifier; and query a first memory according to the interrupt identifier through the first interrupt node to obtain a first identifier corresponding to the interrupt identifier.

[0005] In a case where the first identifier indicates a second interrupt node in the multi-level interrupt nodes, the interrupt request is sent to a target processor cluster in the one or more processor clusters through the first interrupt node and the second interrupt node, so that the target processor cluster processes the interrupt request; or, in a case where the first identifier indicates the target processor cluster, the interrupt request is sent directly to the target processor cluster through the first interrupt node, so that the target processor cluster processes the interrupt request.

[0006] In an exemplary embodiment, the interrupt circuit is also used to: receive the interrupt request through a third interrupt node in the multi-level interrupt nodes; query the second memory according to the interrupt identifier through the third interrupt node to obtain a second identifier corresponding to the interrupt identifier; and send the interrupt request to the first interrupt node indicated by the second identifier through the third interrupt node.

[0007] In an exemplary embodiment, the interrupt circuit is further used to: query the third memory according to the interrupt identifier through the third interrupt node to obtain a third identifier corresponding to the interrupt identifier. The interrupt circuit is used to: query the second memory according to the interrupt identifier through the third interrupt node to obtain a second identifier corresponding to the interrupt identifier when the value of the third identifier indicates that the third interrupt node is authorized to send the interrupt request to the first interrupt node.

[0008] In an exemplary embodiment, the interrupt circuit is further configured to: query a fourth memory according to the second identifier through the third interrupt node to obtain a fourth identifier corresponding to the second identifier. The interrupt circuit is configured to: send the interrupt request to the first interrupt node through the third interrupt node when the value of the fourth identifier indicates that the first interrupt node is authorized to receive the interrupt request.

[0009] In an exemplary embodiment, the interrupt circuit is also used to: query the fifth memory according to the interrupt identifier through the first interrupt node to obtain a fifth identifier corresponding to the interrupt identifier; wherein, when the value of the fifth identifier indicates that the first interrupt node is authorized to send the interrupt request to other interrupt nodes, the first identifier indicates the second interrupt node.

[0010] In an exemplary embodiment, the interrupt circuit is further used to: query a sixth memory according to the first identifier through the first interrupt node to obtain a sixth identifier corresponding to the first identifier. In an exemplary embodiment, the interrupt circuit is used to: send the interrupt request to the target processor cluster through the first interrupt node and the second interrupt node when the value of the sixth identifier indicates that the second interrupt node is authorized to receive the interrupt request.

[0011] In an exemplary embodiment, the interrupt request is an MSI (Message Signaled Interrupt) type interrupt request; the interrupt circuit is also used to: query the fifth memory according to the interrupt identifier through the first interrupt node to obtain a fifth identifier corresponding to the interrupt identifier; wherein, when the value of the fifth identifier indicates that the first interrupt node is not authorized to send the interrupt request to other interrupt nodes, the first identifier indicates the target processor cluster.

[0012] In a second aspect, a method for processing an interrupt request is provided, the method comprising: receiving an interrupt request through a first interrupt node in a multi-level interrupt node, the interrupt request having an interrupt identifier; querying a first memory according to the interrupt identifier through the first interrupt node to obtain a first identifier corresponding to the interrupt identifier. In the case where the first identifier indicates a second interrupt node in the multi-level interrupt node, the interrupt request is sent to a target processor cluster in one or more processor clusters through the first interrupt node and the second interrupt node, so that the target processor cluster processes the interrupt request; or, in the case where the first identifier indicates the target processor cluster, the interrupt request is directly sent to the target processor cluster through the first interrupt node, so that the target processor cluster processes the interrupt request.

[0013] In an exemplary embodiment, the method also includes: receiving the interrupt request through a third interrupt node in the multi-level interrupt node; querying a second memory according to the interrupt identifier through the third interrupt node to obtain a second identifier corresponding to the interrupt identifier; and sending the interrupt request to the first interrupt node indicated by the second identifier through the third interrupt node.

[0014] In an exemplary embodiment, the method further includes: querying the third memory according to the interruption identifier through the third interruption node to obtain a third identifier corresponding to the interruption identifier. Querying the second memory according to the interruption identifier through the third interruption node includes: when the value of the third identifier indicates that the third interruption node is authorized to send the interruption request to the first interruption node, querying the second memory according to the interruption identifier through the third interruption node to obtain a second identifier corresponding to the interruption identifier.

[0015] In an exemplary embodiment, the method further includes: querying a fourth memory according to the second identifier through the third interrupt node to obtain a fourth identifier corresponding to the second identifier. The sending of the interrupt request to the first interrupt node indicated by the second identifier through the third interrupt node includes: sending the interrupt request to the first interrupt node through the third interrupt node when the value of the fourth identifier indicates that the first interrupt node is authorized to receive the interrupt request.

[0016] In an exemplary embodiment, the method further includes: querying a fifth memory according to the interrupt identifier through the first interrupt node to obtain a fifth identifier corresponding to the interrupt identifier; wherein, when the value of the fifth identifier indicates that the first interrupt node is authorized to send the interrupt request to other interrupt nodes, the first identifier indicates the second interrupt node.

[0017] In an exemplary embodiment, the method also includes: querying a sixth memory according to the first identifier through the first interrupt node to obtain a sixth identifier corresponding to the first identifier; sending the interrupt request to a target processor cluster in the one or more processor clusters through the first interrupt node and the second interrupt node, including: when the value of the sixth identifier indicates that the second interrupt node is authorized to receive the interrupt request, sending the interrupt request to the target processor cluster through the first interrupt node and the second interrupt node.

[0018] In an exemplary embodiment, the interrupt request is a message signal interrupt (MSI) type interrupt request; the method also includes: querying a fifth memory according to the interrupt identifier through the first interrupt node to obtain a fifth identifier corresponding to the interrupt identifier; wherein, when the value of the fifth identifier indicates that the first interrupt node is not authorized to send the interrupt request to other interrupt nodes, the first identifier indicates the target processor cluster.

[0019] In a third aspect, a system for processing an interrupt request is provided, the system comprising an acquisition source and an integrated circuit provided by the first aspect or any exemplary embodiment of the first aspect. The acquisition source is used to acquire an interrupt request and send the interrupt request to the integrated circuit; the integrated circuit is used to process the interrupt request.

[0020] The technical solution provided by the embodiments of the present application brings at least the following technical effects.

[0021] In an embodiment of the present application, the first interrupt node included in the interrupt circuit can quickly determine the first identifier by querying the first memory after receiving the interrupt request, thereby realizing fast, accurate and flexible routing of the interrupt request according to the first identifier. It only takes a short time for the target processor cluster to receive (directly or through the second interrupt node) and process the interrupt request, thereby improving the processing efficiency of the interrupt request. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is a structural schematic diagram of a processing integrated circuit provided in an embodiment of the present application;

[0023] Figure 2 is a schematic diagram of the structure of a first sub-memory provided in an embodiment of the present application;

[0024] Figure 3 is a schematic diagram of the structure of a fifth sub-memory provided in an embodiment of the present application;

[0025] Figure 4 is a schematic diagram of the structure of a sixth sub-memory provided in an embodiment of the present application;

[0026] Figure 5 is a schematic diagram of the structure of another integrated circuit provided in an embodiment of the present application;

[0027] Figure 6 is a schematic diagram of the structure of a second sub-memory provided in an embodiment of the present application;

[0028] Figure 7 is a schematic diagram of the structure of a third sub-memory provided in an embodiment of the present application;

[0029] Figure 8 is a schematic diagram of the structure of a fourth sub-memory provided in an embodiment of the present application;

[0030] Fig. 9 is a schematic diagram of the structure of a multi-chip system provided in an embodiment of the present application;

[0031] Fig.10 It is a flowchart of a method for processing an interrupt request provided by an embodiment of the present application. DETAILED DESCRIPTION

[0032] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0033] The development of modern processors has brought about tremendous changes in various fields of human society. For example, modern processors have promoted the development of industrial automation, health care, scientific research, and entertainment. Among them, the processor is, for example, a CPU (central processing unit).

[0034] From the perspective of the instruction set architecture of modern processors, it can be divided into complex instruction sets and RISC (reduced instruction set computer). Complex instruction sets have first-mover advantages, such as X86. RISC has lower power consumption and higher frequency, and has gradually replaced complex instruction sets in recent years. RISC is ARM (advanced RISC machine) or RISC-V, etc., where V stands for five.

[0035] In addition, with the in-depth study of semiconductor technology and processor architecture, the performance of processors has also been improved to a certain extent, making it possible to design highly complex processor systems. In such a complex processor system, peripheral devices can be set according to actual needs to expand the functions of the complex processor system. Peripheral devices can be connected to the processor to help users access the complex processor system and use the additional functions of the complex processor system.

[0036] The interrupt system can improve the efficiency of the processor in processing interrupt requests sent by peripheral devices. After the interrupt system receives an interrupt request from a peripheral device, the processor will interrupt the currently executing program flow according to the interrupt request, and then select the appropriate interrupt handler to respond and process the interrupt request according to the source of the interrupt request.

[0037] In the RISC-V architecture, the traditional interrupt system only supports wired interrupt requests, such as processing wired interrupt requests through PLIC (platform level interrupt controller). However, in a complex processor system, the number of peripheral devices that send wired interrupt requests (i.e., the source of interrupt requests) is large, and the number of processors used to process wired interrupt requests is also large, which will make the layout and wiring of the entire interrupt system complex and reduce feasibility.

[0038] AIA (Advanced Interrupt Architecture) is a new interrupt system under the RISC-V architecture. AIA adds support for MSI type interrupt requests. In other words, in AIA, wired type interrupt requests are uniformly converted to MSI type interrupt requests to facilitate the processor to process interrupt requests. This conversion function is completed through APLIC (Advanced Platform Level Interrupt Controller).

[0039] However, when there are many peripheral devices, the number of interrupt requests is also large. It takes a long time for APLIC to process a large number of interrupt requests. Therefore, after the peripheral device sends an interrupt request, the processor needs to wait for a long time to receive the interrupt request to be processed, which affects the processing efficiency of the interrupt request. In addition, in a multi-chip (die, also called bare die) scenario, that is, a complex multi-core scenario, the die that receives the interrupt request and the die where the processor for processing the interrupt request is located may be different dies, so it is necessary to implement the processing of interrupt requests in this scenario.

[0040] The present application embodiment provides an integrated circuit, such as Figure 1 As shown, the integrated circuit includes one or more processor clusters, and an interrupt circuit coupled to the one or more processor clusters, wherein the interrupt circuit includes a multi-level interrupt node.

[0041] Among them, multi-level interrupt nodes refer to at least two levels of interrupt nodes. At least two levels of interrupt nodes include interrupt nodes for interrupt control, and the interrupt nodes for interrupt control can have one level. The interrupt nodes for interrupt control are connected to the processor cluster, and the interrupt nodes for interrupt control are, for example, APLIC. At least two levels of interrupt nodes also include interrupt nodes for routing interrupt requests, and the interrupt nodes for routing interrupt requests can have one level or multiple levels. When there is one level of interrupt nodes for routing interrupt requests, the interrupt nodes for routing interrupt requests are connected to the interrupt nodes for interrupt control. When there are multiple levels of interrupt nodes for routing interrupt requests, the multiple levels of interrupt nodes for routing interrupt requests are connected in sequence, and one level of interrupt nodes for routing interrupt requests is connected to the interrupt nodes for interrupt control.

[0042] When a multi-level interrupt node includes two levels of interrupt nodes, the two levels of interrupt nodes are a first interrupt node and a second interrupt node, the first interrupt node is an interrupt node for routing interrupt requests, and the second interrupt node is an interrupt node for performing interrupt control (e.g., APLIC), the first interrupt node, the second interrupt node, and the processor cluster are connected in sequence, and the transmission direction of the interrupt request is, for example, the first interrupt node, the second interrupt node, and the processor cluster, and in the multi-level interrupt node, the second interrupt node is the next-level interrupt node of the first interrupt node.

[0043] When a multi-level interrupt node includes three-level interrupt nodes, the three-level interrupt nodes are a first interrupt node, a second interrupt node and a third interrupt node. The first interrupt node and the third interrupt node are interrupt nodes for routing interrupt requests, the second interrupt node is an interrupt node for performing interrupt control, the third interrupt node, the first interrupt node, the second interrupt node and the processor cluster are connected in sequence, and the transmission direction of the interrupt request is, for example, the third interrupt node, the first interrupt node, the second interrupt node and the processor cluster. In the multi-level interrupt node, the first interrupt node is the next-level interrupt node of the third interrupt node.

[0044] When the multi-level interruption node includes a fourth-level interruption node, there may also be a fourth interruption node, which is an interruption node for routing interruption requests, and the fourth interruption node is connected to the third interruption node, and the third interruption node is the next-level interruption node of the fourth interruption node. When the multi-level interruption node includes a fifth-level interruption node, there may also be a fifth interruption node, which is an interruption node for routing interruption requests, and the fifth interruption node is connected to the fourth interruption node, and the fourth interruption node is the next-level interruption node of the fifth interruption node. And so on, and no further examples are given here.

[0045] The above-mentioned processor cluster may also be referred to as a processor cluster or a processor group. A processor cluster includes a configurable cache and multiple processor cores, and the cache is, for example, a level 3 (L3) cache. In one example, a processor cluster includes 4 cores and 1 L3 cache, that is, 4 cores share one L3 cache, that is, 4 cores and 1 L3 cache are called 1 CPU Cluster. When a CPU die includes 64 cores, it means that the CPU die includes 16 CPU Clusters.

[0046] An interrupt circuit including a multi-level interrupt node is used for: receiving an interrupt request through a first interrupt node in the multi-level interrupt node, the interrupt request having an interrupt identifier; querying a first memory according to the interrupt identifier through the first interrupt node to obtain a first identifier corresponding to the interrupt identifier; when the first identifier indicates a second interrupt node in the multi-level interrupt node, sending an interrupt request to a target processor cluster in one or more processor clusters through the first interrupt node and the second interrupt node, so that the target processor cluster processes the interrupt request; or, when the first identifier indicates a target processor cluster, sending an interrupt request directly to the target processor cluster through the first interrupt node, so that the target processor cluster processes the interrupt request.

[0047] Among them, the peripheral device can generate an interrupt request when an emergency occurs, and the interrupt request is used to request to improve the emergency event that occurs in the peripheral device. Exemplarily, the embodiment of the present application obtains the interrupt request generated by the peripheral device through the HMI (hub management interface), and then performs address conversion on the interrupt request through the IOMMU (input / output memory management unit), and sends the interrupt request after the address conversion to the first interrupt node. The interrupt request received by the first interrupt node is the interrupt request after the address conversion, and the first interrupt node routes the interrupt request after the address conversion to at least one processor cluster in one or more processor clusters, for example, to a target processor cluster. Optionally, address conversion refers to converting the virtual address carried by the interrupt request into a physical address, and the interrupt request after the address conversion carries a physical address. The processor cluster that receives the interrupt request after the address conversion (such as the target processor cluster exemplified above) processes the interrupt request by accessing the interrupt file at the physical address.

[0048] In some embodiments, the peripheral device is a wired interrupt device, and the wired interrupt device sends a wired interrupt request. Exemplarily, the IOMMU can send a wired interrupt request to the first interrupt node through the first line, and the wired interrupt request has an interrupt identifier that is a line identifier of the first line.

[0049] In some other embodiments, the peripheral device is a PCI-E (peripheral component interconnect express) device, and the PCI-E device sends an MSI type interrupt request. Exemplarily, the IOMMU sends an MSI type interrupt request to the first interrupt node through a second line (different from the first line mentioned above), and the MSI type interrupt request has an interrupt identifier that is included in the MSI type interrupt request.

[0050] Optionally, an HMI for obtaining wired type interrupt requests is also referred to as wired HMI, and an HMI for obtaining MSI type interrupt requests is also referred to as PCI-E HMI. Wired HMI and PCI-E HMI may be collectively referred to as device HMI.

[0051] It can be seen that no matter what type of interrupt request the first interrupt node receives, the interrupt request has an interrupt identifier, and the interrupt request corresponds to the interrupt identifier one by one, and different interrupt requests have different interrupt identifiers. Therefore, the first interrupt node performs a routing process based on the interrupt identifier, and the routing process is used to route the interrupt request to the target processor cluster so that the interrupt request can be processed by the target processor cluster, thereby improving the emergency events occurring in the peripheral device. The first interrupt node can be recorded as an arbiter.

[0052] The first interrupt node queries the first memory according to the interrupt identifier to obtain the first identifier corresponding to the interrupt identifier. The first interrupt node can send an interrupt request to the target processor cluster according to the first identifier, so that the target processor cluster receives and processes the interrupt request. Optionally, the first memory is, for example, a register. The other memories mentioned below may also be registers. The embodiments of the present application do not limit the form of each memory, and each memory may also adopt other forms other than registers. In addition, the value of each memory can be enabled by the operating system, and the operating system and the integrated circuit are located in the same computer device.

[0053] Exemplarily, there are two different situations for the first identification.

[0054] In the first case, the first identifier indicates the second interrupt node in the multi-level interrupt node, and the second interrupt node corresponds to the target processor cluster. In this regard, the first interrupt node sends an interrupt request to the second interrupt node indicated by the first identifier, and the second interrupt node forwards the interrupt request to the corresponding target processor cluster, so that the target processor cluster processes the interrupt request. In other words, the interrupt circuit sends the interrupt request to the target processor cluster through the first interrupt node and the second interrupt node.

[0055] Among them, the second interrupt node can process the interrupt request (for example, perform type conversion on the interrupt request, see the following description for details), and then forward the interrupt request to the target processor cluster, that is, the second interrupt node forwards the processed interrupt request to the target processor cluster. Of course, the second interrupt node may also not process the interrupt request (for example, not perform type conversion on the interrupt request), and directly forward the interrupt request to the target processor cluster, that is, the second interrupt node performs transparent transmission of the interrupt request.

[0056] Alternatively, in the second case, the first identifier indicates the target processor cluster. In this regard, the first interrupt node directly sends an interrupt request to the target processor cluster indicated by the first identifier (i.e., without passing through the second interrupt node), so that the target processor cluster processes the interrupt request. In other words, the interrupt circuit directly sends the interrupt request to the target processor cluster through the first interrupt node.

[0057] Whether it is the first case where the second interrupt node transparently transmits the interrupt request, or the second case where the interrupt request does not pass through the second interrupt node, both belong to bypassing the second interrupt node.

[0058] Next, these two situations are described in detail.

[0059] In the first case, the first part of the first memory (the first part may refer to a separate memory, for example, the first part may be a separate register) may store multiple first identifiers, each of which indicates a second interrupt node. Thus, when the first interrupt node queries the first part of the first memory according to the interrupt identifier, it can obtain the first identifier corresponding to the interrupt identifier from the multiple first identifiers, and the second interrupt node indicated by the first identifier obtained by the query is the second interrupt node connected to the target processor cluster, and the second interrupt node is used to receive and forward the interrupt request to the target processor cluster.

[0060] According to the above description, the interrupt request corresponds to the interrupt identifier one by one. Since there may be multiple emergency events in the peripheral device, there are also multiple interrupt requests, and correspondingly there are multiple interrupt identifiers. In the embodiment of the present application, the first part of the first memory stores the interrupt identifier and the first identifier bit by bit, so that the order of an interrupt identifier among multiple interrupt identifiers is equal to the order of the first identifier corresponding to the interrupt identifier among multiple first identifiers.

[0061] For example, if interrupt identifier 0 is the 0th interrupt identifier among the multiple interrupt identifiers, then the first identifier corresponding to interrupt identifier 0 is located in the 0th bit group in the first part of the first memory. For another example, if interrupt identifier 1 is the 1st interrupt identifier among the multiple interrupt identifiers, then the first identifier corresponding to interrupt identifier 1 is located in the 1st bit group in the first part of the first memory. And so on, no more examples are given for other interrupt identifiers.

[0062] In an exemplary embodiment, the number of bits included in each bit group can be determined according to the number of second interruption nodes. For example, if the number of second interruption nodes is 256, and the corresponding multiple first identifiers are 0 to 255, then the number of bits included in each bit group is 8, because the first identifier 255 with the largest value needs to be represented by 8 bits. For another example, if the number of second interruption nodes is 512, and the corresponding multiple first identifiers are 0 to 511, then the number of bits included in each bit group is 9, because the first identifier 511 with the largest value needs to be represented by 9 bits.

[0063] Optionally, the first part of the first memory includes at least one first sub-memory, and each first sub-memory is used to store a part of the interruption identifier and a part of the first identifier in bit order.

[0064] For example, if each bit group includes 8 bits and each first sub-memory is a 64-bit memory, each first sub-memory is used to store 8 bit groups, that is, to store 8 first identifiers corresponding to 8 interrupt identifiers. On this basis, if there are 1024 interrupt identifiers in total, a total of 128 first sub-memories are required.

[0065] The first sub-memory is represented as AB_INTPROUTE[x], and the 128 first sub-memories are represented as AB_INTPROUTE[0] to AB_INTPROUTE

[127] . AB_INTPROUTE[0] is used to store the first identifiers corresponding to interrupt identifiers 0 to 7, AB_INTPROUTE[1] is used to store the first identifiers corresponding to interrupt identifiers 8 to 15, and so on. AB_INTPROUTE

[127] is used to store the first identifiers corresponding to interrupt identifiers 1016 to 1023.

[0066] In an example, the structure of the first sub-memory AB_INTPROUTE[0] can be found in Figure 2 .exist Figure 2 In the example, the first identifier AP_id[0] corresponding to the interrupt identifier 0 occupies bits 0 to 7 (i.e. Figure 2 The width shown is 8, that is, the 0th bit group described above), the first identifier AP_id[1] corresponding to interrupt identifier 1 occupies the 8th to 15th bits (that is, the 1st bit group described above), and so on, the first identifier AP_id[7] corresponding to interrupt identifier 7 occupies the 56th to 63rd bits.

[0067] Based on the above description, taking the interrupt request received by the first interrupt node with interrupt identifier 1 as an example, the first interrupt node queries the first bit group according to the interrupt identifier 1, that is, the 8th to 15th bits of AB_INTPROUTE[0], and obtains the first identifier AP_id[1], so that it can send an interrupt request to the second interrupt node indicated by the first identifier AP_id[1].

[0068] Optionally, in addition to sending an interrupt request to a second interrupt node connected to the target processor cluster, the first interrupt node can also send an interrupt request to other second interrupt nodes that are not connected to the target processor cluster, that is, the first interrupt node performs the broadcast of the interrupt request. However, in this case, only the second interrupt node connected to the target processor cluster can respond to the interrupt request, and other second interrupt nodes will only receive and ignore the interrupt request. The reason is that each second interrupt node can have a corresponding resource configuration (source configure) register, also known as sourcecfg register, in which the sourcecfg register includes a system management (system management, SM) domain, and the value of the SM domain can be configured by the operating system. When the value of the SM domain is 0, it indicates inactive (inactive), so even if the second interrupt node receives an interrupt request, it will not send an interrupt request to the corresponding processor cluster. In addition, when the value of the SM domain is 1, it indicates active (active), so after the second interrupt node receives the interrupt request, it will send an interrupt request to the corresponding processor cluster. Therefore, the embodiment of the present application can make the value of the SM field included in the sourcecfg register corresponding to the second interrupt node connected to the target processor cluster be 1, while the value of the SM field included in the sourcecfg register corresponding to other second interrupt nodes is 0. Thus, it is achieved that only the second interrupt node connected to the target processor cluster can respond to the interrupt request, and other second interrupt nodes will only receive and ignore the interrupt request.

[0069] After receiving the interrupt request, the second interrupt node connected to the target processor cluster sends the interrupt request to the corresponding target processor cluster among the multiple processor clusters.

[0070] Since the second interrupt node is connected to the first interrupt node, after the first interrupt node sends an interrupt request to the second interrupt node, the second interrupt node can receive the interrupt request. Wherein, the second interrupt node and the processor cluster can be one-to-one corresponding, that is, each second interrupt node corresponds to a processor cluster, and the second interrupt node connected to the target processor cluster corresponds to the target processor cluster. Therefore, the second interrupt node can send an interrupt request to the target processor cluster.

[0071] Exemplarily, after receiving the interrupt request, the second interrupt node may perform type conversion on the interrupt request, and the interrupt request sent by the second interrupt node to the target processor cluster is the interrupt request after type conversion. For example, when the interrupt request is of wired type, the second interrupt node may convert the wired type interrupt request into an MSI type interrupt request, and send the MSI type interrupt request to the target processor cluster.

[0072] Alternatively, after receiving the interrupt request, the second interrupt node may directly send the interrupt request to the target processor cluster without performing type conversion on the interrupt request, that is, the second interrupt node transparently transmits the interrupt request. For example, when the interrupt request is of MSI type, the second interrupt node may transparently transmit the MSI type interrupt request.

[0073] Since the target processor cluster is connected to the second interrupt node, the target processor cluster can receive the interrupt request after the second interrupt node sends the interrupt request. Exemplarily, the target processor cluster can process the interrupt request sent by the second interrupt node through the target processing core in at least one processing core to improve the emergency event occurring in the peripheral device.

[0074] When there is only one processing core in the target processor cluster, the processing core is the target processing core. When there are multiple processing cores in the target processor cluster, the target processing core can be a processing core specified by the operating system among the multiple processing cores. For example, when a PCI-E device initiates an interrupt request (wired type or MSI type), the hypervisor (a virtualized operating system) will allocate a target processing core to the interrupt request based on the load of the processors included in the current multiple processor clusters to respond to the interrupt request.

[0075] Optionally, the second interrupt node corresponds to a target register, which can also be configured by the operating system. The target register includes a processing core identifier corresponding to the interrupt identifier of the interrupt request. After the second interrupt node receives the interrupt request, it queries the target register according to the interrupt identifier to obtain the processing core identifier corresponding to the interrupt identifier. The processing core indicated by the processing core identifier is the target processing core for processing the interrupt request. The second interrupt node sends an interrupt request to the target processor cluster where the target processing core is located, so that the target processing core processes the interrupt request.

[0076] In the embodiment of the present application, since the integrated circuit includes a first interrupt node, and the first interrupt node receives an interrupt request and distributes the interrupt request to the second interrupt node according to the first part of the first memory, it is beneficial to realize the fast routing of the interrupt request and improve the processing efficiency of the processor cluster.

[0077] In the second case, the second part of the first memory (the second part may refer to a separate memory, for example, the second part may be a separate register) may store multiple first identifiers, the multiple first identifiers correspond one-to-one to the multiple processor clusters, and each first identifier indicates a processor cluster among the multiple processor clusters. Thus, when the first interrupt node queries the second part of the first memory according to the interrupt identifier, it can obtain the first identifier corresponding to the interrupt identifier from the multiple first identifiers, and the processor cluster indicated by the first identifier obtained by the query is the target processor cluster.

[0078] In the embodiment of the present application, the second part of the first memory stores the interruption flag and the first flag bit by bit, so that the order of an interruption flag in multiple interruption flags is equal to the order of the first flag corresponding to the interruption flag in multiple first flags. The storage method can refer to the storage method described in the first case above, and will not be repeated here.

[0079] As mentioned above, the second interrupt node can convert the wired type interrupt request into an MSI type interrupt request. Then, if the interrupt request itself is of MSI type, there is no need to perform type conversion through the second interrupt node, that is, the interrupt request is sent directly to the target processor cluster without passing through the second interrupt node. Accordingly, the target processor cluster can receive and process the interrupt request. The way the target processor cluster processes the interrupt request is described in the first case above, which will not be repeated here.

[0080] In an exemplary embodiment, the first interrupt node queries the fifth memory, and distinguishes the first situation from the second situation through the fifth identifier stored in the fifth memory.

[0081] Wherein, the interrupt circuit is also used for: querying the fifth memory according to the interrupt identifier through the first interrupt node to obtain the fifth identifier corresponding to the interrupt identifier. Wherein, the value of the fifth identifier indicates whether the first interrupt node is authorized to send interrupt requests to other interrupt nodes (the next-level interrupt node of the first interrupt node, for example, the second interrupt node). Wherein, since the value of the fifth memory is configured by the operating system, the value of the fifth identifier indicates whether the first interrupt node is authorized by the operating system to send interrupt requests to other interrupt nodes. The other "authorized" mentioned below is the same as here and will not be repeated.

[0082] In one example, the values ​​of all the fifth identifiers in the fifth memory indicate that the first interrupt node is not authorized to send interrupt requests to other interrupt nodes, that is, for any interrupt request, the first interrupt node will not send it to other interrupt nodes, thereby realizing global interrupt control. In another example, the values ​​of some or all of the fifth identifiers in the fifth memory indicate that the first interrupt node is authorized to send interrupt requests to other interrupt nodes, then the first interrupt node can selectively send interrupt requests to other interrupt nodes, which is more flexible.

[0083] In an exemplary embodiment, the value of the fifth identifier includes the following two cases.

[0084] In case A (corresponding to the first case above), the value of the fifth identifier indicates that the first interrupt node is authorized to send interrupt requests to other interrupt nodes. In case A, the first identifier indicates the second interrupt node, so the interrupt circuit can send interrupt requests to the target processor cluster through the first interrupt node and the second interrupt node.

[0085] That is to say, the first interrupt node can first query the fifth memory to obtain the fifth identifier. If the value of the fifth identifier indicates that the first interrupt node is authorized to send an interrupt request to other interrupt nodes, the first interrupt node queries the first part of the first memory according to the above description to obtain the first identifier indicating the second interrupt node, and the first interrupt node sends an interrupt request to the second interrupt node.

[0086] In the case where the interrupt request is of a wired type, the second interrupt node converts the wired type interrupt request into an MSI type interrupt request, and then sends the MSI type interrupt request to the target processor cluster, and the target processor cluster processes the MSI type interrupt request. Alternatively, in the case where the interrupt request is of an MSI type, the second interrupt node transparently transmits the MSI type interrupt request, and the target processor cluster processes the MSI type interrupt request.

[0087] In case B (corresponding to the second case above), when the interrupt request is of the MSI type, the value of the fifth identifier indicates that the first interrupt node is not authorized to send an interrupt request to other interrupt nodes. In case B, the first identifier indicates the target processor cluster, so the interrupt circuit can send the interrupt request directly to the target processor cluster through the first interrupt node.

[0088] That is to say, the first interrupt node can first query the fifth memory to obtain the fifth identifier. If the value of the fifth identifier indicates that the first interrupt node is not authorized to send interrupt requests to other interrupt nodes, the first interrupt node queries the second part of the first memory according to the above instructions to obtain the first identifier indicating the target processor cluster. The first interrupt node does not need to send an MSI type interrupt request to the second interrupt node, but directly sends an MSI type interrupt request to the target processor cluster.

[0089] In the embodiment of the present application, the fifth memory stores the interrupt flag and the fifth flag bit by bit, so that the order of an interrupt flag among multiple interrupt flags is equal to the order of the fifth flag corresponding to the interrupt flag among the multiple fifth flags.

[0090] For example, if interrupt identifier 0 is the 0th interrupt identifier among the multiple interrupt identifiers, then the fifth identifier corresponding to interrupt identifier 0 is located in the 0th bit group in the fifth memory. For another example, if interrupt identifier 1 is the 1st interrupt identifier among the multiple interrupt identifiers, then the fifth identifier corresponding to interrupt identifier 1 is located in the 1st bit group in the fifth memory. By analogy, other interrupt identifiers will not be given examples one by one.

[0091] Exemplarily, the number of bits included in each bit group can be determined according to the value of the fifth identifier. For example, if the value of the fifth identifier is 0 and 1, the number of bits included in each bit group is 1, because 0 and 1 only need to be represented by 1 bit. For another example, if the value of the fifth identifier is 2 and 3 (i.e., 10 and 11), the number of bits included in each bit group is 2, because 2 and 3 need to be represented by 2 bits.

[0092] Optionally, the fifth memory includes at least one fifth sub-memory, and each fifth sub-memory is used to store part of the interruption flag and part of the fifth flag bit by bit.

[0093] For example, if the number of bits included in each bit group is 1 and each fifth sub-memory is a 64-bit memory, each fifth sub-memory is used to store 64 bit groups, that is, to store 64 fifth identifiers corresponding to 64 interrupt identifiers. On this basis, if there are 1024 interrupt identifiers in total, a total of 16 fifth sub-memories are required.

[0094] The fifth sub-memory is represented as AB_INTPCTRL[x], and the 16 fifth sub-memories are represented as AB_INTPCTRL[0] to AB_INTPCTRL

[15] . AB_INTPCTRL[0] is used to store the fifth identifiers corresponding to interrupt identifiers 0 to 63, respectively, AB_INTPCTRL[1] is used to store the fifth identifiers corresponding to interrupt identifiers 64 to 127, respectively, and so on. AB_INTPCTRL

[15] is used to store the fifth identifiers corresponding to interrupt identifiers 960 to 1023, respectively.

[0095] In an example, the structure of the fifth sub-memory AB_INTPCTRL[0] can be seen in Figure 3 .exist Figure 3 In the figure, the fifth identifier AB_i_en[0] corresponding to the interrupt identifier 0 occupies the 0th bit (the width is 1, i.e., the 0th bit group described above), the fifth identifier AB_i_en[1] corresponding to the interrupt identifier 1 occupies the 1st bit (i.e., the 1st bit group described above), and so on. The fifth identifier AB_i_en

[63] corresponding to the interrupt identifier 63 occupies the 63rd bit.

[0096] Based on the above description, taking the interrupt request received by the first interrupt node with interrupt identifier 1 as an example, the first interrupt node queries the first bit group, that is, the first bit of AB_INTPCTRL[0], according to the interrupt identifier 1, and obtains the fifth identifier AB_i_en[1], so as to determine whether to send an interrupt request to the second interrupt node according to the value of the fifth identifier AB_i_en[1].

[0097] For the first situation described above, in an exemplary embodiment, after the first interrupt node obtains the first identifier (indicating the second interrupt node) corresponding to the interrupt request, it does not need to perform other query processes and directly sends the interrupt request to the second interrupt node. Alternatively, after the first interrupt node obtains the first identifier corresponding to the interrupt request, it also performs the following query process.

[0098] Exemplarily, the interrupt circuit is further used to query the sixth memory according to the first identifier through the first interrupt node to obtain the sixth identifier corresponding to the first identifier. The interrupt circuit is used to send an interrupt request to the target processor cluster through the first interrupt node and the second interrupt node when the value of the sixth identifier indicates that the second interrupt node is authorized to receive the interrupt request.

[0099] In the embodiment of the present application, the sixth memory stores the first identifier and the sixth identifier bit by bit so that the order of a first identifier among multiple first identifiers is equal to the order of the sixth identifier corresponding to the first identifier among multiple sixth identifiers.

[0100] For example, if the first identifier AP_id[0] is the 0th first identifier among multiple first identifiers, then the sixth identifier corresponding to the first identifier AP_id[0] is located in the 0th bit group in the sixth memory. For another example, if the first identifier AP_id[1] is the 1st first identifier among multiple first identifiers, then the sixth identifier corresponding to the first identifier AP_id[1] is located in the 1st bit group in the sixth memory. And so on, no further examples are given for other first identifiers.

[0101] Exemplarily, the number of bits included in each bit group is determined according to the value of the sixth identifier. For example, if the value of the sixth identifier is 0 and 1, the number of bits included in each bit group is 1, because 0 and 1 only need to be represented by 1 bit. For another example, if the value of the sixth identifier is 2 and 3 (i.e., 10 and 11), the number of bits included in each bit group is 2, because 2 and 3 need to be represented by 2 bits.

[0102] Optionally, the sixth memory includes at least one sixth sub-memory, and each sixth sub-memory is used to store part of the first identifier and part of the sixth identifier bit by bit.

[0103] For example, if the number of bits included in each bit group is 1 and each sixth sub-memory is a 64-bit memory, then each sixth sub-memory is used to store 64 bit groups, that is, to store 64 sixth identifiers corresponding to 64 first identifiers. On this basis, if there are 256 first identifiers in total, that is, one first interrupt node is connected to 256 second interrupt nodes, then a total of 4 sixth sub-memories are required.

[0104] The sixth sub-memory is represented as AB_APCTRL[x], and the four sixth sub-memories are represented as AB_APCTRL[0] to AB_APCTRL[3]. AB_APCTRL[0] is used to store the sixth identifiers corresponding to the first identifier AP_id[0] to the first identifier AP_id

[63] , AB_APCTRL[1] is used to store the sixth identifiers corresponding to the first identifier AP_id

[64] to the first identifier AP_id

[127] , and so on. AB_APCTRL[3] is used to store the sixth identifiers corresponding to the first identifier AP_id

[960] to the first identifier AP_id

[1023] .

[0105] In an example, the structure of the sixth sub-memory AB_APCTRL[0] can be seen in Figure 4 .exist Figure 3In the figure, the sixth identifier AP_en[0] corresponding to the first identifier AP_id[0] occupies the 0th bit (the width is 1, i.e., the 0th bit group described above), the sixth identifier AP_en[1] corresponding to the first identifier AP_id[1] occupies the 1st bit (i.e., the 1st bit group described above), and so on. The sixth identifier AP_en

[63] corresponding to the first identifier AP_en

[63] occupies the 63rd bit.

[0106] Based on the above description, taking the first interrupt node querying and obtaining the first identifier AP_id[1] as an example, the first interrupt node queries the first bit group, that is, the first bit of AB_APCTRL[0], based on the first identifier AP_id[1], and obtains the sixth identifier AP_en[1], thereby being able to determine whether the second interrupt node is authorized to receive the interrupt request based on the value of the sixth identifier AP_en[1].

[0107] If the second interrupt node is authorized to receive the interrupt request, the first interrupt node can send the interrupt request to the second interrupt node. If the second interrupt node is not authorized to receive the interrupt request, it means that the target processor cluster corresponding to the second interrupt node may be in an abnormal state, such as an abnormal state where the processing core occupancy rate exceeds a threshold, and the first interrupt node can wait for the value of the sixth identifier corresponding to the first identifier to be updated to indicate that the second interrupt node is authorized to receive the interrupt request, and then send the interrupt request to the second interrupt node.

[0108] In an exemplary embodiment, the interrupt circuit is also used to: receive an interrupt request through a third interrupt node in the multi-level interrupt node; query the second memory according to the interrupt identifier through the third interrupt node to obtain a second identifier corresponding to the interrupt identifier; and send an interrupt request to the first interrupt node indicated by the second identifier through the third interrupt node.

[0109] Exemplarily, after the peripheral device generates an interrupt request, the interrupt request is obtained through the HMI, and the IOMMU performs address conversion on the interrupt request, thereby sending the interrupt request after address conversion to the third interrupt node. After receiving the interrupt request, the third interrupt node sends the interrupt request to the first interrupt node. Figure 5 , Figure 5 An exemplary integrated circuit is shown, wherein the third interrupt node can be recorded as a dispatcher.

[0110] In the embodiment of the present application, the second memory stores the interrupt flag and the second flag bit by bit, so that the order of an interrupt flag among multiple interrupt flags is equal to the order of the second flag corresponding to the interrupt flag among the multiple second flags.

[0111] For example, if interrupt identifier 0 is the 0th interrupt identifier among the multiple interrupt identifiers, the second identifier corresponding to interrupt identifier 0 is located in the 0th bit group in the second memory. For another example, if interrupt identifier 1 is the 1st interrupt identifier among the multiple interrupt identifiers, the second identifier corresponding to interrupt identifier 1 is located in the 1st bit group in the second memory. And so on, no examples are given one by one for other interrupt identifiers.

[0112] In an exemplary embodiment, the number of bits included in each bit group may be determined according to the number of first interrupt nodes.

[0113] For example, if the number of first interruption nodes is 256, and the corresponding multiple second identifiers are 0 to 255, then the number of bits included in each bit group is 8, because the second identifier 255 with the largest value needs to be represented by 8 bits. For another example, if the number of first interruption nodes is 512, and the corresponding multiple second identifiers are 0 to 511, then the number of bits included in each bit group is 9, because the second identifier 511 with the largest value needs to be represented by 9 bits.

[0114] Optionally, the second memory includes at least one second sub-memory, and each second sub-memory is used to store a portion of the interruption identifier and a portion of the second identifier in bit order.

[0115] For example, if each bit group includes 8 bits and each second sub-memory is a 64-bit memory, each second sub-memory is used to store 8 bit groups, that is, to store 8 second identifiers corresponding to 8 interrupt identifiers. On this basis, if there are 1024 interrupt identifiers in total, a total of 128 second sub-memories are required.

[0116] The second sub-memory is represented as DP_INTPROUTE[x], and the 128 second sub-memories are represented as DP_INTPROUTE[0] to DP_INTPROUTE

[127] . DP_INTPROUTE[0] is used to store the second identifiers corresponding to interrupt identifiers 0 to 7, DP_INTPROUTE[1] is used to store the second identifiers corresponding to interrupt identifiers 8 to 15, and so on. DP_INTPROUTE

[127] is used to store the second identifiers corresponding to interrupt identifiers 1016 to 1023.

[0117] In one example, the structure of the second sub-memory DP_INTPROUTE[0] can be found in Figure 6 .exist Figure 6In the figure, the second identifier AB_id[0] corresponding to interrupt identifier 0 occupies the 0th to 7th bits (the width is 8, that is, the 0th bit group described above), the second identifier AB_id[1] corresponding to interrupt identifier 1 occupies the 8th to 15th bits (that is, the 1st bit group described above), and so on. The second identifier AB_id[7] corresponding to interrupt identifier 7 occupies the 56th to 63rd bits.

[0118] Based on the above description, taking the interrupt request received by the third interrupt node with interrupt identifier 1 as an example, the first interrupt node queries the first bit group according to the interrupt identifier 1, that is, the 8th to 15th bits of DP_INTPROUTE[0], and obtains the second identifier AB_id[1], so that the interrupt request can be sent to the first interrupt node indicated by the second identifier AB_id[1].

[0119] In an exemplary embodiment, the interrupt circuit is also used to: query the third memory according to the interrupt identifier through the third interrupt node to obtain a third identifier corresponding to the interrupt identifier; the interrupt circuit is used to: query the second memory according to the interrupt identifier through the third interrupt node to obtain a second identifier corresponding to the interrupt identifier when the value of the third identifier indicates that the third interrupt node is authorized to send an interrupt request to the first interrupt node.

[0120] In one example, the values ​​of all third identifiers in the third memory indicate that the third interrupt node is not authorized to send an interrupt request to the first interrupt node, that is, for any interrupt request, the third interrupt node will not send it to the first interrupt node, thereby realizing global interrupt control. In another example, the values ​​of some or all third identifiers in the third memory indicate that the third interrupt node is authorized to send an interrupt request to the first interrupt node, then the third interrupt node can selectively send an interrupt request to the first interrupt node, which is more flexible.

[0121] In the embodiment of the present application, the third memory stores the interrupt flag and the third flag bit by bit, so that the order of an interrupt flag among multiple interrupt flags is equal to the order of the third flag corresponding to the interrupt flag among the multiple third flags.

[0122] For example, if interrupt identifier 0 is the 0th interrupt identifier among the multiple interrupt identifiers, then the third identifier corresponding to interrupt identifier 0 is located in the 0th bit group in the third memory. For another example, if interrupt identifier 1 is the 1st interrupt identifier among the multiple interrupt identifiers, then the third identifier corresponding to interrupt identifier 1 is located in the 1st bit group in the third memory. By analogy, other interrupt identifiers will not be given examples one by one.

[0123] Exemplarily, the number of bits included in each bit group can be determined according to the value of the third identifier. For example, if the value of the third identifier is 0 and 1, the number of bits included in each bit group is 1, because 0 and 1 only need to be represented by 1 bit. For another example, if the value of the third identifier is 2 and 3 (i.e., 10 and 11), the number of bits included in each bit group is 2, because 2 and 3 need to be represented by 2 bits.

[0124] Optionally, the third memory includes at least one third sub-memory, and each third sub-memory is used to store part of the interruption flag and part of the third flag bit by bit.

[0125] For example, if the number of bits included in each bit group is 1 and each third sub-memory is a 64-bit memory, each third sub-memory is used to store 64 bit groups, that is, to store 64 third identifiers corresponding to 64 interrupt identifiers. On this basis, if there are 1024 interrupt identifiers in total, a total of 16 third sub-memories are required.

[0126] The third sub-memory is represented as DP_INTPCTRL[x], and the 16 third sub-memories are represented as DP_INTPCTRL[0] to DP_INTPCTRL

[15] . DP_INTPCTRL[0] is used to store the third identifiers corresponding to interrupt identifiers 0 to 63, DP_INTPCTRL[1] is used to store the third identifiers corresponding to interrupt identifiers 64 to 127, and so on. DP_INTPCTRL

[15] is used to store the third identifiers corresponding to interrupt identifiers 960 to 1023.

[0127] In an example, the structure of the third sub-memory DP_INTPCTRL[0] can be seen in Figure 7 .exist Figure 7 In the figure, the third identifier DP_i_en[0] corresponding to interrupt identifier 0 occupies the 0th bit (the width is 1, i.e., the 0th bit group described above), the third identifier DP_i_en[1] corresponding to interrupt identifier 1 occupies the 1st bit (i.e., the 1st bit group described above), and so on. The third identifier DP_i_en

[63] corresponding to interrupt identifier 63 occupies the 63rd bit.

[0128] Based on the above description, taking the interrupt request received by the third interrupt node with interrupt identifier 1 as an example, the first interrupt node queries the first bit group, that is, the first bit of DP_INTPCTRL[0], according to the interrupt identifier 1, and obtains the third identifier DP_i_en[1], thereby being able to determine whether to send an interrupt request to the first interrupt node according to the value of the third identifier DP_i_en[1].

[0129] In an exemplary embodiment, the interrupt circuit is also used to: query the fourth memory according to the second identifier through the third interrupt node to obtain a fourth identifier corresponding to the second identifier; the interrupt circuit is used to: send an interrupt request to the first interrupt node through the third interrupt node when the value of the fourth identifier indicates that the first interrupt node is authorized to receive the interrupt request.

[0130] In the embodiment of the present application, the fourth memory stores the second identifier and the fourth identifier bit by bit so that the order of a second identifier among multiple second identifiers is equal to the order of a fourth identifier corresponding to the second identifier among multiple fourth identifiers.

[0131] For example, if the second identifier AB_id[0] is the 0th second identifier among multiple second identifiers, then the fourth identifier corresponding to the second identifier AB_id[0] is located in the 0th bit group in the fourth memory. For another example, if the second identifier AB_id[1] is the 1st second identifier among multiple second identifiers, then the fourth identifier corresponding to the second identifier AB_id[1] is located in the 1st bit group in the fourth memory. And so on, no more examples are given for other second identifiers.

[0132] Exemplarily, the number of bits included in each bit group can be determined according to the value of the fourth identifier. For example, if the value of the fourth identifier is 0 and 1, the number of bits included in each bit group is 1, because 0 and 1 only need to be represented by 1 bit. For another example, if the value of the fourth identifier is 2 and 3 (i.e., 10 and 11), the number of bits included in each bit group is 2, because 2 and 3 need to be represented by 2 bits.

[0133] Optionally, the fourth memory includes at least one fourth sub-memory, and each fourth sub-memory is used to store part of the second identifier and part of the fourth identifier bit by bit.

[0134] For example, if the number of bits included in each bit group is 1 and each fourth sub-memory is a 64-bit memory, each fourth sub-memory is used to store 64 bit groups, that is, to store 64 fourth identifiers corresponding to 64 second identifiers. On this basis, if there are 256 second identifiers in total, that is, one third interrupt node is connected to 256 first interrupt nodes, then a total of 4 fourth sub-memories are required.

[0135] The fourth sub-memory is represented as DP_ABCTRL[x], and the four fourth sub-memories are represented as DP_ABCTRL[0] to DP_ABCTRL[3]. DP_ABCTRL[0] is used to store the fourth identifiers corresponding to the second identifiers AB_id[0] to AB_id

[63] , DP_ABCTRL[1] is used to store the fourth identifiers corresponding to the second identifiers AB_id

[64] to AB_id

[127] , and so on. AB_ABCTRL[3] is used to store the fourth identifiers corresponding to the second identifiers AB_id

[960] to AB_id

[1023] .

[0136] In an example, the structure of the fourth sub-memory DP_ABCTRL[0] can be seen in Figure 8 .exist Figure 8 In the figure, the fourth identifier AB_en[0] corresponding to the second identifier AB_id[0] occupies the 0th bit (the width is 1, i.e., the 0th bit group described above), the fourth identifier AB_en[1] corresponding to the second identifier AB_id[1] occupies the 1st bit (i.e., the 1st bit group described above), and so on. The fourth identifier AB_en

[63] corresponding to the second identifier AB_en

[63] occupies the 63rd bit.

[0137] Based on the above description, taking the example of the third interrupt node querying and obtaining the second identifier AB_id[1], the third interrupt node queries the first bit group, that is, the first bit of DP_ABCTRL[0], according to the second identifier AB_id[1], and obtains the fourth identifier AB_en[1], thereby being able to determine whether the first interrupt node is authorized to receive the interrupt request according to the value of the fourth identifier AB_en[1].

[0138] If the first interrupt node is authorized to receive the interrupt request, the third interrupt node can send the interrupt request to the first interrupt node. If the first interrupt node is not authorized to receive the interrupt request, it means that the target processor cluster corresponding to the first interrupt node may be in an abnormal state, such as an abnormal state where the processing core occupancy rate exceeds a threshold, and the third interrupt node can wait for the value of the fourth identifier corresponding to the second identifier to be updated to indicate that the first interrupt node is authorized to receive the interrupt request, and then send the interrupt request to the first interrupt node.

[0139] As mentioned above, there may be multiple levels of interrupt nodes for routing interrupt requests, for example, in addition to the third interrupt node and the first interrupt node, there may also be a fourth interrupt node, a fifth interrupt node, etc. Thus, flexible expansion of the topology in the interrupt circuit is achieved.

[0140] Exemplarily, in addition to the third interrupt node, the fourth interrupt node, the fifth interrupt node, etc. may also be connected to the memory to implement the routing of the interrupt request. For example, the fifth interrupt node is connected to the memory A, the memory B and the memory C. After the fifth interrupt node receives the interrupt request, according to the interrupt identifier of the interrupt request, the memory A is queried to determine whether the fifth interrupt node is authorized to send the interrupt request to the fourth interrupt node of the next level, the memory B is queried to determine the fourth interrupt node X for receiving the interrupt request, and the memory C is queried to determine whether the fourth interrupt node X is authorized to receive the interrupt request. Based on this, the fifth interrupt node can send an interrupt request to the fourth interrupt node X if certain conditions are met, so that the fourth interrupt node X continues to route the interrupt request (for example, forwarding the interrupt request to the third interrupt node of the next level), so that the target processor cluster can receive the interrupt request. Among them, satisfying certain conditions may mean that the fifth interrupt node is authorized to send an interrupt request to the fourth interrupt node of the next level, and the fourth interrupt node X is authorized to receive the interrupt request.

[0141] In an exemplary embodiment, the third interrupt node and the target processor cluster are located on different chips in. That is to say, the element receiving the interrupt request (i.e., the third interrupt node) and the element processing the interrupt request (i.e., the target processor cluster) are located on different chips (i.e., dies). In this regard, the second memory can store the second identifiers of all first interrupt nodes included in the interrupt circuit, so that the third interrupt node routes the interrupt request to any first interrupt node in the interrupt circuit, regardless of whether the first interrupt node and the third interrupt node are located on the same die. In addition, the first memory can store all first identifiers included in the integrated circuit (indicating the second interrupt node, or indicating the target processor cluster), so that the first interrupt node routes the interrupt request to the target processor cluster, regardless of whether the first interrupt node and the second interrupt node (or the target processor cluster) are located on the same die. As a result, the routing method is more flexible and suitable for complex situations with multiple dies.

[0142] like Fig. 9 As shown, a D2D (die to die, chip to chip) high-speed interconnection interface is used between dies. Fig. 9An exemplary 3DIE structure is shown, including 1 IO DIE and 2 CPU DIEs (CPU DIE 0 and CPU DIE 1), forming a SOC (system on chip). IO DIE is used to send interrupt requests to CPU DIE, and CPU DIE is used to route interrupt requests to the corresponding CPU Cluster according to actual needs after the Dispatcher (DP) receives the interrupt request. Among them, each CPU DIE includes 1 Dispatcher, 2 Arbiters (AB), 4 APLICs (AP) and 4 CPUClusters.

[0143] For wired interrupt requests, after the Dispatcher (DP 0) in CPU DIE 0 receives the wired interrupt request, it sends the wired interrupt request to the Arbiter (AB 1) in CPU DIE 1 through D2D. After the wired interrupt request is converted into an MSI interrupt request by APLIC (AP), the MSI interrupt request is processed by the CPU Cluster.

[0144] Alternatively, for an MSI type interrupt request, after the Dispatcher (DP 0) in CPU DIE 0 receives the MSI type interrupt request, it sends the MSI type interrupt request to the Arbiter (AB 1) in CPU DIE 1 through D2D, APLIC (AP) transparently transmits the MSI type interrupt request, and the CPU Cluster processes the MSI type interrupt request.

[0145] For MSI type interrupt requests, after receiving the MSI type interrupt request, the Dispatcher (DP 0) in CPU DIE 0 sends the MSI type interrupt request to the Arbiter (AB 1) in CPU DIE 1 through D2D. AB 1 bypasses APLIC (AP), and the CPU Cluster directly receives and processes the MSI type interrupt request. For example, AB 1 is directly connected to the CPU Cluster through a circuit ( Fig. 9 (not shown), AB 1 directly sends an MSI type interrupt request to the CPU Cluster through the circuit, thereby bypassing the AP, and the CPU Cluster directly receives and processes the MSI type interrupt request.

[0146] To sum up, in the embodiment of the present application, the first interrupt node included in the interrupt circuit can quickly determine the first identifier by querying the first memory after receiving the interrupt request, thereby realizing fast, accurate and flexible routing of the interrupt request according to the first identifier. It only takes a short time for the target processor cluster to receive (directly, or through the second interrupt node) and process the interrupt request, thereby improving the processing efficiency of the interrupt request.

[0147] The integrated circuit provided in the embodiment of the present application has a tree topology structure of a third interrupt node (optional), a first interrupt node, a second interrupt node and multiple processor clusters. This topology structure has low complexity, strong scalability and strong robustness, which is conducive to the hierarchical management and routing of interrupt requests, improves routing efficiency, and thus improves the processing efficiency of interrupt requests.

[0148] The present application also provides a method for processing an interrupt request, which can be applied to the integrated circuit described above. Fig.10 As shown, the method includes the following steps 1001 to 1004.

[0149] Step 1001: receiving an interrupt request through a first interrupt node in a multi-level interrupt node, where the interrupt request has an interrupt identifier.

[0150] Step 1002: query the first memory according to the interruption identifier through the first interruption node to obtain a first identifier corresponding to the interruption identifier.

[0151] Step 1003 , when the first identifier indicates a second interrupt node in the multi-level interrupt nodes, an interrupt request is sent to a target processor cluster in one or more processor clusters through the first interrupt node and the second interrupt node, so that the target processor cluster processes the interrupt request.

[0152] Step 1004 , when the first identifier indicates a target processor cluster, directly send an interrupt request to the target processor cluster through the first interrupt node, so that the target processor cluster processes the interrupt request.

[0153] In an exemplary embodiment, the method also includes: receiving an interrupt request through a third interrupt node in the multi-level interrupt node; querying the second memory according to the interrupt identifier through the third interrupt node to obtain a second identifier corresponding to the interrupt identifier; and sending an interrupt request to the first interrupt node indicated by the second identifier through the third interrupt node.

[0154] In an exemplary embodiment, the method further includes: querying the third memory according to the interruption identifier through the third interruption node to obtain a third identifier corresponding to the interruption identifier. Querying the second memory according to the interruption identifier through the third interruption node includes: when the value of the third identifier indicates that the third interruption node is authorized to send an interruption request to the first interruption node, querying the second memory according to the interruption identifier through the third interruption node to obtain a second identifier corresponding to the interruption identifier.

[0155] In an exemplary embodiment, the method further includes: querying a fourth memory according to the second identifier through a third interrupt node to obtain a fourth identifier corresponding to the second identifier. Sending an interrupt request to a first interrupt node indicated by the second identifier through the third interrupt node includes: sending an interrupt request to the first interrupt node through the third interrupt node when the value of the fourth identifier indicates that the first interrupt node is authorized to receive the interrupt request.

[0156] In an exemplary embodiment, the method also includes: querying the fifth memory according to the interrupt identifier through the first interrupt node to obtain a fifth identifier corresponding to the interrupt identifier; wherein, when the value of the fifth identifier indicates that the first interrupt node is authorized to send an interrupt request to other interrupt nodes, the first identifier indicates the second interrupt node.

[0157] In an exemplary embodiment, the method also includes: querying the sixth memory according to the first identifier through the first interrupt node to obtain the sixth identifier corresponding to the first identifier; sending an interrupt request to the target processor cluster in one or more processor clusters through the first interrupt node and the second interrupt node, including: when the value of the sixth identifier indicates that the second interrupt node is authorized to receive the interrupt request, sending the interrupt request to the target processor cluster through the first interrupt node and the second interrupt node.

[0158] In an exemplary embodiment, the interrupt request is an MSI type interrupt request; the method also includes: querying the fifth memory according to the interrupt identifier through the first interrupt node to obtain a fifth identifier corresponding to the interrupt identifier; wherein, when the value of the fifth identifier indicates that the first interrupt node is not authorized to send an interrupt request to other interrupt nodes, the first identifier indicates the target processor cluster.

[0159] It should be noted that Fig.10 The method shown belongs to the same concept as the integrated circuit embodiment described above. Its specific implementation process and technical effects are detailed in the integrated circuit embodiment and will not be repeated here.

[0160] The embodiment of the present application also provides a system for processing an interrupt request, which includes an acquisition source (such as the above-mentioned IO DIE) and an integrated circuit (such as the above-mentioned CPU DIE). The acquisition source is used to obtain the interrupt request and send the interrupt request to the integrated circuit; the integrated circuit is used to process the interrupt request.

[0161] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. The embodiments described in the above exemplary embodiments do not represent all embodiments consistent with the present application. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0162] It should be understood that the "plurality" mentioned in this article refers to two or more. The character " / " generally indicates that the objects before and after are in an "or" relationship.

[0163] The above description is only an exemplary embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the principles of the present application shall be included in the protection scope of the present application.

Claims

1. An integrated circuit, characterized in that: The system comprises one or more processor clusters and an interrupt circuit coupled to the one or more processor clusters, wherein the interrupt circuit comprises a multi-level interrupt node and is used for: Receiving an interrupt request through a first interrupt node in the multi-level interrupt nodes, wherein the interrupt request has an interrupt identifier; querying a first memory according to the interruption identifier through the first interruption node to obtain a first identifier corresponding to the interruption identifier; In a case where the first identifier indicates a second interrupt node in the multi-level interrupt nodes, sending the interrupt request to a target processor cluster in the one or more processor clusters through the first interrupt node and the second interrupt node, so that the target processor cluster processes the interrupt request; Alternatively, when the first identifier indicates the target processor cluster, the interrupt request is directly sent to the target processor cluster through the first interrupt node, so that the target processor cluster processes the interrupt request.

2. The integrated circuit according to claim 1, characterized in that The interrupt circuit is also used for: Receiving the interrupt request through a third interrupt node in the multi-level interrupt nodes; querying the second memory according to the interruption identifier through the third interruption node to obtain a second identifier corresponding to the interruption identifier; The interrupt request is sent to the first interrupt node indicated by the second identifier through the third interrupt node.

3. The integrated circuit according to claim 2, characterized in that The interrupt circuit is also used for: querying a third memory according to the interruption identifier through the third interruption node to obtain a third identifier corresponding to the interruption identifier; The interrupt circuit is used to: When the value of the third identifier indicates that the third interrupt node is authorized to send the interrupt request to the first interrupt node, the third interrupt node queries the second memory according to the interrupt identifier to obtain a second identifier corresponding to the interrupt identifier.

4. The integrated circuit according to claim 2, characterized in that The interrupt circuit is also used for: querying a fourth memory according to the second identifier through the third interrupt node to obtain a fourth identifier corresponding to the second identifier; The interrupt circuit is used for: In a case where the value of the fourth identifier indicates that the first interrupt node is authorized to receive the interrupt request, the interrupt request is sent to the first interrupt node through the third interrupt node.

5. The integrated circuit according to any one of claims 1 to 4, characterized in that: The interrupt circuit is also used for: querying a fifth memory according to the interruption identifier through the first interruption node to obtain a fifth identifier corresponding to the interruption identifier; Wherein, when the value of the fifth identifier indicates that the first interruption node is authorized to send the interruption request to other interruption nodes, the first identifier indicates the second interruption node.

6. The integrated circuit according to claim 5, characterized in that The interrupt circuit is also used for: querying a sixth memory according to the first identifier through the first interrupt node to obtain a sixth identifier corresponding to the first identifier; The interrupt circuit is used to: In a case where the value of the sixth identifier indicates that the second interrupt node is authorized to receive the interrupt request, the interrupt request is sent to the target processor cluster through the first interrupt node and the second interrupt node.

7. The integrated circuit according to any one of claims 1 to 4, characterized in that: The interrupt request is a message signal interrupt (MSI) type interrupt request; The interrupt circuit is also used for: querying a fifth memory according to the interruption identifier through the first interruption node to obtain a fifth identifier corresponding to the interruption identifier; Wherein, when the value of the fifth identifier indicates that the first interrupt node is not authorized to send the interrupt request to other interrupt nodes, the first identifier indicates the target processor cluster.

8. A method for processing an interrupt request, characterized in that: The method comprises: Receiving an interrupt request through a first interrupt node in the multi-level interrupt nodes, wherein the interrupt request has an interrupt identifier; querying a first memory according to the interruption identifier through the first interruption node to obtain a first identifier corresponding to the interruption identifier; In a case where the first identifier indicates a second interrupt node in the multi-level interrupt nodes, sending the interrupt request to a target processor cluster in one or more processor clusters through the first interrupt node and the second interrupt node, so that the target processor cluster processes the interrupt request; Alternatively, when the first identifier indicates the target processor cluster, the interrupt request is directly sent to the target processor cluster through the first interrupt node, so that the target processor cluster processes the interrupt request.

9. The method according to claim 8, characterized in that The method further comprises: Receiving the interrupt request through a third interrupt node in the multi-level interrupt nodes; querying the second memory according to the interruption identifier through the third interruption node to obtain a second identifier corresponding to the interruption identifier; The interrupt request is sent to the first interrupt node indicated by the second identifier through the third interrupt node.

10. The method according to claim 9, characterized in that The method further includes: querying a third memory according to the interruption identifier through the third interruption node to obtain a third identifier corresponding to the interruption identifier; The querying of the second memory according to the interrupt identifier through the third interrupt node includes: when the value of the third identifier indicates that the third interrupt node is authorized to send the interrupt request to the first interrupt node, querying the second memory according to the interrupt identifier through the third interrupt node to obtain a second identifier corresponding to the interrupt identifier.

11. The method according to claim 9, characterized in that The method further includes: querying a fourth memory according to the second identifier through the third interrupt node to obtain a fourth identifier corresponding to the second identifier; The sending the interrupt request to the first interrupt node indicated by the second identifier through the third interrupt node includes: sending the interrupt request to the first interrupt node through the third interrupt node when the value of the fourth identifier indicates that the first interrupt node is authorized to receive the interrupt request.

12. The method according to any one of claims 8 to 11, characterized in that The method further includes: querying a fifth memory according to the interruption identifier through the first interruption node to obtain a fifth identifier corresponding to the interruption identifier; Wherein, when the value of the fifth identifier indicates that the first interruption node is authorized to send the interruption request to other interruption nodes, the first identifier indicates the second interruption node.

13. The method according to claim 12, characterized in that The method further includes: querying a sixth memory according to the first identifier through the first interrupt node to obtain a sixth identifier corresponding to the first identifier; The sending of the interrupt request to the target processor cluster in the one or more processor clusters through the first interrupt node and the second interrupt node includes: when the value of the sixth identifier indicates that the second interrupt node is authorized to receive the interrupt request, sending the interrupt request to the target processor cluster through the first interrupt node and the second interrupt node.

14. The method according to any one of claims 8 to 11, characterized in that: The interrupt request is a message signal interrupt (MSI) type interrupt request; The method further includes: querying a fifth memory according to the interruption identifier through the first interruption node to obtain a fifth identifier corresponding to the interruption identifier; Wherein, when the value of the fifth identifier indicates that the first interrupt node is not authorized to send the interrupt request to other interrupt nodes, the first identifier indicates the target processor cluster.

15. A system for processing an interrupt request, characterized in that: The system comprises an acquisition source and an integrated circuit as claimed in any one of claims 1 to 7; The acquisition source is used to acquire an interrupt request and send the interrupt request to the integrated circuit; The integrated circuit is used to process the interrupt request.

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