Equipment debugging method and system based on FPGA (Field Programmable Gate Array) serial interface

Abstract

The invention provides an equipment debugging method and system based on an FPGA serial interface. The method comprises the steps that first data output by the output end of a computer host is analyzed through a first serial interface analysis device and then enters an information scheduling device; under the condition that the first data does not meet the interface protocol content in the external solid-state memory, a fixed serial port protocol of the information scheduling device changes the interface protocol content; under the condition that the first data meets the interface protocol content, the first information data analysis unit caches the first data into a first data cache unit; and after the first data is received, the information scheduling device takes out the first data in the first data cache unit and sends the first data of the corresponding type of interface protocol to the sub-equipment so as to debug the sub-equipment. According to the invention, a computer universal serial interface is converted into a specified serial interface, and equipment debugging of a computer serial interface protocol and various test interactive interface protocols is completed.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic equipment control, and in particular to a device debugging method and system based on FPGA serial interface. Background Art

[0002] In the development of equipment products, the interaction between various units may not be based on the universal interface. However, other units need to be simulated during the development and debugging of equipment units. However, the universal interface cannot meet the debugging requirements.

[0003] The common practice is to develop a general interface for each product unit to simulate external data input to verify the data path and functional integrity, but it cannot verify the function of the interactive interface under real conditions, which brings unnecessary joint debugging work to the subsequent whole machine verification. Summary of the invention

[0004] The present invention provides a device debugging method and system based on FPGA serial interface, which are used to solve the defect that the general interface in the prior art cannot meet the debugging demand, realize the conversion of computer general serial interface based on FPGA to a specified serial interface, and complete the device debugging of computer serial interface protocol and various test interactive interface protocols through interface protocol conversion.

[0005] The present invention provides a device debugging method based on FPGA serial interface, comprising:

[0006] The first data outputted from the output terminal of the computer host is parsed by the first serial interface parsing device and then enters the information scheduling device;

[0007] In the case where the first data does not satisfy the interface protocol content in the external solid-state memory, changing the interface protocol content through the fixed serial port protocol of the information scheduling device;

[0008] When the first data meets the content of the interface protocol, the first data is cached in a first data cache unit through a first information data parsing unit in the information scheduling device;

[0009] After the first data is received, the first data in the first data cache unit is taken out by the information scheduling device, and the first data of the corresponding type interface protocol is sent to the sub-device to debug the sub-device.

[0010] According to the present invention, a device debugging method based on FPGA serial interface also includes:

[0011] inputting the second data outputted from the output terminal of the sub-device into the information scheduling device according to a specified interface protocol;

[0012] When the second data satisfies the interface protocol content, caching the second data in a second data cache unit;

[0013] After the second data is received, the second data in the second data cache unit is retrieved through the information scheduling device;

[0014] The retrieved second data is sent to a second serial interface parsing device through a second information data parsing unit in the information scheduling device, and the second serial interface parsing device sends the second data to an input end of the computer host.

[0015] According to a device debugging method based on an FPGA serial interface provided by the present invention, the interface protocol content includes one or more of a protocol type, a frame header, a frame trailer, and a check type.

[0016] According to a device debugging method based on FPGA serial interface provided by the present invention, the first data is sent to the first data cache unit after sampling and analyzing according to a specified baud rate or clock signal, and after the first data cache unit completes receiving the first data, a first reception completion flag is sent to the information scheduling device, so that the information scheduling device can take out the first data from the first data cache unit; and / or,

[0017] The second data is sent to the second data cache unit after sampling and analyzing according to the specified baud rate or clock signal. After the second data cache unit completes receiving the second data, a second reception completion flag is sent to the information scheduling device so that the information scheduling device can take out the second data from the second data cache unit.

[0018] According to a device debugging method based on an FPGA serial interface provided by the present invention, the first data is cached in the first data cache unit according to the first-in-first-out principle, and after the first information data parsing unit completes parsing of each eight bits of the first data, the eight bits of the first data are cached in the first data cache unit; and / or,

[0019] The second data is cached in the second data cache unit according to the first-in first-out principle. After each eight bits of the second data are taken out from the first data cache unit, the second information data parsing unit parses the eight bits of the second data.

[0020] According to a device debugging method based on an FPGA serial interface provided by the present invention, when the amount of the first data is less than a first preset threshold, the first data cache unit uses an FPGA internal RAM resource FIFO or a dual-port RAM for cache;

[0021] When the amount of the first data is greater than or equal to the first preset threshold, the first data cache unit uses an external SRAM or DDR device for cache; and / or,

[0022] When the amount of the second data is less than a second preset threshold, the second data cache unit uses FPGA internal RAM resource FIFO or dual-port RAM for cache;

[0023] When the amount of the second data is greater than or equal to the second preset threshold, the second data cache unit uses an external SRAM or DDR device for cache.

[0024] According to a device debugging method based on an FPGA serial interface provided by the present invention, the clock for processing the first data is twice or more of the transmission frequency of the first data;

[0025] A clock for processing the second data is twice or more of a transmission frequency of the second data.

[0026] The present invention also provides a device debugging system based on FPGA serial interface, comprising:

[0027] A first serial interface parsing device, used for parsing first data outputted from an output terminal of a computer host;

[0028] An information scheduling device, used for changing the interface protocol content through a fixed serial port protocol of the information scheduling device when the first data does not satisfy the interface protocol content in the external solid-state memory;

[0029] When the first data meets the content of the interface protocol, the first data is cached in a first data cache unit through a first information data parsing unit in the information scheduling device;

[0030] After the first data is received, the first data in the first data cache unit is taken out by the information scheduling device, and the first data of the corresponding type interface protocol is sent to the sub-device to debug the sub-device.

[0031] According to a device debugging system based on FPGA serial interface provided by the present invention, the information scheduling device is also used for:

[0032] inputting the second data outputted from the output terminal of the sub-device into the information scheduling device according to a specified interface protocol;

[0033] When the second data satisfies the interface protocol content, caching the second data in a second data cache unit;

[0034] After the second data is received, the second data in the second data cache unit is retrieved through the information scheduling device;

[0035] The retrieved second data is sent to a second serial interface parsing device through a second information data parsing unit in the information scheduling device, and the second serial interface parsing device sends the second data to an input end of the computer host.

[0036] The present invention also provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the device debugging method based on the FPGA serial interface as described above is implemented.

[0037] The present invention also provides a non-transitory computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the device debugging method based on the FPGA serial interface as described above is implemented.

[0038] The present invention also provides a computer program product, comprising a computer program, wherein when the computer program is executed by a processor, the device debugging method based on the FPGA serial interface as described above is implemented.

[0039] The device debugging method and system based on FPGA serial interface provided by the present invention realize the conversion of computer general serial interface based on FPGA to specified serial interface through serial interface parsing device and information scheduling device, and complete the device debugging of computer serial interface protocol and various test interactive interface protocols through interface protocol conversion, which not only ensures the integrity of data received by the self-device, but also ensures the integrity of the protocol function received by the self-device, reduces the complexity and repeatability of debugging of private interface protocol in debugging and development, and optimizes the process of repeated debugging interface in debugging and development. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0041] Figure 1 This is one of the flow charts of the device debugging method based on FPGA serial interface provided by the present invention;

[0042] Figure 2 This is the second flow chart of the device debugging method based on FPGA serial interface provided by the present invention;

[0043] Figure 3 It is a structural schematic diagram of a device debugging system based on an FPGA serial interface provided by the present invention;

[0044] Figure 4 It is the FPGA resource software architecture in the device debugging system based on the FPGA serial interface provided by the present invention;

[0045] Figure 5 An example physical structure diagram of an electronic device is provided. DETAILED DESCRIPTION

[0046] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0047] Combine the following Figure 1 The present invention describes a device debugging method based on an FPGA (Field Programmable Gate Array) serial interface, comprising:

[0048] Step 1001, the first data outputted from the output terminal of the computer host is parsed by the first serial interface parsing device and then enters the information scheduling device;

[0049] This embodiment is applied to the output terminal of a computer host. The first data is the data output by the output terminal of the computer host.

[0050] The computer host transmits the first data to the first serial interface parsing device through a serial port, USB (Universal Serial Bus) or other links for parsing, and then sends the first data to the information scheduling device after parsing.

[0051] Step 1002, when the first data does not satisfy the interface protocol content in the external solid-state memory, changing the interface protocol content through the fixed serial port protocol of the information scheduling device;

[0052] Determine whether the first data satisfies the interface protocol content stored in the external solid-state memory. If it satisfies the protocol content, proceed to step 1003. If it does not comply with the interface protocol content, the host computer program can change the interface protocol content in the external solid-state memory through the fixed serial port protocol of the information scheduling device, thereby increasing the versatility of the information scheduling device.

[0053] When the interface protocol content is changed, the relevant address storing the interface protocol content in the external memory is erased and the data in the memory is changed according to the erase protocol. Receiving serial port data and receiving data uploaded by the lower computer will read the stored data.

[0054] Step 1003: When the first data meets the interface protocol content, the first data is cached in a first data cache unit through a first information data parsing unit in the information scheduling device;

[0055] Step 1004, after the first data is received, the first data in the first data cache unit is taken out by the information scheduling device, and the first data of the corresponding type interface protocol is sent to the sub-device to debug the sub-device.

[0056] It is worth noting that it is necessary to wait until the first data cache unit has completed receiving the first data before proceeding to the next step. This is because in most cases there is generally a rate difference between the computer serial universal interface and the lower computer interface protocol. This is to avoid data discontinuity caused by the rate difference and inconsistency between the experimental data and the actual state.

[0057] After receiving the first data, the information scheduling device takes the first data out of the first data cache unit, and then outputs the first data according to the lower computer interface receiving protocol. The information scheduling device transmits the taken out first data to the lower computer through the protocol interface, and the data is received and processed by the lower computer.

[0058] This embodiment converts the computer's universal serial interface to a specified serial interface through a universal serial parsing device and an information dispatching device. Based on FPGA development, FPGA's RAM (Random Access Memory), LUT (Look-Up Table), BUFG (global buffer) and other on-chip resources are used, as well as external serial port parsing chips and external storage devices, such as FLASH (flash memory) devices.

[0059] This embodiment realizes the conversion of a computer's general serial interface to a specified serial interface based on FPGA through a serial interface parsing device and an information scheduling device, and completes the device debugging of the computer serial interface protocol and various test interactive interface protocols through interface protocol conversion, which not only ensures the integrity of the data received by the self-device, but also ensures the integrity of the protocol function received by the self-device, reduces the complexity and repeatability of debugging of private interface protocols during debugging and development, and optimizes the process of repeated debugging of interfaces during debugging and development.

[0060] Based on the above embodiment, this embodiment also includes:

[0061] inputting the second data outputted from the output terminal of the sub-device into the information scheduling device according to a specified interface protocol;

[0062] When the second data satisfies the interface protocol content, caching the second data in a second data cache unit;

[0063] After the second data is received, the second data in the second data cache unit is retrieved through the information scheduling device;

[0064] The retrieved second data is sent to a second serial interface parsing device through a second information data parsing unit in the information scheduling device, and the second serial interface parsing device sends the second data to an input end of the computer host.

[0065] This embodiment is applied to the input end of the computer host. The second data is the data output by the output end of the sub-device, that is, the data input by the input end of the computer host.

[0066] The computer host is the upper computer, and the sub-device is the lower computer. The lower computer transmits the second data to the information scheduling device through a specified serial interface protocol.

[0067] Determine whether the second data meets the interface protocol content stored in the external solid-state memory. If it meets the interface protocol content, the data analysis module analyzes the second data and sends the second data to the second data cache unit for caching; if it does not meet the interface protocol content, the program ends and waits for the next string of data to be uploaded.

[0068] After the second data is received, the second data is taken out from the second data buffer unit, and then the second data is output in sequence through the universal serial interface standard protocol. Note that the data transmission rate here cannot exceed the maximum clock frequency of the system. It is also recommended that the system clock should be more than twice the transmission rate.

[0069] The information dispatching device transmits the data to the computer host through the serial port, USB, etc., and the data is received and processed by the computer.

[0070] On the basis of the above embodiment, the interface protocol content described in this embodiment includes one or more of a protocol type, a frame header, a frame trailer and a check type.

[0071] The interface protocol content in this embodiment includes but is not limited to the protocol type, frame header, frame trailer and check type, thereby increasing the versatility of this conversion system.

[0072] On the basis of the above embodiment, in this embodiment, the first data is sent to the first data cache unit after sampling and analyzing according to the specified baud rate or clock signal, and after the first data cache unit completes receiving the first data, a first reception completion flag is sent to the information scheduling device, so that the information scheduling device can take out the first data from the first data cache unit; and / or,

[0073] The second data is sent to the second data cache unit after sampling and analyzing according to the specified baud rate or clock signal. After the second data cache unit completes receiving the second data, a second reception completion flag is sent to the information scheduling device so that the information scheduling device can take out the second data from the second data cache unit.

[0074] The length of the first data is compared with the length of the first data cache unit. When the length of the first data is less than or equal to the length of the first data cache unit, the information scheduling device takes out the first data from the first data cache unit after the first data cache unit completes receiving the first data.

[0075] When the length of the first data is greater than the length of the first data cache unit, and when the length of the first data stored in the first data cache unit reaches half the length of the first data cache unit, the information scheduling device starts to fetch the first data from the first data cache unit, and stores the first data in the first data cache unit at the same time;

[0076] Real-time monitoring of the ratio of the length of the first data stored in the first data cache unit to the length of the first data cache unit;

[0077] If the ratio is greater than 1 / 2, the difference between the ratio and 1 / 2 is calculated, and according to the difference, the speed of storing the first data in the first data cache unit is reduced and / or the speed of retrieving the first data from the first data cache unit is increased. The larger the difference, the greater the reduction in the storage speed and the greater the increase in the retrieval speed. For example, if the storage speed is v1 and the retrieval speed is v2, and the difference is a, then the storage speed after adjustment is The adjusted removal speed is n1+n2=1, n1 and n2 are preset coefficients, so that data is not overwritten, the data reading speed is improved, and the continuity of the read data is guaranteed.

[0078] If the ratio is less than 1 / 2, the difference between the ratio and 1 / 2 is calculated, and according to the difference, the speed of storing the first data in the first data cache unit is increased and / or the speed of retrieving the first data from the first data cache unit is reduced. The larger the difference, the greater the reduction in the retrieving speed and the greater the increase in the storing speed. For example, if the storing speed is v1 and the retrieving speed is v2, and the difference is a, then the adjusted storing speed is The adjusted removal speed is n1+n2=1, n1 and n2 are preset coefficients to ensure the continuity of the read data.

[0079] The length of the second data is compared with the length of the second data cache unit. When the length of the second data is less than or equal to the length of the second data cache unit, the information scheduling device takes out the second data from the second data cache unit after the second data cache unit completes receiving the second data.

[0080] When the length of the second data is greater than the length of the second data cache unit, and when the length of the second data stored in the second data cache unit reaches half the length of the second data cache unit, the information scheduling device starts to fetch the second data from the second data cache unit, and stores the second data in the second data cache unit at the same time;

[0081] Real-time monitoring of the ratio of the length of the second data stored in the second data cache unit to the length of the second data cache unit;

[0082] If the ratio is greater than 1 / 2, the difference between the ratio and 1 / 2 is calculated, and according to the difference, the speed of storing the second data in the second data cache unit is reduced and / or the speed of retrieving the second data from the second data cache unit is increased. The larger the difference, the greater the reduction in the storage speed and the greater the increase in the retrieval speed. For example, if the storage speed is v3 and the retrieval speed is v4, and the difference is a, then the adjusted storage speed is The adjusted removal speed is n1+n2=1, n3 and n4 are preset coefficients, so that data is not overwritten, the data reading speed is improved, and the continuity of the read data is guaranteed.

[0083] If the ratio is less than 1 / 2, the difference between the ratio and 1 / 2 is calculated, and according to the difference, the speed of storing the second data in the second data cache unit is increased and / or the speed of retrieving the second data from the second data cache unit is reduced. The larger the difference, the greater the reduction in the retrieving speed and the greater the increase in the storing speed. For example, if the storing speed is v3 and the retrieving speed is v4, and the difference is a, then the adjusted storing speed is The adjusted removal speed is n3+n4=1, n3 and n4 are preset coefficients to ensure the continuity of read data.

[0084] On the basis of the above embodiment, in this embodiment, the first data is cached in the first data cache unit according to the first-in-first-out principle, and after the first information data parsing unit completes parsing of each eight bits of the first data, the eight bits of the first data are cached in the first data cache unit; and / or,

[0085] The second data is cached in the second data cache unit according to the first-in first-out principle. After each eight bits of the second data are taken out from the first data cache unit, the second information data parsing unit parses the eight bits of the second data.

[0086] Note that here, the data is not cached one by one in the data cache unit after a complete string of data is received. Instead, after an eight-digit number is input and parsed, it is directly cached in the data cache unit. The protocol parsing of a string of data and the reception parsing of a single data are performed at the same time. This way, data processing efficiency will be more efficient than processing after reception is completed, and it will also save more resources.

[0087] On the basis of the above embodiment, in this embodiment, when the amount of the first data is less than the first preset threshold, the first data cache unit uses the FPGA internal RAM resource FIFO or dual-port RAM for cache;

[0088] When the amount of the first data is greater than or equal to the first preset threshold, the first data cache unit uses an external SRAM or DDR device for cache; and / or,

[0089] When the amount of the second data is less than the second preset threshold, the second data cache unit uses FPGA internal RAM resource FIFO (First In First Out) or dual-port RAM for cache;

[0090] When the amount of the second data is greater than or equal to the second preset threshold, the second data cache unit uses an external SRAM (Static Random-Access Memory) or DDR (Double Data Rate) device for cache.

[0091] Based on the above embodiment, in this embodiment, the clock for processing the first data is twice or more of the transmission frequency of the first data;

[0092] A clock for processing the second data is twice or more of a transmission frequency of the second data.

[0093] like Figure 2 As shown in the figure, the processing flow of the computer input end includes:

[0094] S101, the lower computer transmits the second data to the information scheduling device through the specified serial interface protocol. The serial-parallel interface samples according to the specified clock or baud rate, and finally collects and obtains a string of data. Here, the operating frequency of the entire system is preferably twice or more than the upload data rate of the lower computer, so that the reception and analysis will be more accurate and the bit error rate will be greatly reduced.

[0095] S102, determine whether the protocol content stored in the external solid-state memory is satisfied, if it is satisfied, proceed to step S103, if it is not satisfied, end the program and wait for the next string of data to be uploaded.

[0096] S103, after judging through the protocol, the data analysis module analyzes the second data and sends the second data to the second data cache unit. After the second data is received, a completion mark is given to S105.

[0097] S104, receiving the second data of the data analysis module, and caching the received second data into the second data cache unit according to the first-in first-out principle, and entering the next step. The second data cache unit here can be selected according to the actual situation. When the amount of data is small, the FPGA internal RAM resource FIFO, dual-port RAM, etc. can be used. When the amount of data is large, external SRAM or DDR devices can be used for caching.

[0098] S105, after receiving the data receiving completion mark, the second data is taken out from the second data buffer unit, and then the second data is sequentially output through the universal serial interface standard protocol. Note that the data transmission rate here cannot exceed the maximum clock frequency of the system. It is also recommended that the system clock should be more than twice the transmission rate.

[0099] S106, the information scheduling device transmits the second data to the computer host through the serial port, USB, etc., and the second data is received and processed by the computer.

[0100] The processing flow at the computer output end includes:

[0101] S201, the computer host transmits the first data to the serial interface parsing device through a serial port, USB or other link, and then sends it to the information scheduling device.

[0102] S202, determine whether the protocol content stored in the external solid-state memory is satisfied, if it is satisfied, proceed to step S203, if it is not satisfied, proceed to step S211.

[0103] S203, the information scheduling device samples and analyzes the first data according to the specified baud rate or clock signal, and sends the first data to the first data cache unit, and after the first data is received, a completion mark is given to S204. Similarly, the clock for processing data here should be twice or more of the data transmission rate.

[0104] S204, receiving data from the data analysis module, and caching the first data sent after data analysis into the first data cache unit according to the first-in-first-out principle, and entering the next step. Here, the cache module can use on-chip RAM resource FIFO, dual-port RAM, etc.; when the amount of data is huge, external SRAM or DDR devices can be used for caching.

[0105] S205, after receiving the data receiving completion flag, taking out the first data from the first data cache unit, and then outputting the first data according to the lower computer interface receiving protocol.

[0106] S206, the information scheduling device transmits the data to the lower computer through the protocol interface, and the data is received and processed by the lower computer.

[0107] S211, determine whether the conditions for modifying the protocol content stored in the storage device are met. If so, proceed to step S212; if not, end the program and wait for the next string of serial port data;

[0108] S212: Erasing the data at the address related to the protocol content stored in the external memory, and changing the data in the memory according to the erasing protocol; receiving serial port data and receiving data uploaded by the lower computer will read the stored data.

[0109] The device debugging system based on FPGA serial interface provided by the present invention is described below. The device debugging system based on FPGA serial interface described below and the device debugging method based on FPGA serial interface described above can be referenced to each other.

[0110] like Figure 3 and Figure 4 As shown, the device debugging system based on FPGA serial interface provided by the present invention includes:

[0111] A first serial interface parsing device, used for parsing first data outputted from an output terminal of a computer host;

[0112] An information scheduling device, used for changing the interface protocol content through a fixed serial port protocol of the information scheduling device when the first data does not satisfy the interface protocol content in the external solid-state memory;

[0113] When the first data meets the content of the interface protocol, the first data is cached in a first data cache unit through a first information data parsing unit in the information scheduling device;

[0114] After the first data is received, the first data in the first data cache unit is taken out by the information scheduling device, and the first data of the corresponding type interface protocol is sent to the sub-device to debug the sub-device.

[0115] This embodiment realizes the conversion of a computer's general serial interface to a specified serial interface based on FPGA through a serial interface parsing device and an information scheduling device, and completes the device debugging of the computer serial interface protocol and various test interactive interface protocols through interface protocol conversion, which not only ensures the integrity of the data received by the self-device, but also ensures the integrity of the protocol function received by the self-device, reduces the complexity and repeatability of debugging of private interface protocols during debugging and development, and optimizes the process of repeated debugging of interfaces during debugging and development.

[0116] On the basis of the above embodiment, the information scheduling device in this embodiment is also used for:

[0117] inputting the second data outputted from the output terminal of the sub-device into the information scheduling device according to a specified interface protocol;

[0118] When the second data satisfies the interface protocol content, caching the second data in a second data cache unit;

[0119] After the second data is received, the second data in the second data cache unit is retrieved through the information scheduling device;

[0120] The retrieved second data is sent to a second serial interface parsing device through a second information data parsing unit in the information scheduling device, and the second serial interface parsing device sends the second data to an input end of the computer host.

[0121] Figure 5 An example of a physical structure diagram of an electronic device is shown in FIG. Figure 5As shown, the electronic device may include: a processor 510, a communication interface 520, a memory 530 and a communication bus 540, wherein the processor 510, the communication interface 520 and the memory 530 communicate with each other through the communication bus 540. The processor 510 may call the logic instructions in the memory 530 to execute the device debugging method based on the FPGA serial interface, the method comprising: parsing the first data outputted from the output end of the computer host through the first serial interface parsing device and entering the information scheduling device; in the case where the first data does not meet the interface protocol content in the external solid-state memory, changing the interface protocol content through the fixed serial port protocol of the information scheduling device; in the case where the first data meets the interface protocol content, caching the first data into the first data cache unit through the first information data parsing unit in the information scheduling device; after the first data is received, taking out the first data in the first data cache unit through the information scheduling device, and sending the first data of the corresponding type of interface protocol to the sub-device to debug the sub-device.

[0122] In addition, the logic instructions in the above-mentioned memory 530 can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when it is sold or used as an independent product. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc. Various media that can store program codes.

[0123] On the other hand, the present invention also provides a computer program product, which includes a computer program, which can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the device debugging method based on the FPGA serial interface provided by the above methods, and the method includes: parsing the first data output from the output end of the computer host through a first serial interface parsing device and entering the information scheduling device; when the first data does not meet the interface protocol content in the external solid-state memory, changing the interface protocol content through the fixed serial port protocol of the information scheduling device; when the first data meets the interface protocol content, caching the first data into a first data cache unit through the first information data parsing unit in the information scheduling device; after the first data is received, taking out the first data in the first data cache unit through the information scheduling device, and sending the first data of the corresponding type of interface protocol to the sub-device to debug the sub-device.

[0124] On the other hand, the present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, it is implemented to execute the device debugging method based on the FPGA serial interface provided by the above-mentioned methods, the method comprising: parsing the first data output from the output end of the computer host through a first serial interface parsing device and entering the information scheduling device; when the first data does not meet the interface protocol content in the external solid-state memory, changing the interface protocol content through the fixed serial port protocol of the information scheduling device; when the first data meets the interface protocol content, caching the first data into a first data cache unit through the first information data parsing unit in the information scheduling device; after the first data is received, taking out the first data in the first data cache unit through the information scheduling device, and sending the first data of the corresponding type of interface protocol to the sub-device to debug the sub-device.

[0125] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative labor.

[0126] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0127] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A device debugging method based on FPGA serial interface, characterized in that: include: The first data outputted from the output terminal of the computer host is parsed by the first serial interface parsing device and then enters the information scheduling device; In the case where the first data does not satisfy the interface protocol content in the external solid-state memory, changing the interface protocol content through the fixed serial port protocol of the information scheduling device; When the first data meets the content of the interface protocol, the first data is cached in a first data cache unit through a first information data parsing unit in the information scheduling device; After the first data is received, the first data in the first data cache unit is taken out by the information scheduling device, and the first data of the corresponding type interface protocol is sent to the sub-device to debug the sub-device.

2. The device debugging method based on FPGA serial interface according to claim 1, characterized in that: Also includes: inputting the second data outputted from the output terminal of the sub-device into the information scheduling device according to a specified interface protocol; When the second data satisfies the interface protocol content, caching the second data in a second data cache unit; After the second data is received, the second data in the second data cache unit is retrieved through the information scheduling device; The retrieved second data is sent to a second serial interface parsing device through a second information data parsing unit in the information scheduling device, and the second serial interface parsing device sends the second data to an input end of the computer host.

3. The device debugging method based on FPGA serial interface according to claim 1, characterized in that: The interface protocol content includes one or more of a protocol type, a frame header, a frame trailer, and a check type.

4. The device debugging method based on FPGA serial interface according to claim 2, characterized in that: The first data is sent to the first data cache unit after sampling and analyzing according to the specified baud rate or clock signal, and after the first data cache unit completes receiving the first data, a first reception completion flag is sent to the information scheduling device, so that the information scheduling device can take out the first data from the first data cache unit; and / or, The second data is sent to the second data cache unit after sampling and analyzing according to the specified baud rate or clock signal. After the second data cache unit completes receiving the second data, a second reception completion flag is sent to the information scheduling device so that the information scheduling device can take out the second data from the second data cache unit.

5. The device debugging method based on FPGA serial interface according to claim 2, characterized in that: Cache the first data in the first data cache unit according to the first-in-first-out principle, and cache the eight bits of first data in the first data cache unit after the first information data parsing unit completes parsing each eight bits of first data; and / or, The second data is cached in the second data cache unit according to the first-in first-out principle. After each eight bits of the second data are taken out from the first data cache unit, the second information data parsing unit parses the eight bits of the second data.

6. The device debugging method based on FPGA serial interface according to claim 2 is characterized in that: When the amount of the first data is less than a first preset threshold, the first data cache unit uses FPGA internal RAM resource FIFO or dual-port RAM for cache; When the amount of the first data is greater than or equal to the first preset threshold, the first data cache unit uses an external SRAM or DDR device for cache; and / or, When the amount of the second data is less than a second preset threshold, the second data cache unit uses FPGA internal RAM resource FIFO or dual-port RAM for cache; When the amount of the second data is greater than or equal to the second preset threshold, the second data cache unit uses an external SRAM or DDR device for cache.

7. The device debugging method based on FPGA serial interface according to claim 2, characterized in that: The clock of the first data processing is twice or more of the transmission frequency of the first data; A clock for processing the second data is twice or more of a transmission frequency of the second data.

8. A device debugging system based on FPGA serial interface, characterized in that: include: A first serial interface parsing device, used for parsing first data outputted from an output terminal of a computer host; An information scheduling device, used for changing the interface protocol content through a fixed serial port protocol of the information scheduling device when the first data does not satisfy the interface protocol content in the external solid-state memory; When the first data meets the content of the interface protocol, the first data is cached in a first data cache unit through a first information data parsing unit in the information scheduling device; After the first data is received, the first data in the first data cache unit is taken out by the information scheduling device, and the first data of the corresponding type interface protocol is sent to the sub-device to debug the sub-device.

9. The device debugging system based on FPGA serial interface according to claim 8, characterized in that: The information scheduling device is also used for: inputting the second data outputted from the output terminal of the sub-device into the information scheduling device according to a specified interface protocol; When the second data satisfies the interface protocol content, caching the second data in a second data cache unit; After the second data is received, the second data in the second data cache unit is retrieved through the information scheduling device; The retrieved second data is sent to a second serial interface parsing device through a second information data parsing unit in the information scheduling device, and the second serial interface parsing device sends the second data to an input end of the computer host.

10. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the program, the device debugging method based on the FPGA serial interface as described in any one of claims 1 to 7 is implemented.

Images