Equipment hardware self-checking method and device, computer equipment and storage medium

Abstract

The invention relates to the technical field of electric power and communication, in particular to an equipment hardware self-checking method and device, computer equipment and a storage medium. According to the invention, during detection, only the interface test frame needs to be sent to the short-circuited hardware interface through the hardware interface, and the test result frame is generated through verification of the interface test frame. Therefore, the self-checking method does not need to develop any tool device, and the development and board investment cost and the research and development workload are greatly reduced. Besides, due to the fact that the distributed power supply access unit is provided with a plurality of interfaces, one chip can not carry a plurality of interfaces, a double-chip framework of the main control chip and the coprocessor is adopted in the embodiment, more interfaces can be expanded, the double-chip framework has the advantages of being capable of processing more service logics, the main control chip and the coprocessor do not interfere with each other, and the service logic processing efficiency is improved. The coprocessor can cooperate with some simple operations, the main control chip has more resources to do more important things, and the operation efficiency is greatly improved.

Description

Technical Field

[0001] The present invention relates to the field of power and communication technology, and in particular to a method and device for self-checking equipment hardware, a computer device and a storage medium. Background Art

[0002] In recent years, distributed photovoltaic power stations have been actively promoted, and because distributed photovoltaic control pilot projects have good convenience, reliability and economy, distributed photovoltaic power stations have been rapidly rolled out. Based on this, in order to improve the observability, measurability, adjustability and controllability of low-voltage distributed photovoltaic power generation, related products such as distributed power access units have been developed.

[0003] However, for related products such as distributed power access units, if there are potential hidden dangers or damage in the distributed power access units but there is no corresponding test method to detect them, a large number of product functions will have problems after delivery, which not only greatly affects the efficiency of production and troubleshooting, but also indirectly affects the benefits and customer satisfaction with the product. Therefore, there is an urgent need for a method to perform spot inspection tests on the hardware functions and peripheral functions of the distributed power access unit product. Summary of the invention

[0004] In view of this, the present invention provides a device hardware self-check method, apparatus, computer equipment and storage medium to solve the problem in the prior art of lacking a method for detecting the hardware and related functions of a distributed power supply access unit.

[0005] In the first aspect, the present invention provides a device hardware self-test method, the device includes multiple types of hardware interfaces, a main control chip and a coprocessor, the method is applied to the main control chip, and the method includes: receiving a message test frame; parsing the message test frame to determine the interface type, the number of interfaces, and the management processor of the test interface; if the test interface is two hardware interfaces of the same type with the same management processor, the two hardware interfaces are short-circuited, interface test frames are sent in sequence, and a test result frame is received; if the test interface is two hardware interfaces of the same type with different management processors, that is, the two hardware interfaces are respectively managed by the main control chip and the coprocessor, the two hardware interfaces are short-circuited, and the coprocessor is interacted with based on a preset private protocol, and interface test frames are sent between the hardware interface managed by it and the hardware interface managed by the coprocessor, and the interface test frames received by the hardware interface managed by it are verified to generate a test result frame, or the test result frame returned by the coprocessor is received, and the test result frame returned by the coprocessor is generated by verifying the interface test frame received by the hardware interface managed by it.

[0006] In the present invention, by short-circuiting the same type of hardware interfaces in the distributed power access unit in pairs during detection, and by sending a message test frame to the main control chip, the main control chip independently or interacts with the coprocessor to realize the detection of the hardware interface according to the message test frame. During detection, it is only necessary to send an interface test frame to the short-circuited hardware interface through the hardware interface, and generate a test result frame by checking the interface test frame. Therefore, the self-checking method does not need to develop any tooling device, which greatly reduces the development and board investment cost and research and development workload. In addition, by setting the main control chip and the coprocessor in the distributed power access unit, by judging whether the hardware interface to be tested is managed by the main control chip and / or the coprocessor, different methods are used for testing, thereby ensuring the smooth progress of the test. In addition, since there are many interfaces in the distributed power access unit, one chip may not be able to carry many interfaces. Therefore, in this embodiment, a dual-chip architecture of the main control chip and the coprocessor is adopted, so that more interfaces can be expanded. Secondly, the advantage of the dual-chip architecture can handle more business logic, and the two do not interfere with each other, so that the coprocessor can cooperate in some simple operations, and the main control chip has more resources to do more important things, which will also greatly improve the operating efficiency.

[0007] In an optional implementation, the two short-circuited hardware interfaces are a first communication serial port managed by a main control chip and a second communication serial port managed by a coprocessor; based on a preset private protocol, the coprocessor interacts with the coprocessor, and an interface test frame is sent between the hardware interface managed by the coprocessor and the hardware interface managed by the coprocessor, including: controlling the opening of the first communication serial port and setting the parameters of the first communication serial port; based on a preset private protocol, the coprocessor interacts with the coprocessor, and the coprocessor controls the opening of the second communication serial port and the parameter setting; based on the first communication serial port after the parameter setting, an interface test frame is sent to the second communication serial port; after a preset delay, a test frame is sent to the coprocessor, and the test frame is used to be parsed by the coprocessor and then sent to the first communication serial port based on the second communication serial port. Test frame.

[0008] In an optional embodiment, based on the interaction with the coprocessor with a preset private protocol, the coprocessor controls the opening of the second communication serial port and parameter setting, including: sending a communication protocol frame for opening the second communication serial port to the coprocessor, the communication protocol frame is used to be parsed by the coprocessor to control the opening of the second communication serial port; receiving a reporting frame sent by the coprocessor after controlling the opening of the second communication serial port; sending a parameter message frame to the coprocessor based on the reporting frame; receiving the parameters of the second communication serial port reported by the coprocessor according to the parameter message frame; sending a parameter setting frame to the coprocessor based on the parameters of the second communication serial port, the parameter setting frame is used to be parsed by the coprocessor to set the parameters, and the parameters of the second communication serial port after setting are the same as the parameters of the first communication serial port after setting; receiving a parameter result frame sent by the coprocessor after setting the parameters of the second communication serial port.

[0009] In an optional embodiment, interface test frames are sent in sequence and test result frames are received, including: sending a protocol frame for opening two communication serial ports of the same type managed by the coprocessor, the protocol frame is used to be parsed by the coprocessor to control the opening of the communication serial port; receiving a reporting frame sent by the coprocessor after controlling the opening of the communication serial port; sending a parameter message frame to the coprocessor based on the reporting frame; receiving the parameters of the communication serial port reported by the coprocessor according to the parameter message frame; sending a parameter setting frame to the coprocessor based on the parameters of the communication serial port, the parameter setting frame is used to be parsed by the coprocessor to set the parameters of the communication serial port, and the parameters of the two short-circuited communication serial ports are set to be the same; receiving a parameter result frame sent by the coprocessor after setting the parameters of the communication serial port; sending a test frame to the coprocessor based on the parameter result frame, the test frame is used to be parsed by the coprocessor to send an interface test frame based on the communication serial port to another short-circuited communication serial port; receiving a test result frame reported by the coprocessor, the test result frame is generated after the coprocessor verifies the interface test frames received by the two communication serial ports.

[0010] In the present invention, for the detection of the first communication serial port managed by the main control chip and the second communication serial port managed by the coprocessor or the two communication serial ports managed by the coprocessor, the reliability of the detection implementation is guaranteed through the interaction between the main control chip and the coprocessor or the expansion chip.

[0011] In an optional embodiment, the device also includes a first expansion chip and a second expansion chip, and the first expansion chip and the second expansion chip respectively manage two communication serial ports, and the test method of the two communication serial ports managed by the two expansion chips is the same as the test method of the two communication serial ports managed by the coprocessor; the coprocessor, the first expansion chip and the second expansion chip include a test frame processing module, and the two communication serial ports include a forwarding communication serial port and a receiving communication serial port. The forwarding communication serial port is used to obtain preset data and send it to the receiving communication serial port through the inside of the device when used; the test frame processing module is used to change the data transmission mode of the forwarding communication serial port after receiving the interface test frame, and control the forwarding communication serial port to send the interface test frame to the receiving communication serial port.

[0012] In the present invention, for testing of a communication serial port that does not output data in actual applications, a test frame processing module is provided to change the data transmission mode during the detection process, thereby ensuring reliable detection.

[0013] In an optional embodiment, the hardware interface also includes a telesignaling interface, and the method also includes: if the test interface is a telesignaling interface, receiving a first telesignaling status test frame; obtaining a first telesignaling status of the telesignaling interface based on the telesignaling status test frame and sending it to a host computer; receiving a second telesignaling test frame, the second telesignaling test frame being issued by the host computer when it determines that the first telesignaling status meets preset requirements; short-circuiting the telesignaling interface and obtaining a second telesignaling status of the telesignaling interface; and generating a telesignaling result frame according to the second telesignaling status.

[0014] In the present invention, the remote signal state is first obtained during the remote signal test to avoid the influence of the remote signal being short-circuited on the detection result, thereby improving the reliability of the detection result.

[0015] In an optional implementation, the device to be detected includes a distributed power supply access unit, and the hardware interface includes multiple groups of CAN interfaces and multiple groups of 485 interfaces.

[0016] In a second aspect, the present invention provides a device hardware self-test device, the device includes multiple types of hardware interfaces, a main control chip and a coprocessor. When testing hardware interfaces of the same type, they are short-circuited in pairs. The device is applied to the main control chip, and the device includes: a test frame receiving module, used to receive a message test frame; a test interface determination module, used to parse the message test frame to determine the interface type, interface quantity and management processor of the test interface; a first test module, used to short-circuit the two hardware interfaces if the test interfaces are two hardware interfaces of the same type with the same management processor, send interface test frames in sequence, and receive test result frames; a second test module, used to interact with the coprocessor based on a preset private protocol if the test interfaces are two hardware interfaces of the same type with different management processors, that is, the two hardware interfaces are respectively managed by the main control chip and the coprocessor, send interface test frames between the hardware interface managed by it and the hardware interface managed by the coprocessor, and verify the interface test frames received by the hardware interface managed by it to generate test result frames, or receive the test result frames returned by the coprocessor, and the test result frames returned by the coprocessor are generated by verifying the interface test frames received by the hardware interface managed by it.

[0017] In a third aspect, the present invention provides a computer device, comprising: a memory and a processor, the memory and the processor being communicatively connected to each other, the memory storing computer instructions, and the processor executing the device hardware self-test method of the first aspect or any corresponding embodiment thereof by executing the computer instructions.

[0018] In a fourth aspect, the present invention provides a computer-readable storage medium having computer instructions stored thereon, the computer instructions being used to enable a computer to execute the device hardware self-check method of the first aspect or any corresponding embodiment thereof.

[0019] In a fifth aspect, the present invention provides a computer program product, comprising computer instructions for causing a computer to execute the device hardware self-check method of the first aspect or any corresponding embodiment thereof. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0021] Figure 1 is a flowchart of a hardware self-checking method according to an embodiment of the present invention; Figure 2 is a structural block diagram of a distributed power supply access unit according to an embodiment of the present invention; Figure 3 is a schematic diagram of the connection relationship of the hardware interface during the detection of the distributed power supply access unit according to an embodiment of the present invention; Figure 4 is a schematic diagram of the structure of a message test frame according to an embodiment of the present invention; Figure 5 is a flowchart of another hardware self-checking method according to an embodiment of the present invention; Figure 6 is a flowchart of another hardware self-checking method according to an embodiment of the present invention; Figure 7 is a schematic diagram of the internal structure and function of a distributed power supply access unit according to an embodiment of the present invention; Figure 8 is a structural block diagram of a hardware self-checking device according to an embodiment of the present invention; Fig. 9 It is a schematic diagram of the hardware structure of a computer device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0022] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0023] According to an embodiment of the present invention, a hardware self-check method embodiment is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0024] In this embodiment, a hardware self-check method is provided. Figure 1 is a flowchart of a hardware self-checking method according to an embodiment of the present invention. Figure 1 As shown, the process includes the following steps: Step S101, receiving a message test frame.

[0025] Specifically, the hardware self-check method can be applied to distributed power access units and other equipment. Figure 2 As shown, the distributed power access unit includes various types of hardware interfaces such as 485 interface, CAN interface and main control chip, among which the hardware interface includes Figure 2 The two CAN interfaces, two 485 interfaces, one 12V interface and one remote signal interface are shown in the lower left corner. In addition, the hardware interface also includes an expansion interface with a 12V interface and a 485 interface. For these hardware interfaces, the main control chip is used Figure 2 The management of one CAN interface, two 485 interfaces, one 12V interface and one remote signal interface shown in the lower left corner. At the same time, in addition to the main control chip, the distributed power access unit also includes a coprocessor and an expansion slot chip (referred to as expansion chip) installed in two expansion slots. The coprocessor and expansion chip realize the management of other hardware interfaces except the main control chip management interface.

[0026] At the same time, in order to enable the distributed power access unit to have the monitoring function of the distributed photovoltaic power station, the distributed power access unit also includes a Bluetooth module, a carrier module, a metering module and a power management module. In addition, the distributed power access unit can use the J-link tool to realize the burning of various functions in the chip.

[0027] In this embodiment, when performing hardware detection on the distributed power access unit, hardware interfaces of the same type are short-circuited in pairs, for example, CAN interfaces are short-circuited with CAN interfaces, 485 interfaces are short-circuited with 485 interfaces, etc. Figure 3 As shown, each CAN interface in the distributed power access unit includes signal lines H1, L1 or H2, L2. For the two 485 interfaces managed by the main control chip, each 485 interface includes signal lines A1, B1 or A2, B2. During testing, the corresponding signal lines can be connected respectively.

[0028] In addition, there are three groups of expansion interfaces in the hardware interface, which are managed by the coprocessor and two expansion chips respectively. Each group of expansion interfaces includes one 12V interface and two 485 interfaces. The two 485 interfaces are short-circuited during detection. For the 12V voltage interface, existing voltmeters and other devices can be used for detection.

[0029] During the detection, the host computer sends a message test frame to the distributed power access unit, and the distributed power access unit performs a hardware self-test based on the message test frame. The format of the message test frame is as follows: Figure 4 As shown, it includes frame header, frame length, test frame command, frame sequence number, test object, frame check and frame tail. Since the hardware interface in the distributed power access unit includes multiple types, the hardware interface to be tested can be distinguished by the message test frame sent by the host computer, for example, it can be distinguished by the test object in the message test frame. In addition, the message test frame sent by the host computer can be received and processed by the main control chip in the distributed power access unit.

[0030] Step S102, parse the message test frame to determine the interface type, number of interfaces, and management processor of the test interface. Specifically, after receiving the message test frame, the main control chip first parses the test frame to determine the specific test object. The test object may include a single hardware interface or two hardware interfaces of the same type. Among them, the same type of hardware interface here can be understood as the same communication protocol of the two. For example, two hardware interfaces of the same type can be two CAN interfaces or two 485 interfaces. In addition, if the test object obtained by parsing cannot be matched to the relevant hardware interface, the main control chip returns an error frame to the host computer, and the host computer displays the error frame to prompt the operator.

[0031] Step S103: If the test interfaces are two hardware interfaces of the same type of the same management processor, the two hardware interfaces are short-circuited, interface test frames are sent in sequence, and test result frames are received.

[0032] When the two short-circuited hardware interfaces are both hardware interfaces managed by the main control chip, an interface test frame is sent between the two hardware interfaces, and the interface test frames received by the two hardware interfaces are verified to generate a test result frame.

[0033] Among them, when the two short-circuited hardware interfaces are both hardware interfaces managed by the coprocessor, the coprocessor interacts with the coprocessor based on a preset private protocol, controls the coprocessor to send interface test frames between the two hardware interfaces, and receives the test result frames returned by the coprocessor. The test result frames are generated by verifying the interface test frames received by the two hardware interfaces.

[0034] Step S104, if the test interface is two hardware interfaces of the same type of different management processors, that is, the two hardware interfaces are managed by the main control chip and the coprocessor respectively, the two hardware interfaces are short-circuited, and the coprocessor interacts with the coprocessor based on a preset private protocol, and an interface test frame is sent between the hardware interface managed by it and the hardware interface managed by the coprocessor, and the interface test frame received by the hardware interface managed by it is verified to generate a test result frame, or the test result frame returned by the coprocessor is received, and the test result frame returned by the coprocessor is generated by verifying the interface test frame received by the hardware interface managed by it.

[0035] Specifically, during testing, the specific test method can be determined based on who manages the hardware interface. For example, when both hardware interfaces are managed by the main control chip, the main control chip can directly control the test of the two hardware interfaces; when at least one is managed by a coprocessor, the main control chip needs to interact with the coprocessor, and the coprocessor performs related actions to complete the test. In addition, the generated test result frame can be sent to the host computer, which obtains the result and writes it back to the database of the local server to facilitate other personnel to view the test record of the table number. This achieves the traceability of the test results.

[0036] The hardware self-test method provided by the embodiment of the present invention is to short-circuit the same type of hardware interfaces in the distributed power access unit in pairs during detection, and send a message test frame to the main control chip. The main control chip realizes the detection of the hardware interface independently or in interaction with the coprocessor according to the message test frame. During detection, it is only necessary to send an interface test frame to the short-circuited hardware interface through the hardware interface, and generate a test result frame by verifying the interface test frame. Therefore, the self-test method does not need to develop any tooling device, which greatly reduces the development and board investment costs and research and development workload. In addition, since there are many interfaces in the distributed power access unit, one chip may not be able to carry many interfaces. Therefore, the dual-chip architecture of the main control chip and the coprocessor is adopted in this embodiment, so that more interfaces can be expanded. Secondly, the advantage of the dual-chip architecture can handle more business logic, and the two do not interfere with each other, so that the coprocessor can cooperate in some simple operations, and the main control chip has more resources to do more important things, which will also greatly improve the operating efficiency.

[0037] In this embodiment, a hardware self-check method is provided, which comprises the following steps: Step S201: Receive a message test frame; see Figure 1 Step S101 of the illustrated embodiment will not be described in detail here.

[0038] Step S202: parse the message test frame to determine the interface type, interface quantity, and management processor of the test interface. Figure 1Step S102 of the illustrated embodiment will not be described in detail here.

[0039] Step S203: If the test interfaces are two hardware interfaces of the same type of the same management processor, the two hardware interfaces are short-circuited, interface test frames are sent in sequence, and test result frames are received.

[0040] In an optional implementation, when the two short-circuited hardware interfaces are both hardware interfaces managed by the main control chip, interface test frames are sent between the two hardware interfaces, and the interface test frames received by the two hardware interfaces are verified to generate test result frames.

[0041] Specifically, the two short-circuited hardware interfaces include a first 485 interface and a second 485 interface, and the above step S203 includes: Step S2031, control the first 485 interface and the second 485 interface to be turned on.

[0042] Step S2032, obtaining the parameters of the opened first 485 interface and the parameters of the opened second 485 interface, and setting the parameters of the first 485 interface and the second 485 interface to be the same.

[0043] Step S2033: Send an interface test frame to the second 485 interface based on the parameter settings of the first 485 interface.

[0044] Step S2034: after a preset delay, the second 485 interface sends an interface test frame to the first 485 interface based on the parameter settings.

[0045] Specifically, when the hardware interface to be tested is determined to be the first 485 interface and the second 485 interface by parsing the message test frame, both 485 interfaces are controlled to be opened, and if the opening fails, an error frame is returned to the upper computer. After the opening is successful, the parameters of the two 485 interfaces are obtained, and an error frame is also returned if the acquisition fails. After the parameters are successfully obtained, the parameters are configured according to the obtained parameters, that is, the obtained parameters are adjusted to meet the test requirements, wherein the parameters of the two 485 interfaces are set to be the same when setting the parameters to facilitate communication between the two.

[0046] After the parameter setting is completed, interface detection is implemented by sending interface test frames to each other through the two 485 interfaces. For example, the interface test frame is first sent to the second 485 interface through the first 485 interface after parameter setting. After the second 485 interface receives the interface test frame, it is transmitted to the main control chip, which is verified by the main control chip. After the first 485 interface sends the interface test frame for a preset time, the interface test frame is sent to the first 485 interface through the second 485 interface. After the first 485 interface receives the interface test frame, it is transmitted to the main control chip, which is verified by the main control chip.

[0047] Step S2035: Verify the interface test frames received by the two hardware interfaces to generate a test result frame.

[0048] Specifically, when the main control chip receives the interface test frame transmitted by the second 485 interface, it parses it and verifies the format of the parsed data content, etc.; then the main control chip receives the interface test frame transmitted by the first 485 interface, parses it, and verifies the format of the parsed data content, etc. When both checks pass, it means that both 485 interfaces are qualified. In addition, after the detection of the two 485 interfaces is completed, the parameters of the 485 interfaces need to be adjusted according to the parameters of the 485 interfaces obtained before the detection, that is, the parameters of the two 485 interfaces are adjusted to the parameters obtained before the detection, so as to ensure that they can be used normally.

[0049] In an optional embodiment, when the two short-circuited hardware interfaces are both hardware interfaces managed by the coprocessor, the coprocessor interacts with the coprocessor based on a preset private protocol, controls the coprocessor to send interface test frames between the two hardware interfaces, and receives test result frames returned by the coprocessor, where the test result frames are generated by verifying the interface test frames received by the two hardware interfaces.

[0050] Specifically, the above step S203 includes: Step S20311, sending a 485 protocol frame for opening the 485 interface to the coprocessor, where the 485 protocol frame is used to be parsed by the coprocessor to control the opening of the 485 interface.

[0051] Step S20312, receiving the reporting frame sent after the coprocessor controls the 485 interface to be opened.

[0052] Step S20313: Send a parameter message frame to the coprocessor based on the reporting frame.

[0053] Step S20314, receiving the parameters of the 485 interface reported by the coprocessor according to the parameter message frame.

[0054] Step S20315: Send a parameter setting frame to the coprocessor based on the parameters of the 485 interface. The parameter setting frame is used to be parsed by the coprocessor to set the parameters of the 485 interface. The parameters of the two short-circuited 485 interfaces are set to be the same.

[0055] Step S20316, receiving a parameter result frame sent by the coprocessor after setting the parameters of the 485 interface.

[0056] Step S20317: Send a test frame to the coprocessor based on the parameter result frame. The test frame is used to send an interface test frame to another short-circuited 485 interface based on the 485 interface after being parsed by the coprocessor.

[0057] Step S20318, receiving the test result frame reported by the coprocessor, where the test result frame is generated after the coprocessor verifies the interface test frames received by the two 485 interfaces.

[0058] In an optional embodiment, the distributed power access unit also includes a first expansion chip and a second expansion chip, and the first expansion chip and the second expansion chip respectively manage two 485 interfaces, and the test method of the two 485 interfaces managed by the two expansion chips is the same as the test method of the two 485 interfaces managed by the coprocessor; the coprocessor, the first expansion chip and the second expansion chip include a test frame processing module, and the two 485 interfaces include a forwarding 485 interface and a receiving 485 interface. The forwarding 485 interface is used to obtain preset data and send it to the receiving 485 interface through the distributed power access unit when applied; the test frame processing module is used to change the data transmission mode of the forwarding 485 interface after receiving the interface test frame, and control the forwarding 485 interface to send an interface test frame to the receiving 485 interface.

[0059] Specifically, the two 485 interfaces managed by the coprocessor, the first expansion chip and the second expansion chip in the distributed power access unit can be called expansion interfaces, that is, a total of three groups of expansion interfaces are included, but the coprocessor, the first expansion chip and the second expansion chip cannot communicate with the host computer to obtain the message test frame, so when the two 485 interfaces in each group of expansion interfaces are detected, the main control chip controls the coprocessor or the expansion chip to perform related actions. The following takes the detection of a group of 485 interfaces managed by the coprocessor as an example to illustrate that when detecting the expansion interface managed by the expansion chip, the coprocessor is simply replaced with the expansion chip, and the rest remains unchanged.

[0060] When the main control chip parses the message test frame and determines that the hardware interface to be tested is an extended interface, it sends a 485 protocol frame to the coprocessor based on a private protocol such as the TTL (Transistor-Transistor Logic) serial port. After receiving the 485 protocol frame, the coprocessor controls the two 485 interfaces it manages to open. And according to the opening result, a report frame is sent to the main control chip, and the report frame includes the result of whether it is opened. When the report frame received by the main control chip contains a report frame that is not successfully opened or does not receive a reply from the coprocessor within the preset time, an error frame is returned to the host computer.

[0061] When the report frame contains the result of successful opening, the main control chip continues to send the parameter message frame for obtaining the two 485 interfaces to the coprocessor. After receiving the parameter message frame, the coprocessor obtains the parameters of the two 485 interfaces and reports it to the main control chip. The main control chip then sends the parameter setting frame to the coprocessor based on the obtained parameters. After receiving it, the coprocessor sets the parameters of the two 485 interfaces and sends the parameter result frame to the main control chip after the setting is completed. After receiving the parameter result frame, the main control chip further sends a test frame to the coprocessor. After receiving the test frame, the coprocessor sends interface test frames to each other through the two 485 interfaces to realize interface detection.

[0062] For example, first, a 485 interface after parameter setting sends an interface test frame to another 485 interface in the extended interface. After receiving the interface test frame, the other 485 interface transmits it to the coprocessor for verification. After the 485 interface sends the interface test frame for a preset time, the coprocessor controls another 485 interface to send an interface test frame to the 485 interface, and the 485 interface receives the interface test frame and transmits it to the coprocessor for verification.

[0063] In addition, in actual application scenarios, for the two 485 interfaces in each group of expansion interfaces, one 485 interface is connected to the inverter, and the other 485 interface is connected to the 4G stick. The 485 interface connected to the 4G stick obtains the relevant inverter data input from the outside through the 4G stick, and sends it to the 485 interface connected to the inverter inside the distributed power access unit, and then the 485 interface sends it to the inverter. Therefore, in actual applications, one 485 interface in the expansion interface only receives data and does not send data outward, that is, the two 485 interfaces in the expansion interface can be respectively called the forwarding 485 interface (connected to the 4G stick) and the receiving 485 interface. Among them, for the forwarding 485 interface, since it does not send data outward in actual applications, in order to realize the detection of the forwarding 485 interface, a test frame processing module is set in the coprocessor in this embodiment. When the coprocessor receives the test frame, the data transmission mode of the forwarding 485 interface is changed, that is, the forwarding 485 interface is not allowed to send the interface test frame to the receiving 485 interface through the distributed power supply access unit, but the interface test frame is sent to the receiving 485 interface through the connection between the two 485 interfaces.

[0064] The coprocessor or expansion chip detects the two 485 interfaces it manages, and after receiving the interface test frame transmitted by the corresponding 485 interface, it parses it and verifies the parsed data content format, etc. After verification, it generates a test result frame and sends it to the main control chip, which then sends it to the host computer. In addition, after the detection of the two 485 interfaces is completed, the parameters of the 485 interfaces need to be adjusted according to the parameters of the 485 interfaces obtained before the detection, that is, the parameters of the two 485 interfaces are adjusted to the parameters obtained before the detection, so as to ensure that they can be used normally.

[0065] In addition, it should be noted that the selection of the two expansion chips can be the same as that of the coprocessor, thereby reducing the amount of software code development, managing similar driver peripherals, and leaving more space for the main control chip to manage core business logic processing.

[0066] Step S204, if the test interface is two hardware interfaces of the same type of different management processors, that is, the two hardware interfaces are managed by the main control chip and the coprocessor respectively, the two hardware interfaces are short-circuited, and the coprocessor interacts with the coprocessor based on a preset private protocol, and an interface test frame is sent between the hardware interface managed by it and the hardware interface managed by the coprocessor, and the interface test frame received by the hardware interface managed by it is verified to generate a test result frame, or the test result frame returned by the coprocessor is received. The test result frame returned by the coprocessor is generated by verifying the interface test frame received by the hardware interface managed by it. In this embodiment, the two hardware interfaces managed by the main control chip and the coprocessor are the first communication serial port and the second communication serial port. When the device to be tested includes a distributed power supply access unit, the first communication serial port and the second communication serial port are the first CAN interface and the second CAN interface respectively.

[0067] Specifically, the above step S204 includes: Step S2041, controlling the first CAN interface to open, and setting parameters of the first CAN interface.

[0068] Step S2042, interacting with the coprocessor based on a preset private protocol, and the coprocessor controls the opening of the second CAN interface and parameter setting.

[0069] The above step S2042 includes: Step a1, sending a CAN protocol frame for opening the second CAN interface to the coprocessor, where the CAN protocol frame is used to control the opening of the second CAN interface after being parsed by the coprocessor.

[0070] Step a2, receiving the reporting frame sent after the coprocessor controls the second CAN interface to be opened.

[0071] Step a3: Send a parameter message frame to the coprocessor based on the reporting frame.

[0072] Step a4, receiving the parameters of the second CAN interface reported by the coprocessor according to the parameter message frame.

[0073] Step a5, sending a parameter setting frame to the coprocessor based on the parameters of the second CAN interface, the parameter setting frame is used to be parsed by the coprocessor for parameter setting, and the parameters of the second CAN interface after setting are the same as the parameters of the first CAN interface after setting.

[0074] Step a6, receiving a parameter result frame sent by the coprocessor after performing parameter setting of the second CAN interface.

[0075] Step S2043: Send an interface test frame to the second CAN interface based on the first CAN interface after parameter setting.

[0076] Step S2044: after a preset delay, a test frame is sent to the coprocessor, the test frame is used to be parsed by the coprocessor and then send an interface test frame to the first CAN interface based on the second CAN interface.

[0077] Specifically, when the hardware interface to be tested is determined to be the first CAN interface and the second CAN interface by parsing the message test frame, both CAN interfaces are controlled to be turned on. Among them, the first CAN interface is managed by the main control chip, so the first CAN interface can be controlled by the main control chip. If the opening fails, an error frame is returned to the upper computer. After the opening is successful, the parameters of the corresponding interface such as the baud rate are obtained, and an error frame is also returned if the acquisition fails. After the parameters are successfully obtained, the parameters are configured according to the obtained parameters.

[0078] As for the second CAN interface managed by the coprocessor, since the coprocessor cannot communicate with the host computer to obtain the message test frame, the main control chip controls the coprocessor to perform relevant actions when detecting the second CAN interface. When the main control chip parses the message test frame to determine that the hardware interface to be tested is the first CAN interface and the second CAN interface, it sends a CAN protocol frame to the coprocessor based on a private protocol such as a TTL serial port. After receiving the CAN protocol frame, the coprocessor controls the corresponding second CAN interface to open. And according to the opening result, a reporting frame is sent to the main control chip, and the reporting frame includes the result of whether it is opened. When the reporting frame received by the main control chip contains a reporting frame that is not successfully opened or the coprocessor reply is not received within the preset time, an error frame is returned to the host computer.

[0079] When the reporting frame contains the result of successful opening, the main control chip continues to send the parameter message frame for obtaining the second CAN interface to the coprocessor. After receiving the parameter message frame, the coprocessor obtains the parameters of the second CAN interface and reports it to the main control chip. The main control chip then sends a parameter setting frame to the coprocessor based on the obtained parameters. After receiving it, the coprocessor sets the parameters of the second CAN interface and sends a parameter result frame to the main control chip after the setting is completed. It should be noted that when setting the parameters of the second CAN interface, it is set to be the same as the parameters of the first CAN interface to ensure normal communication between the two.

[0080] After the parameters of the two CAN interfaces are set, interface detection is implemented by sending interface test frames to each other through the two CAN interfaces. For example, the first CAN interface after parameter setting sends an interface test frame to the second CAN interface. After the second CAN interface receives the interface test frame, it transmits it to the coprocessor, which is verified by the coprocessor. After the first CAN interface sends the interface test frame for a preset time, the main control chip sends a test frame to the coprocessor again. After the coprocessor receives the test frame, it controls the second CAN interface to send an interface test frame to the first CAN interface. After the first CAN interface receives the interface test frame, it transmits it to the main control chip, which is verified by the main control chip.

[0081] When the coprocessor receives the interface test frame transmitted by the second CAN interface, it parses it and verifies the format of the parsed data content, etc. After the verification, a test result frame is generated and sent to the main control chip through a preset private protocol. After the main control chip determines this result, it decides whether to continue the subsequent operation and continue to send the private protocol of the test to the coprocessor. When the main control chip receives the interface test frame transmitted by the first CAN interface, it also parses it, verifies the format of the parsed data content, etc., and generates a test result frame. When the test result frame generated by the main control chip and the test result frame sent by the received coprocessor are both passed, it means that both CAN interfaces are qualified. If one test result frame fails, both CAN interfaces are unqualified. In addition, after the detection of the two CAN interfaces is completed, it is necessary to adjust the parameters of the CAN interface according to the parameters of the CAN interface obtained before the detection, that is, adjust the parameters of the two CAN interfaces to the parameters obtained before the detection, so as to ensure that they can be used normally.

[0082] In this embodiment, a hardware self-check method is provided, which comprises the following steps: Step S301: Receive a message test frame; see Figure 1 Step S101 of the illustrated embodiment will not be described in detail here.

[0083] Step S302: parse the message test frame to determine the interface type, interface quantity, and management processor of the test interface.

[0084] Step S303: If the test interfaces are two hardware interfaces of the same type of the same management processor, the two hardware interfaces are short-circuited, interface test frames are sent in sequence, and test result frames are received.

[0085] Step S304, if the test interface is two hardware interfaces of the same type of different management processors, that is, the two hardware interfaces are managed by the main control chip and the coprocessor respectively, the two hardware interfaces are short-circuited, and the coprocessor interacts with the coprocessor based on a preset private protocol, and an interface test frame is sent between the hardware interface managed by it and the hardware interface managed by the coprocessor, and the interface test frame received by the hardware interface managed by it is verified to generate a test result frame, or the test result frame returned by the coprocessor is received, and the test result frame returned by the coprocessor is generated by verifying the interface test frame received by the hardware interface managed by it.

[0086] Step S305, if the test interface is a telesignaling interface, receive a first telesignaling status test frame; obtain the first telesignaling status of the telesignaling interface based on the telesignaling status test frame and send it to the host computer; receive a second telesignaling test frame, the second telesignaling test frame is sent by the host computer when it determines that the first telesignaling status meets the preset requirements; short-circuit the telesignaling interface and obtain the second telesignaling status of the telesignaling interface; generate a telesignaling result frame according to the second telesignaling status.

[0087] Specifically, when the telesignaling interface test is required, the host computer sends the first telesignaling state test frame, and the main control chip first obtains the first telesignaling state of the telesignaling interface based on the first telesignaling state test frame, and reports it to the host computer. The host computer determines whether the first telesignaling state is 0, that is, the telesignaling interface is not short-circuited. When it is determined that the telesignaling interface is not short-circuited, the host computer continues to send the second telesignaling state test frame. Before the main control chip receives the second telesignaling state test frame to obtain the second telesignaling state, the telesignaling interface is first short-circuited using a pin or a flat cable, and then the second telesignaling state is obtained, and a telesignaling result frame is generated according to the second telesignaling state. Among them, when the second telesignaling state is 1, that is, the telesignaling interface is short-circuited, the telesignaling interface is judged to be qualified. In addition, it should be noted that when performing the telesignaling test, a timeout period can be set from the start of the test to the reception of the telesignaling result test frame. If the telesignaling result frame is received but the timeout occurs, an error will also be reported.

[0088] Step S306, using a voltage detection device to collect the voltage of the voltage interface; generating a voltage detection result based on the voltage. Specifically, when detecting a voltage interface such as a 12V voltage interface, a voltage detection device such as a voltmeter is used to obtain the interface voltage, and a voltage detection result is generated based on the obtained voltage range. For example, for a 12V voltage interface, whether the voltage detection is qualified is determined based on whether the obtained voltage value is around 12V.

[0089] In an optional embodiment, the distributed power access unit also includes a relay, and the normally closed contact of the relay, i.e., the CR terminal, can also be detected when the distributed power access unit is detected. After the distributed power access unit is powered on, the relay will automatically close, and the detection of the CR terminal can be achieved by detecting the feedback automatic closing signal. At the same time, after the distributed power access unit is powered off, the communication function can also be realized due to the supercapacitor power supply. At this time, it can be further determined whether the CR terminal is qualified by detecting the opening signal. As a specific application example of the embodiment of the present invention, taking the device to be detected as a distributed power supply access unit as an example, the hardware self-test method is described: like Figure 5 As shown in the figure, when the distributed power access unit is powered on, the main control chip is initialized and runs, and the relevant test objects are allocated in the memory and the corresponding test program is generated. During the detection, the message test frame is sent on the PC host computer, and the main control chip recognizes the message test frame sent by the serial port, and performs parsing and judgment. If the relevant test item object is not found in the memory table, an error frame is returned to the host computer, and the host computer displays the return frame to the operator to inform whether the test is successful or not. If the table lookup is successful, jump to the corresponding test program according to the specific test object to process different functional test logics such as 12V test, remote signal test, CAN test, 485 test, etc. Specific functional tests to detect the quality of hardware functions will also package different frames and report them to the host computer through the serial port for display.

[0090] In specific testing, such as Figure 6 As shown, the host computer sends a message test frame to the main control chip. After receiving and parsing, if the main control chip determines that it needs to detect the two 485 interfaces managed by it, namely 485-1 or 485-2, the main control chip will detect the interface through the test process such as opening the control interface, obtaining parameters, setting parameters, and sending interface test frames to the corresponding connected interface. For the detection of the remote signal interface, the detection is realized by detecting the remote signal state of the remote signal interface before and after short-circuiting. For the detection of the 12V voltage interface, the voltage of the voltage interface is collected by a voltmeter for detection.

[0091] When testing the first CAN interface and the second CAN interface, first short-circuit the two interfaces, then the main control chip opens the first CAN interface it manages, obtains parameters and sets the parameters, then the main control chip converts the message test frame to generate a protocol frame of the private protocol and sends it to the coprocessor. After receiving it, the coprocessor controls the second CAN interface to open, obtain parameters and set parameters. Then the main control chip controls the first CAN interface to send an interface test frame to the second CAN interface, which is received and checked by the coprocessor; then the coprocessor controls the second CAN interface to send an interface test frame to the first CAN interface, which is received and checked by the main control chip.

[0092] For each group of extended interfaces including two 485 interfaces managed by the coprocessor and the extended chip, in actual application scenarios, the two 485 interfaces are connected to the 4G stick and the inverter respectively, and the 485 interface connected to the 4G stick obtains the relevant inverter data input from the outside through the 4G stick, and sends it to the 485 interface connected to the inverter inside the distributed power access unit, and then sent to the inverter by the 485 interface. That is, the 485 interface connected to the 4G stick does not send data to the outside in actual applications. In order to realize the detection of the 485 interface, in this embodiment, a test frame processing module is set in the coprocessor or the extended interface. When the coprocessor or the extended chip receives the protocol frame, the data transmission mode of the 485 interface (connected to the 4G stick) is changed, that is, the 485 interface is not allowed to send the interface test frame to the 485 interface connected to the inverter through the distributed power access unit, but the interface test frame is sent to the 485 interface connected to the inverter through the connection of the two interfaces.

[0093] Specifically, Figure 7As shown, the distributed power access unit includes a main control module, a metering module and a conversion module (expansion chip). Among them, the main control module includes an application, an operating system and hardware peripherals. The application includes a main control chip and a coprocessor. The main control chip completes the exchange task (AC sampling task) through data acquisition, protocol processing, serial port processing and event reporting. At the same time, the main control chip can also realize parameter verification, light display, safety management, log tasks, event reporting, data storage and local control. Processing. Since the coprocessor cannot communicate directly with the host computer, the TTL group protocol is used to realize data interaction through the serial port between the main control chip and the coprocessor. In the operating system, it includes drivers, RTOS (Real Time Operate System, real-time operating system), task management, inter-task communication, BootLoader (boot loader), system components, memory management, interrupt service and clock management, etc. The drivers include IIC, CAN, SPI, UART, GPIO and Bluetooth. Hardware peripherals include 485, CAN, ESAM (Embedded Secure Access Module), EEPROM (Electrically Erasable Programmable Read Only Memory), FLASH, LED, ADC, watchdog, remote signal, Bluetooth, etc.

[0094] The metering module includes a management chip (i.e., a real-time clock chip (RTC)) and a metering chip. The management chip and the metering chip communicate with each other using SPI (Serial Peripheral Interface). The conversion module uses the same type of chip as the coprocessor. The conversion module also includes an application, an operating system, and hardware peripherals. Since the conversion module cannot communicate directly with the host computer, the TTL group protocol is also used to achieve data interaction through the serial port between the main control chip and the conversion module. The operating system in the conversion module includes UART driver and GPIO driver, and the hardware peripherals include two 485 serial ports.

[0095] Based on the structure of the above-mentioned distributed power access unit, I2C pins and EEPROM can be used to store configuration data such as device ID, address, and communication protocol settings, so it is also necessary to detect the two. For the EEPROM test, the hardware abstraction layer can be called to write a value to the address and then compare the read value of the address to determine whether the function is complete. In addition, in order to ensure the information security of the distributed power unit, the SPI test can be implemented by judging and detecting the serial number obtained by ESAM. For the test of FLASH, operations such as reading and erasing blocks and writing can be used to verify whether the data acquisition is achieved normally. For the metering module in the distributed power access unit, the test can be performed in the following way: the main control chip is used to send a metering data frame such as voltage to the management chip, and the management chip retrieves the data in the metering chip and returns it. If it can be successfully acquired, it is judged to be successful.

[0096] In this embodiment, a device hardware self-checking device is also provided, which is used to implement the above-mentioned embodiments and preferred implementation modes, and the descriptions that have been made will not be repeated. As used below, the term "module" can implement a combination of software and / or hardware of a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, the implementation of hardware, or a combination of software and hardware, is also possible and conceivable.

[0097] This embodiment provides a device hardware self-test device, the device includes various types of hardware interfaces, a main control chip and a coprocessor, and the device is applied to the main control chip, such as Figure 8 As shown, the device comprises: The test frame receiving module 81 is used to receive a message test frame.

[0098] The test interface determination module 82 is used to parse the message test frame to determine the interface type, interface quantity, and management processor of the test interface.

[0099] The first test module 83 is used for short-circuiting the two hardware interfaces if the test interfaces are two hardware interfaces of the same type of the same management processor, sending interface test frames in sequence, and receiving test result frames.

[0100] The second test module 84 is used to short-circuit the two hardware interfaces if the test interfaces are two hardware interfaces of the same type of different management processors, that is, the two hardware interfaces are managed by the main control chip and the coprocessor respectively, interact with the coprocessor based on a preset private protocol, send interface test frames between the hardware interface managed by it and the hardware interface managed by the coprocessor, and verify the interface test frames received by the hardware interface managed by it to generate a test result frame, or receive the test result frame returned by the coprocessor, and the test result frame returned by the coprocessor is generated by verifying the interface test frames received by the hardware interface managed by it.

[0101] In an optional embodiment, the two short-circuited hardware interfaces are a first communication serial port managed by the main control chip and a second communication serial port managed by the coprocessor; the second test module includes: a control module, used to control the opening of the first communication serial port and set the parameters of the first communication serial port; an interaction module, used to interact with the coprocessor based on a preset private protocol, and the coprocessor controls the opening of the second communication serial port and the parameter setting; a first test frame sending module, used to send an interface test frame to the second communication serial port based on the first communication serial port after the parameter setting; a second test frame sending module, used to send a test frame to the coprocessor after a preset delay, and the test frame is used to be parsed by the coprocessor and then send an interface test frame to the first communication serial port based on the second communication serial port.

[0102] In an optional embodiment, the interaction module is specifically used to: send a communication protocol frame for opening the second communication serial port to the coprocessor, the communication protocol frame is used to be parsed by the coprocessor to control the opening of the second communication serial port; receive a reporting frame sent by the coprocessor after controlling the opening of the second communication serial port; send a parameter message frame to the coprocessor based on the reporting frame; receive the parameters of the second communication serial port reported by the coprocessor according to the parameter message frame; send a parameter setting frame to the coprocessor based on the parameters of the second communication serial port, the parameter setting frame is used to be parsed by the coprocessor to set the parameters, and the parameters of the second communication serial port after setting are the same as the parameters of the first communication serial port after setting; receive a parameter result frame sent by the coprocessor after setting the parameters of the second communication serial port.

[0103] In an optional embodiment, the first test module is specifically used to: send a protocol frame to the coprocessor to open two communication serial ports of the same type managed by it, the protocol frame is used to be parsed by the coprocessor to control the opening of the communication serial port; receive a reporting frame sent by the coprocessor after controlling the opening of the communication serial port; send a parameter message frame to the coprocessor based on the reporting frame; receive the parameters of the communication serial port reported by the coprocessor according to the parameter message frame; send a parameter setting frame to the coprocessor based on the parameters of the communication serial port, the parameter setting frame is used to be parsed by the coprocessor to set the parameters of the communication serial port, and the parameters of the two short-circuited communication serial ports are set to the same; receive a parameter result frame sent by the coprocessor after setting the parameters of the communication serial port; send a test frame to the coprocessor based on the parameter result frame, the test frame is used to be parsed by the coprocessor to send an interface test frame based on one communication serial port to another short-circuited communication serial port; receive a test result frame reported by the coprocessor, the test result frame is generated after the coprocessor verifies the interface test frames received by the two communication serial ports.

[0104] In an optional embodiment, the device also includes a first expansion chip and a second expansion chip, and the first expansion chip and the second expansion chip respectively manage two communication serial ports, and the test method of the two communication serial ports managed by the two expansion chips is the same as the test method of the two communication serial ports managed by the coprocessor; the coprocessor, the first expansion chip and the second expansion chip include a test frame processing module, and the two communication serial ports include a forwarding communication serial port and a receiving communication serial port. The forwarding communication serial port is used to obtain preset data and send it to the receiving communication serial port through the inside of the device when used; the test frame processing module is used to change the data transmission mode of the forwarding communication serial port after receiving the interface test frame, and control the forwarding communication serial port to send the interface test frame to the receiving communication serial port.

[0105] In an optional embodiment, the hardware interface also includes a telesignaling interface, and the device also includes: a telesignaling test module, which is used to receive a first telesignaling status test frame if the test interface is a telesignaling interface; obtain a first telesignaling status of the telesignaling interface based on the first telesignaling status test frame and send it to a host computer; receive a second telesignaling test frame, the second telesignaling test frame is issued when the host computer determines that the first telesignaling status meets preset requirements; short-circuit the telesignaling interface and obtain a second telesignaling status of the telesignaling interface; and generate a telesignaling result frame according to the second telesignaling status.

[0106] In an optional implementation, the device includes a distributed power supply access unit, and the hardware interface includes multiple groups of CAN interfaces and multiple groups of 485 interfaces.

[0107] The further functional description of each of the above modules and units is the same as that of the above corresponding embodiments and will not be repeated here.

[0108] The embodiment of the present invention also provides a computer device having the above Figure 8 The device hardware self-test device is shown.

[0109] See also Fig. 9 , Fig. 9 is a schematic diagram of the structure of a computer device provided by an optional embodiment of the present invention, such as Fig. 9As shown, the computer device includes: one or more processors 10, a memory 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. Various components are connected to each other using different buses for communication, and can be installed on a common mainboard or installed in other ways as needed. The processor can process the instructions executed in the computer device, including instructions stored in or on the memory to display the graphical information of the GUI on an external input / output device (such as, a display device coupled to the interface). In some optional embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Similarly, multiple computer devices can be connected, and each device provides some necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). Fig. 9 A processor 10 is taken as an example.

[0110] The processor 10 may be a central processing unit, a network processor or a combination thereof. The processor 10 may further include a hardware chip. The hardware chip may be a dedicated integrated circuit, a programmable logic device or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic or any combination thereof.

[0111] The memory 20 stores instructions executable by at least one processor 10, so that at least one processor 10 executes the method shown in the above embodiment.

[0112] The memory 20 may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store data created by the use of a computer device based on the presentation of a small program landing page, etc. In addition, the memory 20 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory 20 may optionally include a memory remotely arranged relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0113] The memory 20 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk or a solid state drive; the memory 20 may also include a combination of the above types of memory.

[0114] The computer device further comprises a communication interface 30 for the computer device to communicate with other devices or a communication network.

[0115] The embodiment of the present invention also provides a computer-readable storage medium. The method according to the embodiment of the present invention can be implemented in hardware, firmware, or can be implemented as a computer code that can be recorded in a storage medium, or can be implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and will be stored in a local storage medium through a network download, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state hard disk, etc.; further, the storage medium can also include a combination of the above types of memories. It can be understood that a computer, a processor, a microprocessor controller, or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor, or hardware, the method shown in the above embodiment is implemented.

[0116] A part of the present invention may be applied as a computer program product, such as a computer program instruction, which, when executed by a computer, can call or provide the method and / or technical solution according to the present invention through the operation of the computer. Those skilled in the art should understand that the existence of the computer program instruction in a computer-readable medium includes, but is not limited to, a source file, an executable file, an installation package file, etc., and accordingly, the way in which the computer program instruction is executed by the computer includes, but is not limited to: the computer directly executes the instruction, or the computer compiles the instruction and then executes the corresponding compiled program, or the computer reads and executes the instruction, or the computer reads and installs the instruction and then executes the corresponding installed program. Here, the computer-readable medium may be any available computer-readable storage medium or communication medium accessible to the computer.

[0117] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A device hardware self-check method, characterized in that: The device includes multiple types of hardware interfaces, a main control chip and a coprocessor. The method is applied to the main control chip. The method includes: Receive message test frame; Parsing the message test frame to determine the interface type, interface quantity, and management processor of the test interface; If the test interfaces are two hardware interfaces of the same type of the same management processor, short-circuit the two hardware interfaces, send interface test frames in sequence, and receive test result frames; If the test interfaces are two hardware interfaces of the same type of different management processors, that is, the two hardware interfaces are managed by the main control chip and the coprocessor respectively, the two hardware interfaces are short-circuited, and the coprocessor interacts with the coprocessor based on a preset private protocol. Interface test frames are sent between the hardware interface managed by it and the hardware interface managed by the coprocessor, and the interface test frames received by the hardware interface managed by it are verified to generate a test result frame, or the test result frame returned by the coprocessor is received. The test result frame returned by the coprocessor is generated by verifying the interface test frame received by the hardware interface managed by it.

2. The method according to claim 1, characterized in that The two short-circuited hardware interfaces are the first communication serial port managed by the main control chip and the second communication serial port managed by the coprocessor; Interact with the coprocessor based on a preset private protocol and send interface test frames between the hardware interface managed by it and the hardware interface managed by the coprocessor, including: Controlling the first communication serial port to open, and setting parameters of the first communication serial port; Interacting with the coprocessor based on a preset private protocol, the coprocessor controlling the opening of the second communication serial port and parameter setting; Sending an interface test frame to the second communication serial port based on the first communication serial port after parameter setting; After a preset delay time, a test frame is sent to the coprocessor, and the test frame is used to be parsed by the coprocessor and then send an interface test frame to the first communication serial port based on the second communication serial port.

3. The method according to claim 2, characterized in that Based on the preset private protocol, the coprocessor interacts with the coprocessor, and the coprocessor controls the opening of the second communication serial port and parameter setting, including: Sending a communication protocol frame for opening the second communication serial port to the coprocessor, wherein the communication protocol frame is used to control the opening of the second communication serial port after being parsed by the coprocessor; receiving a reporting frame sent by the coprocessor after controlling the second communication serial port to be opened; Sending a parameter message frame to the coprocessor based on the reporting frame; receiving the parameters of the second communication serial port reported by the coprocessor according to the parameter message frame; Sending a parameter setting frame to the coprocessor based on the parameters of the second communication serial port, wherein the parameter setting frame is used to be parsed by the coprocessor for parameter setting, and the parameters of the second communication serial port after setting are the same as the parameters of the first communication serial port after setting; A parameter result frame is received which is sent by the coprocessor after setting the parameters of the second communication serial port.

4. The method according to claim 1, characterized in that Send interface test frames in sequence and receive test result frames, including: Sending a protocol frame for opening two communication serial ports of the same type managed by the coprocessor to the coprocessor, wherein the protocol frame is used to control the opening of the communication serial ports after being parsed by the coprocessor; Receiving a reporting frame sent after the coprocessor controls the communication serial port to be opened; Sending a parameter message frame to the coprocessor based on the reporting frame; Receiving the parameters of the communication serial port reported by the coprocessor according to the parameter message frame; Sending a parameter setting frame to the coprocessor based on the parameters of the communication serial port, wherein the parameter setting frame is used to be parsed by the coprocessor to set the parameters of the communication serial port, and the parameters of the two short-circuited communication serial ports are set to be the same; Receiving a parameter result frame sent by the coprocessor after setting the parameters of the communication serial port; Sending a test frame to the coprocessor based on the parameter result frame, wherein the test frame is used to send an interface test frame based on one communication serial port to another short-circuited communication serial port after being parsed by the coprocessor; A test result frame reported by the coprocessor is received, wherein the test result frame is generated after the coprocessor verifies the interface test frames received by the two communication serial ports.

5. The method according to claim 4, characterized in that The device also includes a first expansion chip and a second expansion chip, the first expansion chip and the second expansion chip respectively manage two communication serial ports, and the test method of the two communication serial ports managed by the two expansion chips is the same as the test method of the two communication serial ports managed by the coprocessor; The coprocessor, the first expansion chip and the second expansion chip include a test frame processing module, and the two communication serial ports include a forwarding communication serial port and a receiving communication serial port. The forwarding communication serial port is used to obtain preset data and send it to the receiving communication serial port through the inside of the device when used; the test frame processing module is used to change the data transmission mode of the forwarding communication serial port after receiving the interface test frame, and control the forwarding communication serial port to send the interface test frame to the receiving communication serial port.

6. The method according to claim 1, characterized in that The hardware interface also includes a remote signaling interface, and the method further includes: If the test interface is a telesignaling interface, receiving a first telesignaling state test frame; Acquiring the first telesignaling state of the telesignaling interface based on the first telesignaling state test frame and sending it to the host computer; receiving a second telesignaling test frame, where the second telesignaling test frame is issued when the host computer determines that the first telesignaling state meets a preset requirement; Short-circuit the remote signal interface and obtain the second remote signal status of the remote signal interface; A telesignaling result frame is generated according to the second telesignaling state.

7. The method according to claim 1, characterized in that The device comprises a distributed power supply access unit, and the hardware interface comprises a plurality of groups of CAN interfaces and a plurality of groups of 485 interfaces.

8. A device hardware self-checking device, characterized in that: The device includes various types of hardware interfaces, a main control chip and a coprocessor. The apparatus is applied to the main control chip and includes: A test frame receiving module, used for receiving a message test frame; A test interface determination module, used for parsing the message test frame to determine the interface type, interface quantity, and management processor of the test interface; The first test module is used for short-circuiting the two hardware interfaces if the test interfaces are two hardware interfaces of the same type of the same management processor, sending interface test frames in sequence, and receiving test result frames; The second test module is used to interact with the coprocessor based on a preset private protocol if the test interface is two hardware interfaces of the same type of different management processors, that is, the two hardware interfaces are respectively managed by the main control chip and the coprocessor, and to send interface test frames between the hardware interface managed by it and the hardware interface managed by the coprocessor, and to verify the interface test frames received by the hardware interface managed by it to generate test result frames, or to receive the test result frames returned by the coprocessor, and the test result frames returned by the coprocessor are generated by verifying the interface test frames received by the hardware interface managed by it.

9. A computer device, characterized in that: include: A memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the device hardware self-check method according to any one of claims 1 to 7 by executing the computer instructions.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a computer to execute the device hardware self-check method according to any one of claims 1 to 7.

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