Data transmission method and system, electronic equipment and storage medium

Abstract

The invention relates to a data transmission method and system, electronic equipment and a storage medium, the method is applied to a master node, the master node corresponds to a plurality of slave nodes, the master node comprises a counter corresponding to each slave node, and a numerical value in the counter corresponding to each slave node is used for indicating the data receiving capability of the slave node; the method comprises the following steps: for any slave node, under the conditions that a numerical value in a counter corresponding to the slave node is not 0 and data needing to be sent to the slave node is prepared, determining the slave node as a first slave node, and generating an effective signal corresponding to the first slave node; under the condition that the plurality of first slave nodes exist, selecting one of the plurality of first slave nodes to be determined as a second slave node; and sending data to the second slave node. According to the embodiment of the invention, the condition that the slave node without the data receiving capability blocks the pipeline channel can be effectively avoided.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, and in particular to a data transmission method and system, an electronic device, and a storage medium. Background Art

[0002] In the prior art, the bus interface corresponding to the master node is shared by multiple slave nodes, that is, multiple slave nodes share the same pipeline channel. If the slave node selected by the master node for data transmission cannot receive data in time at the exit of the pipeline channel, the pipeline channel is easily blocked. Summary of the invention

[0003] The present disclosure proposes a technical solution of a data transmission method and system, an electronic device, and a storage medium.

[0004] According to one aspect of the present disclosure, there is provided a data transmission method, which is applied to a master node, the master node corresponds to a plurality of slave nodes, the master node includes a counter corresponding to each slave node, and the value in the counter corresponding to each slave node is used to indicate the data receiving capability of the slave node; the method comprises: for any slave node, when the value in the counter corresponding to the slave node is not 0 and the data to be sent to the slave node is ready, determining the slave node as a first slave node and generating a valid signal corresponding to the first slave node; when there are a plurality of the first slave nodes, selecting one from the plurality of the first slave nodes as a second slave node; and sending data to the second slave node.

[0005] In one possible implementation, for any slave node, the slave node includes a first-in-first-out FIFO memory with a depth of N, wherein the depth N of the FIFO memory is used to indicate support for storing data of N target data bit widths, and the upper limit of the value in the counter corresponding to the slave node is N, where N is a positive integer greater than or equal to 2; the method also includes: receiving a credit signal sent by the second slave node, wherein the credit signal is used to indicate that the second slave node has completed a data read from the FIFO memory; based on the credit signal, adjusting the value in the counter corresponding to the second slave node.

[0006] In one possible implementation, the number of data of the target data bit width sent by the master node in one clock cycle is x, and the number of data of the target data bit width read by the second slave node in one clock cycle is y, wherein x and y are both positive integers greater than or equal to 1 and less than N; adjusting the value in the counter corresponding to the second slave node based on the credit signal includes: in the current clock cycle, when the credit signal is received and no data is sent to the second slave node, controlling the value in the counter corresponding to the second slave node to increase by y; in the current clock cycle, when the credit signal is not received and data is sent to the second slave node, controlling the value in the counter corresponding to the second slave node to decrease by x; in the current clock cycle, when the credit signal is received and data is sent to the second slave node, controlling the value in the counter corresponding to the second slave node to increase by yx; in the current clock cycle, when the credit signal is not received and no data is sent to the second slave node, controlling the value in the counter corresponding to the second slave node to remain unchanged.

[0007] In a possible implementation, the master node corresponds to multiple pipeline modules, and the multiple slave nodes share the multiple pipeline modules; sending data to the second slave node includes: sending data to the second slave node using the sequential data transmission of the multiple pipeline modules.

[0008] In a possible implementation, for any slave node, a multi-stage trigger is included between the slave node and the master node; receiving the credit signal sent by the second slave node includes: receiving the credit signal by utilizing sequential data transmission of the multi-stage trigger.

[0009] In a possible implementation, sending data to the second slave node includes: determining a corresponding data reading address for the data to be sent to the second slave node; and based on the data reading address, the master node reads data from a corresponding data storage device.

[0010] In one possible implementation, the method further includes: for any slave node, based on the data transmission delay between the master node and the slave node, determining the 100% bandwidth utilization FIFO depth corresponding to the slave node; according to the 100% bandwidth utilization FIFO depth corresponding to the slave node and the target bandwidth utilization required by the slave node, determining the depth N of the FIFO memory included in the slave node, wherein the target bandwidth utilization is greater than 0 and less than or equal to 100%.

[0011] According to one aspect of the present disclosure, there is provided a data transmission system, including: a master node and multiple slave nodes, the master node including a counter corresponding to each slave node, the value in the counter corresponding to each slave node being used to indicate the data receiving capability of the slave node; the master node being used to determine, for any slave node, as a first slave node and generate a valid signal corresponding to the first slave node when the value in the counter corresponding to the slave node is not 0 and the data to be sent to the slave node is ready; the master node being used to select one from the multiple first slave nodes as a second slave node when there are multiple first slave nodes; the master node being used to send data to the second slave node.

[0012] According to one aspect of the present disclosure, an electronic device is provided, comprising: a processor; and a memory for storing processor-executable instructions; wherein the processor is configured to call the instructions stored in the memory to execute the above method.

[0013] According to one aspect of the present disclosure, a computer-readable storage medium is provided, on which computer program instructions are stored, and the computer program instructions implement the above method when executed by a processor.

[0014] In the disclosed embodiment, a counter is set in the master node for each corresponding slave node, and the data receiving capability of the slave node is indicated based on the value in the counter, so that for any slave node, the master node can determine the slave node as the first slave node and generate a valid signal corresponding to the first slave node when the value in the counter corresponding to the slave node is not 0, that is, the slave node has the data receiving capability and the data to be sent to the slave node is ready. Compared with the method of generating a valid signal only when the data preparation is completed, it can effectively avoid generating a valid signal for a slave node that does not have the data receiving capability, causing such a slave node to block the pipeline channel; further, in the case of multiple first slave nodes, one is selected from the multiple first slave nodes to be determined as the second slave node, and data is sent to the second slave node, thereby effectively realizing data transmission between the master node and the second slave node.

[0015] It should be understood that the above general description and the following detailed description are exemplary and explanatory only and do not limit the present disclosure. Other features and aspects of the present disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The drawings herein are incorporated into the specification and constitute a part of the specification. These drawings illustrate embodiments consistent with the present disclosure and are used to illustrate the technical solutions of the present disclosure together with the specification.

[0017] Figure 1 A schematic diagram showing a pipeline channel between a master node and a slave node in the prior art.

[0018] Figure 2 A schematic diagram showing a shared pipeline channel between a master node and multiple slave nodes in the prior art.

[0019] Figure 3 A flow chart of a data transmission method according to an embodiment of the present disclosure is shown.

[0020] Figure 4 A schematic diagram showing a data transmission channel between a master node and a slave node according to an embodiment of the present disclosure.

[0021] Figure 5 A schematic diagram showing a data transmission channel between a master node and a slave node according to an embodiment of the present disclosure.

[0022] Figure 6 A block diagram of a data transmission system according to an embodiment of the present disclosure is shown.

[0023] Figure 7 A block diagram of an electronic device according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0024] Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise specified.

[0025] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0026] The term "and / or" herein is only a description of the association relationship of the associated objects, indicating that there may be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the term "at least one" herein represents any combination of at least two of any one or more of a plurality of. For example, including at least one of A, B, and C can represent including any one or more elements selected from the set consisting of A, B, and C.

[0027] In addition, in order to better illustrate the present disclosure, numerous specific details are given in the following specific embodiments. It should be understood by those skilled in the art that the present disclosure can also be implemented without certain specific details. In some examples, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present disclosure.

[0028] In the prior art, when designing a graphics processing unit (GPU) system, a pipeline structure is usually used for issuing instructions and transmitting data, which can minimize the waiting delay when the GPU system is running. Usually, the interface protocol of the pipeline is a valid-enable handshake protocol, in which the valid signal and the enable signal are both control flows. Under the valid-enable handshake protocol, a valid signal is initiated by the master node, indicating that the payload data of the master node has been prepared and can be transmitted downstream; and the slave node indicates whether it is capable of receiving the payload data of the master node through an enable signal. When the valid signal and the enable signal are both valid, it means that the payload data of the current clock cycle has been successfully transmitted from the master node to the slave node. In digital design, the valid signal and the enable signal are usually unrelated, especially the valid signal of the master node should not be directly dependent on the enable signal generation to avoid deadlock in the design.

[0029] The bus module is the control module responsible for resource scheduling and allocation in the GPU. Since there are usually a large number of data processing nodes (Data masters) on the GPU system that need to read and write caches in parallel or serially and at a high frequency, and the access bandwidth of the cache is limited, the bus module is needed to schedule various operation resources. At this time, the bus module is the master node and multiple Data masters are slave nodes. At the same time, the GPU system usually has certain physical area limitations, so it is usually necessary to reuse functional resources as much as possible. When the Data master reads the cache, it usually reads multiple data with continuous virtual addresses based on a single instruction (depending on different requirements, the data bit width of each data can be 16 bytes, 32 bytes, 64 bytes, etc.), but the physical addresses of these data in the cache are not necessarily always on the same page. Based on the efficiency principle of GPU system operation, if the cache is allowed to jump on different pages for each read request, the efficiency is undoubtedly low. Therefore, in order to improve efficiency, the data returned by the cache can usually be out of order, and the bus module needs to preserve the order of the returned data before distributing it to the data request source Data master. In a typical example, the throughput of any channel (instruction channel, data channel) of any two of the data master-bus module-cache is one interaction per clock cycle.

[0030] In actual scenarios, there may be multiple Data Masters whose data needs to be kept in order by the bus module, and in a certain clock cycle, the data of multiple Data Masters have been arranged in order and are waiting to be returned. Under the valid-enable protocol, the bus module should only rely on the status of the returnable data, and through a certain algorithm (including but not limited to polling arbitration), select one Data Master in each clock cycle to indicate a valid signal to it, and return the data in the payload. The selected data to be returned will wait to be collected or absorbed into the next level of the pipeline at the interface between the bus and the Data Master according to the bus structure. Figure 1 A schematic diagram showing a pipeline channel between a master node and a slave node in the prior art. Figure 1 The master node in the GPU system can be a bus module, and the slave node can be a Data master in the GPU system that needs the bus module to schedule and allocate resources. Figure 1 As shown in p0), pipeline module 1 ( Figure 1 As shown in p1), there is a register array that can store data sent from the previous level and transfer data to the next level. Figure 1The master node and slave node shown in the figure transmit data based on the valid-enable protocol. The existence of p0 and p1 may be a simple register array that meets the timing requirements, or it may be a functional module that needs to perform some special processing and calculation on the data.

[0031] Usually, the data channel resources of multiple Data maters in the bus interface are shared, or, in some scenarios, the data channel resources of multiple Data maters may be shared by the bus interface, that is, multiple Data maters share the same pipeline channel. Therefore, if the Data master that has been initiated with a valid signal by the bus module cannot initiate an enable signal in time at the pipeline channel exit to collect data, it is easy for the pipeline channel to be blocked, and eventually the pressure is reversed upward to the bus module step by step. Figure 2 FIG. 1 is a schematic diagram showing a shared pipeline channel between a master node and multiple slave nodes in the prior art. Figure 2 As shown, multiple slave nodes (slave node 0, slave node 1, slave node 2) share pipeline module 0 ( Figure 2 p0) and pipeline module 1 ( Figure 2 As shown in p1, the data is selected at the exit of p1 to be assigned to which slave node. The valid signal of p1 depends on whether there is data to be transmitted in the internal register array. There is data0 to be transmitted in p1. p1 determines slave node 1 for data0 among slave nodes 0, 1, and 2 through the demultiplexer (Demux) structure, that is, data0 needs to be sent to slave node 1. At this time, p1 sends a valid_p1 signal to slave node 1. Figure 2 The enable signal marked in is used to indicate the current data receiving status of slave node 1. If the enable signal is invalid, for example, enable=0, it means that slave node 1 currently does not have the ability to receive data, that is, slave node 1 and p1 cannot complete the protocol handshake in the current clock cycle, and data0 cannot be sent to slave node 1 in the next clock cycle, and still needs to be stored in p1. p1 further back-pressures p0 through enable_p1=0, and p0 back-pressures the master node through enable_p0=0, causing the master node to return data bandwidth unsatisfied. Worse still, if the data that needs to be sent to slave nodes 0 and 2 in the master node is ready, but the exits of p0 and p1 are blocked by the back pressure of slave node 1, the functional efficiency of the master node is also reduced.

[0032] This bus module, which may reduce the GPU working efficiency or hang the GPU due to a less efficient or faulty Data Master, is obviously not a high-efficiency bus module. Since the Data Master failure is unpredictable for the bus module, and the inefficient Data Master often has bottlenecks that are difficult to handle, it is necessary to configure the bus module to reduce the pipeline channel blocking probability of such inefficient Data Master, or customize the bandwidth utilization for the Data Master according to demand, so as to effectively improve the GPU system performance.

[0033] Based on the problem that a certain slave node may block the pipeline channel when multiple slave nodes share the pipeline channel, the embodiment of the present disclosure provides a data transmission method, which can be applied to the master node to reduce the situation where a certain slave node causes the pipeline channel to be blocked, and effectively realize the data transmission between the master node and the slave nodes. The data transmission method of the embodiment of the present disclosure is described in detail below.

[0034] Figure 3 A flow chart of a data transmission method according to an embodiment of the present disclosure is shown. The method is applied to a master node, wherein the master node corresponds to multiple slave nodes, and the master node includes a counter corresponding to each slave node, and the value in the counter corresponding to each slave node is used to indicate the data receiving capability of the slave node; the master node can be a bus module for resource scheduling and allocation in electronic devices such as terminal devices or servers, and the slave node can be a Data master in electronic devices such as terminal devices or servers that requires the master node to schedule and allocate resources. The method can be executed by an electronic device such as a terminal device or a server, and the terminal device can be a user equipment (User Equipment, UE), a mobile device, a user terminal, a terminal, a cellular phone, a cordless phone, a personal digital assistant (Personal Digital Assistant, PDA), a handheld device, a computing device, a vehicle-mounted device, a wearable device, etc. The method can be implemented by a processor calling a computer-readable instruction stored in a memory. Alternatively, the method can be executed by a server. As Figure 3 As shown, the method includes:

[0035] In step S31, for any slave node, when the value in the counter corresponding to the slave node is not 0 and the data to be sent to the slave node is ready, the slave node is determined as the first slave node and a valid signal corresponding to the first slave node is generated.

[0036] For any slave node, if the value in the counter corresponding to the slave node is not 0, it can indicate that the slave node currently has the ability to receive data. Only by knowing whether the slave node has the ability to receive data can we determine whether the slave node is able to receive data from the pipeline channel in time after the data is sent to the slave node, so as to avoid pipeline channel blocking.

[0037] For any slave node, when the value in the counter corresponding to the slave node is not 0, that is, the slave node has the ability to receive data and the data to be sent to the slave node is ready, the slave node can be identified as the first slave node, and a valid signal corresponding to the first slave node is generated to indicate that after the master node sends data to the first slave node, the first slave node is capable of receiving data from the pipeline channel.

[0038] The first slave node refers to a slave node that has data receiving capability and to which the data that the master node needs to send is already prepared.

[0039] The generation of a valid signal may be directly generated, or may be performed by updating a valid signal in an invalid state to a valid state, for example, updating valid=0 to valid=1, and the embodiments of the present disclosure do not specifically limit this.

[0040] Compared with the method of generating a valid signal only when data preparation is completed, the embodiment of the present disclosure can further consider the data receiving capability of the slave node, effectively avoiding generating a valid signal for slave nodes that do not have the data receiving capability, causing such slave nodes to block the pipeline channel.

[0041] In one example, for any slave node, when the value in the counter corresponding to the slave node is 0, even if the data to be sent to the slave node has been prepared, a corresponding valid signal will not be generated for the slave node.

[0042] In one example, for any slave node, when the value in the counter corresponding to the slave node is not 0, if the data to be sent to the slave node is not ready yet, a corresponding valid signal will not be generated for the slave node.

[0043] In step S32, when there are multiple first slave nodes, one is selected from the multiple first slave nodes and determined as the second slave node.

[0044] Since multiple slave nodes share the pipeline channel with the master node, when there are multiple first slave nodes, that is, when there are multiple slave nodes corresponding to valid signals, that is, the master node can send data to multiple first slave nodes. At this time, the master node needs to select one from the multiple first slave nodes as the second slave node for the next data transmission.

[0045] The method for the master node to select a second slave node from a plurality of first slave nodes having corresponding valid signals may be based on a polling arbitration method or other selection algorithms, which is not specifically limited in the present disclosure.

[0046] In step S33, data is sent to the second slave node.

[0047] After the master node selects a second slave node from a plurality of first slave nodes having corresponding valid signals, the master node may send data to the second slave node.

[0048] In the disclosed embodiment, a counter is set in the master node for each corresponding slave node, and the data receiving capability of the slave node is indicated based on the value in the counter, so that for any slave node, the master node can determine the slave node as the first slave node and generate a valid signal corresponding to the first slave node when the value in the counter corresponding to the slave node is not 0, that is, the slave node has the data receiving capability and the data to be sent to the slave node is ready. Compared with the method of generating a valid signal only when the data preparation is completed, it can effectively avoid generating a valid signal for a slave node that does not have the data receiving capability, causing such a slave node to block the pipeline channel; further, in the case of multiple first slave nodes, one is selected from the multiple first slave nodes to be determined as the second slave node, and data is sent to the second slave node, thereby effectively realizing data transmission between the master node and the second slave node.

[0049] In one possible implementation, for any slave node, the slave node includes a first-in-first-out (FIFO) memory with a depth of N, wherein the depth N of the FIFO memory is used to indicate support for storing data of N target data bit widths, and the upper limit of the value in the counter corresponding to the slave node is N, where N is a positive integer greater than or equal to 2; the method also includes: receiving a credit signal sent by a second slave node, wherein the credit signal is used to indicate that the second slave node has completed a data read from the FIFO memory; based on the credit signal, adjusting the value in the counter corresponding to the second slave node.

[0050] Each port for receiving data from a slave node is configured with a FIFO memory of a specific depth to absorb the data consumption and processing delay of the slave node. At the same time, the master node increases the counter corresponding to each slave node to indicate the data receiving capability of the slave node according to the value in the counter corresponding to each slave node. The upper limit of the value in the counter corresponding to each slave node is the depth of the FIFO memory in the slave node, that is, the maximum number of data of the target bit width supported by the slave node.

[0051] The target data bit width may be flexibly set according to the actual scenario. For example, the target data bit width may be 16 Byte, 32 Byte, 64 Byte, etc., and the embodiments of the present disclosure do not specifically limit this.

[0052] For example, slave node 1 includes a FIFO memory with a depth of N=4, that is, slave node 1 supports storing data of a target data width of up to 4. At this time, the upper limit of the value in the counter corresponding to slave node 1 included in the master node is 4; slave node 2 includes a FIFO memory with a depth of N=7, that is, slave node 2 supports storing data of a target data width of up to 7. At this time, the upper limit of the value in the counter corresponding to slave node 2 included in the master node is 7; and so on.

[0053] Figure 4 A schematic diagram showing a data transmission channel between a master node and a slave node according to an embodiment of the present disclosure. Figure 4 As shown, the master node includes a counter corresponding to the slave node. When the value in the counter corresponding to the slave node is not 0 and the data to be sent to the slave node is ready and passes through the logic, a valid signal corresponding to the slave node is generated, and the master node transmits data to the slave node. When the value in the counter corresponding to the slave node decreases to 0, the master node limits sending data to the slave node.

[0054] In addition, for any slave node, the slave node can directly send a credit signal to the master node without passing through the pipeline channel to synchronize the data consumption status of the slave node. Figure 4 As shown, the slave node directly sends a credit signal to the master node without passing through the pipeline channel. After receiving the credit signal sent by the slave node, the master node can adjust the value in the counter corresponding to the slave node, for example, increment until the upper limit of the value is reached.

[0055] Taking the second slave node selected above as an example, the master node uses the pipeline channel to send data to the second slave node. After the second slave node completes a data read in the FIFO memory, the second slave node returns a credit signal directly to the master node without going through the pipeline channel to prompt the master node that the second slave node has consumed the data, that is, the FIFO memory has increased its data receiving capacity.

[0056] For any slave node, within one clock cycle, the master node receives a credit signal sent by the slave node. Since the credit signal is used to indicate the data consumption status of the slave node, the master node adjusts the value in the counter corresponding to the slave node based on the credit signal to accurately indicate the data receiving capability of the slave node.

[0057] In one possible implementation, the number of data of the target data bit width sent by the master node in one clock cycle is x, and the number of data of the target data bit width read by the second slave node in one clock cycle is y, wherein x and y are both positive integers greater than or equal to 1 and less than N; based on a credit signal, adjusting the value in the counter corresponding to the second slave node, including: in the current clock cycle, when a credit signal is received and no data is sent to the second slave node, controlling the value in the counter corresponding to the second slave node to increase by y; in the current clock cycle, when no credit signal is received and data is sent to the second slave node, controlling the value in the counter corresponding to the second slave node to decrease by x; in the current clock cycle, when a credit signal is received and data is sent to the second slave node, controlling the value in the counter corresponding to the second slave node to increase by yx; in the current clock cycle, when no credit signal is received and no data is sent to the second slave node, controlling the value in the counter corresponding to the second slave node to remain unchanged.

[0058] In the current clock cycle, when the master node receives a credit signal sent by the second slave node and does not send data to the second slave node, it can indicate that the second slave node has not received data and has consumed y data, that is, the second slave node currently has an increased data receiving capacity of y data. At this time, the value in the counter corresponding to the second slave node is controlled to increase by y.

[0059] In the current clock cycle, when the master node does not receive the credit signal sent by the second slave node and sends data to the second slave node, it can be indicated that the second slave node has received x data and has not consumed them, that is, the second slave node currently has a reduced data receiving capacity of x. At this time, the value in the counter corresponding to the second slave node is controlled to decrease by x.

[0060] In the current clock cycle, when the master node does not receive the credit signal sent by the second slave node and does not send data to the second slave node, it can indicate that the second slave node has not received or consumed data, that is, the current data reception ability of the second slave node remains unchanged. At this time, the value in the counter corresponding to the second slave node is controlled to remain unchanged.

[0061] In the current clock cycle, when the master node receives the credit signal sent by the second slave node and sends data to the second slave node, it can indicate that the second slave node has received x data and consumed y data, that is, the current data reception ability of the second slave node changes to y - x. At this time, the value in the counter corresponding to the second slave node is controlled to change by y - x. When y > x, the value in the counter corresponding to the second slave node increases by y - x; when y < x, the value in the counter corresponding to the second slave node decreases by y - x; when y = x, the value in the counter corresponding to the second slave node remains unchanged, that is, it increases by 0.

[0062] The above logic for increasing and decreasing the value in the counter corresponding to the second slave node also applies to other slave nodes and will not be elaborated here. After the value in the counter corresponding to the slave node is updated, it takes effect in the next clock cycle.

[0063] In an example, assume that the number of data with the target data width sent by the master node in one clock cycle is 1, and the number of data with the target data width read by the slave node in one clock cycle is 1. At this time, the logic for increasing and decreasing the value in the counter corresponding to the slave node can be: in the current clock cycle, when receiving the credit signal sent by the slave node and not sending data to the slave node, control the value in the counter corresponding to the slave node to be incremented by 1, and it takes effect in the next clock cycle after the update; in the current clock cycle, when not receiving the credit signal sent by the slave node and sending data to the slave node, control the value in the counter corresponding to the slave node to be decremented by 1, and it takes effect in the next clock cycle after the update; in the current clock cycle, when receiving the credit signal sent by the slave node and sending data to the slave node, control the value in the counter corresponding to the slave node to remain unchanged, and it takes effect in the next clock cycle after the update; in the current clock cycle, when not receiving the credit signal sent by the slave node and not sending data to the slave node, control the value in the counter corresponding to the slave node to remain unchanged, and it takes effect in the next clock cycle after the update.

[0064] In one example, assuming that the number of data of the target data bit width sent by the master node in one clock cycle is 1, and the number of data of the target data bit width read by the slave node in one clock cycle is 2, at this time, the increase and decrease logic of the value in the counter corresponding to the slave node can be: in the current clock cycle, when a credit signal is received from the slave node and no data is sent to the slave node, the value in the counter corresponding to the slave node is controlled to be increased by 2, and the updated value takes effect in the next clock cycle; in the current clock cycle, when a credit signal is not received from the slave node and data is sent to the slave node, the value in the counter corresponding to the slave node is controlled to be decreased by 1, and the updated value takes effect in the next clock cycle; in the current clock cycle, when a credit signal is received from the slave node and data is sent to the slave node, the value in the counter corresponding to the slave node is controlled to be increased by 1, and the updated value takes effect in the next clock cycle; in the current clock cycle, when a credit signal is not received from the slave node and no data is sent to the slave node, the value in the counter corresponding to the slave node is controlled to remain unchanged, and the updated value takes effect in the next clock cycle.

[0065] In a possible implementation, the master node corresponds to multiple pipeline modules, and multiple slave nodes share the multiple pipeline modules; sending data to the second slave node includes: using the sequential data transmission of the multiple pipeline modules to send data to the second slave node.

[0066] The master node corresponds to multiple pipeline modules, and multiple slave nodes share multiple pipeline modules, that is, multiple slave nodes share the pipeline channel between the master node. For any slave node, the master node sends data to the slave node through the shared pipeline channel.

[0067] The existence of multiple pipeline modules may be a simple register array that meets timing requirements, or it may be a functional module that needs to perform certain special processing and calculations on data. The specific number and specific form of multiple pipeline modules can be flexibly set according to actual needs, and the present disclosure does not make specific limitations on this.

[0068] like Figure 4 As shown, the pipeline channel between the master node and the slave node includes pipeline module 0 ( Figure 4 As shown in p0), pipeline module 1 ( Figure 4 The master node transmits data to the slave node based on the pipeline channel formed by p0 and p1. The interface protocol of the pipeline can be a valid-enable handshake protocol.

[0069] In a possible implementation, for any slave node, a multi-stage trigger is included between the slave node and the master node; receiving a credit signal sent by a second slave node includes: sequentially transmitting data using the multi-stage trigger to receive the credit signal.

[0070] In actual layout and routing, the credit signal cannot be directly connected from the slave node to the master node due to timing and layout and routing of the chip itself, and may need to pass through some triggers (Flip-Flop, FF). Therefore, for any slave node, there are multiple levels of FFs between the slave node and the master node to send the credit signal from the slave node to the master node through the multiple levels of FFs. Figure 5 A schematic diagram showing a data transmission channel between a master node and a slave node according to an embodiment of the present disclosure is shown in FIG. Figure 5 As shown, there are multiple stages of FFs between the master node and the slave node, and the slave node sends a credit signal from the slave node to the master node through the multiple stages of FFs. The number of stages of the multiple stages of FFs corresponding to each slave node can be flexibly set according to actual conditions, and this disclosure does not make specific restrictions on this.

[0071] In a possible implementation, sending data to the second slave node includes: determining a corresponding data read address for the data to be sent to the second slave node; and based on the data read address, the master node reading data from a corresponding data storage device.

[0072] After the master node selects a second slave node from multiple first slave nodes with corresponding valid signals, it first needs to obtain the data read address of the data to be sent to the second slave node, and then, based on the data read address, read data from the data storage device corresponding to the master node to return the data to the second slave node.

[0073] In one example, the data storage device corresponding to the master node may be a static random access memory (SRAM) or other forms of memory, which is not specifically limited in the present disclosure.

[0074] In practical applications, operations such as obtaining a data read address and reading data according to the data read address often require a certain number of clock cycles. In addition, due to the insertion of multiple FFs, the value in the counter corresponding to the slave node included in the master node will be less than or equal to the actual data receiving capacity of the slave node. All these will cause the slave node to have unexpected idle data (bubble) in the data transmission channel, resulting in a scenario where the bandwidth utilization does not meet the preset expectations.

[0075] by Figure 5For example, assume that the depth of the FIFO memory in the slave node is N=4, that is, the upper limit of the value in the counter corresponding to the slave node in the master node is 4. The slave node consumes 1 data in one clock cycle, and there is no delay in reading the FIFO memory from the slave node, that is, the slave node sends 1 credit signal in the clock cycle when the FIFO reads data. The selection delay and data reading delay of the master node are 2 clock cycles, that is, the master node determines the slave node that needs to return data and reads data from the SRAM. Each pipeline module ( Figure 5 As shown in Figure 1, p0 and p1 consume one clock cycle, and the credit signal needs to pass through two FFs (FF0 and FF1) from the slave node back to the master node. Assume that there are no other slave nodes and Figure 5 The slave nodes are competing, and the master node has already responded to the Figure 5 All data sent from the node are ready and in order. Figure 5 The data transmission process between the master node and the slave node shown can be as follows.

[0076] The first clock cycle: the value in the counter corresponding to the slave node in the master node is 4; the data read address of data0 that needs to be returned to the slave node is determined, and an SRAM read signal of data0 is generated based on the data read address of data0.

[0077] The second clock cycle: the value in the counter corresponding to the slave node in the master node is 3; it is determined that the data read address of data1 needs to be returned to the slave node, and an SRAM read signal of data1 is generated based on the data read address of data1.

[0078] The third clock cycle: the value in the counter corresponding to the slave node in the master node is 2; the data read address of data2 that needs to be returned to the slave node is determined, and the SRAM read signal of data2 is generated based on the data read address of data2; data0 enters p0.

[0079] The 4th clock cycle: the value in the counter corresponding to the slave node in the master node is 1; the data read address of data3 that needs to be returned to the slave node is determined, and the SRAM read signal of data3 is generated based on the data read address of data3; data0 enters p1, and data1 enters p0.

[0080] The 5th clock cycle: the value in the counter corresponding to the slave node in the master node is 0; it is determined that data cannot be returned to the slave node; data0 enters the FIFO memory in the slave node, the slave node returns credit0 to FF0, FF1 is empty, data1 enters p1, and data2 enters p0.

[0081] The 6th clock cycle: the value in the counter corresponding to the slave node in the master node is 0; it is determined that no data can be returned to the slave node; data1 enters the FIFO memory in the slave node, the slave node returns credit1 to FF0, credit0 is sent to FF1, data2 enters p1, and data3 enters p0.

[0082] The 7th clock cycle: the value in the counter corresponding to the slave node in the master node is 0; it is determined that data cannot be returned to the slave node; data2 enters the FIFO memory in the slave node, the slave node returns credit2 to FF0, credit1 is sent to FF1, credit0 is sent to the master node, data3 enters p1, and p0 is empty.

[0083] The 8th clock cycle: the value in the counter corresponding to the slave node in the master node is 1; the data read address of data4 that needs to be returned to the slave node is determined, and the SRAM read signal of data4 is generated based on the data read address of data4; data3 enters the FIFO memory in the slave node, the slave node returns credit3 to FF0, credit2 is sent to FF1, and p1 and p0 are empty. The subsequent clock cycles are similar and will not be repeated here.

[0084] According to the above description, the 1st to 7th clock cycles are the entire transmission process of data0, that is, the master node determines that it needs to read data0 from SRAM, and the slave node returns credit0 corresponding to data0, so that the master node increments the value in the counter corresponding to the slave node. 7 clock cycles actually return 4 data (data0 to data3), at this time, the bandwidth utilization rate corresponding to the slave node is 4 / 7=57.14%.

[0085] In one possible implementation, the method further includes: for any slave node, based on the data transmission delay between the master node and the slave node, determining the 100% bandwidth utilization FIFO depth corresponding to the slave node; according to the 100% bandwidth utilization FIFO depth corresponding to the slave node and the target bandwidth utilization required by the slave node, determining the depth N of the FIFO memory included in the slave node, wherein the target bandwidth utilization is greater than 0 and less than or equal to 100%.

[0086] In actual application scenarios, the slave node may require that data transmission must not have bubbles, that is, the bandwidth utilization rate must be 100%. At this time, it is necessary to determine the 100% bandwidth utilization FIFO depth corresponding to the slave node based on the data transmission delay between the master node and the slave node, that is, the depth of the FIFO memory when the bandwidth utilization rate of the slave node is 100%.

[0087] Among them, the data transmission delay includes at least one of the following: the selection delay of the master node, the data reading delay of the master node, the pipeline delay between the master node and the slave node, the credit signal generation delay, the credit signal transmission delay between the slave node and the master node, and the counter update delay of the master node.

[0088] The data reading delay of the master node may include: data reading address acquisition delay and data reading delay.

[0089] The selection delay of the master node refers to the clock cycle required for the master node to generate a data reading address from when the master node determines that the value in the counter corresponding to the slave node is not 0 and the data to be sent to the slave node is ready.

[0090] Data read address acquisition delay refers to the clock cycle required to send the data read address to the data storage device, for example, the clock cycle required to transfer the SRAM read address to the SRAM.

[0091] Data read latency refers to the clock cycle required to read data from a data storage device based on a data read address and send the read data to the output port of a master node. For example, the clock cycle required for an SRAM to read data based on an SRAM read address and send the read data to the output port of a master node.

[0092] The pipeline delay between the master node and the slave node refers to the clock cycle required for the pipeline channel between the master node and the slave node to transmit data.

[0093] The credit signal generation delay refers to the clock cycle required for data to be written into the FIFO memory in the slave node and then read out / consumed based on the logic of generating the credit signal in the slave node.

[0094] The credit signal transmission delay between the slave node and the master node refers to the clock cycle required for the slave node to transmit the credit signal to the master node through multiple stages of FFs, for example, it may be the clock cycle corresponding to the multiple stages of FFs.

[0095] The counter update delay of the master node refers to the clock cycle required for the master node to feed back the credit signal received to the counter.

[0096] The data transmission delay between the master node and the slave node may include at least one of the above, or may also include other delays according to the actual application scenario, and the present disclosure does not make specific limitations on this.

[0097] by Figure 5For example, the data transmission delay only includes: data read address acquisition delay, data read delay, pipeline delay between the master node and the slave node, and credit signal transmission delay between the slave node and the master node.

[0098] Since the entire transmission process of data0 requires 7 clock cycles, it is necessary to increase the upper limit of the counter corresponding to the slave node in the master node to 7, that is, to increase the depth of the FIFO memory in the slave node to 7. After modification, Figure 5 The data transmission process between the master node and the slave node shown can be as follows.

[0099] The first clock cycle: the value in the counter corresponding to the slave node in the master node is 7; it is determined that the data read address of data0 needs to be returned to the slave node, and an SRAM read signal of data0 is generated based on the data read address of data0.

[0100] The second clock cycle: the value in the counter corresponding to the slave node in the master node is 6; it is determined that the data read address of data1 needs to be returned to the slave node, and an SRAM read signal of data1 is generated based on the data read address of data1.

[0101] The third clock cycle: the value in the counter corresponding to the slave node in the master node is 5; the data read address of data2 that needs to be returned to the slave node is determined, and the SRAM read signal of data2 is generated based on the data read address of data2; data0 enters p0.

[0102] The 4th clock cycle: the value in the counter corresponding to the slave node in the master node is 4; the data read address of data3 that needs to be returned to the slave node is determined, and the SRAM read signal of data3 is generated based on the data read address of data3; data0 enters p1, and data1 enters p0.

[0103] The 5th clock cycle: the value in the counter corresponding to the slave node in the master node is 3; determine the data read address of data4 that needs to be returned to the slave node, and generate the SRAM read signal of data4 based on the data read address of data4; data0 enters the FIFO memory in the slave node, and the slave node returns credit0 to FF0, FF1 is empty, data1 enters p1, and data2 enters p0.

[0104] The 6th clock cycle: the value in the counter corresponding to the slave node in the master node is 2; the data read address of data5 that needs to be returned to the slave node is determined, and the SRAM read signal of data5 is generated based on the data read address of data5; data1 enters the FIFO memory in the slave node, the slave node returns credit1 to FF0, credit0 is sent to FF1, data2 enters p1, and data3 enters p0.

[0105] The 7th clock cycle: the value in the counter corresponding to the slave node in the master node is 1; the data read address of data6 that needs to be returned to the slave node is determined, and the SRAM read signal of data6 is generated based on the data read address of data6; data2 enters the FIFO memory in the slave node, the slave node returns credit2 to FF0, credit1 is sent to FF1, credit0 is sent to the master node, data3 enters p1, and data4 enters p0.

[0106] The 8th clock cycle: the value in the counter corresponding to the slave node in the master node is 1; the data read address of data7 that needs to be returned to the slave node is determined, and the SRAM read signal of data7 is generated based on the data read address of data7; data3 enters the FIFO memory in the slave node, the slave node returns credit3 to FF0, credit2 is sent to FF1, credi1 is sent to the master node, data4 enters p1, and data5 enters p0. The subsequent clock cycles are similar and will not be repeated here.

[0107] Since the FIFO memory in the slave node is used to collect data, assuming that the target data bit width of 1 data is 32Byte, at this time, for each increase in the depth of the FIFO memory, at least 256 FFs need to be added physically. Since there may be many slave nodes corresponding to the master node, some slave nodes may not require 100% bandwidth utilization, so blindly increasing the area overhead caused by the FIFO memory depth is meaningless.

[0108] Since the relative position of each slave node to the master node in the physical design of the chip is different, the logic of generating credit signals of different slave nodes is different, the data consumption capacity of each slave node is different, and the bandwidth utilization requirements are different, therefore, based on the personalized differences of each slave node, the 100% bandwidth utilization FIFO depth of each slave node can be determined based on the above method, and then according to the target bandwidth utilization actually required by each slave node, the depth N of the FIFO memory in each slave node can be flexibly determined, thereby effectively realizing the customized allocation of bandwidth resources according to the function and performance requirements of each slave node, and being able to achieve the required resource allocation requirements with lower area consumption, so that the overall efficiency of the data transmission system is improved.

[0109] For example, for any slave node, the depth of the FIFO memory in the slave node = the 100% bandwidth utilization FIFO depth corresponding to the slave node × the target bandwidth utilization corresponding to the slave node.

[0110] In the disclosed embodiment, a counter is set in the master node for each corresponding slave node, and the data receiving capability of the slave node is indicated based on the value in the counter, so that for any slave node, the master node can determine the slave node as the first slave node and generate a valid signal corresponding to the first slave node when the value in the counter corresponding to the slave node is not 0, that is, the slave node has the data receiving capability and the data to be sent to the slave node is ready. Compared with the method of generating a valid signal only when the data preparation is completed, it can effectively avoid generating a valid signal for a slave node that does not have the data receiving capability, causing such a slave node to block the pipeline channel; further, in the case of multiple first slave nodes, one is selected from the multiple first slave nodes to be determined as the second slave node, and data is sent to the second slave node, thereby effectively realizing data transmission between the master node and the second slave node.

[0111] It can be understood that the above-mentioned various method embodiments mentioned in the present disclosure can be combined with each other to form a combined embodiment without violating the principle logic. Due to space limitations, the present disclosure will not repeat them. It can be understood by those skilled in the art that in the above-mentioned method of the specific implementation method, the specific execution order of each step should be determined according to its function and possible internal logic.

[0112] In addition, the present disclosure also provides a data transmission system, an electronic device, a computer-readable storage medium, and a program, all of which can be used to implement any data transmission method provided by the present disclosure. The corresponding technical solutions and descriptions are referred to in the corresponding records of the method part and will not be repeated here.

[0113] Figure 6 FIG. 2 is a block diagram of a data transmission system according to an embodiment of the present disclosure. Figure 6 As shown, the data transmission system includes: a master node and multiple slave nodes, the master node includes a counter corresponding to each slave node, and the value in the counter corresponding to each slave node is used to indicate the data receiving capability of the slave node;

[0114] The master node is used for, for any slave node, if the value in the counter corresponding to the slave node is not 0 and the data to be sent to the slave node is ready, determining the slave node as the first slave node and generating a valid signal corresponding to the first slave node;

[0115] The master node is used to select one from the plurality of first slave nodes to be determined as the second slave node when there are a plurality of first slave nodes;

[0116] The master node is used to send data to the second slave node.

[0117] In a possible implementation, for any slave node, the slave node includes a FIFO memory with a depth of N, wherein the depth N of the FIFO memory is used to indicate support for storing data of N target data bit widths, and an upper limit of a value in a counter corresponding to the slave node is N, where N is a positive integer greater than or equal to 2;

[0118] The master node is used to:

[0119] Receiving a credit signal sent by the second slave node, wherein the credit signal is used to indicate that the second slave node has completed a data read from the FIFO memory;

[0120] Based on the credit signal, the value in the counter corresponding to the second slave node is adjusted.

[0121] In a possible implementation, the number of data of the target data width sent by the master node in one clock cycle is x, and the number of data of the target data width read by the second slave node in one clock cycle is y, where x and y are both positive integers greater than or equal to 1 and less than N;

[0122] The master node is used to:

[0123] In the current clock cycle, when a credit signal is received and no data is sent to the second slave node, the value in the counter corresponding to the second slave node is controlled to increase by y;

[0124] In the current clock cycle, when no credit signal is received and data is sent to the second slave node, the value in the counter corresponding to the second slave node is controlled to decrease by x;

[0125] In the current clock cycle, when a credit signal is received and data is sent to the second slave node, the value in the counter corresponding to the second slave node is controlled to increase by yx;

[0126] In the current clock cycle, when no credit signal is received and no data is sent to the second slave node, the value in the counter corresponding to the second slave node is controlled to remain unchanged.

[0127] In a possible implementation, the master node corresponds to multiple pipeline modules, and multiple slave nodes share the multiple pipeline modules;

[0128] The master node is used to:

[0129] The data is sent to the second slave node by using the sequential data transmission of the multiple pipeline modules.

[0130] In a possible implementation, for any slave node, a multi-level trigger is included between the slave node and the master node;

[0131] The master node is used to:

[0132] The credit signal is received by sequential data transmission using multi-stage triggers.

[0133] In a possible implementation, the master node is specifically used to:

[0134] Determine a corresponding data reading address for the data to be sent to the second slave node;

[0135] Based on the data read address, data is read from the corresponding data storage device.

[0136] In a possible implementation, the data transmission system further includes:

[0137] A first determination module is used to determine, for any slave node, a 100% bandwidth utilization FIFO depth corresponding to the slave node based on a data transmission delay between the master node and the slave node;

[0138] The second determination module is used to determine the depth N of the FIFO memory included in the slave node according to the 100% bandwidth utilization FIFO depth corresponding to the slave node and the target bandwidth utilization required by the slave node, wherein the target bandwidth utilization is greater than 0 and less than or equal to 100%.

[0139] This method has a specific technical connection with the internal structure of the computer system, and can solve the technical problem of how to improve the hardware computing efficiency or execution effect (including reducing the amount of data storage, reducing the amount of data transmission, increasing the hardware processing speed, etc.), thereby obtaining the technical effect of improving the internal performance of the computer system in accordance with the laws of nature.

[0140] In some embodiments, the functions or modules included in the device provided by the embodiments of the present disclosure can be used to execute the method described in the above method embodiments. The specific implementation can refer to the description of the above method embodiments, and for the sake of brevity, it will not be repeated here.

[0141] The embodiment of the present disclosure also provides a computer-readable storage medium on which computer program instructions are stored, and the computer program instructions implement the above method when executed by a processor. The computer-readable storage medium can be a volatile or non-volatile computer-readable storage medium.

[0142] An embodiment of the present disclosure further proposes an electronic device, comprising: a processor; and a memory for storing instructions executable by the processor; wherein the processor is configured to call the instructions stored in the memory to execute the above method.

[0143] The embodiments of the present disclosure also provide a computer program product, including a computer-readable code, or a non-volatile computer-readable storage medium carrying the computer-readable code. When the computer-readable code runs in a processor of an electronic device, the processor in the electronic device executes the above method.

[0144] The electronic device may be provided as a terminal, a server, or a device in other forms.

[0145] Figure 7 A block diagram of an electronic device according to an embodiment of the present disclosure is shown. Figure 7 , the electronic device 1900 can be provided as a server or a terminal device. Figure 7 , the electronic device 1900 includes a processing component 1922, which further includes one or more processors, and a memory resource represented by a memory 1932 for storing instructions executable by the processing component 1922, such as an application. The application stored in the memory 1932 may include one or more modules, each corresponding to a set of instructions. In addition, the processing component 1922 is configured to execute instructions to perform the above method.

[0146] The electronic device 1900 may also include a power supply component 1926 configured to perform power management of the electronic device 1900, a wired or wireless network interface 1950 configured to connect the electronic device 1900 to a network, and an input / output interface 1958. The electronic device 1900 may operate based on an operating system stored in the memory 1932, such as a Microsoft Server operating system (Windows Server 2003). TM ), a graphical user interface operating system launched by Apple (Mac OS X TM ), a multi-user, multi-process computer operating system (Unix TM ), a free and open source Unix-like operating system (Linux TM ), an open source Unix-like operating system (FreeBSD TM ) or similar.

[0147] In an exemplary embodiment, a non-volatile computer-readable storage medium is also provided, such as a memory 1932 including computer program instructions, which can be executed by the processing component 1922 of the electronic device 1900 to perform the above method.

[0148] The present disclosure may be a system, a method and / or a computer program product. The computer program product may include a computer-readable storage medium carrying computer-readable program instructions for causing a processor to implement various aspects of the present disclosure.

[0149] Computer readable storage medium can be a tangible device that can hold and store instructions used by an instruction execution device. Computer readable storage medium can be, for example, (but not limited to) an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof. More specific examples (non-exhaustive list) of computer readable storage medium include: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disk read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device, for example, a punch card or a convex structure in a groove on which instructions are stored, and any suitable combination thereof. The computer readable storage medium used here is not interpreted as a transient signal itself, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagated by a waveguide or other transmission medium (for example, a light pulse by an optical fiber cable), or an electrical signal transmitted by a wire.

[0150] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to each computing / processing device, or downloaded to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network can include copper transmission cables, optical fiber transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in the computer-readable storage medium in each computing / processing device.

[0151] The computer program instructions for performing the operation of the present disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-related instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages, such as Smalltalk, C++, etc., and conventional procedural programming languages, such as "C" language or similar programming languages. Computer-readable program instructions may be executed completely on a user's computer, partially on a user's computer, as an independent software package, partially on a user's computer, partially on a remote computer, or completely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., using an Internet service provider to connect via the Internet). In some embodiments, an electronic circuit, such as a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA), may be customized by utilizing the state information of the computer-readable program instructions, and the electronic circuit may execute the computer-readable program instructions, thereby realizing various aspects of the present disclosure.

[0152] Various aspects of the present disclosure are described herein with reference to the flowcharts and / or block diagrams of the methods, devices (systems) and computer program products according to the embodiments of the present disclosure. It should be understood that each box in the flowchart and / or block diagram and the combination of each box in the flowchart and / or block diagram can be implemented by computer-readable program instructions.

[0153] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, thereby producing a machine, so that when these instructions are executed by the processor of the computer or other programmable data processing device, a device that implements the functions / actions specified in one or more boxes in the flowchart and / or block diagram is generated. These computer-readable program instructions can also be stored in a computer-readable storage medium, and these instructions cause the computer, programmable data processing device, and / or other equipment to work in a specific manner, so that the computer-readable medium storing the instructions includes a manufactured product, which includes instructions for implementing various aspects of the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0154] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device so that a series of operating steps are performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to implement the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0155] The flow chart and block diagram in the accompanying drawings show the possible architecture, function and operation of the system, method and computer program product according to multiple embodiments of the present disclosure. In this regard, each square box in the flow chart or block diagram can represent a part of a module, program segment or instruction, and a part of the module, program segment or instruction includes one or more executable instructions for realizing the specified logical function. In some alternative implementations, the function marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two continuous square boxes can actually be executed substantially in parallel, and they can sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs the specified function or action, or can be implemented with a combination of special hardware and computer instructions.

[0156] The computer program product may be implemented in hardware, software or a combination thereof. In one optional embodiment, the computer program product is embodied as a computer storage medium, and in another optional embodiment, the computer program product is embodied as a software product, such as a software development kit (SDK) and the like.

[0157] The above description of various embodiments tends to emphasize the differences between the various embodiments. The same or similar aspects can be referenced to each other, and for the sake of brevity, they will not be repeated herein.

[0158] Those skilled in the art will appreciate that, in the above method of specific implementation, the order in which the steps are written does not imply a strict execution order and does not constitute any limitation on the implementation process. The specific execution order of the steps should be determined by their functions and possible internal logic.

[0159] If the technical solution of this application involves personal information, the product using the technical solution of this application has clearly informed the personal information processing rules and obtained the individual's voluntary consent before processing the personal information. If the technical solution of this application involves sensitive personal information, the product using the technical solution of this application has obtained the individual's separate consent before processing the sensitive personal information, and at the same time meets the "explicit consent" requirement. For example, on personal information collection devices such as cameras, clear and prominent signs are set to inform that the personal information collection scope has been entered and personal information will be collected. If the individual voluntarily enters the collection scope, it is deemed that he or she agrees to the collection of his or her personal information; or on the device that processes personal information, the personal information processing rules are notified by obvious signs / information, and the individual's authorization is obtained through pop-up information or by asking the individual to upload his or her personal information; among them, the personal information processing rules may include information such as the personal information processor, the purpose of personal information processing, the processing method, and the type of personal information processed.

[0160] The embodiments of the present disclosure have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or improvements to the technology in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A data transmission method, characterized in that: The method is applied to a master node, the master node corresponds to a plurality of slave nodes, the master node includes a counter corresponding to each slave node, and the value in the counter corresponding to each slave node is used to indicate the data receiving capability of the slave node; The method comprises: For any slave node, when the value in the counter corresponding to the slave node is not 0 and the data to be sent to the slave node is ready, the slave node is determined as a first slave node, and a valid signal corresponding to the first slave node is generated; In the case where there are multiple first slave nodes, selecting one from the multiple first slave nodes to be determined as the second slave node; Send data to the second slave node.

2. The method according to claim 1, characterized in that: For any slave node, the slave node includes a first-in first-out FIFO memory with a depth of N, wherein the depth N of the FIFO memory is used to indicate that it supports storing data of N target data bit widths, and the upper limit of the value in the counter corresponding to the slave node is N, and N is a positive integer greater than or equal to 2; The method further comprises: Receiving a credit signal sent by the second slave node, wherein the credit signal is used to indicate that the second slave node has completed a data reading from the FIFO memory; Based on the credit signal, a value in a counter corresponding to the second slave node is adjusted.

3. The method according to claim 2, characterized in that The number of data of the target data width sent by the master node in one clock cycle is x, and the number of data of the target data width read by the second slave node in one clock cycle is y, where x and y are both positive integers greater than or equal to 1 and less than N; The adjusting, based on the credit signal, a value in a counter corresponding to the second slave node comprises: In the current clock cycle, when the credit signal is received and no data is sent to the second slave node, controlling the value in the counter corresponding to the second slave node to increase by y; In the current clock cycle, when the credit signal is not received and data is sent to the second slave node, controlling the value in the counter corresponding to the second slave node to decrease by x; In the current clock cycle, when the credit signal is received and data is sent to the second slave node, the value in the counter corresponding to the second slave node is controlled to increase by yx; In the current clock cycle, when the credit signal is not received and data is not sent to the second slave node, the value in the counter corresponding to the second slave node is controlled to remain unchanged.

4. The method according to claim 1, characterized in that: The master node corresponds to a plurality of pipeline modules, and the plurality of slave nodes share the plurality of pipeline modules; The sending data to the second slave node comprises: Data is sent to the second slave node by utilizing the sequential data transmission of the multiple pipeline modules.

5. The method according to claim 2, characterized in that: For any slave node, a multi-level trigger is included between the slave node and the master node; The receiving the credit signal sent by the second slave node comprises: The credit signal is received by sequentially transmitting data through the multi-stage flip-flops.

6. The method according to claim 1, characterized in that The sending data to the second slave node comprises: For the data to be sent to the second slave node, determining a corresponding data reading address; Based on the data read address, the master node reads data from the corresponding data storage device.

7. The method according to any one of claims 2 to 6, characterized in that The method further comprises: For any slave node, based on the data transmission delay between the master node and the slave node, determine the 100% bandwidth utilization FIFO depth corresponding to the slave node; The depth N of the FIFO memory included in the slave node is determined according to the 100% bandwidth utilization FIFO depth corresponding to the slave node and the target bandwidth utilization required by the slave node, wherein the target bandwidth utilization is greater than 0 and less than or equal to 100%.

8. A data transmission system, characterized in that: include: A master node and a plurality of slave nodes, wherein the master node includes a counter corresponding to each slave node, and a value in the counter corresponding to each slave node is used to indicate the data receiving capability of the slave node; The master node is used for, for any slave node, if the value in the counter corresponding to the slave node is not 0 and the data to be sent to the slave node is ready, determining the slave node as the first slave node and generating a valid signal corresponding to the first slave node; The master node is used to select one from the plurality of first slave nodes as the second slave node when there are a plurality of the first slave nodes; The master node is used to send data to the second slave node.

9. An electronic device, characterized in that: include: processor; a memory for storing processor-executable instructions; The processor is configured to call the instructions stored in the memory to execute the method described in any one of claims 1 to 7.

10. A computer-readable storage medium having computer program instructions stored thereon, characterized in that: When the computer program instructions are executed by a processor, the method according to any one of claims 1 to 7 is implemented.

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