Large-scale chip verification method, electronic device and medium

Abstract

The present invention relates to the field of chip technology, and in particular to a large-scale chip verification method, electronic device and medium, the method comprising step S1, constructing a target test case; step S2, obtaining a test case group name, a verification configuration information name and a test parameter corresponding to the target test case; step S3, obtaining the corresponding target verification configuration information from a preset verification configuration information list; step S4, configuring a large-scale chip verification system based on the target verification configuration information, and generating a target large-scale chip verification system; step S5, obtaining a corresponding target test case group from a preset test case group library; step S6, passing the test parameters corresponding to the target test case to the test case in the target test case group, and then running on the target large-scale chip verification system to verify the verification target. The present invention improves the efficiency and stability of large-scale chip verification and reduces the cost of large-scale chip verification.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular to a large-scale chip verification method, electronic equipment and medium. Background Art

[0002] As the requirements for chip computing power continue to increase, the scale of chips is also increasing. As the scale of chips continues to increase, extremely high requirements are placed on the chip verification platform. In the prior art, the full-chip and full-area verification method is often used to verify large-scale chips. However, the full-chip and full-area verification method has a slow simulation time, consumes a lot of time, has poor operating stability, consumes a lot of resources, and is easily affected by uncertain factors. In response to the shortcomings of full-chip and full-area verification, a modular verification method of module verification is further proposed in the prior art. Different verification platforms are built for different modules, the verification cost is high, and cross-module verification cannot be achieved. It can be seen from this that how to improve the efficiency and stability of large-scale chip verification and reduce the cost of large-scale chip verification has become a technical problem that needs to be solved urgently. Summary of the invention

[0003] The purpose of the present invention is to provide a large-scale chip verification method, electronic equipment and medium, which improve the efficiency and stability of large-scale chip verification and reduce the cost of large-scale chip verification.

[0004] According to a first aspect of the present invention, a large-scale chip verification method is provided, comprising:

[0005] Step S1, constructing a target test case based on a preset python data structure, wherein the preset python data structure includes a test case name data segment, a test case group name data segment, a verification configuration information name data segment, and a test parameter data segment, wherein the test case name data segment is used to define the name of the test target test case, the test case group name data segment is used to specify the test case group name corresponding to the target test case, the test case group is a set of multiple test cases for verifying the same functional attribute of the chip, the verification configuration information name data segment is used to specify the verification configuration information name corresponding to the target test case, and the test parameter data segment is used to define the test parameters corresponding to the target test case;

[0006] Step S2: parse the target test case, obtain the test case group name corresponding to the target test case, the verification configuration information name corresponding to the target test case, and the test parameters corresponding to the target test case;

[0007] Step S3: acquiring corresponding target verification configuration information from a preset verification configuration information list based on the verification configuration information name corresponding to the target test case;

[0008] Step S4: configuring a large-scale chip verification system based on the target verification configuration information to generate a target large-scale chip verification system;

[0009] Step S5: acquiring the corresponding target test case group from a preset test case group library based on the test case group name corresponding to the target test case;

[0010] Step S6: passing the test parameters corresponding to the target test case to the test case in the target test case group, and then running the test case in the target test case group on the target large-scale chip verification system to verify the verification target.

[0011] According to a second aspect of the present invention, there is provided an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being configured to execute the method described in the first aspect of the present invention.

[0012] According to a third aspect of the present invention, there is provided a computer-readable storage medium storing computer-executable instructions, wherein the computer instructions are used to execute the method described in the first aspect of the present invention.

[0013] Compared with the prior art, the present invention has obvious advantages and beneficial effects. By means of the above technical solution, the large-scale chip verification method, electronic device and medium provided by the present invention can achieve considerable technical advancement and practicality, and have wide industrial utilization value, and at least have the following beneficial effects:

[0014] The method of the present invention is based on a pre-built verification configuration information list and a test cluster library, directly, quickly and accurately builds a target test case based on a preset Python data structure, and then runs the test case in the target test cluster on a target large-scale chip verification system based on the target test case, the pre-built verification configuration information list and the test cluster library to verify the verification target, thereby improving the efficiency and stability of large-scale chip verification and reducing the chip verification cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0016] Figure 1 A flow chart of a large-scale chip verification method provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0017] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0018] The embodiment of the present invention provides a large-scale chip verification method, such as Figure 1 As shown, including:

[0019] Step S1, construct a target test case based on a preset python data structure, the preset python data structure includes a test case name data segment, a test case group name data segment, a verification configuration information name data segment and a test parameter data segment. The test case name data segment is used to define the name of the test target test case, the test case group name data segment is used to specify the name of the test case group corresponding to the target test case, the test case group is a set of multiple test cases for verifying the same functional attribute of the chip, the verification configuration information name data segment is used to specify the verification configuration information name corresponding to the target test case, and the test parameter data segment is used to define the test parameters corresponding to the target test case, and the test parameters can be one or more.

[0020] Among them, Python is an existing programming language and will not be described in detail here.

[0021] As an example, the target test case is constructed based on the preset Python data structure:

[0022] test0:smoke_engine0_test

[0023] group:group0

[0024] config:config1

[0025] Test parameter 1: ab

[0026] Test parameter 2: cd

[0027] endtest0

[0028] Among them, "smoke_engine0_test" is the test case name data segment. From the name, we can know that the target test case is to verify engine 0 (engine0). "group:group0" is the test case group name data segment, which specifies the test case group name of the target test case as group0. "config:config1" is the verification configuration information name data segment, which specifies the verification configuration information of the target test case as config1. "Test parameter 1: ab, test parameter 2: cd" is the test parameter data segment, which defines the test parameters ab and cd.

[0029] Step S2: parse the target test case to obtain the test case group name corresponding to the target test case, the verification configuration information name corresponding to the target test case, and the test parameters corresponding to the target test case.

[0030] It should be noted that step S2 specifically parses the target test case through Python syntax.

[0031] Step S3: based on the verification configuration information name corresponding to the target test case, obtain the corresponding target verification configuration information from the preset verification configuration information list.

[0032] It should be noted that, through step S3, the corresponding verification configuration information can be directly obtained from the pre-generated preset verification configuration information list based on the verification configuration information corresponding to the target test case, which is efficient and accurate.

[0033] Step S4: configuring a large-scale chip verification system based on the target verification configuration information to generate a target large-scale chip verification system.

[0034] It should be noted that configuring the large-scale chip verification system based on the verification configuration information enables flexible configuration of the large-scale chip verification system.

[0035] Step S5: based on the test case group name corresponding to the target test case, obtain the corresponding target test case group from a preset test case group library.

[0036] It should be noted that, through step S5, the corresponding target test case group can be directly obtained from the pre-built preset test case group library based on the test case group name corresponding to the target test case, and regression testing can be implemented based on the test case group.

[0037] Step S6: passing the test parameters corresponding to the target test case to the test case in the target test case group, and then running the test case in the target test case group on the target large-scale chip verification system to verify the verification target.

[0038] It should be noted that after the target large-scale chip verification system is built, the test cases with passed test parameters are transmitted to the target large-scale chip verification system, so that the test cases with passed test parameters can be run on the target large-scale chip verification system to realize the verification of the verification target.

[0039] As an embodiment, before step S1, the step further includes:

[0040] Step S01: Generate corresponding verification configuration information {A1, A2, ..., A n ,...,A N},A n is the verification configuration information of the nth component module of the large-scale chip verification system, where n ranges from 1 to N, and N is the total number of components of the large-scale chip verification system. n =(A1 n ,A2 n ), A1 n is the identifier of the nth component module, A2 n For A1 n The corresponding module type identifier.

[0041] Among them, the module type identifier includes a first identifier and a second identifier. The module type corresponding to the first identifier is a hardware module, and the module type corresponding to the second identifier is a behavioral functional model. The hardware module includes the complete internal logic and interface of the module, and the behavioral functional model includes the module functional logic and interface. The functional logic is a kind of logic in the complete internal logic. The interface functions of the hardware module and the behavioral functional model are consistent. It should be noted that the complete internal logic of the module needs to consider factors such as module function, back-end synthesis, timing, area, and tape-out, while the module functional logic only needs to consider module functional factors. Therefore, the behavioral functional model is extremely streamlined compared to the hardware module. The use of the behavioral functional model can greatly improve the simulation speed and reduce resource consumption without affecting the overall function of the system. It should be noted that both the hardware module and the behavioral functional model are implemented based on the hardware description language, and the hardware description language can be specifically Verilog, SystemVerilog, etc.

[0042] Step S02: construct a mapping relationship between the verification target and the corresponding verification configuration information, and store it in a preset verification configuration information list.

[0043] It should be noted that storing the mapping relationship between the verification target and the corresponding verification configuration information in the preset verification configuration information list means storing the verification target name, the verification configuration information, and the corresponding relationship between the verification target name and the verification configuration information in the preset verification configuration information list. On this basis, in the process of constructing the target test case in step S1, the corresponding verification configuration information name can be directly obtained from the preset verification configuration information list based on the verification target corresponding to the target test case, and the corresponding verification configuration information name can be specified in the target test case. If the corresponding verification configuration information name does not exist in the preset verification configuration information list, it is necessary to first construct it based on steps S01 and S02.

[0044] As an embodiment, before step S1, the step further includes:

[0045] Step S10: construct different test case groups {G1, G2, ..., G q ,...,G Q}, G q is the g-th test case group, the value range of q is 1 to Q, Q is the total number of test case groups, and the chip functional attributes include power consumption, chip interconnection, virtual implementation, chip reset, etc.

[0046] Step S20: construct a mapping relationship between chip functional attributes and test case groups, and store the mapping relationship in a preset test case group library.

[0047] It should be noted that storing the mapping relationship between chip functional attributes and test case groups in a preset test case group library refers to storing the chip functional attribute identifier, the test case group, and the corresponding relationship between the chip functional attribute identifier and the test case group in the preset test case group library. On this basis, in the process of building the target test case, step S1 can directly obtain the corresponding test case group name in the preset test case group library based on the chip functional attributes corresponding to the verification target. If the corresponding test case group name does not exist in the preset test case group library, it is necessary to first build it based on steps S10-S20.

[0048] As an embodiment, a large-scale chip verification system includes multiple engine modules, a data path bus, a configuration path bus, a storage module and a PCIE module. Each engine module is used to implement a chip function, such as an image processing function, an encryption and decryption function, a computing function, etc. The PCIE module is a module that complies with the high-speed serial communication interconnection standard protocol (Peripheral Component Interconnect Express). Each engine module is used to implement a chip function, such as an image processing function, an encryption and decryption function, a computing function, etc. Each engine module is connected to the data path bus and the configuration path bus respectively, the storage module is connected to the data path bus and the configuration path bus respectively, and the PCIE module is connected to the data path bus and the configuration path bus respectively. The engine module, the storage module and the PCIE module are all configurable modules, and the configurable modules are set as hardware modules or behavior-level function models (Behavior Function Model) by configuring the module type. The data path bus and the configuration path bus are always set as hardware modules and are non-configurable modules. The hardware module includes the complete internal logic and interface of the module, the behavior-level function model includes the module function logic and interface, the function logic is a logic in the complete internal logic, and the interface functions of the hardware module and the behavior-level function model are consistent. The data path subsystem of a large-scale chip is composed of the engine module, the data path bus, and the storage module. The PCIE module can communicate with the CPU (Central Processing Unit) outside the large-scale chip through the PCIE slot, and the configuration path subsystem of the large-scale chip is composed of the PCIE module, the configuration path bus, and the engine module.

[0049] As an embodiment, step S4 includes:

[0050] Step S41: Based on the target verification configuration information, the configurable modules involved in the verification target in the large-scale chip verification system are set as hardware modules, and the configurable modules not involved in the verification target are set as behavioral functional models to generate a target large-scale chip verification system.

[0051] It should be noted that the verification target is a subsystem or system composed of one module or multiple modules, that is, based on the system, verification of any component module can be achieved, such as any engine module, storage module, PCIE module. It can also be a subsystem composed of an engine module, a storage module, or an engine module and a storage module, or it can be the entire system composed of all the component modules.

[0052] As an embodiment, each configurable module is pre-set with a first file list and a second file list, wherein the first file list is a file list corresponding to the hardware module of the configurable module, and the second file list is a file list corresponding to the behavioral functional model of the configurable module. It should be noted that the size of the first file list of the same configurable module is larger than the size of the second file list.

[0053] The target verification configuration information sets a module type identifier for each configurable module. If the type identifier of the configurable module is set to the first identifier, the first file list corresponding to the configurable module is called to set the configurable module as a hardware module. If the type identifier of the configurable module is set to the second identifier, the second file list corresponding to the configurable module is called to set the configurable module as a behavioral functional model. It should be noted that the configurable modules involved in the verification target in the system are set as hardware modules, and the configurable modules not involved in the verification target are set as behavioral functional models.

[0054] As an embodiment, if the verification target is one of the target engine modules or the interaction between multiple target engine modules, the target verification configuration information sets the target engine module as a hardware module, sets the non-target engine module as well as the storage module and the PCIE module as behavioral-level functional models, and inputs corresponding test stimuli to the system through the target engine to verify the verification target.

[0055] As an embodiment, if the verification target is a storage module, the target verification configuration information sets all engine modules and PCIE modules as behavioral-level functional models, sets the storage module as a hardware module, and inputs an external test stimulus to the storage module through the data path bus to verify the storage module.

[0056] As an embodiment, if the verification target is a PCIE module, the target verification configuration information sets all engine modules and storage modules as behavioral-level functional models, sets the PCIE module as a hardware module, and the PCIE module receives test stimuli from an external CPU to verify the PCIE module.

[0057] As an embodiment, if the verification target is a data path subsystem, the target verification configuration information selects at least one target engine module, sets the target engine module and the storage module as hardware modules, sets the non-target engine module and the PCIE module as behavioral-level functional models, and the target engine module transmits a test stimulus to a data path bus, and performs corresponding read or write operations in the storage module based on the transmitted test stimulus through the data path bus to verify the data path.

[0058] As an embodiment, if the verification target is a configuration path subsystem, the target verification configuration information selects at least one target engine module, sets the target engine module and the PCIE module as hardware modules, sets the non-target engine module and the storage module as behavioral-level functional models, and an external CPU inputs a test stimulus to the PCIE module. The PCIE module executes corresponding configuration operations in the target engine module through the configuration path bus to verify the configuration path.

[0059] It should be noted that the target test case is generated based on Python, so it can be inherited based on the generated test case to quickly generate new test cases, further improving the efficiency of large-scale chip verification. As an embodiment, the step S1 further includes step C0, adding the constructed target test case to the preset test case library;

[0060] The method further comprises:

[0061] Step C1, constructing an inheritance test case based on a preset Python inheritance data structure, wherein the preset Python inheritance data structure includes an inheritance information data segment and an information data segment to be updated, wherein the inheritance information data segment is used to define the name of the target test case and specify the name of the test case to be inherited, and the information data segment to be updated is used to specify the parameter name and target value to be updated in the test case to be inherited.

[0062] Step C2: parse the inherited test case to obtain the name of the target test case, the name of the test case to be inherited, and the name and target value of the parameter to be updated in the test case to be inherited.

[0063] Step C3: based on the name of the test case to be inherited, obtain the test case to be inherited from the preset test case library, modify the parameters that need to be updated in the test case to be inherited to the corresponding target values, generate the target test case, and then execute step S2.

[0064] Take the test case to be inherited as test0 as an example:

[0065] test0:smoke_engine0_test

[0066] group:group0

[0067] config:config1

[0068] Test parameter 1: ab

[0069] Test parameter 2: cd

[0070] endtest0

[0071] Construct inheritance test case test1 based on the preset python inheritance data structure:

[0072] test1→test0

[0073] config:config0

[0074] Endtest1

[0075] Among them, "test1→test0" is the inherited information data segment, "→" represents the inheritance symbol, "test1" represents the name of the target test case, "test0" represents the name of the test case to be inherited, and "config:config0" represents the information data segment to be updated. The target test case obtained after inheritance is:

[0076] test1:smoke_engine0_test

[0077] group:group0

[0078] config:config0

[0079] Test parameter 1: ab

[0080] Test parameter 2: cd

[0081] Endtest1

[0082] As an embodiment, if the inherited test case is a multi-level inherited test case, there are multiple test cases to be inherited.

[0083] In step C2, it is necessary to obtain the names of all test cases to be inherited.

[0084] In step C3, it is necessary to obtain all the test cases to be inherited from the preset test case library based on the names of all the test cases to be inherited, merge them into a combined test case to be inherited, modify the parameters that need to be updated in the combined test case to be inherited to the corresponding target values, generate the target test case, and then execute step S2.

[0085] It should be noted that obtaining all test cases to be inherited and merging them into a combined test case to be inherited means inheriting all parameters of multiple test cases to be inherited, and then all inherited parameters can be updated according to specific verification requirements to generate a target test case.

[0086] It should be noted that some exemplary embodiments are described as processes or methods depicted as flow charts. Although the flow charts describe the steps as sequential processes, many of the steps can be implemented in parallel, concurrently or simultaneously. In addition, the order of the steps can be rearranged. The process can be terminated when its operation is completed, but it can also have additional steps not included in the accompanying drawings. The process can correspond to a method, function, procedure, subroutine, subprogram, etc.

[0087] An embodiment of the present invention also provides an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are configured to execute the method described in the embodiment of the present invention.

[0088] The embodiment of the present invention further provides a computer-readable storage medium storing computer-executable instructions, wherein the computer instructions are used to execute the method described in the embodiment of the present invention.

[0089] The method described in the embodiment of the present invention is based on a pre-built verification configuration information list and a test cluster library, and directly, quickly and accurately builds a target test case based on a preset python data structure. Then, based on the target test case, the pre-built verification configuration information list and the test cluster library, the test case in the target test cluster is run on a target large-scale chip verification system to verify the verification target, thereby improving the efficiency and stability of large-scale chip verification and reducing the chip verification cost.

[0090] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technician familiar with this profession can make some changes or modifications to equivalent embodiments of equivalent changes using the technical contents disclosed above without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of the technical solution of the present invention.

Claims

1. A large-scale chip verification method, characterized in that: include: Step S1, constructing a target test case based on a preset python data structure, wherein the preset python data structure includes a test case name data segment, a test case group name data segment, a verification configuration information name data segment, and a test parameter data segment, wherein the test case name data segment is used to define the name of the test target test case, the test case group name data segment is used to specify the test case group name corresponding to the target test case, the test case group is a set of multiple test cases for verifying the same functional attribute of the chip, the verification configuration information name data segment is used to specify the verification configuration information name corresponding to the target test case, and the test parameter data segment is used to define the test parameters corresponding to the target test case; Step S2: parse the target test case, obtain the test case group name corresponding to the target test case, the verification configuration information name corresponding to the target test case, and the test parameters corresponding to the target test case; Step S3: acquiring corresponding target verification configuration information from a preset verification configuration information list based on the verification configuration information name corresponding to the target test case; Step S4: configuring a large-scale chip verification system based on the target verification configuration information to generate a target large-scale chip verification system; The step S4 comprises: Step S41, based on the target verification configuration information, the configurable modules involved in the verification target in the large-scale chip verification system are set as hardware modules, and the configurable modules not involved in the verification target are set as behavioral functional models, to generate a target large-scale chip verification system; Step S5: acquiring the corresponding target test case group from a preset test case group library based on the test case group name corresponding to the target test case; Step S6: passing the test parameters corresponding to the target test case to the test case in the target test case group, and then running the test case in the target test case group on the target large-scale chip verification system to verify the verification target.

2. The method according to claim 1, characterized in that Before step S1, the following steps are also included: Step S01: Generate corresponding verification configuration information {A1, A2, ..., A n ,...,A N },A n is the verification configuration information of the nth component module of the large-scale chip verification system, where n ranges from 1 to N, and N is the total number of components of the large-scale chip verification system. n =(A1 n ,A2 n ), A1 n is the identifier of the nth component module, A2 n A1 n The corresponding module type identifier; Step S02: construct a mapping relationship between the verification target and the corresponding verification configuration information, and store it in a preset verification configuration information list.

3. The method according to claim 1, characterized in that Before step S1, the following steps are also included: Step S10: construct different test case groups {G1, G2, ..., G q ,...,G Q }, G q is the qth test case group, where the value of q ranges from 1 to Q, where Q is the total number of test case groups, and the chip functional attributes include power consumption, chip interconnection, virtual implementation, and chip reset; Step S20: construct a mapping relationship between chip functional attributes and test case groups, and store the mapping relationship in a preset test case group library.

4. The method according to claim 1, characterized in that: The large-scale chip verification system includes a plurality of engine modules, a data path bus, a configuration path bus, a storage module and a PCIE module, each engine module is used to realize a chip function, each engine module is respectively connected to the data path bus and the configuration path bus, the storage module is respectively connected to the data path bus and the configuration path bus, and the PCIE module is respectively connected to the data path bus and the configuration path bus; The engine module, storage module and PCIE module are all configurable modules. The configurable module can be set as a hardware module or a behavioral-level functional model by configuring the module type; the data path bus and the configuration path bus are always set as hardware modules; the hardware module includes the complete internal logic and interface of the module, and the behavioral-level functional model includes the module functional logic and interface. The functional logic is a type of logic in the complete internal logic, and the interface functions of the hardware module and the behavioral-level functional model are consistent.

5. The method according to claim 1, characterized in that: After step S1, the method further includes step C0, adding the constructed target test case to a preset test case library; The method further comprises: Step C1, constructing an inheritance test case based on a preset Python inheritance data structure, wherein the preset Python inheritance data structure includes an inheritance information data segment and an information data segment to be updated, wherein the inheritance information data segment is used to define the name of the target test case and specify the name of the test case to be inherited, and the information data segment to be updated is used to specify the parameter name and target value to be updated in the test case to be inherited; Step C2: parsing the inherited test case to obtain the name of the target test case, the name of the test case to be inherited, and the name and target value of the parameter to be updated in the test case to be inherited; Step C3: based on the name of the test case to be inherited, obtain the test case to be inherited from the preset test case library, modify the parameters that need to be updated in the test case to be inherited to the corresponding target values, generate the target test case, and then execute step S2.

6. The method according to claim 5, characterized in that If the inherited test case is a multi-level inherited test case, there are multiple test cases to be inherited; In the step C2, it is necessary to obtain the names of all test cases to be inherited; In step C3, it is necessary to obtain all the test cases to be inherited from the preset test case library based on the names of all the test cases to be inherited, merge them into a combined test case to be inherited, modify the parameters that need to be updated in the combined test case to be inherited to the corresponding target values, generate the target test case, and then execute step S2.

7. An electronic device, characterized in that: include: at least one processor; and, a memory communicatively coupled to the at least one processor; The memory stores instructions executable by the at least one processor, wherein the instructions are configured to execute the method according to any one of claims 1 to 6.

8. A computer-readable storage medium, characterized in that: Computer executable instructions are stored, and the computer executable instructions are used to execute the method according to any one of the preceding claims 1-6.

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