Radar signal source design method based on FPGA

Abstract

The invention belongs to the technical field of radars, and particularly relates to a radar signal source design method based on an FPGA (Field Programmable Gate Array), which comprises the following steps of: acquiring an initial address and an end address of a signal slice capable of forming a radar signal from a long pulse width signal; the data address mapping module sends address mapping information of the long pulse width signal and the slice signal to the storage unit; the radar signal real-time reconstruction module schedules the corresponding slice signals from the storage unit according to the received control signals to recombine the slice signals to obtain real-time recombined signals; the pulse width and the phase of the real-time recombined signal are converted by using a pseudo-random hopping module, and the real-time recombined signal is converted by using a frequency agility complex multiplication module to change the carrier frequency; the real-time recombination signal converted by the pseudo-random hopping module and the frequency agility complex multiplication module is sent through a signal sending module; according to the radar signal source designed by the invention, high performance is maintained, system resource consumption is remarkably reduced, and the radar signal source has good universality and expansibility.

Description

Technical Field

[0001] The invention belongs to the field of radar technology, and in particular relates to a radar signal source design method based on FPGA. Background Art

[0002] Radar technology plays an extremely important role in many fields. As the complexity and diversity of radar systems continue to increase, the training requirements for radar operators are becoming more stringent. Traditional radar training equipment is often expensive, bulky, and complex to maintain, making it difficult to meet the growing training needs. In order to solve these problems, it is urgent to develop efficient, low-cost, and miniaturized radar training equipment.

[0003] Current radar training equipment faces two problems. On the one hand, the traditional data storage method is to store all radar signals that need to be sent. This method occupies too many system resources, and the real-time generation of the required radar waveform data based on the direct digital synthesizer (DDS) has problems such as poor real-time performance and untimely response. On the other hand, the radar waveform emitted by traditional radar equipment is single in form and has a relatively fixed frequency range, which is easily intercepted by reconnaissance aircraft and has poor anti-interference ability. Summary of the invention

[0004] In view of the problems existing in the prior art, the present invention proposes a radar signal source design method based on FPGA, including a radar signal source data generation module, a data address mapping module, a pseudo-random jump module, a frequency agility complex multiplication module, a radar signal real-time reconstruction module, and a storage unit, wherein:

[0005] The radar signal source data generation module generates a long pulse width signal;

[0006] According to the radar signal source data, the data address mapping module generates the address mapping of the radar signal, that is, obtaining the starting address and length of the signal slice that can constitute the radar signal from a long pulse width signal;

[0007] The data address mapping module sends the address mapping information of the long pulse width signal and the slice signal to the storage unit;

[0008] The radar signal real-time reconstruction module schedules the corresponding slice signal from the storage unit according to the received control signal to reconstruct the real-time reconstructed signal;

[0009] The pulse width and phase of the real-time reorganized signal are changed by using a pseudo-random hopping module, and the carrier frequency of the real-time reorganized signal is changed by using a frequency agility complex multiplication module;

[0010] The real-time recombined signal transformed by the pseudo-random hopping module and the frequency agility multiplication module is sent through the signal sending module.

[0011] On the basis of meeting the requirements of conventional target simulation, the present invention has anti-interference functions such as time-frequency agility, and realizes a low-cost radar signal source device that can adapt to complex environments. Specifically, based on the FPGA hardware architecture, the present invention designs an anti-interference radar waveform generation method, improves the complexity and anti-interference ability of radar signals through pseudo-random hopping and frequency agility technology; optimizes data processing and storage, and greatly saves storage resources through lookup table slicing scheduling. The radar signal source generated according to the present invention significantly reduces system resource consumption while maintaining high performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 The present invention is a schematic diagram of the architecture of a radar signal source design method based on FPGA;

[0013] Figure 2 This is a schematic diagram of slice scheduling adopted by the present invention;

[0014] Figure 3 It is a schematic diagram of radar signal reconstruction in the present invention;

[0015] Figure 4 This is the functional block diagram of the multi-phase DDS module. DETAILED DESCRIPTION

[0016] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0017] The present invention proposes a radar signal source design method based on FPGA, comprising a radar signal source data generation module, a data address mapping module, a pseudo-random jump module, a frequency agility complex multiplication module, a radar signal real-time reconstruction module, and a storage unit, wherein:

[0018] The radar signal source data generation module generates a long pulse width signal;

[0019] According to the radar signal source data, the data address mapping module generates the address mapping of the radar signal, that is, obtaining the starting address and length of the signal slice that can constitute the radar signal from a long pulse width signal;

[0020] The data address mapping module sends the address mapping information of the long pulse width signal and the slice signal to the storage unit;

[0021] The radar signal real-time reconstruction module schedules the corresponding slice signal from the storage unit according to the received control signal to reconstruct the real-time reconstructed signal;

[0022] The pulse width and phase of the real-time reorganized signal are changed by using a pseudo-random hopping module, and the carrier frequency of the real-time reorganized signal is changed by using a frequency agility complex multiplication module;

[0023] The real-time recombined signal transformed by the pseudo-random hopping module and the frequency agility multiplication module is sent through the signal sending module.

[0024] like Figure 1 In this embodiment, a radar signal source design method based on FPGA performs waveform design according to the parameters set by the user end, including the following steps:

[0025] The user end sends the parameter configuration of the radar signal to be sent, and uses this parameter configuration to complete the generation of radar data. At the same time, the data format is converted and packaged to generate UDP packets, which are transmitted to the data processing unit through the Ethernet interface.

[0026] In this embodiment, the generated radar data is expressed as:

[0027] lfm(t)=Acos(πKt 2 +2πf0t)

[0028] in, B is the frequency modulation width, T is the signal pulse width; f0 is the initial frequency of the signal; A is the signal amplitude.

[0029] The data processing unit parses the UDP message through the lwip network transmission protocol, forms a mapping relationship between the waveform data and the storage address and waveform configuration information, and calculates the starting address and ending address of each waveform sub-pulse pattern storage. Figure 2 As shown, a long pulse width signal is stored in the storage unit DDR of the FPGA, and signals of different lengths are intercepted from different positions through the storage unit DDR address to form different sub-pulses.

[0030] Before executing radar signal transmission, it is necessary to configure the waveform configuration parameters of this task, including style selection, frequency selection, pulse interval, etc., that is, how to combine and repeat various waveform styles to form the pulse waveform style required for the task. Figure 3 , specifically including the following steps:

[0031] In the radar waveform reconstruction configuration module, the waveform configuration parameters are received and parsed to obtain information such as pulse width interval;

[0032] According to the address mapping table of the waveform data, the waveform sequence register is used to form the read start address sequence of the waveform of this task, and the corresponding data information is read out from the DDR according to this address;

[0033] Then, according to the sequence and the pulse interval timing, the storage is read in waveform pattern in chronological order;

[0034] Then the pulse group number is determined. If the pulse group number is the number required by the current parameter configuration, it means that the current radar waveform data has been sent and the baseband signal data is generated.

[0035] If not, continue to repeat the above steps.

[0036] The waveform parameter pseudo-random jump uses linear feedback shift to generate pseudo-random numbers, and its feedback function is expressed as:

[0037] y=a0x 0 +a1x 1 +a2x 2 +…+a n x n

[0038] Where, y represents the feedback function; {a0, a1, a2, …, an,} represents the feedback coefficients of n+1 feedback shift registers; {x 0 ,x 1 ,x 2 ,…,xn} represents n+1 feedback shift registers.

[0039] The feedback function determines the difference in random algorithms. Taking 0 means that there is no such feedback loop. To ensure that the linear feedback shift obtains the longest shift period, the polynomial formed by the tap sequence plus 1 must be a primitive polynomial, that is, it is irreducible. The mathematical expression of the baseband waveform of pseudo-random hopping is:

[0040]

[0041] in, t m is the phase and time of the mth sub-pulse, and τ is the baseband pulse width. Without loss of generality, let: t1 = 0, t CPI =MT then:

[0042] t m+1 =[m+δ(m)]T,m=1,2,…,M-1

[0043] Where T is the PRI of the fixed repetition rate signal.

[0044] Rapid frequency hopping reduces the probability of being intercepted, and its signal model is expressed as:

[0045]

[0046] In the formula, u(t) represents the complex envelope information of the signal, δ represents the noise, and t mFor fast time and slow time, T r is the pulse repetition interval, t m =mT r , f m is the carrier frequency of the mth pulse, as shown below:

[0047] f m =f c +r(m)Δf,m=1,2,…,M

[0048] Where, M represents the number of pulses, r(m) represents a random number, that is, a frequency modulation codeword, N represents the total frequency modulation number, the range is 0≤a(m)≤N-1, and N<M; Δf represents the frequency interval of adjacent carriers, in order to improve the orthogonality between different pulse signals, so that:

[0049] Δf=k / T p .

[0050] The frequency carrier is generated by a direct digital synthesizer (DDS), but a single DDS is not enough to generate the required high carrier frequency. A multi-phase DDS frequency synthesizer is used, which parallels N DDS modules. Each DDS has a specific phase accumulator and a ROM containing sine and cosine waveforms, and generates N samples of the carrier frequency waveform in parallel. Each DDS actually works at a rate N times lower than the global sampling rate, so it is not limited by the hardware rate. Figure 4 The phase calculation block shown performs the mapping between the desired carrier frequency, phase step size, and the corresponding DDS phase offset.

[0051] X RF (n) = Re (x (n) cos (w c n))-Im(x(n)sin(w c n))

[0052] Among them, X RF (n) is the RF signal after the mixer multiplication; Re(·) represents the value of the real part of a complex number, Im(·) represents the value of the imaginary part of a complex number; x(n) represents the radar signal; w c Indicates the carrier frequency.

[0053] like Figure 4 As shown, in the digital mixer, the output sine and cosine carrier frequency value samples are complex-multiplied with the IQ data to obtain the final RF signal.

[0054] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A radar signal source design method based on FPGA, characterized in that: It includes a radar signal source data generation module, a data address mapping module, a pseudo-random jump module, a frequency agility complex multiplication module, a radar signal real-time reconstruction module, and a storage unit, wherein: The radar signal source data generation module generates radar signal source data according to the user-side waveform configuration parameters; According to the radar signal source data, the data address mapping module generates the address mapping of the radar signal, that is, obtaining the starting address and the ending address of the signal slice that can constitute the radar signal from a long pulse width signal; The data address mapping module sends the address mapping information of the long pulse width signal and the slice signal to the storage unit; The radar signal real-time reconstruction module schedules the corresponding slice signal from the storage unit according to the received control signal to reconstruct the real-time reconstructed signal; The pulse width and phase of the real-time reorganized signal are changed by using a pseudo-random hopping module, and the carrier frequency of the real-time reorganized signal is changed by using a frequency agility complex multiplication module; The real-time recombined signal transformed by the pseudo-random hopping module and the frequency agility multiplication module is sent through the signal sending module.

2. The radar signal source design method based on FPGA according to claim 1, characterized in that: The process of the radar signal source data generation module generating a long pulse width signal is expressed as: Among them, s(t) represents the long pulse width signal generated by the radar signal source data generation module; j represents the imaginary unit; f0 is the initial frequency of the signal; K is the ratio of the frequency modulation width to the signal pulse width; T is the pulse repetition interval of the fixed repetition frequency signal.

3. The radar signal source design method based on FPGA according to claim 1, characterized in that: The process of the pseudo-random hopping module changing the pulse width and phase of the real-time reorganized signal is expressed as: Wherein, s1(t) represents the signal after the pseudo-random hopping module transformation; N is the total frequency modulation number; is the phase of the mth sub-pulse; t m is the time of the mth sub-pulse; τ is the baseband pulse width; s(t) is the signal input to the pseudo-random hopping module for transformation; u(·) represents the complex envelope signal of the radar signal.

4. The radar signal source design method based on FPGA according to claim 3, characterized in that: The complex envelope signal of the radar signal is expressed as: Wherein, u(t) represents the complex envelope signal of the radar signal changing with time t; T p represents the pulse repetition interval; γ represents the initial phase of the radar signal; rect(t) represents the window function.

5. The FPGA-based radar signal source design method according to claim 3, characterized in that: Let the time t1 of the first sub-pulse be 0, t CPI =MT, then the time of the mth sub-pulse is expressed as: t m+1 =[m+δ(m)]T,m=1,2,...,M-1 Where M is the number of pulses; δ(m) is the noise; and T is the pulse repetition interval of the fixed repetition rate signal.

6. The method for designing a radar signal source based on FPGA according to claim 3, characterized in that: The process of using the frequency agility complex multiplication module to transform the real-time recombined signal to change the carrier frequency includes: in, represents the radar signal after frequency agility; u(t) represents the complex envelope information of the signal; represents noise, For fast time, t m The slow time of the mth pulse is denoted as t m =mT r , T r is the pulse repetition interval; f m is the carrier frequency after the agile frequency change of the mth pulse.

7. The radar signal source design method based on FPGA according to claim 6, characterized in that: The carrier frequency f of the mth pulse m It is expressed as: f m =f c +r(m)Δf,m=1,2,...,M Among them, f c is the carrier frequency of the current pulse; r(m) represents the frequency modulation codeword; Δf is the frequency interval of adjacent carriers, expressed as Δf = k / T p , k is the number of carriers in one cycle, T p is the pulse repetition interval.

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