Storage and calculation integrated artificial intelligence chip architecture construction method based on three-dimensional stacking

Abstract

The invention relates to the technical field of artificial intelligence chips, in particular to a storage and calculation integrated artificial intelligence chip architecture construction method based on three-dimensional stacking, and the method comprises the steps: carrying out the three-dimensional integration of a plurality of target processing units meeting a first preset condition and a target memory unit, and obtaining a three-dimensional integrated unit, and based on the three-dimensional integration unit and the target thermal management mechanism, determining a three-dimensional stacked chip architecture meeting a second preset condition, thereby quantifying a target parameter of a preset deep learning model, and optimizing a target data flow path of the three-dimensional stacked chip architecture by using quantized parameter distribution and a target instruction set, thereby improving the reliability of the three-dimensional stacked chip architecture. And the storage and calculation integrated artificial intelligence chip architecture based on three-dimensional stacking is constructed by using the optimized data flow path. Therefore, the power consumption of the AI chip during high-performance calculation is reduced, the integration level of the AI chip architecture is improved, the flexibility of the AI chip architecture is enhanced, and the hardware adaptability of a neural network model and an algorithm is improved.

Description

Technical Field

[0001] The present application relates to the field of artificial intelligence chip technology, and in particular to a method for constructing a storage-computing integrated artificial intelligence chip architecture based on three-dimensional stacking. Background Art

[0002] With the rapid development of AI (Artificial Intelligence) technology, deep learning and machine learning algorithms have been widely used in image recognition, natural language processing, autonomous driving, medical diagnosis and other fields. The efficient execution of AI algorithms depends on the support of hardware architecture. Therefore, designing high-performance AI chips has become a research hotspot.

[0003] In the related technology, existing general-purpose processors, such as CPU (Central Processing Unit), are highly versatile and flexible, but have low efficiency when processing deep learning tasks. To solve this problem, researchers have developed hardware accelerators specifically for AI computing, including GPU (Graphics Processing Unit), FPGA (Field-Programmable Gate Array) and ASIC (Application-Specific Integrated Circuit).

[0004] Among them, GPU was originally used for graphics rendering. Due to its highly parallel computing power, it has gradually been applied to deep learning tasks. GPU can handle a large number of parallel computing tasks at the same time, significantly improving the training speed of deep learning algorithms; FPGA is highly flexible, allowing users to reconfigure the hardware structure as needed, making FPGA perform well when processing specific AI tasks and more energy-efficient than GPU; ASIC is designed for specific applications, has the highest performance and energy efficiency, and is suitable for large-scale AI computing tasks. Famous AI accelerators such as Google TPU (Tensor Processing Unit) are based on ASIC.

[0005] However, in the related technologies, AI hardware accelerators consume high power when performing high-performance computing, and different neural network models and algorithms require different hardware support, which reduces the performance and efficiency of AI computing, fails to meet the needs of different application scenarios, and reduces the flexibility and applicability of AI chip architecture, which needs to be urgently resolved. Summary of the invention

[0006] The present application provides a method for constructing an integrated storage and computing artificial intelligence chip architecture based on three-dimensional stacking, so as to reduce the power consumption of the AI ​​chip during high-performance computing, improve the integration of the AI ​​chip architecture, enhance the flexibility of the AI ​​chip architecture, and improve the hardware adaptability of neural network models and algorithms.

[0007] The first aspect of the present application provides a method for constructing a storage-computing integrated artificial intelligence chip architecture based on three-dimensional stacking, comprising the following steps: identifying multiple target processing units that meet a first preset condition; performing three-dimensional integration of the multiple target processing units and a target memory unit to obtain a three-dimensional integrated unit, and based on the three-dimensional integrated unit and a target thermal management mechanism, determining a three-dimensional stacked chip architecture that meets a second preset condition; based on the three-dimensional stacked chip architecture, quantizing target parameters of a preset deep learning model to obtain a quantized parameter distribution, and using the quantized parameter distribution and a target instruction set to optimize a target data flow path of the three-dimensional stacked chip architecture, so as to use the optimized data flow path to construct a storage-computing integrated artificial intelligence chip architecture based on three-dimensional stacking.

[0008] Optionally, in one embodiment of the present application, the identifying of multiple target processing units that meet preset conditions includes: identifying at least one central processing unit based on a target general task; identifying at least one graphics processing unit based on a graphics computing task; and identifying multiple artificial neurons of a neuromorphic array based on a neural network computing task.

[0009] Optionally, in one embodiment of the present application, the three-dimensional integration of the multiple target processing units and the target memory units to obtain a three-dimensional integrated unit includes: determining a three-dimensional interlayer interconnection structure based on a preset three-dimensional stacking method; optimizing the data transmission paths corresponding to the processing units and memory units between different layers of the three-dimensional interlayer interconnection structure to obtain an optimized target data transmission path; and based on the target data transmission path, three-dimensionally integrating the multiple target processing units and the target memory unit to obtain the three-dimensional integrated unit.

[0010] Optionally, in one embodiment of the present application, the three-dimensional stacked chip architecture that meets preset conditions is determined based on the three-dimensional integrated unit and the target thermal management mechanism, including: using the three-dimensional integrated unit and the target thermal management mechanism to design target heat dissipation channels in the layers of the three-dimensional interlayer interconnection structure, and designing vertical heat dissipation channels between the layers of the three-dimensional interlayer interconnection structure to determine the three-dimensional stacked chip that meets the preset conditions.

[0011] Optionally, in one embodiment of the present application, based on the three-dimensional stacked chip architecture, the target parameters of the pre-set deep learning model are quantized to obtain the quantized parameter distribution, and the target data flow path of the three-dimensional stacked chip architecture is optimized using the quantized parameter distribution and the target instruction set, including: introducing a target scale factor into the three-dimensional stacked chip architecture to quantize the target parameters of the pre-set deep learning model to obtain the parameter quantization error and parameter information entropy of the deep learning model; based on the parameter quantization error, the parameter information entropy and the target instruction set, optimizing the target data flow path of the three-dimensional stacked chip architecture.

[0012] The second aspect of the present application provides a device for constructing a storage-computing integrated artificial intelligence chip architecture based on three-dimensional stacking, including: an identification module for identifying multiple target processing units that meet a first preset condition; a determination module for performing three-dimensional integration of the multiple target processing units and a target memory unit to obtain a three-dimensional integrated unit, and based on the three-dimensional integrated unit and a target thermal management mechanism, determining a three-dimensional stacked chip architecture that meets a second preset condition; a construction module for quantizing a preset target parameter of a deep learning model based on the three-dimensional stacked chip architecture to obtain a quantized parameter distribution, and optimizing a target data flow path of the three-dimensional stacked chip architecture using the quantized parameter distribution and a target instruction set, so as to construct a storage-computing integrated artificial intelligence chip architecture based on three-dimensional stacking using the optimized data flow path.

[0013] Optionally, in one embodiment of the present application, the identification module includes: a first identification unit, used to identify at least one central processing unit based on a target general task; a second identification unit, used to identify at least one graphics processing unit based on a graphics computing task; and a third identification unit, used to identify artificial neurons of multiple neuromorphic arrays based on a neural network computing task.

[0014] Optionally, in one embodiment of the present application, the determination module includes: a first determination unit, used to determine the three-dimensional interlayer interconnection structure based on a preset three-dimensional stacking method; a second determination unit, used to respectively optimize the data transmission paths corresponding to the processing units and memory units between different layers of the three-dimensional interlayer interconnection structure to obtain an optimized target data transmission path; and a third determination unit, used to perform three-dimensional integration of the multiple target processing units and the target memory unit based on the target data transmission path to obtain the three-dimensional integrated unit.

[0015] Optionally, in one embodiment of the present application, the determination module includes: a fourth determination unit, used to design a target heat dissipation channel in the layer of the three-dimensional interlayer interconnection structure using the three-dimensional integrated unit and the target thermal management mechanism, and to design a vertical heat dissipation channel between the layers of the three-dimensional interlayer interconnection structure, so as to determine the three-dimensional stacked chip that meets the preset conditions.

[0016] Optionally, in one embodiment of the present application, the construction module includes: an acquisition unit, used to introduce a target scale factor into the three-dimensional stacked chip architecture to quantize the target parameters of the preset deep learning model, and obtain the parameter quantization error and parameter information entropy of the deep learning model; an optimization unit, used to optimize the target data flow path of the three-dimensional stacked chip architecture based on the parameter quantization error, the parameter information entropy and the target instruction set.

[0017] The third aspect of the present application provides an electronic device, including: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the method for constructing a storage-computing integrated artificial intelligence chip architecture based on three-dimensional stacking as described in the above embodiment.

[0018] The fourth aspect of the present application provides a computer program product, including a computer program, which, when executed, is used to implement the above-mentioned method for constructing a storage and computing integrated artificial intelligence chip architecture based on three-dimensional stacking.

[0019] The embodiment of the present application can perform three-dimensional integration of multiple target processing units and target memory units that meet the first condition to obtain a three-dimensional integrated unit, and based on the target thermal management mechanism, determine the three-dimensional stacked chip architecture that meets the second condition, thereby quantifying the target parameters of the pre-set deep learning model, and using the quantized parameter distribution and target instruction set to optimize the target data flow path of the three-dimensional stacked chip architecture, and then construct a storage-computing integrated artificial intelligence chip architecture based on three-dimensional stacking. As a result, the power consumption of AI chips during high-performance computing is reduced, the integration of AI chip architecture is improved, the flexibility of AI chip architecture is enhanced, and the hardware adaptability of neural network models and algorithms is improved.

[0020] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0022] Figure 1A flowchart of a method for constructing a storage-computing integrated artificial intelligence chip architecture based on three-dimensional stacking according to an embodiment of the present application;

[0023] Figure 2 A schematic diagram of a storage-computing integrated artificial intelligence chip architecture based on three-dimensional stacking according to a specific embodiment of the present application;

[0024] Figure 3 A schematic diagram of an artificial neuron of a neuromorphic array structure according to a specific embodiment of the present application;

[0025] Figure 4 A schematic diagram of the principle of artificial neuron calculation convolution according to a specific embodiment of the present application;

[0026] Figure 5 This is a working diagram of a data buffer module according to a specific embodiment of the present application;

[0027] Figure 6 A schematic diagram of the structure of a device for constructing a storage-computing integrated artificial intelligence chip architecture based on three-dimensional stacking according to an embodiment of the present application;

[0028] Figure 7 It is a schematic diagram of the structure of an electronic device provided according to an embodiment of the present application. DETAILED DESCRIPTION

[0029] Embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be construed as limiting the present application.

[0030] The following describes the method for constructing an integrated artificial intelligence chip architecture based on three-dimensional stacking of the embodiment of the present application with reference to the accompanying drawings. In view of the related technologies mentioned in the background technology center, the AI ​​hardware accelerator has high power consumption when performing high-performance computing, which reduces the performance and efficiency of AI computing, cannot meet the needs of different application scenarios, and reduces the flexibility and applicability of the AI ​​chip architecture. The present application provides a method for constructing an integrated artificial intelligence chip architecture based on three-dimensional stacking. In this method, multiple target processing units and target memory units that meet the first condition can be three-dimensionally integrated to obtain a three-dimensional integrated unit, and based on the target thermal management mechanism, a three-dimensional stacked chip architecture that meets the second condition is determined, thereby quantifying the target parameters of the pre-set deep learning model, and using the quantized parameter distribution and target instruction set to optimize the target data flow path of the three-dimensional stacked chip architecture, and then constructing an integrated artificial intelligence chip architecture based on three-dimensional stacking. As a result, the power consumption of the AI ​​chip during high-performance computing is reduced, the integration of the AI ​​chip architecture is improved, the flexibility of the AI ​​chip architecture is enhanced, and the hardware adaptability of the neural network model and algorithm is improved.

[0031] Specifically, Figure 1 A flowchart of a method for constructing a storage and computing integrated artificial intelligence chip architecture based on three-dimensional stacking provided in an embodiment of the present application.

[0032] like Figure 1 As shown, the method for constructing a storage-computing integrated artificial intelligence chip architecture based on three-dimensional stacking includes the following steps:

[0033] In step S101, a plurality of target processing units that meet a first preset condition are identified.

[0034] It can be understood that the embodiments of the present application can identify multiple target processing units that meet the first condition in the following steps, for example, multi-core processing units, wherein the multi-core processing units communicate with each other through a high-speed interconnection network to improve the efficiency of data parallel processing.

[0035] In an embodiment of the present application, the multi-core processing unit can adopt low-power and high-performance design technology to improve overall energy efficiency. First, the processing unit adopts advanced process technology, such as 7nm or 5nm process, to reduce power consumption and heat generation. Each processing unit can independently perform computing tasks. The processing unit includes multiple computing cores, and each core is responsible for processing a part of the data, thereby realizing parallel processing.

[0036] For example, the multi-core processing unit in this embodiment can be used in a variety of high-performance computing scenarios. In the big data processing scenario, multiple processing units can process large-scale data in parallel to improve the speed of data analysis; in the artificial intelligence computing scenario, the processing unit can perform the training and reasoning of deep learning algorithms in parallel to accelerate the model training and reasoning process. In the real-time image processing scenario, the processing unit can process image data in parallel to achieve real-time processing of high-resolution images.

[0037] Among them, in one embodiment of the present application, identifying multiple target processing units that meet preset conditions includes: based on the target general task, identifying at least one central processing unit; based on the graphics computing task, identifying at least one graphics processing unit; based on the neural network computing task, identifying multiple artificial neurons of the neuromorphic array.

[0038] During the actual execution process, the multi-core processing unit includes at least one central processing unit CPU for performing general tasks; at least one graphics processing unit GPU for performing graphics computing tasks; and multiple artificial neurons of neuromorphic arrays for performing neural network computing tasks, wherein the artificial neurons of the neuromorphic array should support at least one of the neural network structures such as fully connected networks, convolutional neural networks, recurrent neural networks, and residual networks, and multiple processing units are connected through a bus architecture to achieve efficient data transmission and control, wherein the bus architecture is implemented using a high-bandwidth, low-latency, and highly flexible Internet network.

[0039] In an embodiment of the present application, communication between processing units is carried out through a high-speed interconnection network. The high-speed interconnection network can adopt advanced communication protocols, such as NoC (Network on Chip) or High-Speed ​​Bus, to ensure efficient and low latency data transmission. The network topology can adopt a star, ring, mesh or other structure suitable for high-performance computing to minimize communication delays and data transmission bottlenecks.

[0040] For example, the bus structure can be divided into three levels: Main BUS, Sub BUS and Local BUS. Main BUS is a module located at the top level of the bus architecture, connecting to subsystems or high-speed IO upwards, meeting the interconnectivity requirements between subsystems, and adjusting data transmission for different scenarios and needs; Sub BUS is a module in the middle layer of the bus architecture, used to connect to Main BUS upwards and Local BUS downwards, scheduling and optimizing access within the system, and at the same time, considering the requirements of each subsystem for bandwidth, latency, stability and flexibility, and adaptively controlling and adjusting data for different scenarios; Local BUS is the lowest level module in the bus architecture, used to connect to Sub BUS upwards, perform routing management and cache management for data between components within the system, and achieve the interconnectivity requirements between components within the subsystem.

[0041] In one embodiment of the present application, in order to further improve the data transmission efficiency, the high-speed interconnection network can be optimized in design. First, a multi-level cache mechanism can be used to set up a shared cache between processing units to reduce repeated data transmission; second, a dynamic routing algorithm can be used to dynamically adjust the data transmission path according to the data flow and network load to avoid network congestion; finally, data compression transmission technology can be used to compress large data blocks before transmission to reduce the amount of data transmission.

[0042] During the actual execution process, each processing unit in the embodiment of the present application is integrated with a memory management and data cache module for storing frequently accessed data to reduce frequent data transmission and access delays. Specifically, the embodiment of the present application can use a memory management unit and a buffer structure to manage the data of the CPU and GPU, thereby improving the utilization efficiency and access speed of memory resources; using on-chip memory for artificial neurons to achieve high reuse of input data, integrating simple computing capabilities in the memory, and reducing the amount of data movement of artificial neurons; greatly simplifying the reading and writing of data based on the architecture of artificial neurons, and avoiding complex calculations of access addresses by artificial neurons through the form of inflow and outflow data streams, wherein data can be transferred between processing units through predefined data flow paths to avoid complex address calculations during each access.

[0043] Among them, MMU (Memory Management Unit) supports multiple memory access modes, including DMA (Direct Memory Access), virtual memory and shared memory; the data cache module includes L1 Cache, L2 Cache and L3 Cache, and the data cache module is configured in a hierarchical structure to achieve fast access to data at different levels. MMU is a key component in the processing unit. MMU can divide the virtual address space into several fixed-size pages through the paging mechanism and map these pages to the corresponding locations in the physical memory. In this way, when accessing data, the processing unit can quickly locate the physical memory through the virtual address, thereby improving the memory access speed. In addition, MMU also supports a multi-level page table structure to reduce memory access latency through level-by-level address conversion.

[0044] Furthermore, on-chip SRAM (Static Random-Access Memory) is used as the storage medium for artificial neurons, thereby greatly reducing static power consumption. The on-chip memory units mainly include data memory units (6k byte), parameter memory units (6K byte), neural network memory (1k byte), and configuration memory (1kbyte), among which parameter memory and neural network memory belong to the memory within artificial neurons.

[0045] In particular, the data memory is used to store the input data of the neural network. Before the neural network starts to operate, the data input from the outside will be stored here, and the inter-layer storage data, that is, the data obtained after the calculation of each network layer, will also be sent to this memory by the input and output register group for storage to be used as the input of the next layer. After the final operation of the neural network is completed, its final output data will also be stored in it, and finally output to the outside of the chip. In the embodiment of the present application, a data memory is used to store input, inter-layer and output data, and the logic control unit flexibly reads and writes the data.

[0046] In addition, since the network weights and bias of the neural network remain basically unchanged after its network structure has been finalized and trained, the embodiments of the present application can store the pre-trained weights and parameters in the parameter memory inside the artificial neuron during the network initialization phase. The weights will only be read by the neurons during network operations, and the neurons only read their local parameters, thereby avoiding the possibility of data access between neurons and reducing the additional delay and power consumption caused by frequent data movement.

[0047] In addition, the configuration memory stores neural network-specific instructions, which determine the behavior of the chip. Before the actual neural network calculation begins, the chip reads all the instructions of the framework from the outside into the configuration memory, and then the chip parses the instructions one by one and completes the corresponding actions according to the instructions without the need for CPU or external scheduling. Neural network instructions support network structures such as convolutional networks, regional networks, recurrent networks, and reinforcement learning networks, and can configure parameters such as the number of layer nodes, the number of layers, and the operations implemented in each layer.

[0048] For example, in deep neural network calculations, data flows in from the input layer, is calculated through each hidden layer, and finally flows out to the output layer. Through data flow management, the data transmission path between each layer can be predefined to simplify data reading and writing operations. In addition, in the calculation of the fully connected layer, each neuron needs to access a large amount of weights and input data. Through data flow management, the storage location and access path of this data can be predefined to avoid address conversion during each calculation, significantly improving calculation efficiency.

[0049] In step S102, a plurality of target processing units and target memory units are three-dimensionally integrated to obtain a three-dimensional integrated unit, and based on the three-dimensional integrated unit and a target thermal management mechanism, a three-dimensional stacked chip architecture that meets a second preset condition is determined.

[0050] In the embodiment of the present application, the second preset condition is the condition of performing three-dimensional integration and introducing a thermal management mechanism.

[0051] It can be understood that the embodiments of the present application can perform three-dimensional integration of multiple target processing units and target memory units. For example, the embodiments of the present application can use three-dimensional stacking technology to perform three-dimensional integration of processing units and memory units to obtain three-dimensional integrated units, and introduce target thermal management mechanisms to obtain a three-dimensional stacked chip architecture, thereby effectively improving the processing efficiency and temperature stability of the chip.

[0052] Optionally, in one embodiment of the present application, multiple target processing units and target memory units are three-dimensionally integrated to obtain a three-dimensional integrated unit, including: determining a three-dimensional interlayer interconnection structure based on a preset three-dimensional stacking method; optimizing the data transmission paths corresponding to the processing units and memory units between different layers of the three-dimensional interlayer interconnection structure to obtain an optimized target data transmission path; based on the target data transmission path, three-dimensionally integrating multiple target processing units and target memory units to obtain a three-dimensional integrated unit.

[0053] In the embodiment of the present application, an optimized data path design method can be used to optimize the data transmission path between the processing unit and the memory unit through the shortest path algorithm, thereby reducing the delay of data transmission between layers. Specifically, the embodiment of the present application can achieve data path optimization through the following: (1) Identify the critical path. First, analyze the distribution of the processing unit and the memory unit in the chip to identify the critical path with a high data transmission frequency; (2) Shortest path calculation: Use the shortest path algorithm to optimize these critical paths to ensure that the data transmission path between layers is as short as possible, thereby increasing the data transmission speed and reducing the delay; (3) Direct interconnection channel design: Design a direct interconnection channel between layers so that key data can be directly transmitted between different stacking layers, avoiding unnecessary detours, thereby further reducing the transmission distance and power consumption.

[0054] As a possible implementation method, the embodiment of the present application can optimize the data transmission paths corresponding to the processing units and memory units between different layers of the three-dimensional interlayer interconnection structure according to the data transmission path optimization method in the above steps, obtain the optimized data transmission path, and based on the data transmission path, perform three-dimensional integration of multiple target processing units and target memory units to obtain a three-dimensional integrated unit, thereby effectively reducing the delay in data transmission between layers.

[0055] Optionally, in one embodiment of the present application, based on the three-dimensional integrated unit and the target thermal management mechanism, a three-dimensional stacked chip architecture that meets preset conditions is determined, including: using the three-dimensional integrated unit and the target thermal management mechanism to design a target heat dissipation channel in the layers of the three-dimensional interlayer interconnection structure, and designing a vertical heat dissipation channel between the layers of the three-dimensional interlayer interconnection structure to determine the three-dimensional stacked chip that meets the preset conditions.

[0056] In the embodiment of the present application, the embodiment of the present application can solve the thermal management problem in the three-dimensional stacked chip by designing a multi-layer heat dissipation channel. Specifically, (1) In-layer heat dissipation channel design: design a dedicated heat dissipation channel in each stacked layer. The dedicated heat dissipation channel can use a metal thermal conductive material or a heat pipe structure to efficiently transfer heat from the inside of the chip to the surface; (2) Vertical heat dissipation channel design: set up vertical heat dissipation channels between the stacked layers, and transfer the heat generated by each layer to the top or bottom of the chip through these channels, so that the heat can be quickly dissipated; (3) Dynamic thermal management: deploy temperature sensors in different areas of the chip, and dynamically adjust the working state of the heat dissipation channel by real-time monitoring the temperature of each stacked layer. For example, when the temperature of a stacked layer exceeds a preset threshold, the working intensity of the heat dissipation channel of the layer can be increased, thereby determining the three-dimensional stacked chip and ensuring the temperature stability of the three-dimensional stacked chip under high load.

[0057] In an embodiment of the present application, a thermal-sensitive functional area division technology can be used to further improve the thermal management efficiency of the chip. First, the functional modules inside the chip are classified according to the thermal-sensitive characteristics of the chip. Generally speaking, high-energy consumption modules such as processing units generate more heat, while low-energy consumption modules such as memory units generate less heat.

[0058] Furthermore, high-energy consumption modules are concentrated in areas with higher heat dissipation efficiency, such as near heat dissipation channels or vertical heat dissipation structures. Temperature control in these areas is more critical. By placing high-heat modules in these areas, the overall temperature of the chip can be better managed; low-heat memory units are arranged in areas with relatively low heat dissipation requirements, while considering their relative position to the processing unit to ensure the shortest data transmission path. Through this layout, the operating temperature of the memory unit can be guaranteed to be stable and the data transmission delay can be reduced.

[0059] In step S103, based on the three-dimensional stacked chip architecture, the target parameters of the pre-set deep learning model are quantized to obtain the quantized parameter distribution, and the target data flow path of the three-dimensional stacked chip architecture is optimized using the quantized parameter distribution and the target instruction set, so as to construct a storage and computing integrated artificial intelligence chip architecture based on three-dimensional stacking using the optimized data flow path.

[0060] It can be understood that the embodiments of the present application can quantify the target parameters of the pre-set deep learning model based on the three-dimensional stacked chip architecture in the following steps, obtain the quantized parameter distribution, and use the quantized parameter distribution and the target instruction set to accelerate the neural network calculation, and adaptively optimize the data flow path of the three-dimensional stacked chip architecture, so as to use the optimized data flow path to build an integrated storage and computing artificial intelligence chip architecture based on three-dimensional stacking, so that the resources on the chip can be fully utilized, making the chip architecture more adapted to the neural network calculation, reducing data access latency, reducing computing power consumption, and improving the computing efficiency of the artificial intelligence chip.

[0061] Optionally, in one embodiment of the present application, based on the three-dimensional stacked chip architecture, target parameters of a pre-set deep learning model are quantized to obtain a quantized parameter distribution, and the target data flow path of the three-dimensional stacked chip architecture is optimized using the quantized parameter distribution and the target instruction set, including: introducing a target scale factor into the three-dimensional stacked chip architecture to quantize the target parameters of the pre-set deep learning model to obtain a parameter quantization error and parameter information entropy of the deep learning model; and optimizing the target data flow path of the three-dimensional stacked chip architecture based on the parameter quantization error, parameter information entropy and target instruction set.

[0062] During the actual implementation process, the embodiments of the present application can introduce a scale factor into a three-dimensional stacked chip architecture, so that the chip can automatically adjust the parameter distribution of the model during the artificial intelligence model training process, balance the model parameter quantization error and parameter information entropy, and avoid quantizing a large amount of information loss; provide a dedicated instruction set for artificial neurons, thereby realizing the reuse of a limited number of artificial neurons within and between network layers, optimizing the data flow path, and making full use of on-chip resources to adapt to application scenarios with low computing resources on the terminal.

[0063] Among them, during the deep learning model training process, the parameters of the deep learning model are first statistically analyzed, and the scale factor of each parameter is calculated. The scale factor is used to measure the importance and information entropy of the parameter. According to the size of the scale factor, the parameters are quantified to different degrees.

[0064] For example, assuming that the model parameter is θ and the scale factor is α, the calculation formula of the scale factor is:

[0065]

[0066] Among them, N represents the overview of parameters, θ i represents the value of the i-th parameter, and α represents the scale factor.

[0067] Furthermore, the embodiments of the present application can automatically adjust the parameters of the deep network model according to the calculated scale factor, and dynamically adjust the quantization level of the parameters during the training process, so that important parameters maintain a high accuracy during the quantization process and reduce information loss. At the same time, non-important parameters are quantized more coarsely to save computing resources.

[0068] After the deep network model training is completed, the deep network model parameters can be quantized, that is, different quantization levels are selected according to the size of the scale factor to quantize the parameters. Specifically, the following quantization strategies can be adopted: (1) For parameters with larger scale factors, higher quantization accuracy is adopted, such as 8-bit or 16-bit floating point representation; (2) For parameters with smaller scale factors, lower quantization accuracy is adopted, such as 4-bit or 8-bit fixed point representation. Through the above method, the deep network model parameters can be automatically adjusted and balanced, which reduces the loss of information during the quantization process and improves the performance of the deep network model.

[0069] Among them, the dedicated instruction set provided for artificial neurons may include data loading instructions for loading input data into the input port of the neuron; calculation instructions for performing calculation operations of the neuron, including but not limited to weighted sum, activation function, etc.; data storage instructions for storing calculation results into designated storage units; and reuse instructions for realizing the reuse of neurons within and between network layers, and dynamically adjusting the calculation tasks of neurons.

[0070] During the actual execution process, the processing unit can perform data loading, calculation and storage operations in sequence according to the instructions of the dedicated instruction set; by reusing instructions, the data flow of neurons can be quickly switched between different computing tasks, making full use of on-chip resources. For example, in the calculation of CNN (Convolutional Neural Network), the same group of neurons can be reused between different convolutional layers by reusing instructions, reducing the demand for the number of neurons and improving computing efficiency.

[0071] Furthermore, the dedicated instruction set can be optimized and designed to improve computing efficiency. For example, by adding vectorized instructions, parallel computing of multiple neurons can be achieved; by adding pipeline instructions, pipeline processing of data flow in artificial intelligence computing tasks can be achieved, thereby improving computing speed.

[0072] For example, combined with Figure 3 and Figure 4 As shown, the embodiment of the present application takes an artificial neuron suitable for a convolutional neural network as an example, and uses asymmetric quantization to quantize the neural network parameters. The specific method is as follows:

[0073] (1) The chip circuit in the embodiment of the present application needs to include a multi-core processing unit to improve the efficiency of data parallel processing, and the processing units communicate with each other through a high-speed interconnection network. Among them, the multi-core processing unit includes at least one central processing unit, at least one graphics processing unit and multiple artificial neurons of a neuromorphic array, which are used to perform general tasks, graphics computing tasks and neural network computing tasks respectively.

[0074] like Figure 3 As shown, the artificial neuron in the embodiment of the present application is suitable for the calculation of CNN. The artificial neuron in the embodiment of the present application is composed of a basic computing unit (multiplier-adder module, activation module, address generation module), a control unit (neuron control module, configuration chain register) and a storage unit (parameter memory, register unit).

[0075] In the actual implementation process, Figure 3As shown, during initialization, the serial input control parameters of the In_Cfg port can be used to configure the activation mode of the neuron, the activation threshold, the type of computing layer, and the parameters required for the convolution calculation and address generation module. The neural network weight parameters are stored in the WeightSRAM from the input port In_Weight in the same way. Although the Weight SRAM is only 6k bytes, when the weight parameter assigned to a single artificial neuron is greater than 6k bytes during the calculation of the convolution layer, the artificial neuron automatically optimizes the same layer of computing layer (fully connected layer, convolution layer) and divides it into blocks. By calculating a part of the computing layer each time, convolution layers and fully connected layers of any size can be calculated.

[0076] Among them, Figure 3 As shown, the configuration data is stored in the Config Data register group. The control module configures the neuron calculation process according to the configuration parameters. Specifically, it controls four functional modules, M1, M2, M3 and M4, and has a module G1. When the input data enters the artificial neuron from the port Data_In, M1 is used to decide whether to skip (Bypass) the multiplication and addition calculations, because for a single artificial neuron, a lot of the incoming data is unnecessary. When unnecessary data enters the neuron, the neuron will not process it and skip (Bypass). This process is also called "data selection". Generally speaking, after the data is selected by the M1 module and before entering the module M2, the module G1 will be used to compare whether the current input data is zero. If it is equal to 0, no subsequent calculation will be performed to save a lot of power consumption.

[0077] Then, if Figure 3 As shown, the selected data will enter the subsequent multiplier and adder, and the multiplier and adder is located in module M2. Module M2 is mainly used to control the multiplication and addition process. It is a key module for artificial neurons to realize diversified networks. It also has an accumulation register (ACC REG) to store the accumulated data. After completing the multiplication and addition operation, the next step is to enter the M3 module. The function of the M3 module is to realize a variety of rich activation functions, such as the common sigmoid activation function and Relu function. And the bit width of the entire calculation process can also be controlled by the M4 module. For example, in application scenarios where the accuracy requirements are not very high, a 4-bit bit width can be used for calculation, while in applications where the calculation accuracy requirements are very high, a 16-bit bit width can be used for calculation. When the calculation is completed, the final result will be output from Data_Out. Because the configuration data and the neural network weight data enter from the same port, M5 is used to control the flow direction of the input data stream, that is, to the Weight SRAM or config chain.

[0078] Furthermore, if Figure 4 As shown in the figure, the process of artificial neurons for calculating convolution in CNN, artificial neurons only need to access some parameters needed for specific calculations in the parameter memory, without accessing all convolution kernel parameters, thus greatly reducing the usage of parameter memory. The address generation module (Addr Gen) accurately controls the convolution kernel parameters and input feature parameters to correspond to each other, and when the input feature data is zero, this calculation will be skipped to achieve the purpose of low power consumption, and the controller (CTRL) controls the bypass feature data that needs to be padded with zero (Pad).

[0079] (2) Each processing unit is integrated with a memory management and data cache module to store frequently accessed data to reduce frequent data transmission and access delays.

[0080] In the embodiments of the present application, Figure 5 As shown, the embodiment of the present application can adopt Figure 5 The regional data buffer module and memory controller shown are used to improve the data reuse rate of convolution calculation and reduce data buffering time. Specifically, the memory controller can integrate the data requested by all computing units into a streamlined data stream based on the parameters of the convolution calculation, such as the input feature size, the output feature size, the convolution kernel size, etc., and simultaneously pass each data in the data stream to multiple computing units requesting the data, thereby improving the data reuse rate. Moreover, the method of integrating multiple requests into a data stream by the memory controller eliminates the operation of discontinuous reading of memory data in a single request, and utilizes the characteristic that the continuous reading and writing rate of the memory is higher than the discontinuous reading and writing, which reduces the response time of the memory request and improves the efficiency of memory control.

[0081] Among them, the regional data fast buffering method mainly improves the speed of data buffering in two aspects: 1. Improving data reuse rate; 2. Maximizing the continuous reading and writing of memory. Its specific implementation method and workflow are as follows:

[0082] a. Decode the convolution calculation instructions and extract the convolution calculation parameters: width, height, and channels of the input features; width, height, and channels of the output features; width and height of the convolution kernel; step size; and pad inserted to widen the input features.

[0083] b. Using the width and height of the input and output features as coordinates, calculate the starting coordinates of each output feature and the coordinates of the corresponding input feature that needs to be transmitted based on the number of available computing units; the starting point of the input feature coordinates is calculated from the starting point of the output feature coordinates, the widened Pad size, the convolution kernel size, and the step size.

[0084] c. Based on the starting coordinates of the input features calculated in b, the data is continuously read and transmitted to the computing unit array in the order in which it is stored in the memory. If a coordinate with a Pad is encountered during the transmission process, the memory access will be paused and the Pad value will be transmitted. The Pad value will be determined based on the quantized zero point.

[0085] d. The data read sequentially in c is regarded as a data stream and numbered according to the time of entry. The controller will calculate and save the numbering interval of the data required by each computing unit in advance. Each computing unit determines whether to load the data by checking whether the time number of the data matches its own numbering interval.

[0086] e. Repeat the above steps until the output feature coordinates reach the maximum.

[0087] (3) Use three-dimensional stacking technology to integrate the processing unit and memory unit in three dimensions, and introduce a thermal management mechanism to improve the processing efficiency and temperature stability of the chip.

[0088] (4) Accelerate neural network calculations by quantizing model parameters and using dedicated instruction sets, adaptively optimize data flow paths, and make full use of on-chip resources. The quantization method uses the UniformAffine Quantizer introduced in the Google Quantization White Paper, also known as asymmetric quantization. The mapping process of int8 asymmetric quantization is as follows.

[0089] First, before quantization, the quantization factor must be calculated, including the two quantization parameters of step size and zero point. The quantization factor is used to ensure that all variables in the floating point range can be mapped to the value range of the quantized bit number without omission. The calculation formulas for step size and zero point are as follows:

[0090] Δ=(rmax-rmin) / 255

[0091] Z=-rmin / Δ

[0092] Among them, rmax and rmin represent the maximum and minimum values ​​of the original data respectively, Z represents the zero point of the data quantized to int8, and Δ represents the step size.

[0093] The data zero point is an integer number, which is used to ensure that there is no quantization error in the original data 0. For example, when the convolution layer has padding, the original data 0 value is also involved in the calculation. The floating-point 0 is quantized to an eight-bit fixed point and then the quantization zero point Z is used for calculation. This quantization is more accurate. This is equivalent to making the entire interval after mapping offset, the floating-point minimum value corresponds to 0, and after calculating the quantization factor, the quantization process of randomly selecting a data from the floating-point interval is:

[0094] X int =round(X / Δ)+Z

[0095] X Q =clamp(0,Nlevel-1,X int )+Z

[0096] Among them, X int Indicates the process of quantizing the data X to be quantized to 8-bit fixed point, round indicates the rounding function, clamp indicates the interval approximation function, Nlevel is 256 when it is 8-bit fixed point, X Q It means the quantization result of accurately representing the quantized integer through the approximation function. Among them, the inverse quantization formula is:

[0097] X float =(X Q -Z)*Δ

[0098] The quantized result obtained by multiplying two quantized data is obtained by the following formula:

[0099]

[0100] Among them, Δ1 and Δ2 are obtained by quantizing data X1 and data X2, and the result Δ3 needs to be quantized by counting all the product results of X1 and X2. When calculating quantization, it is necessary to obtain the coefficients Δ1, Δ2 and Δ3, and the zero points Z1, Z2, and Z3. Then the calculation can be simplified to:

[0101]

[0102]

[0103] Among them, Δ M Represents the quantized coefficients of the product of X1 and X2.

[0104] Furthermore, the dedicated instruction set can be optimized and designed to improve computing efficiency. For example, by adding vectorized instructions, parallel computing of multiple neurons can be achieved; by adding pipeline instructions, pipeline processing of data flow in artificial intelligence computing tasks can be achieved, thereby improving computing speed.

[0105] According to the method for constructing an integrated storage and computing artificial intelligence chip architecture based on three-dimensional stacking proposed in the embodiment of the present application, multiple target processing units and target memory units that meet the first condition can be integrated in three dimensions to obtain a three-dimensional integrated unit, and based on the target thermal management mechanism, a three-dimensional stacked chip architecture that meets the second condition is determined, thereby quantifying the target parameters of the pre-set deep learning model, and using the quantized parameter distribution and target instruction set to optimize the target data flow path of the three-dimensional stacked chip architecture, thereby constructing an integrated storage and computing artificial intelligence chip architecture based on three-dimensional stacking. As a result, the power consumption of the AI ​​chip during high-performance computing is reduced, the integration of the AI ​​chip architecture is improved, the flexibility of the AI ​​chip architecture is enhanced, and the hardware adaptability of the neural network model and algorithm is improved.

[0106] Secondly, the device for constructing a storage and computing integrated artificial intelligence chip architecture based on three-dimensional stacking proposed in accordance with an embodiment of the present application is described with reference to the accompanying drawings.

[0107] Figure 6 It is a block diagram of a device for constructing a storage and computing integrated artificial intelligence chip architecture based on three-dimensional stacking according to an embodiment of the present application.

[0108] like Figure 6 As shown, the storage and computing integrated artificial intelligence chip architecture construction device 10 based on three-dimensional stacking includes: an identification module 100, a determination module 200 and a construction module 300.

[0109] Specifically, the identification module 100 is used to identify multiple target processing units that meet a first preset condition.

[0110] The determination module 200 is used to perform three-dimensional integration on multiple target processing units and target memory units to obtain a three-dimensional integrated unit, and determine a three-dimensional stacked chip architecture that meets a second preset condition based on the three-dimensional integrated unit and the target thermal management mechanism.

[0111] Construction module 300 is used to quantify the target parameters of a pre-set deep learning model based on a three-dimensional stacked chip architecture, obtain the quantized parameter distribution, and use the quantized parameter distribution and the target instruction set to optimize the target data flow path of the three-dimensional stacked chip architecture, so as to use the optimized data flow path to build a storage and computing integrated artificial intelligence chip architecture based on three-dimensional stacking.

[0112] Optionally, in one embodiment of the present application, the identification module 100 includes: a first identification unit, a second identification unit and a third identification unit.

[0113] Wherein, the first identification unit is used to identify at least one central processing unit based on the target general task.

[0114] The second identification unit is used to identify at least one graphics processing unit based on the graphics computing task.

[0115] The third recognition unit is used to recognize artificial neurons of multiple neuromorphic arrays based on a neural network computing task.

[0116] Optionally, in one embodiment of the present application, the determination module 200 includes: a first determination unit, a second determination unit and a third determination unit.

[0117] Wherein, the first determination unit is used to determine the three-dimensional interlayer interconnection structure based on a preset three-dimensional stacking method.

[0118] The second determining unit is used to respectively optimize the data transmission paths corresponding to the processing units and the memory units between different layers of the three-dimensional interlayer interconnection structure to obtain an optimized target data transmission path.

[0119] The third determining unit is used to perform three-dimensional integration of multiple target processing units and target memory units based on a target data transmission path to obtain a three-dimensional integrated unit.

[0120] Optionally, in one embodiment of the present application, the determination module 200 includes: a fourth determination unit.

[0121] Among them, the fourth determination unit is used to design a target heat dissipation channel in the layer of the three-dimensional interlayer interconnection structure using a three-dimensional integrated unit and a target thermal management mechanism, and to design a vertical heat dissipation channel between the layers of the three-dimensional interlayer interconnection structure to determine a three-dimensional stacked chip that meets preset conditions.

[0122] Optionally, in one embodiment of the present application, the construction module 300 includes: an acquisition unit and an optimization unit.

[0123] Among them, the acquisition unit is used to introduce the target scale factor into the three-dimensional stacked chip architecture to quantify the target parameters of the pre-set deep learning model, and obtain the parameter quantization error and parameter information entropy of the deep learning model.

[0124] The optimization unit is used to optimize the target data flow path of the three-dimensional stacked chip architecture based on parameter quantization error, parameter information entropy and target instruction set.

[0125] It should be noted that the aforementioned explanation of the embodiment of the method for constructing an integrated storage and computing artificial intelligence chip architecture based on three-dimensional stacking is also applicable to the device for constructing an integrated storage and computing artificial intelligence chip architecture based on three-dimensional stacking of this embodiment, and will not be repeated here.

[0126] According to the device for constructing an integrated storage and computing artificial intelligence chip architecture based on three-dimensional stacking proposed in the embodiment of the present application, multiple target processing units and target memory units that meet the first condition can be integrated in three dimensions to obtain a three-dimensional integrated unit, and based on the target thermal management mechanism, a three-dimensional stacked chip architecture that meets the second condition is determined, thereby quantifying the target parameters of the pre-set deep learning model, and using the quantized parameter distribution and target instruction set to optimize the target data flow path of the three-dimensional stacked chip architecture, thereby constructing an integrated storage and computing artificial intelligence chip architecture based on three-dimensional stacking. As a result, the power consumption of the AI ​​chip during high-performance computing is reduced, the integration of the AI ​​chip architecture is improved, the flexibility of the AI ​​chip architecture is enhanced, and the hardware adaptability of the neural network model and algorithm is improved.

[0127] Figure 7 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. The electronic device may include:

[0128] A memory 701 , a processor 702 , and a computer program stored in the memory 701 and executable on the processor 702 .

[0129] When the processor 702 executes the program, it implements the method for constructing the storage and computing integrated artificial intelligence chip architecture based on three-dimensional stacking provided in the above embodiment.

[0130] Furthermore, the electronic device further comprises:

[0131] The communication interface 703 is used for communication between the memory 701 and the processor 702 .

[0132] The memory 701 is used to store computer programs that can be executed on the processor 702 .

[0133] The memory 701 may include a high-speed RAM memory, and may also include a non-volatile memory (non-volatile memory), such as at least one disk memory.

[0134] If the memory 701, the processor 702 and the communication interface 703 are implemented independently, the communication interface 703, the memory 701 and the processor 702 can be connected to each other through a bus and communicate with each other. The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 7 Only one thick line is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0135] Optionally, in a specific implementation, if the memory 701, the processor 702 and the communication interface 703 are integrated on a chip, the memory 701, the processor 702 and the communication interface 703 can communicate with each other through an internal interface.

[0136] The processor 702 may be a central processing unit (CPU), or an application specific integrated circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of the present application.

[0137] This embodiment also provides a computer program product, including a computer program, which, when executed, is used to implement the above-mentioned method for constructing a storage and computing integrated artificial intelligence chip architecture based on three-dimensional stacking.

[0138] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example" or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or N embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0139] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of this application, "N" means at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0140] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, fragment or portion of code comprising one or N executable instructions for implementing the steps of a custom logical function or process, and the scope of the preferred embodiments of the present application includes alternative implementations in which functions may not be performed in the order shown or discussed, including performing functions in a substantially simultaneous manner or in reverse order depending on the functions involved, which should be understood by technicians in the technical field to which the embodiments of the present application belong.

[0141] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as an ordered list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by an instruction execution system, device or apparatus (such as a computer-based system, a system including a processor, or other system that can fetch instructions from an instruction execution system, device or apparatus and execute instructions), or in combination with these instruction execution systems, devices or apparatuses. For the purposes of this specification, a "computer-readable medium" can be any device that can contain, store, communicate, propagate or transmit a program for use by an instruction execution system, device or apparatus, or in combination with these instruction execution systems, devices or apparatuses. More specific examples of computer-readable media (a non-exhaustive list) include the following: an electrical connection with one or N wirings (electronic devices), a portable computer disk box (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), a fiber optic device, and a portable compact disk read-only memory (CDROM). In addition, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically by optically scanning the paper or other medium and then editing, interpreting or processing in other suitable ways as necessary and then storing it in a computer memory.

[0142] It should be understood that the various parts of the present application can be implemented by hardware, software, firmware or a combination thereof. In the above embodiment, the N steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one or a combination of the following technologies known in the art: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0143] A person skilled in the art may understand that all or part of the steps in the method for implementing the above-mentioned embodiment may be completed by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, which, when executed, includes one or a combination of the steps of the method embodiment.

[0144] In addition, each functional unit in each embodiment of the present application may be integrated into a processing module, or each unit may exist physically separately, or two or more units may be integrated into one module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of a software functional module. If the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it may also be stored in a computer-readable storage medium.

[0145] The storage medium mentioned above may be a read-only memory, a magnetic disk or an optical disk, etc. Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limiting the present application. A person of ordinary skill in the art may change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. A method for constructing a storage-computing integrated artificial intelligence chip architecture based on three-dimensional stacking, characterized in that: The following steps are involved: identifying a plurality of target processing units that meet a first preset condition; Performing three-dimensional integration on the multiple target processing units and the target memory unit to obtain a three-dimensional integrated unit, and determining a three-dimensional stacked chip architecture that meets a second preset condition based on the three-dimensional integrated unit and the target thermal management mechanism; Based on the three-dimensional stacked chip architecture, the target parameters of the pre-set deep learning model are quantified to obtain the quantized parameter distribution, and the quantized parameter distribution and the target instruction set are used to optimize the target data flow path of the three-dimensional stacked chip architecture, so as to use the optimized data flow path to build an integrated storage and computing artificial intelligence chip architecture based on three-dimensional stacking.

2. The method according to claim 1, characterized in that The identifying of a plurality of target processing units that meet a preset condition comprises: Based on the target general purpose task, identifying at least one central processing unit; Based on the graphics computing task, identifying at least one graphics processing unit; Identify artificial neurons of multiple neuromorphic arrays based on neural network computational tasks.

3. The method according to claim 1, characterized in that The three-dimensional integration of the plurality of target processing units and the target memory unit to obtain a three-dimensional integrated unit includes: Based on a preset three-dimensional stacking method, determine the three-dimensional interlayer interconnection structure; Respectively optimizing the data transmission paths corresponding to the processing units and the memory units between different layers of the three-dimensional interlayer interconnection structure to obtain an optimized target data transmission path; Based on the target data transmission path, the multiple target processing units and the target memory unit are three-dimensionally integrated to obtain the three-dimensional integrated unit.

4. The method according to claim 3, characterized in that The determining of a three-dimensional stacked chip architecture that meets preset conditions based on the three-dimensional integrated unit and the target thermal management mechanism includes: The three-dimensional integrated unit and the target thermal management mechanism are used to design target heat dissipation channels in the layers of the three-dimensional interlayer interconnection structure, and vertical heat dissipation channels are designed between the layers of the three-dimensional interlayer interconnection structure to determine the three-dimensional stacked chip that meets the preset conditions.

5. The method according to claim 1, characterized in that The method of quantizing a preset target parameter of a deep learning model based on the three-dimensional stacked chip architecture to obtain a quantized parameter distribution, and optimizing a target data flow path of the three-dimensional stacked chip architecture using the quantized parameter distribution and a target instruction set includes: Introducing a target scale factor into the three-dimensional stacked chip architecture to quantize the target parameter of the preset deep learning model, and obtaining a parameter quantization error and a parameter information entropy of the deep learning model; Based on the parameter quantization error, the parameter information entropy and the target instruction set, a target data flow path of the three-dimensional stacked chip architecture is optimized.

6. A device for constructing a storage-computing integrated artificial intelligence chip architecture based on three-dimensional stacking, characterized in that: include: An identification module, used to identify a plurality of target processing units that meet a first preset condition; A determination module, configured to perform three-dimensional integration of the plurality of target processing units and the target memory unit to obtain a three-dimensional integrated unit, and determine a three-dimensional stacked chip architecture that meets a second preset condition based on the three-dimensional integrated unit and the target thermal management mechanism; A construction module is used to quantify the target parameters of a pre-set deep learning model based on the three-dimensional stacked chip architecture, obtain the quantized parameter distribution, and use the quantized parameter distribution and the target instruction set to optimize the target data flow path of the three-dimensional stacked chip architecture, so as to use the optimized data flow path to build an integrated storage and computing artificial intelligence chip architecture based on three-dimensional stacking.

7. The device according to claim 6, characterized in that The identification module comprises: A first identification unit, configured to identify at least one central processing unit based on a target general purpose task; A second identification unit, configured to identify at least one graphics processing unit based on the graphics computing task; The third recognition unit is used to recognize artificial neurons of multiple neuromorphic arrays based on a neural network computing task.

8. The device according to claim 6, characterized in that The determination module comprises: A first determining unit, configured to determine a three-dimensional interlayer interconnection structure based on a preset three-dimensional stacking method; A second determination unit is used to respectively optimize the data transmission paths corresponding to the processing units and the memory units between different layers of the three-dimensional inter-layer interconnection structure to obtain an optimized target data transmission path; A third determining unit is configured to perform three-dimensional integration on the multiple target processing units and the target memory unit based on the target data transmission path to obtain the three-dimensional integrated unit.

9. The device according to claim 8, characterized in that The determination module comprises: The fourth determination unit is used to design a target heat dissipation channel in the layer of the three-dimensional interlayer interconnection structure by using the three-dimensional integrated unit and the target thermal management mechanism, and to design a vertical heat dissipation channel between the layers of the three-dimensional interlayer interconnection structure, so as to determine the three-dimensional stacked chip that meets the preset conditions.

10. The device according to claim 6, characterized in that The building blocks include: An acquisition unit, configured to introduce a target scale factor into the three-dimensional stacked chip architecture to quantize the target parameter of the preset deep learning model, and obtain a parameter quantization error and a parameter information entropy of the deep learning model; An optimization unit is used to optimize the target data flow path of the three-dimensional stacked chip architecture based on the parameter quantization error, the parameter information entropy and the target instruction set.

11. An electronic device, characterized in that: include: A memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the method for constructing a storage-computing integrated artificial intelligence chip architecture based on three-dimensional stacking as described in any one of claims 1 to 5.

12. A computer program product, comprising a computer program, characterized in that The computer program is executed by a processor to implement the method for constructing a storage and computing integrated artificial intelligence chip architecture based on three-dimensional stacking as described in any one of claims 1 to 5.

Images