Memory and refresh management method

Abstract

The invention provides a memory and a refresh management method, and the method comprises the steps: executing at least one conventional refresh operation on a memory block with a target number in each memory block group if the target number is the first occurrence of the same memory block refresh cycle of this round; and if the target number is that the same memory block refresh cycle does not appear for the first time, executing at least one hammering refresh operation on the memory block with the target number in each memory block group.

Description

Technical Field

[0001] The present disclosure relates to the semiconductor field, and in particular to a memory and a refresh management method. Background Art

[0002] In dynamic memory, it is necessary to frequently refresh the storage rows to avoid data loss. At present, dynamic memory has a same bank refresh mechanism (REFSB), under which the refresh command issued by the memory controller will instruct the memory to perform regular refresh on the target numbered storage blocks in each storage block group. However, if the memory controller issues a refresh command with a duplicate address, the memory cannot respond well, resulting in a waste of resources. Summary of the invention

[0003] The present disclosure provides a memory and a refresh management method.

[0004] The technical solution of the present disclosure is achieved as follows:

[0005] In a first aspect, an embodiment of the present disclosure provides a memory,

[0006] The memory includes M storage block groups, each of which includes N storage blocks, where N and M are both positive integers, and the memory also includes:

[0007] A command handling circuit is configured to receive a same storage block refresh command, and based on each same storage block refresh command, generate and output a refresh window pulse; and if the target number selected by the same storage block refresh command appears for the first time in this round of same storage block refresh cycle, output a first type of address selection signal during the existence of the refresh window pulse; if the target number selected by the same storage block refresh command does not appear for the first time in this round of same storage block refresh cycle, output a second type of address selection signal during the existence of the refresh window pulse; wherein the same storage block refresh command indicates that the storage block of the target number in each storage block group is normally refreshed;

[0008] A refresh circuit connected to the command handling circuit and configured to receive the refresh window pulse and the address selection signal; during the existence of the refresh window pulse, if the address selection signal is of the first type, at least one normal refresh operation is performed on the target numbered storage block in each of the storage block groups; if the address selection signal is of the second type, at least one hammer refresh operation is performed on the target numbered storage block in each of the storage block groups;

[0009] The memory is further configured to end the current round of same storage block refresh cycle after performing a conventional refresh operation on all numbered storage blocks in each storage block group based on the received same storage block refresh command.

[0010] In some embodiments, the address selection signal includes N+1 address selection sub-signals;

[0011] The command handling circuit includes N command handling modules, and the nth command handling module has a corresponding relationship with the nth storage block in each storage block group;

[0012] The nth command handling module is configured to receive an nth same storage block refresh command, and based on each of the nth same storage block refresh commands, generate the refresh window pulse on the output nth refresh window sub-signal, and based on the count value of the nth same storage block refresh commands received in this round of same storage block refresh cycle, generate and output the nth address selection sub-signal;

[0013] The nth same storage block refresh command refers to the same storage block refresh command with a selected target number of n, where n is a natural number and n≤N-1.

[0014] In some embodiments, each of the command handling modules includes a count handling unit, a first delay unit, an intermediate logic unit, a refresh window generation unit, and an address selection control unit;

[0015] In the nth command handling module:

[0016] The counting processing unit is configured to receive and count the nth same storage block refresh command to generate an nth count value; decode the nth count value to generate and output a preprocessing signal; wherein, if the nth same storage block refresh command is received for the first time in this round of the same storage block refresh cycle, the preprocessing signal is valid; if the nth same storage block refresh command is not received for the first time in this round of the same storage block refresh cycle, the preprocessing signal is invalid;

[0017] The first delay unit is configured to receive the nth same storage block refresh command, delay the nth same storage block refresh command to output a first delay command;

[0018] The intermediate logic unit is connected to the first delay unit and the counting processing unit respectively, and is configured to output the received first delay command as a first intermediate pulse when the preprocessing signal is valid; and output the received first delay command as a second intermediate pulse when the preprocessing signal is invalid;

[0019] The refresh window generation unit is connected to the intermediate logic unit and is configured to generate the refresh window pulse on the outputted nth refresh window sub-signal if the first intermediate pulse or the second intermediate pulse is received;

[0020] The address selection control unit is connected to the intermediate logic unit and the refresh window generation unit respectively, and is configured to generate and output the nth address selection sub-signal based on the nth refresh window sub-signal and the second intermediate pulse.

[0021] In some embodiments, the first type of the address selection signal means that N address selection sub-signals are all at the first level, and the second type of the address selection signal means that there is only one address selection sub-signal at the second level;

[0022] In the nth command handling module:

[0023] The address selection control unit is specifically configured to output the nth address selection sub-signal of a first level if the nth refresh window sub-signal does not generate the refresh window pulse; and

[0024] During the period when the nth refresh window sub-signal generates the refresh window pulse, if the second intermediate pulse is not received, keeping the nth address selection sub-signal at the first level unchanged;

[0025] If the second intermediate pulse is received during the period when the nth refresh window sub-signal generates the refresh window pulse, the nth address selection sub-signal is adjusted to a second level during the period when the second intermediate pulse exists.

[0026] In some embodiments, the memory further comprises a reset logic module;

[0027] The reset logic module is configured to generate a reset command after each round of refresh cycle of the same storage block ends;

[0028] The counting handling unit is connected to the reset logic module, and is further configured to receive the reset command and reset the nth counting value based on the reset command.

[0029] In some embodiments, the reset logic module includes:

[0030] A latch module is configured to receive N refresh window sub-signals and output corresponding N refresh flag signals; wherein, in each round of the same storage block refresh cycle, the nth refresh flag signal is adjusted from invalid to valid based on the first refresh window pulse on the nth refresh window sub-signal;

[0031] an operation module connected to the latch module and configured to receive a global refresh command and the N refresh flag signals; when the global refresh command is received or when the N refresh flag signals are all valid, generate the reset command; wherein the global refresh command instructs the memory to perform a regular refresh on all storage blocks at the same time;

[0032] a second delay unit connected to the operation module, configured to receive the reset command, perform delay processing on the reset command, and output a delayed reset command;

[0033] The latch module is connected to the second delay unit, and is further configured to receive the delay reset command, and adjust the N refresh flag signals to be invalid based on the delay reset command.

[0034] In some embodiments, the command handling circuit is further configured to generate and output one of the refresh window pulses when receiving one same storage block refresh management command, and output a second type of address selection signal during the existence of the refresh window pulse; wherein the same storage block refresh management command instructs to perform hammer refresh on the storage block of the target number in each of the storage block groups;

[0035] Correspondingly, the nth command handling module is further configured to generate the refresh window pulse on the output nth refresh window sub-signal when receiving an nth same storage block refresh management command, and switch the output nth address selection sub-signal to the second level during the existence of the refresh window pulse; wherein the nth same storage block refresh management command refers to the same storage block refresh management command with the target number n selected;

[0036] Correspondingly, the intermediate logic unit of the nth command handling module is further configured to generate the second intermediate pulse when receiving the nth same storage block refresh management command.

[0037] In some embodiments, when the validity of the pre-processing signal refers to the pre-processing signal being at a high level:

[0038] In the nth command handling module: the counting handling unit includes a counter and a decoder;

[0039] The counter comprises a first trigger, a second trigger and a third trigger, wherein input terminals of the first trigger, the second trigger and the third trigger are all connected to their own inverting output terminals, a clock terminal of the first trigger receives the nth identical storage block refresh command, a clock terminal of the second trigger is connected to the inverting output terminal of the first trigger, a clock terminal of the third trigger is connected to the inverting output terminal of the second trigger, and reset terminals of the first trigger, the second trigger and the third trigger all receive the reset command;

[0040] The positive phase output terminal of the first flip-flop outputs the 0th sub-signal of the nth count value, the positive phase output terminal of the second flip-flop outputs the 1st sub-signal of the nth count value, and the positive phase output terminal of the third flip-flop outputs the 2nd sub-signal of the nth count value;

[0041] The decoder includes a first NOT gate, a second NOT gate and a first AND gate, wherein an input end of the first NOT gate receives a 1st bit sub-signal of the nth count value, an input end of the second NOT gate receives a 2nd bit sub-signal of the nth count value, a first input end of the first AND gate receives a 0th bit sub-signal of the nth count value, a second input end of the first AND gate is connected to an output end of the first NOT gate, a third input end of the first AND gate is connected to an output end of the second NOT gate, and an output end of the first AND gate outputs the preprocessed signal.

[0042] In some embodiments, in the nth command handling module: the intermediate logic unit includes a second AND gate, a third NOT gate, a third AND gate, and a first OR gate;

[0043] The first input end of the second AND gate receives the preprocessing signal, the input end of the third NOT gate receives the preprocessing signal, the first input end of the third AND gate is connected to the output end of the third NOT gate, and the second input end of the second AND gate and the second input end of the third AND gate both receive the first delay command; the first input end of the first OR gate is connected to the output end of the third AND gate, and the second input end of the first OR gate receives the nth identical storage block refresh management command;

[0044] The output terminal of the second AND gate outputs the first intermediate pulse, and the output terminal of the first OR gate outputs the second intermediate pulse.

[0045] In some embodiments, when the first level is a low level and the second level is a high level:

[0046] In the nth command handling module: the refresh window generation unit includes a second OR gate and a pulse generator;

[0047] The first input end of the second OR gate receives the first intermediate pulse, the second input end of the second OR gate receives the second intermediate pulse, the input end of the pulse generator is connected to the output end of the second OR gate, and the output end of the pulse generator outputs the nth refresh window sub-signal.

[0048] In some embodiments, in the nth command handling module: the address selection control unit includes a third delay unit, a first NAND gate, a fourth NAND gate, a first NOR gate, a second NAND gate and a third NAND gate;

[0049] The input end of the third delay unit receives the second intermediate pulse, the first input end of the first NAND gate is connected to the output end of the third delay unit, the second input end of the first NAND gate and the input end of the fourth NAND gate both receive the nth refresh window sub-signal, the first input end of the first NOR gate is connected to the output end of the fourth NOR gate, and the second input end of the first NOR gate receives a power-on reset command;

[0050] The first input end of the second NAND gate is connected to the output end of the first NAND gate, the second input end of the second NAND gate is connected to the output end of the third NAND gate, the first input end of the third NAND gate is connected to the output end of the first NOR gate, the second input end of the third NAND gate is connected to the output end of the second NAND gate, and the output end of the second NAND gate outputs the nth address selection sub-signal.

[0051] In some embodiments, the latch module includes N fourth triggers;

[0052] The input terminals of the N fourth flip-flops all receive the power supply signal, and the reset terminals of the N fourth flip-flops all receive the delayed reset command; the clock terminal of the nth fourth flip-flop receives the nth refresh window sub-signal, and the output terminal of the nth fourth flip-flop outputs the nth refresh flag signal;

[0053] The operation module includes a fourth AND gate and a third OR gate; the input end of the fourth AND gate receives N refresh flag signals, the first input end of the third OR gate is connected to the output end of the fourth AND gate, the second input end of the third OR gate receives the global refresh signal, and the output end of the third OR gate outputs the reset command.

[0054] In some embodiments, the refresh circuit includes M refresh module groups, each refresh module group includes N refresh modules, the M×N refresh modules correspond to the M×N storage blocks one by one, and each refresh module includes an enable control unit, a refresh address selection unit, an address decoding unit, and a command control unit;

[0055] In the nth refresh module of the mth group:

[0056] The enabling control unit is configured to receive and perform a logic operation on the nth refresh window sub-signal and the mth group selection signal, generate and output a storage block enabling signal; wherein the mth group selection signal indicates whether the mth storage block group is selected;

[0057] The refresh address selection unit is configured to receive the nth address selection sub-signal, and when the nth address selection sub-signal is at a first level, output the automatic refresh count row address as the target refresh address signal; when the nth address selection sub-signal is at a second level, output the victim row address as the target refresh address signal; wherein the automatic refresh count row address is generated by a global address counter, and the victim row address is generated by a hammer refresh statistics module in the nth storage block of the mth group;

[0058] The address decoding unit is connected to the enable control unit and the refresh address selection unit respectively, and is configured to receive the storage block enable signal and the target refresh address signal, and decode the target refresh address signal when the storage block enable signal is valid, and generate a word line start signal corresponding to the target refresh address signal;

[0059] The command control unit is configured to receive the nth refresh window sub-signal and the word line start signal, and output the word line start signal during the period when the nth refresh window sub-signal generates the refresh window pulse;

[0060] The command control unit is connected to the nth storage block of the mth group, and the word line start signal is used to select a word line in the nth storage block of the mth group to perform a refresh operation;

[0061] Wherein, m is a natural number, and m≤M-1.

[0062] In some embodiments, the global address counter is further configured to receive the reset command, and to increment the automatic refresh count row address if the reset command is valid.

[0063] In some embodiments, in the nth refresh module of the mth group:

[0064] The enable control unit includes a fifth AND gate and a delay controller; the first input end of the fifth AND gate receives the nth refresh window sub-signal, the second input end of the fifth AND gate receives the mth group selection signal, and the output end of the fifth AND gate is used to output a storage block selection signal; the delay controller is connected to the fifth AND gate, and is used to receive the storage block selection signal, and delay the storage block selection signal by a preset time, and generate and output the storage block enable signal; wherein the preset times corresponding to the M storage block groups are all different;

[0065] The refresh address selection unit includes a data selector, a first input end of the data selector receives the automatic refresh count row address, a second input end of the data selector receives the victim row address, a control end of the data selector is connected to the nth address selection sub-signal, and an output end of the data selector outputs the target refresh address signal.

[0066] In a second aspect, an embodiment of the present disclosure provides a refresh management method, which is applied to a memory, wherein the memory includes M storage block groups, each of which includes N storage blocks, and the refresh management method includes:

[0067] In a same storage block refresh cycle, receiving a same storage block refresh command; wherein the same storage block refresh command instructs to perform a regular refresh operation on the storage block with a target number in each of the storage block groups;

[0068] If the target number is the first appearance of the same storage block refresh cycle in this round, performing at least one conventional refresh operation on the storage block of the target number in each storage block group;

[0069] If the target number is not the first occurrence of the same storage block refresh cycle in this round, performing at least one hammer refresh operation on the storage block with the target number in each storage block group;

[0070] After the conventional refresh operation is performed on the memory blocks with all the numbers in each memory block group, the current round of refresh cycle of the same memory block is ended.

[0071] In some embodiments, the method further comprises:

[0072] receiving a same storage block refresh management command, wherein the same storage block refresh management command instructs to perform a hammer refresh operation on the storage block with a target number in each of the storage block groups;

[0073] At least one hammer refresh operation is performed on the memory blocks of the target number in each of the memory block groups based on the same memory block refresh management command.

[0074] The disclosed embodiments provide a memory and refresh management method, which utilizes the same memory block refresh command with repeated addresses to perform hammer refresh operations, which not only avoids waste of refresh commands and improves refresh efficiency, but also improves the memory's response to row hammer attacks and improves system security. BRIEF DESCRIPTION OF THE DRAWINGS

[0075] Figure 1 This is a schematic diagram of a working scenario of a refresh mechanism;

[0076] Figure 2 A schematic diagram of the structure of a memory provided by an embodiment of the present disclosure;

[0077] Figure 3 A schematic diagram of a working scenario of a refresh mechanism provided by an embodiment of the present disclosure;

[0078] Figure 4 A schematic diagram of the structure of a command processing circuit provided by an embodiment of the present disclosure;

[0079] Figure 5 A detailed structural diagram of a command handling circuit provided in an embodiment of the present disclosure;

[0080] Fig. 6A A schematic diagram of the structure of another memory provided by an embodiment of the present disclosure;

[0081] Figure 6B A schematic diagram of the structure of another command handling circuit provided by an embodiment of the present disclosure;

[0082] Figure 6C A detailed structural diagram of another command handling circuit provided in an embodiment of the present disclosure;

[0083] Figure 7 A schematic diagram of a local structure of a command processing circuit provided in an embodiment of the present disclosure Figure 1 ;

[0084] Figure 8 A partial structural diagram of a command processing circuit provided in an embodiment of the present disclosure Figure 2 ;

[0085] Fig. 9 A schematic diagram of a local structure of a command processing circuit provided in an embodiment of the present disclosure Figure 3 ;

[0086] Fig.10 A schematic diagram of a refresh circuit provided by an embodiment of the present disclosure;

[0087] Fig.11 A detailed structural diagram of a refresh circuit provided in an embodiment of the present disclosure Figure 1 ;

[0088] Fig.12 A detailed structural diagram of a refresh circuit provided in an embodiment of the present disclosure Figure 2 ;

[0089] Fig.13 A flowchart of a refresh management method provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0090] The following will be combined with the drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. It is understood that the specific embodiments described herein are only used to explain the relevant application, not to limit the application. It should also be noted that, for the convenience of description, only the parts related to the relevant application are shown in the drawings. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by technicians in the technical field of the present disclosure. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure. In the following description, "some embodiments" are involved, which describe a subset of all possible embodiments, but it is understood that "some embodiments" can be the same subset or different subsets of all possible embodiments, and can be combined with each other without conflict. It should be noted that the terms "first\second\third" involved in the embodiments of the present disclosure are only used to distinguish similar objects, and do not represent a specific order for the objects. It is understandable that "first\second\third" can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present disclosure described here can be implemented in an order other than that shown or described.

[0091] The following are explanations of professional terms involved in the embodiments of the present disclosure and the corresponding relationships of some terms:

[0092] Dynamic Random Access Memory (DRAM);

[0093] Synchronous Dynamic Random Access Memory (SDRAM);

[0094] Double Data Rate SDRAM (DDR);

[0095] Fifth Generation DDR (DDR5)

[0096] Low Power DDR (LPDDR).

[0097] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0098] For DDR5, there are at least the following refresh mechanisms: Same Bank Refresh (REFSB), Global Refresh (REFAB), and Refresh Management (RFMSB).

[0099] Specifically, when the global refresh command REFAB is received, all storage blocks (Bank) are refreshed, and the specific refresh address is given by the global address counter (Global Refresh Counter); when the same storage block refresh command REFSB is received, the target numbered storage blocks (Bank) in each storage block group (Bank Group) are refreshed, and the specific refresh address is also given by the global address counter (Global Refresh Counter). Both the same storage block refresh mechanism and the global refresh mechanism are designed to ensure that all row addresses in the memory are refreshed at least once within 64 milliseconds.

[0100] In addition, the refresh management mechanism is a refresh mechanism for row hammer protection. Row hammer is a data attack method against dynamic random access memory, which causes data loss in adjacent storage rows (hereinafter referred to as victim rows) by frequently activating a storage row (hereinafter referred to as hammer row) in a short period of time. In DRAM, within the interval between two refreshes (tREFI), each storage block will have a dynamic random lookup table (DLUT) to store the address of the row that has been activated the most times in this interval. The DLUT of each storage block is independent. During the execution of the refresh management command, the row that has been activated the most times will be taken out from the DLUT of the corresponding storage block as the hammer row, and its adjacent rows will be refreshed as victim rows.

[0101] Simply put, the same storage block refresh mechanism REFSB and the global refresh mechanism REFAB both use the automatic refresh count row address given by the global address counter to perform refresh operations, also known as regular refresh operations; while the refresh management mechanism RFMSB performs refresh operations based on the victim row address determined by the dynamic random lookup table in each storage block, also known as hammer refresh operations.

[0102] Further, it is assumed that the memory includes M storage block groups (Bank Group), and each storage block group includes N storage blocks (Bank). For the same storage block refresh mechanism, the memory controller (Controller) needs to issue N REFSB commands to complete a round of same storage block refresh cycle. Exemplarily, it is assumed that the global address counter gives the row address 0. In this round of same storage block refresh cycle, the memory controller needs to issue REFSB <0> (used to indicate that row address 0 in Bank 0 of all storage block groups is refreshed), REFSB <1> (used to indicate refresh of row address 0 in the 1st Bank of all storage block groups)...REFSB_N-1 (used to indicate refresh of row address 0 in the N-1th Bank of all storage block groups), thus ending this round of refresh cycle of the same storage block; then, the global address counter will be incremented by one to give row address 1, and enter the next round of refresh cycle of the same storage block.

[0103] At present, in a refresh cycle of the same storage block, if the memory controller places a REFSB with a repeated address, theoretically, a row of addresses of the corresponding numbered storage blocks in each storage block group will be repeatedly refreshed, which will not bring any beneficial effect but increase power consumption; therefore, the subsequent REFSB with repeated addresses will be blocked and will not be executed by the memory. See Figure 1 For example, suppose that in a refresh cycle of the same storage block, the memory controller sends the following REFSB in sequence: <0> 、REFSB <1> 、REFSB <2> 、REFSB <0> , at this time the second REFSB <0> The corresponding regular refresh operation window will not be pulled up, that is, the second REFSB <0> The memory block will not be refreshed if it is shielded. In this way, although the current consumption is saved and repeated row refreshes in the refresh mechanism of the same memory block are avoided, according to the requirements of the industry standard (SPEC), starting from the memory controller issuing the refresh command, the Bank specified in the reserved time (tRFC time) is not allowed to execute other commands except for unselected (Device Deselected, DES) / low power mode entry command (Power Down Entry, PDE) / no operation (No Operation, NOP) / low power mode exit command (Power Down Exit, PDX) / non-target chip impedance termination (non-Target ODT commands). In this way, although power consumption is saved, this time period is still wasted, and the memory block does not have any operation.

[0104] In one embodiment of the present disclosure, see Figure 2 , which shows a schematic diagram of the structure of a memory 10 provided by an embodiment of the present disclosure. Figure 2 As shown, the memory 10 includes M storage block groups, each storage block group includes N storage blocks, and both N and M are positive integers. It should be understood that in the embodiment of the present disclosure, a storage block refers to a Bank, also called a storage library; a storage block group refers to a Bank Group.

[0105] like Figure 2 As shown, the memory 10 also includes:

[0106] The command handling circuit 11 is configured to receive a same storage block refresh command, and based on each same storage block refresh command, generate and output a refresh window pulse; and if the target number selected by the same storage block refresh command appears for the first time in this round of same storage block refresh cycle, then output a first type of address selection signal during the existence of the refresh window pulse; if the target number selected by the same storage block refresh command does not appear for the first time in this round of same storage block refresh cycle, then output a second type of address selection signal during the existence of the refresh window pulse; wherein the same storage block refresh command indicates that the storage block of the target number in each storage block group is normally refreshed;

[0107] The refresh circuit 12 is connected to the command handling circuit 11 and configured to receive a refresh window pulse and an address selection signal; during the existence of the refresh window pulse, if the address selection signal is of the first type, at least one conventional refresh operation is performed on the target numbered storage block in each storage block group; if the address selection signal is of the second type, at least one hammer refresh operation is performed on the target numbered storage block in each storage block group;

[0108] The memory 10 is further configured to end the current round of same memory block refresh cycle after performing a conventional refresh operation on all numbered memory blocks in each memory block group based on the received same memory block refresh command.

[0109] It should be noted that the refresh window pulse means: a designated signal changes from a low level to a high level, maintains for a period of time, and then returns to a low level. In the disclosed embodiment, the width of the refresh window pulse (the time the designated signal maintains a high level) needs to be limited according to the actual application scenario; in addition, the refresh window pulse can correspond to multiple signals, that is, any of the designated signals that produce the above changes can be considered to have generated a refresh window pulse.

[0110] In some other embodiments, the refresh window pulse means that a specified signal changes from a high level to a low level, maintains for a period of time, and then returns to a high level.

[0111] It should be noted that if Figure 2As shown, storage block group 0 includes storage blocks 0 to storage block N-1, and storage block group 1 includes storage blocks 0 to storage block N-1... Exemplarily, one same storage block refresh command indicates that storage block 0 in all storage block groups is normally refreshed, and another same storage block refresh command indicates that storage block 1 in all storage block groups is normally refreshed...

[0112] That is, in a same memory block refresh loop (LOOP), if the memory 10 receives a same memory block refresh command with a repeated address, it will perform a hammer refresh operation using a subsequent same memory block refresh command with a repeated address. That is, assuming that in a same memory block refresh loop, the memory controller sends the following REFSB <0> 、REFSB <1> 、REFSB <2> 、REFSB <0> , see Figure 3 , at this time the second REFSB <0> The corresponding normal refresh operation window is not pulled up, but the hammer refresh operation window is pulled up, so that the memory 10 performs the hammer refresh operation. It should be understood that according to industry standards, the system reserved time (tRFC) of the normal refresh operation and the system reserved time (tRFC) of the hammer refresh operation are the same, so there is no timing problem.

[0113] It should be noted that for a refresh command of the same memory block, the number of times the normal refresh operation is finally executed (or the number of times the hammer refresh operation is finally executed) and the number of row addresses refreshed in each refresh operation can be set by the user. Figure 3 As shown, there are two pulses in each normal refresh operation window / hammer refresh operation window, which can indicate two normal refresh operations / hammer refresh operations.

[0114] In this way, on the one hand, even if the same storage block refresh command with a repeated address is received, the memory 10 will not perform a repeated refresh action, saving power consumption; on the other hand, after receiving the same storage block refresh command with a repeated address, the hammer refresh operation is performed within the accompanying reserved time (tRFC), which can also improve the effect of hammer protection, improve refresh efficiency and enhance storage security.

[0115] In addition, the memory 10 may be various types of dynamic memory 1 such as DRAM, SDRAM, DDR, LPDDR, etc. The embodiment of the present disclosure only takes DDR5 as an example for illustration but does not constitute a specific limitation.

[0116] In the embodiment of the present disclosure, the same memory block refresh command may be embodied as a pulse.

[0117] See also Figure 4, which takes N=4 (each storage block group includes 4 storage blocks) as an example to illustrate the specific structure of the memory 10, but this does not constitute a corresponding limitation, and M and N can be more or less.

[0118] Please note that, see Figure 4 The address selection signal includes N address selection sub-signals, represented by AddSel <n-1:0>. Exemplarily, the first type of address selection signal means that N address selection sub-signals are all at the first level, and the second type of address selection signal means that there is only one address selection sub-signal at the second level; or, the first type of address selection signal means that there is only one address selection sub-signal at the second level; the second type of address selection signal means that N address selection sub-signals are all at the first level. Here, the specific level values ​​of the first level and the second level can be set according to the actual application scenario.

[0119] In addition, there are N refresh window sub-signals Refwin in the memory 10. <n-1:0>, any one refresh window sub-signal Ref win <n-1:0>The pulses above can all be considered as the aforementioned refresh window pulses.

[0120] At the same time, taking N=4 as an example, the same memory block refresh command that instructs all memory blocks 0 to perform regular refresh is called the 0th same memory block refresh command REFSB <0> All the same memory block refresh commands that instruct memory block 1 to perform normal refresh are referred to as the first same memory block refresh commands REFSB <1> All the same memory block refresh commands that instruct memory block 2 to perform regular refresh are referred to as the second same memory block refresh commands REFSB <2> The same memory block refresh command that instructs all memory blocks 3 to perform normal refresh is referred to as the third same memory block refresh command REFSB <3> That is, the nth same memory block refresh command refers to the same memory block refresh command with the selected target number n, where n is a natural number and n≤N.

[0121] See also Figure 4 The command processing circuit 11 includes N command processing modules (i.e. Figure 4 nth command handling module 11_n, configured to receive nth same storage block refresh command REFSB <n>, and refresh command REFSB based on each nth identical storage block <n>, in the output of the nth refresh window sub-signal Refwin <n>The aforementioned refresh window pulse is generated on the same storage block refresh cycle, and the nth same storage block refresh command REFSB is received in the same storage block refresh cycle. <n>The count value is used to generate and output the nth address selection sub-signal AddSel <n>.

[0122] It should be noted that the nth command handling module 11_n has a corresponding relationship with the nth storage block in each storage block group; for example, the 0th command handling module 11_0 has a corresponding relationship with the 0th storage block in all storage block groups. In addition, the storage blocks numbered n in all storage block groups share the same nth storage block refresh command REFSB <n>Therefore, the nth command handling module 11_n11_n can be distributed near the storage block numbered n in any storage block group.

[0123] Meanwhile, the N command handling modules 11_n may be concentrated near corresponding storage blocks of the same storage block group, or the N command handling modules 11_n may be distributed near corresponding storage blocks in different storage block groups.

[0124] It should be understood that the nth command handling module 11_n only receives the nth same storage block refresh command REFSB <n>, but will not receive refresh commands for the same memory block at other addresses. <0> Only the 0th command processing module 11_0 will be entered, but other command processing modules will not be entered.

[0125] It should be noted that the structures of the N command processing modules are the same, and the following description will be made taking the nth command processing module 11_n as an example.

[0126] In some embodiments, see Figure 5 , each command handling module includes a counting handling unit 21, a first delay unit 22, an intermediate logic unit 23, a refresh window generation unit 24 and an address selection control unit 25;

[0127] See also Figure 5 , in the nth command handling module 11_n:

[0128] The counting processing unit 21 is configured to receive and refresh the nth identical storage block with the command REFSB <n>Counting is performed to generate an nth count value; decoding the nth count value, generating and outputting a preprocessing signal REF_EN; wherein, if the nth same storage block refresh command REFSB is received for the first time in this round of the same storage block refresh cycle <n>, then the pre-processing signal REF_EN is valid; if it is not the first time to receive the nth same storage block refresh command REFSB in this round of the same storage block refresh cycle <n>, then the pre-processing signal REF_EN is invalid;

[0129] The first delay unit 22 is configured to receive the nth same memory block refresh command REFSB <n>, refresh command REFSB for the nth identical storage block <n>Delay to output the first delay command REFSB_CMD_D <n>;

[0130] The intermediate logic unit 23 is connected to the first delay unit 22 and the count processing unit 21, respectively, and is configured to receive the first delay command REFSB_CMD_D when the pre-processing signal REF_EN is valid. <n>The output is the first intermediate pulse REFSB <n>_DD; When the pre-processing signal REF_EN is invalid, the received first delay command REFSB_CMD_D <n>The output is the second intermediate pulse RFMSB <n>_D;

[0131] The refresh window generation unit 24 is connected to the intermediate logic unit 23 and is configured to receive the first intermediate pulse REFSB <n>_DD or the second middle pulse RFMSB <n>_D, then the nth refresh window sub-signal Refwin is output <n>; Generate a refresh window pulse;

[0132] The address selection control unit 25 is connected to the intermediate logic unit 23 and the refresh window generation unit 24, respectively, and is configured to <n>and the second intermediate pulse RFMSB <n>_D, generates and outputs the nth address selection sub-signal AddSel <n>.

[0133] Please note that the aforementioned refresh window pulse corresponds to multiple signals, but the first intermediate pulse REFSB_D <n>Corresponds to only 1 signal, and the second intermediate pulse RFMSB <n>_D also corresponds to only one signal. In simple terms, the intermediate logic unit 23 has two output ports, the first intermediate pulse REFSB_D <n>Only one of the output ports is generated, the second intermediate pulse RFMSB <n>_D is only generated at the other output port.

[0134] A specified scenario is provided: the first type of address selection signal refers to N address selection sub-signals all being at the first level, and the second type of address selection signal refers to one and only one address selection sub-signal being at the second level. Taking the above specified scenario as an example, a specific structure of a command handling module 11_n is provided:

[0135] See also Figure 5 , the refresh window generating unit 24 is specifically configured to: if the nth refresh window sub-signal Refwin <n>If no refresh window pulse is generated, the nth address selection sub-signal AddSel of the first level is output. <n>;as well as,

[0136] In the nth refresh window sub-signal Refwin <n>During the refresh window pulse generation period, if the second intermediate pulse RFMSB is not received <n>_D, then keep the nth address selection sub-signal AddSel <n>The first level remains unchanged;

[0137] In the nth refresh window sub-signal Refwin <n>During the refresh window pulse generation period, if the second intermediate pulse RFMSB is received <n>_D, then during the existence of the second intermediate pulse, the nth address selection sub-signal AddSel <n>Adjust to the second level.

[0138] In this way, as long as the nth command handling module 11_n receives the nth same storage block refresh command REFSB <n>When the first intermediate pulse REFSB is generated <n>_DD or the second middle pulse RFMSB <n>_D, thereby generating the nth refresh window sub-signal Refwin <n>At the same time, (1) if the received nth same memory block refresh command REFSB <n>It is the first time received in this round of the same storage block refresh cycle. At this time, there is a second intermediate pulse RFMSB <n>_D, nth address selection signal AddSel <n>Maintain the first level, that is, the address selection signal is of the first type, thereby indicating the execution of a normal refresh operation; (2) if the received nth same memory block refresh command REFSB <n>This is not the first time received in this round of the same storage block refresh cycle (that is, the memory controller sends a REFSB with a duplicate address). At this time, there is no second intermediate pulse RFMSB <n>_D, nth address selection signal AddSel <n>The address selection signal is adjusted to the second level, that is, the address selection signal is of the second type, thereby indicating that a hammer refresh operation is performed.

[0139] Please note that, see Figure 4 , the memory 10 further includes a reset logic module 30;

[0140] The reset logic module 30 is configured to generate a reset command RST after each round of refresh cycle of the same storage block ends;

[0141] The counting handling unit 21 is connected to the reset logic module 30 , and is further configured to receive a reset command RST, and reset the nth counting value based on the reset command RST.

[0142] It should be noted that the count processing units 21 in the N command processing modules all share the reset command RST. That is, the memory 10 only needs to be provided with one reset logic module 30 .

[0143] In this way, after each round of the same memory block refresh cycle ends, the nth count value will be reset to the initial value. Therefore, if the nth count value jumps from the initial value once to generate a count state of 1, it means that the first nth same memory block refresh command REFSB of this round of the same memory block refresh cycle has been received. <n>, thereby outputting a valid signal to be processed; if the nth count value continues to jump to count state 2 (or count state 3, or count state 4...), it means that the second (or third, or fourth) nth same storage block refresh command REFSB of the same storage block refresh cycle in this round has been received <n>, thereby outputting an invalid signal to be processed.

[0144] Therefore, for the counting processing unit 21, “decoding the nth count value” can be performed by the following means: determining whether the nth count value is a count state 1 generated after the initial value jumps once.

[0145] It should be noted that the counting processing units 21 in the N command processing modules all receive the same reset command RST, so the entire memory 10 is only provided with one counting processing module.

[0146] In some embodiments, Figure 5 As shown, the reset logic module 30 includes:

[0147] The latch module 31 is configured to receive N refresh window sub-signals and output corresponding N refresh mark signals (eg Figure 5 End0~End3 in each round of the same storage block refresh cycle based on the first nth refresh window sub-signal Refwin <n>The first refresh window pulse on the nth refresh flag signal Endn is adjusted from invalid to valid;

[0148] The operation module 32 is connected to the latch module 31 and is configured to receive the global refresh command REFAB and N refresh flag signals End <n-1:0>; When receiving the global refresh command REFAB or when N refresh flag signals End <n-1:0>When all are valid, a reset command RST is generated; wherein the global refresh command REFAB instructs the memory 10 to perform a normal refresh on all storage blocks at the same time;

[0149] The second delay unit 33 is connected to the operation module 32, and is configured to receive the reset command RST, perform delay processing on the reset command RST, and output a delayed reset command;

[0150] The latch module 31 is connected to the second delay unit 33 and is further configured to receive a delayed reset command RST and to reset the N refresh flag signals End based on the delayed reset command RST. <n-1:0>All are adjusted to invalid.

[0151] It should be noted that in the global refresh mechanism, each global refresh command REFAB will instruct all storage blocks to refresh, and the automatic refresh count row address given by the global address counter will also be incremented by one. Therefore, there is no concept of "same storage block refresh cycle", and each global refresh command REFAB can be considered as a "same storage block refresh cycle". Therefore, the global refresh command REFAB is also used as the reset command of the nth count value, so that the global refresh mechanism will not be affected.

[0152] In some embodiments, see Figure 7 , the latch module 31 includes N fourth triggers 311;

[0153] The input terminals of the N fourth flip-flops 311 all receive the power signal, the reset terminals of the N fourth flip-flops 311 all receive the delayed reset command RST_D; the clock terminal of the nth fourth flip-flop 311 receives the nth refresh window sub-signal Refwin <n>, the output terminal of the nth fourth flip-flop 311 outputs the nth refresh flag signal;

[0154] The operation module 32 includes a fourth AND gate 321 and a third OR gate 322; the input end of the fourth AND gate 321 receives N refresh flag signals, the first input end of the third OR gate 322 is connected to the output end of the fourth AND gate 321, the second input end of the third OR gate 322 receives the global refresh signal REFAB, and the output end of the third OR gate 322 outputs a reset command RST.

[0155] In addition, under the refresh management mechanism, the memory controller will directly issue a REFSB command to instruct the target numbered storage blocks in each storage block group to perform hammer refresh.

[0156] Therefore, see Fig. 6A , the command handling circuit 11 is further configured to generate and output a refresh window pulse when receiving a same storage block refresh management command, and output a second type of address selection signal during the existence of the refresh window pulse; wherein the same storage block refresh management command indicates that a hammer refresh is performed on a storage block of a target number in each storage block group;

[0157] For details, see Figure 6B The nth command handling module 11_n is further configured to receive an nth same storage block refresh management command RFMSB <n>When the nth refresh window sub-signal Refwin is output <n>A refresh window pulse is generated on the PWM, and the nth address selection sub-signal AddSel is outputted during the existence of the refresh window pulse. <n>Switch to the second level; wherein the nth same storage block refresh management command RFMSB <n>Refers to the refresh management command of the same storage block with target number n selected;

[0158] For details, see Figure 6C The intermediate logic unit 23 of the nth command handling module 11_n is also configured to receive the nth same storage block refresh management command RFMSB <n>When the second intermediate pulse RFMSB is generated <n>_D.

[0159] In this way, the same storage block refresh mechanism and refresh management mechanism can reuse the same control circuit to implement hammer refresh operation, reducing circuit area.

[0160] The following only takes the nth command processing module 11_n as an example to illustrate the specific circuit structure.

[0161] See also Figure 7 , providing a prescribed scenario: the validity of the preprocessing signal means that the preprocessing signal is at a high level, and the invalidity of the preprocessing signal means that the preprocessing signal is at a low level. The following provides a specific structure of the counting processing unit 21 for this scenario.

[0162] In the nth command handling module 11_n: the counting handling unit 21 includes a counter 211 and a decoder 212;

[0163] The counter 211 includes a first trigger 401, a second trigger 402 and a third trigger 403. The input terminals of the first trigger 401, the second trigger 402 and the third trigger 403 are all connected to their own inverting output terminals. The clock terminal of the first trigger 401 receives the nth same storage block refresh command REFSB <n>, the clock terminal of the second flip-flop 402 is connected to the inverting output terminal of the first flip-flop 401, the clock terminal of the third flip-flop 403 is connected to the inverting output terminal of the second flip-flop 402, and the reset terminals of the first flip-flop 401, the second flip-flop 402 and the third flip-flop 403 all receive a reset command RST;

[0164] The positive phase output terminal of the first flip-flop 401 outputs the 0th bit sub-signal CNT of the nth count value. <0> The positive phase output terminal of the second flip-flop 402 outputs the first bit sub-signal CNT of the nth count value. <1> The positive phase output terminal of the third flip-flop 403 outputs the second bit sub-signal CNT of the nth count value. <2> ;

[0165] The decoder 212 includes a first NOT gate 404, a second NOT gate 405 and a first AND gate 406. The input terminal of the first NOT gate 404 receives the first bit sub-signal CNT of the nth count value. <1> The input terminal of the second NOT gate 405 receives the second bit sub-signal CNT of the nth count value. <2> The first input terminal of the first AND gate 406 receives the 0th bit sub-signal CNT of the nth count value. <0> The second input terminal of the first AND gate 406 is connected to the output terminal of the first NOT gate 404 , the third input terminal of the first AND gate 406 is connected to the output terminal of the second NOT gate 405 , and the output terminal of the first AND gate 406 outputs the preprocessing signal REF_EN.

[0166] It should be noted that Figure 7 The counter 211 in the embodiment includes three triggers, but this does not constitute a specific limitation, and the number of triggers in the counter 211 can be adjusted.

[0167] In some embodiments, a specified scenario is provided: the first intermediate pulse is a positive pulse, and the second intermediate pulse is also a positive pulse. The specific structure of the intermediate logic unit 23 is provided below for this scenario.

[0168] See also Figure 8 , for the nth command handling module 11_n: the intermediate logic unit 23 includes a second AND gate 231, a third NOT gate 232, a third AND gate 233, and a first OR gate 234;

[0169] The first input terminal of the second AND gate 231 receives the preprocessing signal REF_EN, the input terminal of the third NOT gate 232 receives the preprocessing signal REF_EN, the first input terminal of the third AND gate 233 is connected to the output terminal of the third NOT gate 232, and the second input terminal of the second AND gate 231 and the second input terminal of the third AND gate 233 both receive the first delay command REFSB_CMD_D <n>The first input terminal of the first OR gate 234 is connected to the output terminal of the third AND gate 233, and the second input terminal of the first OR gate 234 receives the nth refresh management command RFMSB <n>;

[0170] The output terminal of the second AND gate 231 outputs the first intermediate pulse REFSB <n>_DD, the output terminal of the first OR gate 234 outputs the second intermediate pulse RFMSB <n>_D.

[0171] In some embodiments, a specified scenario is provided: the first level is a low level, and the second level is a high level. The following provides a specific structure of the refresh window generation unit 24 for this scenario.

[0172] See also Figure 8 , in the nth command handling module 11_n: the refresh window generation unit 24 includes a second OR gate 241 and a pulse generator 242;

[0173] The first input terminal of the second OR gate 241 receives the first intermediate pulse REFSB <n>_DD, the second input terminal of the second OR gate 241 receives the second intermediate pulse RFMSB <n>_D, the input end of the pulse generator 242 is connected to the output end of the second OR gate 241, and the output end of the pulse generator 242 outputs the nth refresh window sub-signal Refwin <n>.

[0174] On the basis of the above, see Fig. 9 , in the nth command handling module 11_n: the address selection control unit 25 includes a third delay unit 250, a first NAND gate 251, a fourth NAND gate 252, a first NOR gate 253, a second NAND gate 254 and a third NAND gate 255;

[0175] The input terminal of the third delay unit 250 receives the second intermediate pulse RFMSB <n>_D, the first input end of the first NAND gate 251 is connected to the output end of the third delay unit 250, and the second input end of the first NAND gate 251 and the input end of the fourth NAND gate 252 both receive the nth refresh window sub-signal Refwin <n>, a first input terminal of the first NOR gate 253 is connected to the output terminal of the fourth NOR gate 252, and a second input terminal of the first NOR gate 253 receives a power-on reset command POWERUP_RESET;

[0176] The first input terminal of the second NAND gate 254 is connected to the output terminal of the first NAND gate 251, the second input terminal of the second NAND gate 254 is connected to the output terminal of the third NAND gate 255, the first input terminal of the third NAND gate 255 is connected to the output terminal of the first NOR gate 253, the second input terminal of the third NAND gate 255 is connected to the output terminal of the second NAND gate 254, and the output terminal of the second NAND gate 254 outputs the nth address selection sub-signal AddSel <n>.

[0177] From the above, it can be seen that when receiving the same storage block refresh command REFSB, the refresh module 11 will give a refresh window pulse to indicate a refresh operation; at the same time, according to whether the storage block refresh command REFSB is a repeated address, the refresh module 11 will also give different types of address selection signals to indicate whether a regular refresh operation or a hammer refresh operation is performed this time, which not only improves the efficiency of the refresh operation, but also enhances storage security.

[0178] In some embodiments, the refresh circuit 12 includes M refresh module groups (eg Fig.10 12_0~12_M-1 in ), each refresh module group includes N refresh modules (for example Fig.10 12_0_0~12_N-1_M-1), M×N refresh modules correspond to M×N storage blocks one by one, and each refresh module includes an enable control unit 121, a refresh address selection unit 122, an address decoding unit 123, and a command control unit 124;

[0179] See also Fig.11 , in the nth refresh module 12_n_m of the mth group:

[0180] The enabling control unit 121 is configured to receive and respond to the nth refresh window sub-signal Refwin <n>and the mth group selection signal BankGroup <m>Perform logical operations to generate and output storage block enable signals; among them, the mth group selection signal BankGroup <m>Indicates whether the mth storage block group is selected;

[0181] The refresh address selection unit 122 is configured to receive the nth address selection sub-signal AddSel <n>, at the nth address selector signal AddSel <n>When it is at the first level, the automatic refresh count row address Normal Address<15:0> is output as the target refresh address signal REFAddress<15:0>; at the nth address selection sub-signal AddSel <n>When at the second level, the victim row address Victim Address<15:0> is output as the target refresh address signal REFAddress<15:0>; wherein the automatic refresh count row address is generated by the global address counter 61, and the victim row address is generated by the hammer refresh statistics module 62 in the nth storage block of the mth group;

[0182] The address decoding unit 123 is connected to the enable control unit 121 and the refresh address selection unit 122, respectively, and is configured to receive the storage block enable signal BankEN_n_m and the target refresh address signal REFAddress<15:0>, and decode the target refresh address signal REFAddress<15:0> when the storage block enable signal BankEN_n_m is valid, and generate a word line start signal corresponding to the target refresh address signal REFAddress<15:0>;

[0183] The command control unit 124 is configured to receive the nth refresh window sub-signal Refwin <n>and word line start signal, in the nth refresh window sub-signal Refwin <n>During the period of generating the refresh window pulse, a word line start signal is output;

[0184] The command control unit 124 is connected to the nth storage block of the mth group, and the word line start signal is used to select a word line in the nth storage block of the mth group to perform a refresh operation; wherein m is a natural number, and m≤M.

[0185] Here, if the nth refresh window sub-signal Refwin <n>is high (i.e. generates a refresh window pulse) and the mth group selection signal BankGroup <m>Indicating that the mth memory block group is selected, the memory block enable signal BankEN_n_m is valid.

[0186] In this way, for each memory block, the refresh address corresponding to the current refresh operation can be selected through the refresh address selection unit 122, so as to perform a normal refresh operation or a hammer refresh operation.

[0187] In some embodiments, the global address counter 61 is further configured to receive a reset command RST, and to increment the automatic refresh count row address by one when the reset command RST is valid.

[0188] In addition, if each same memory block refresh command indicates to perform multiple regular refresh operations on the memory blocks with target numbers in each memory group, then after performing one regular refresh operation on the memory blocks with target numbers in each memory group, the global address counter 61 needs to add one to the automatic refresh count row address. Figure 3 , in the normal refresh operation window / hammer refresh operation window, each pulse will cause the automatic refresh count row address to increase by one.

[0189] In some embodiments, see Fig.12 , in the nth refresh module of the mth group: the enabling control unit 121 includes a fifth AND gate 1211 and a delay controller 1212;

[0190] The first input terminal of the fifth AND gate 1211 receives the nth refresh window sub-signal, the second input terminal of the fifth AND gate 1211 receives the mth group selection signal, the input terminal of the fifth AND gate 1211 is connected to the input terminal of the delay controller 1212, and the output terminal of the delay controller 1212 outputs the storage block enable signal BankEN_n_m.

[0191] It should be noted that the function of the delay controller 1212 is as follows: Assuming that the memory 10 has a total of (4×8)=32 banks, if the Refwin <0> The aforementioned refresh window pulse is generated. At this time, the storage block enable signal BankEN_0_0, storage block enable signal BankEN_1_0, storage block enable signal BankEN_2_0, storage block enable signal BankEN_3_0, storage block enable signal BankEN_4_0, storage block enable signal BankEN_5_0, storage block enable signal BankEN_6_0 and storage block enable signal BankEN_7_0 are all pulled high, which will cause a relatively large transient current. Therefore, in order to reduce the transient current, the delay controller 1212 is used to make different storage block enable signals produce different delays, so that the selected storage blocks can be opened in sequence, so as to better ensure the stable performance of the memory.

[0192] In some embodiments, see Fig.12 The refresh address selection unit 122 includes a data selector, a first input terminal of the data selector receives the automatic refresh count row address Normal Address<15:0>, a second input terminal of the data selector receives the victim row address Victim Address<15:0>, and a control terminal of the data selector is connected to the nth address selection sub-signal AddSel <n>connected, and the output end of the data selector outputs the target refresh address signal REFAddress<15:0>.

[0193] It should be noted that the refresh address selection unit 122 may include a plurality of two-to-one data selectors, and the control terminals of all the two-to-one data selectors receive the nth address selection sub-signal AddSel <n>The two input ends of each two-to-one data selector receive a one-bit sub-signal of the automatic refresh count row address and a one-bit sub-signal of the victim row address respectively, and the output end of each two-to-one data selector outputs a one-bit sub-signal of the target refresh address signal.

[0194] Particularly, the number of sub-signals of the auto-refresh count row address, victim row address and target refresh address signals is the same, but the specific number is not limited.

[0195] In some embodiments, the specific structure of the address decoding unit 123 is determined according to specific decoding rules and can be implemented by various logic devices such as NAND gate, NOR gate, NOT gate, XNOR gate, and XOR gate.

[0196] In one embodiment, the command control unit 124 can be implemented by a sixth AND gate, and two input terminals of the sixth AND gate receive the word line start signal and the nth refresh window sub-signal Refwin respectively. <n>, whose output is connected to the word line in the storage array.

[0197] In another embodiment, see Fig.12 The command control unit 124 includes a seventh AND gate and a fourth OR gate, and the two input ends of the fourth OR gate receive the activation command Activate and the nth refresh window sub-signal Refwin respectively. <n>The two input ends of the seventh AND gate receive the word line start signal and the output signal of the fourth OR gate respectively, and its output end is connected to the word line in the storage array. Here, the activation command is essentially sent by the memory controller to the memory 10. That is to say, the activation operation and the refresh operation are performed here via the same line.

[0198] In summary, in the REFSB mechanism, the same storage block refresh command REFSB issued by the memory controller will be accumulated as the clock signal of the counter 211. When N (for example, N=4) banks have received the same storage block refresh command RREFSB, or the memory controller has issued a global refresh command REFAB (indicating that it has been changed to a global refresh sentence at this time), the counter 211 will be reset; further, the output value of the counter 211 will be decoded, and the decoding will successfully output a high level, indicating that the bank at this position has been refreshed; at this time, if the same storage block refresh command REFSB with the same address comes again, the same storage block refresh command REFSB will be shielded, and the hammer refresh operation will be performed at the same time to refresh the victim row address stored in the DLUT of the bank at this position, that is, hammer protection will be performed. It not only avoids the waste of refresh commands and improves refresh efficiency, but also improves the memory's response effect to row hammer attacks and improves system security.

[0199] In another embodiment of the present disclosure, a refresh management method is provided, the refresh management method is applied to a memory, the memory includes M memory block groups, each memory block group includes N memory blocks;

[0200] See also Fig.13 , which shows a flow chart of a refresh management method provided by an embodiment of the present disclosure. Fig.13 As shown, the refresh management method includes:

[0201] S701: In a same memory block refresh cycle, receiving a same memory block refresh command; wherein the same memory block refresh command indicates to perform a regular refresh operation on a memory block with a target number in each memory block group.

[0202] S702a: If the target number is the first appearance of the same memory block refresh cycle in this round, perform at least one regular refresh operation on the memory block of the target number in each memory block group.

[0203] S702b: If the target number is not the first occurrence in this round of the same memory block refresh cycle, perform at least one hammer refresh operation on the memory block with the target number in each memory block group.

[0204] Here, the execution order of S702a and S702b is not particular.

[0205] S703: After performing a conventional refresh operation on all numbered storage blocks in each storage block group, end this round of refresh cycle of the same storage block.

[0206] In some embodiments, the method further comprises:

[0207] receiving a same storage block refresh management command, wherein the same storage block refresh management command instructs to perform a hammer refresh operation on a storage block with a target number in each storage block group;

[0208] At least one hammer refresh operation is performed on the memory blocks of the target number in each memory block group based on the same memory block refresh management command.

[0209] The above are only preferred embodiments of the present disclosure and are not intended to limit the scope of protection of the present disclosure. It should be noted that in the present disclosure, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "includes one..." does not exclude the existence of other identical elements in the process, method, article or device including the element. The above serial numbers of the embodiments of the present disclosure are only for description and do not represent the advantages and disadvantages of the embodiments. The methods disclosed in several method embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments. The features disclosed in several product embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new product embodiments. The features disclosed in several method or device embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments. The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.< / n> < / n> < / n> < / n> < / m> < / n> < / n> < / n> < / n> < / n> < / n> < / m> < / m> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n>

Claims

1. A memory, characterized in that: The memory includes M storage block groups, each of which includes N storage blocks, where N and M are both positive integers, and the memory also includes: A command handling circuit is configured to receive a same storage block refresh command, and based on each same storage block refresh command, generate and output a refresh window pulse; and if the target number selected by the same storage block refresh command appears for the first time in this round of same storage block refresh cycle, output a first type of address selection signal during the existence of the refresh window pulse; if the target number selected by the same storage block refresh command does not appear for the first time in this round of same storage block refresh cycle, output a second type of address selection signal during the existence of the refresh window pulse; wherein the same storage block refresh command indicates that the storage block of the target number in each storage block group is normally refreshed; A refresh circuit connected to the command handling circuit and configured to receive the refresh window pulse and the address selection signal; during the existence of the refresh window pulse, if the address selection signal is of the first type, at least one normal refresh operation is performed on the target numbered storage block in each of the storage block groups; if the address selection signal is of the second type, at least one hammer refresh operation is performed on the target numbered storage block in each of the storage block groups; The memory is further configured to end the current round of same storage block refresh cycle after performing a conventional refresh operation on all numbered storage blocks in each storage block group based on the received same storage block refresh command.

2. The memory according to claim 1, characterized in that: The address selection signal includes N+1 address selection sub-signals; The command handling circuit includes N command handling modules, and the nth command handling module has a corresponding relationship with the nth storage block in each storage block group; The nth command handling module is configured to receive an nth same storage block refresh command, and based on each of the nth same storage block refresh commands, generate the refresh window pulse on the output nth refresh window sub-signal, and based on the count value of the nth same storage block refresh commands received in this round of same storage block refresh cycle, generate and output the nth address selection sub-signal; The nth same storage block refresh command refers to the same storage block refresh command with a selected target number of n, where n is a natural number and n≤N-1.

3. The memory according to claim 2, characterized in that: Each of the command handling modules includes a counting handling unit, a first delay unit, an intermediate logic unit, a refresh window generating unit and an address selection control unit; In the nth command handling module: The counting processing unit is configured to receive and count the nth same storage block refresh command to generate an nth count value; decode the nth count value to generate and output a preprocessing signal; wherein, if the nth same storage block refresh command is received for the first time in this round of the same storage block refresh cycle, the preprocessing signal is valid; if the nth same storage block refresh command is not received for the first time in this round of the same storage block refresh cycle, the preprocessing signal is invalid; The first delay unit is configured to receive the nth same storage block refresh command, delay the nth same storage block refresh command to output a first delay command; The intermediate logic unit is connected to the first delay unit and the counting processing unit respectively, and is configured to output the received first delay command as a first intermediate pulse when the preprocessing signal is valid; and output the received first delay command as a second intermediate pulse when the preprocessing signal is invalid; The refresh window generation unit is connected to the intermediate logic unit and is configured to generate the refresh window pulse on the outputted nth refresh window sub-signal if the first intermediate pulse or the second intermediate pulse is received; The address selection control unit is connected to the intermediate logic unit and the refresh window generation unit respectively, and is configured to generate and output the nth address selection sub-signal based on the nth refresh window sub-signal and the second intermediate pulse.

4. The memory according to claim 3, characterized in that: The first type of address selection signal means that all N address selection sub-signals are at the first level, and the second type of address selection signal means that only one address selection sub-signal is at the second level; In the nth command handling module: The address selection control unit is specifically configured to output the nth address selection sub-signal of a first level if the nth refresh window sub-signal does not generate the refresh window pulse; and During the period when the nth refresh window sub-signal generates the refresh window pulse, if the second intermediate pulse is not received, keeping the nth address selection sub-signal at the first level unchanged; If the second intermediate pulse is received during the period when the nth refresh window sub-signal generates the refresh window pulse, the nth address selection sub-signal is adjusted to a second level during the period when the second intermediate pulse exists.

5. The memory according to claim 4, characterized in that: The memory also includes a reset logic module; The reset logic module is configured to generate a reset command after each round of refresh cycle of the same storage block ends; The counting handling unit is connected to the reset logic module, and is further configured to receive the reset command and reset the nth counting value based on the reset command.

6. The memory according to claim 5, characterized in that: The reset logic module comprises: A latch module is configured to receive N refresh window sub-signals and output corresponding N refresh flag signals; wherein, in each round of the same storage block refresh cycle, the nth refresh flag signal is adjusted from invalid to valid based on the first refresh window pulse on the nth refresh window sub-signal; an operation module connected to the latch module and configured to receive a global refresh command and the N refresh flag signals; when the global refresh command is received or when the N refresh flag signals are all valid, generate the reset command; wherein the global refresh command instructs the memory to perform a regular refresh on all storage blocks at the same time; a second delay unit connected to the operation module, configured to receive the reset command, perform delay processing on the reset command, and output a delayed reset command; The latch module is connected to the second delay unit, and is further configured to receive the delay reset command, and adjust the N refresh flag signals to be invalid based on the delay reset command.

7. The memory according to claim 6, characterized in that: The command handling circuit is further configured to generate and output one of the refresh window pulses when receiving one same storage block refresh management command, and output a second type of address selection signal during the existence of the refresh window pulse; wherein the same storage block refresh management command instructs the storage block with the target number in each of the storage block groups to be hammer refreshed; Correspondingly, the nth command handling module is further configured to generate the refresh window pulse on the output nth refresh window sub-signal when receiving an nth same storage block refresh management command, and switch the output nth address selection sub-signal to the second level during the existence of the refresh window pulse; wherein the nth same storage block refresh management command refers to the same storage block refresh management command with the target number n selected; Correspondingly, the intermediate logic unit of the nth command handling module is further configured to generate the second intermediate pulse when receiving the nth same storage block refresh management command.

8. The memory according to claim 6, characterized in that: When the validity of the preprocessing signal refers to the preprocessing signal being at a high level: In the nth command handling module: the counting handling unit includes a counter and a decoder; The counter comprises a first trigger, a second trigger and a third trigger, wherein input terminals of the first trigger, the second trigger and the third trigger are all connected to their own inverting output terminals, a clock terminal of the first trigger receives the nth identical storage block refresh command, a clock terminal of the second trigger is connected to the inverting output terminal of the first trigger, a clock terminal of the third trigger is connected to the inverting output terminal of the second trigger, and reset terminals of the first trigger, the second trigger and the third trigger all receive the reset command; The positive phase output terminal of the first flip-flop outputs the 0th sub-signal of the nth count value, the positive phase output terminal of the second flip-flop outputs the 1st sub-signal of the nth count value, and the positive phase output terminal of the third flip-flop outputs the 2nd sub-signal of the nth count value; The decoder includes a first NOT gate, a second NOT gate and a first AND gate, wherein an input end of the first NOT gate receives a 1st bit sub-signal of the nth count value, an input end of the second NOT gate receives a 2nd bit sub-signal of the nth count value, a first input end of the first AND gate receives a 0th bit sub-signal of the nth count value, a second input end of the first AND gate is connected to an output end of the first NOT gate, a third input end of the first AND gate is connected to an output end of the second NOT gate, and an output end of the first AND gate outputs the preprocessed signal.

9. The memory according to claim 7, characterized in that: In the nth command handling module: the intermediate logic unit includes a second AND gate, a third NOT gate, a third AND gate, and a first OR gate; The first input end of the second AND gate receives the preprocessing signal, the input end of the third NOT gate receives the preprocessing signal, the first input end of the third AND gate is connected to the output end of the third NOT gate, and the second input end of the second AND gate and the second input end of the third AND gate both receive the first delay command; the first input end of the first OR gate is connected to the output end of the third AND gate, and the second input end of the first OR gate receives the nth identical storage block refresh management command; The output terminal of the second AND gate outputs the first intermediate pulse, and the output terminal of the first OR gate outputs the second intermediate pulse.

10. The memory according to claim 4, characterized in that: When the first level is a low level and the second level is a high level: In the nth command handling module: the refresh window generation unit includes a second OR gate and a pulse generator; The first input end of the second OR gate receives the first intermediate pulse, the second input end of the second OR gate receives the second intermediate pulse, the input end of the pulse generator is connected to the output end of the second OR gate, and the output end of the pulse generator outputs the nth refresh window sub-signal.

11. The memory according to claim 4, characterized in that: In the nth command handling module: the address selection control unit includes a third delay unit, a first NAND gate, a fourth NAND gate, a first NOR gate, a second NAND gate and a third NAND gate; The input end of the third delay unit receives the second intermediate pulse, the first input end of the first NAND gate is connected to the output end of the third delay unit, the second input end of the first NAND gate and the input end of the fourth NAND gate both receive the nth refresh window sub-signal, the first input end of the first NOR gate is connected to the output end of the fourth NOR gate, and the second input end of the first NOR gate receives a power-on reset command; The first input end of the second NAND gate is connected to the output end of the first NAND gate, the second input end of the second NAND gate is connected to the output end of the third NAND gate, the first input end of the third NAND gate is connected to the output end of the first NOR gate, the second input end of the third NAND gate is connected to the output end of the second NAND gate, and the output end of the second NAND gate outputs the nth address selection sub-signal.

12. The memory according to claim 6, characterized in that: The latch module includes N fourth triggers; The input terminals of the N fourth flip-flops all receive the power supply signal, and the reset terminals of the N fourth flip-flops all receive the delayed reset command; the clock terminal of the nth fourth flip-flop receives the nth refresh window sub-signal, and the output terminal of the nth fourth flip-flop outputs the nth refresh flag signal; The operation module includes a fourth AND gate and a third OR gate; the input end of the fourth AND gate receives N refresh flag signals, the first input end of the third OR gate is connected to the output end of the fourth AND gate, the second input end of the third OR gate receives the global refresh signal, and the output end of the third OR gate outputs the reset command.

13. The memory according to claim 6, characterized in that: The refresh circuit includes M refresh module groups, each refresh module group includes N refresh modules, the M×N refresh modules correspond to the M×N storage blocks one by one, and each refresh module includes an enable control unit, a refresh address selection unit, an address decoding unit, and a command control unit; In the nth refresh module of the mth group: The enabling control unit is configured to receive and perform a logic operation on the nth refresh window sub-signal and the mth group selection signal, generate and output a storage block enabling signal; wherein the mth group selection signal indicates whether the mth storage block group is selected; The refresh address selection unit is configured to receive the nth address selection sub-signal, and when the nth address selection sub-signal is at a first level, output the automatic refresh count row address as the target refresh address signal; when the nth address selection sub-signal is at a second level, output the victim row address as the target refresh address signal; wherein the automatic refresh count row address is generated by a global address counter, and the victim row address is generated by a hammer refresh statistics module in the nth storage block of the mth group; The address decoding unit is connected to the enable control unit and the refresh address selection unit respectively, and is configured to receive the storage block enable signal and the target refresh address signal, and decode the target refresh address signal when the storage block enable signal is valid, and generate a word line start signal corresponding to the target refresh address signal; The command control unit is configured to receive the nth refresh window sub-signal and the word line start signal, and output the word line start signal during the period when the nth refresh window sub-signal generates the refresh window pulse; The command control unit is connected to the nth storage block of the mth group, and the word line start signal is used to select a word line in the nth storage block of the mth group to perform a refresh operation; Wherein, m is a natural number, and m≤M-1.

14. The memory according to claim 13, characterized in that: The global address counter is further configured to receive the reset command and, if the reset command is valid, to increment the automatic refresh count row address by one.

15. The memory according to claim 13, characterized in that: In the nth refresh module of the mth group: The enable control unit includes a fifth AND gate and a delay controller; the first input end of the fifth AND gate receives the nth refresh window sub-signal, the second input end of the fifth AND gate receives the mth group selection signal, and the output end of the fifth AND gate is used to output a storage block selection signal; the delay controller is connected to the fifth AND gate, and is used to receive the storage block selection signal, and delay the storage block selection signal by a preset time, and generate and output the storage block enable signal; wherein the preset times corresponding to the M storage block groups are all different; The refresh address selection unit includes a data selector, a first input end of the data selector receives the automatic refresh count row address, a second input end of the data selector receives the victim row address, a control end of the data selector is connected to the nth address selection sub-signal, and an output end of the data selector outputs the target refresh address signal.

16. A refresh management method, characterized in that: Applied to a memory, the memory includes M memory block groups, each of the memory block groups includes N memory blocks, and the refresh management method includes: In a same storage block refresh cycle, receiving a same storage block refresh command; wherein the same storage block refresh command instructs to perform a regular refresh operation on the storage block with a target number in each of the storage block groups; If the target number is the first appearance of the same storage block refresh cycle in this round, performing at least one conventional refresh operation on the storage block of the target number in each storage block group; If the target number is not the first occurrence of the same storage block refresh cycle in this round, performing at least one hammer refresh operation on the storage block of the target number in each storage block group; After the conventional refresh operation is performed on the memory blocks with all the numbers in each memory block group, the current round of refresh cycle of the same memory block is ended.

17. The refresh management method according to claim 16, characterized in that: The method further comprises: receiving a same storage block refresh management command, wherein the same storage block refresh management command instructs to perform a hammer refresh operation on the storage block with a target number in each of the storage block groups; At least one hammer refresh operation is performed on the memory blocks of the target number in each of the memory block groups based on the same memory block refresh management command.

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