Control circuit and memory

Abstract

The embodiment of the invention provides a control circuit and a memory, and the control circuit comprises a command decoding circuit which is used for carrying out the command decoding processing of a first pulse of a chip selection signal and a command address signal according to a first clock signal, and obtaining a first command signal; the address decoding circuit is used for performing row address decoding processing on the second pulse of the chip selection signal and the command address signal according to the first command signal and the first clock signal to obtain n second command signals; the logic processing circuit is used for performing logic processing according to the n second command signals to obtain n segmented activation signals; wherein the storage array comprises m storage libraries, each storage library comprises n segments, and m and n are positive integers; the segment activation signal is used for indicating whether the segment corresponding to at least one storage library in the m storage libraries is activated or not, so that the purpose of saving power is achieved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a control circuit and a memory. Background Art

[0002] With the continuous development of semiconductor technology, people have put forward higher and higher requirements for data transmission speed when manufacturing and using computers and other equipment. In order to obtain faster data transmission speed, a series of devices such as memory that can transmit data at double data rate (DDR) have emerged.

[0003] Take Dynamic Random Access Memory (DRAM) as an example. Data can be stored in DRAM. In order to maintain data integrity, DRAM is refreshed periodically. As the density and speed of DRAM increase, the impact of refresh operation on the overall performance and power consumption of DRAM becomes increasingly greater. Summary of the invention

[0004] The present disclosure provides a control circuit and a memory, which can achieve the purpose of power saving.

[0005] In a first aspect, an embodiment of the present disclosure provides a control circuit, the control circuit comprising a command decoding circuit, an address decoding circuit and a logic processing circuit, the command decoding circuit is connected to the address decoding circuit, and the address decoding circuit is also connected to the logic processing circuit, wherein:

[0006] A command decoding circuit is used to receive a command address signal, a chip select signal and a first clock signal, and perform command decoding processing on a first pulse of the chip select signal and the command address signal according to the first clock signal to obtain a first command signal; wherein the first command signal is used to indicate whether to activate m memory banks in the memory array, where m is a positive integer;

[0007] The address decoding circuit is used to receive the first command signal, the first clock signal, the chip select signal and the command address signal, and perform row address decoding processing on the second pulse of the chip select signal and the command address signal according to the first command signal and the first clock signal to obtain n second command signals; wherein the second command signal is used to indicate whether to activate a certain segment of the m storage banks, and n is a positive integer;

[0008] A logic processing circuit is used to receive n second command signals, perform logic processing according to the n second command signals, and obtain n segment activation signals, wherein the segment activation signal is used to indicate whether a segment corresponding to at least one storage bank in the m storage banks has been activated; wherein the storage array includes m storage banks, each storage bank includes n segments, and there is a corresponding relationship between the n segments and the n segment activation signals.

[0009] In some embodiments, the first command signal includes m first command sub-signals, and the m first command sub-signals have a corresponding relationship with m storage bins, wherein: if the first command sub-signal is in a first level state, it is determined that the storage bin corresponding to the first command sub-signal is activated; if the first command sub-signal is in a second level state, it is determined that the storage bin corresponding to the first command sub-signal is not activated.

[0010] In some embodiments, the address decoding circuit is also used to perform row address decoding processing on the second pulse of the chip select signal and the command address signal according to the first command signal and the first clock signal to obtain n third command signals; wherein the second command signal and the third command signal are inversely proportional to each other; the logic processing circuit is used to receive n second command signals and n third command signals, and perform logic processing according to the n second command signals and n third command signals to obtain n segment activation signals.

[0011] In some embodiments, the logic processing circuit includes n segment processing sub-circuits, wherein: the i-th segment processing sub-circuit is used to receive the i-th second command signal and the i-th third command signal, and perform logic processing according to the i-th second command signal and the i-th third command signal to obtain the i-th segment activation signal; wherein the i-th segment activation signal is used to indicate whether there is at least one storage repository among the m storage repositories whose corresponding i-th segment has been activated, and i is an integer greater than or equal to 0 and less than n.

[0012] In some embodiments, the second command signal includes m second command sub-signals; the third command signal includes m third command sub-signals; wherein the second command sub-signals and the third command sub-signals are in anti-phase relationship with each other, and the kth second command sub-signal in the second command signal and the kth third command sub-signal in the third command signal both have a corresponding relationship with the kth storage memory, and k is an integer greater than or equal to 0 and less than m.

[0013] In some embodiments, the i-th segment processing subcircuit includes m logic subcircuits and a control subcircuit, wherein: the j-th logic subcircuit is used to receive a ground signal, a j-th second command sub-signal and a j-th third command sub-signal, and the output end of the j-th logic subcircuit is used to output the j-th first intermediate signal, where j is an integer greater than or equal to 0 and less than m; the first input end of the control subcircuit is connected to the output ends of the m logic subcircuits, the second input end of the control subcircuit is used to receive a power-on signal, and the output end of the control subcircuit is used to output the i-th segment activation signal; wherein the chip select signal indicates that the target chip is selected, and the power-on signal indicates that all power supplies of the target chip are started up.

[0014] In some embodiments, the jth logic sub-circuit includes a jth latch module and a jth gating buffer module, the output end of the jth latch module is connected to the input end of the jth gating buffer module, and the control end of the jth gating buffer module is used to receive the jth third command sub-signal; wherein: the jth latch module is used to receive the ground signal and the jth second command sub-signal, and control the latch state of the jth latch module according to the jth second command sub-signal to generate the jth second intermediate signal; the jth gating buffer module is used to receive the jth second intermediate signal and the jth third command sub-signal, and control the conduction state of the jth gating buffer module according to the jth third command sub-signal to generate the jth first intermediate signal.

[0015] In some embodiments, the jth logic sub-circuit is used to determine that the jth second intermediate signal is in the second level state and the jth gated buffer module is in the on state when the jth second command sub-signal is in the first level state and the jth third command sub-signal is in the second level state, so that the jth first intermediate signal is in the second level state.

[0016] In some embodiments, the jth logic sub-circuit is used to determine that the jth gated buffer module is in the off state when the jth second command sub-signal is in the second level state and the jth third command sub-signal is in the first level state, so that the output of the jth gated buffer module is in a high impedance state.

[0017] In some embodiments, the control subcircuit includes a first OR gate, a first buffer and an mth gated buffer module, wherein: the first input end of the first OR gate is respectively connected to the output ends of the m logic subcircuits and the output end of the mth gated buffer module, the second input end of the first OR gate is used to receive a power-on signal, the output end of the first OR gate is respectively connected to the input end of the mth gated buffer module and the input end of the first buffer, the control end of the mth gated buffer module is used to receive a power-on signal, and the output end of the first buffer is used to output the i-th segment activation signal.

[0018] In some embodiments, the control circuit further includes a mode register and an output circuit, wherein: the mode register is used to output n initial segment mask signals, wherein the initial segment mask signal is used to indicate whether to perform mask refresh on a certain segment of the m memory banks set by the mode register; the output circuit is used to receive n segment activation signals and n initial segment mask signals, and perform OR logic processing on the n segment activation signals and the n initial segment mask signals to generate n target segment mask signals; wherein:

[0019] If the i-th target segment mask signal is in a first level state, then when a refresh operation is performed, the refresh operation of the i-th segment corresponding to at least one storage bank among the m storage banks is shielded; if the i-th target segment mask signal is in a second level state, then when a refresh operation is performed, the refresh operation of the i-th segment corresponding to all storage banks among the m storage banks is not shielded.

[0020] In some embodiments, the first level state is a high level, and the second level state is a low level.

[0021] In some embodiments, the output circuit includes n second OR gates, wherein: the first input terminal of the pth second OR gate is used to receive the pth segment activation signal, and the second input terminal of the pth second OR gate is used to receive the pth initial segment mask signal; the output terminal of the pth second OR gate is used to output the pth target segment mask signal; wherein p is an integer greater than or equal to 0 and less than n.

[0022] In some embodiments, the output circuit includes n second OR gates and n second buffers, and the input end of the pth second buffer is connected to the output end of the pth second OR gate, wherein: the pth second OR gate is used to receive the pth segmented activation signal and the pth initial segmented mask signal, and perform an OR logic operation on the pth segmented activation signal and the pth initial segmented mask signal to obtain the pth intermediate segmented mask signal; the pth second buffer is used to perform drive enhancement processing on the pth intermediate segmented mask signal to obtain the pth target segmented mask signal; wherein p is an integer greater than 0 and less than or equal to n.

[0023] In a second aspect, an embodiment of the present disclosure provides a memory, which at least includes the control circuit as described in the first aspect.

[0024] The disclosed embodiment provides a control circuit and a memory, the control circuit includes a command decoding circuit, an address decoding circuit and a logic processing circuit. The command decoding circuit is used to perform command decoding processing on the first pulse of the chip selection signal and the command address signal according to the first clock signal to obtain a first command signal, the first command signal is used to indicate whether to activate the m storage banks in the storage array, m is a positive integer; the address decoding circuit is used to perform row address decoding processing on the second pulse of the chip selection signal and the command address signal according to the first command signal and the first clock signal to obtain n second command signals and n third command signals, the second command signal and the third command signal are in an inverse relationship, and the second command signal is used to indicate whether to activate a certain segment of the m storage banks, n is a positive integer; the logic processing circuit is used to perform logic processing according to the n second command signals and the n third command signals to obtain n segment activation signals; wherein the storage array includes m storage banks, each storage bank includes n segments, and there is a corresponding relationship between the n segments and the n segment activation signals, and the segment activation signal is used to indicate whether at least one segment corresponding to the storage bank in the m storage banks has been activated. In this way, if it can be determined based on the segment activation signal that the segments corresponding to some storage libraries have been activated, which means that the segments corresponding to these storage libraries have been accessed, then the segments need to be periodically refreshed during the refresh operation phase; otherwise, if it can be determined based on the segment activation signal that the segments corresponding to some storage libraries have not been activated, which means that the segments corresponding to these storage libraries have not been accessed, then refresh shielding can be performed on the segments during the refresh operation phase; in this way, not only the data integrity in the storage library can be maintained, but also the power consumption can be reduced to achieve the purpose of power saving, and ultimately the memory performance can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 A schematic diagram of a control circuit provided in an embodiment of the present disclosure Figure 1 ;

[0026] Figure 2 A schematic diagram of the structure of a logic processing circuit provided in an embodiment of the present disclosure;

[0027] Figure 3 A schematic diagram of the structure of a segment processing subcircuit provided in an embodiment of the present disclosure;

[0028] Figure 4 A schematic diagram of the structure of a logic subcircuit provided in an embodiment of the present disclosure;

[0029] Figure 5 A schematic diagram of the structure of a control subcircuit provided in an embodiment of the present disclosure;

[0030] Figure 6A schematic diagram of a control circuit provided in an embodiment of the present disclosure Figure 2 ;

[0031] Figure 7 A schematic diagram of the structure of an output circuit provided in an embodiment of the present disclosure Figure 1 ;

[0032] Figure 8 A schematic diagram of the structure of an output circuit provided in an embodiment of the present disclosure Figure 2 ;

[0033] Fig. 9 A schematic diagram of the architecture of a memory provided by an embodiment of the present disclosure;

[0034] Fig.10 A local detailed structure diagram of a control circuit provided in an embodiment of the present disclosure Figure 1 ;

[0035] Fig.11 A local detailed structure diagram of a control circuit provided in an embodiment of the present disclosure Figure 2 ;

[0036] Fig.12 A signal timing diagram provided for an embodiment of the present disclosure;

[0037] Fig.13 A schematic diagram of the composition structure of a memory provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0038] The following will be combined with the drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. It is understood that the specific embodiments described herein are only used to explain the relevant application, rather than to limit the application. It should also be noted that, for the convenience of description, only the parts related to the relevant application are shown in the drawings.

[0039] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0040] In the following description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0041] It should be pointed out that the terms "first\second\third" involved in the embodiments of the present disclosure are only used to distinguish similar objects and do not represent a specific ordering of the objects. It can be understood that "first\second\third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of the present disclosure described here can be implemented in an order other than that illustrated or described here.

[0042] It should also be noted that the high level and low level used in the signal involved in the embodiments of the present disclosure refer to the logic level of the signal. There is a difference between a signal having a high level and a signal having a low level. For example, a high level may correspond to a signal having a first voltage, and a low level may correspond to a signal having a second voltage. In some embodiments, the first voltage is greater than the second voltage. In addition, the logic level of the signal may be different from or opposite to the described logic level. For example, a signal described as having a logic "high" level may alternatively have a logic "low" level, and a signal described as having a logic "low" level may alternatively have a logic "high" level.

[0043] It is understandable that dynamic random access memory (DRAM) needs to maintain data in the storage array through refresh operations. Each refresh operation will open at least one bank in the storage array and perform a refresh operation on the opened bank. However, as the density and speed of DRAM increase, the impact of refresh operations on the overall performance and power consumption of DRAM becomes increasingly greater.

[0044] In the disclosed embodiment, for the storage banks in the storage array, each storage bank can be divided into multiple segments (Segment / Section). The storage density corresponds to the number of segments. For example, if the storage density is 8GB, it can be divided into 8 segments; if the storage density is 6GB, it can be divided into 6 segments; if the storage density is 4GB, it can be divided into 4 segments; but this is not specifically limited here.

[0045] In some embodiments, it is assumed that the storage array includes 8 memory banks, specifically: Bank0, Bank1, Bank2, ..., Bank7. Regardless of whether a self-refresh operation is being performed, the segments corresponding to each of the 8 memory banks can be independently configured. Taking the mode register 23 (Mode Register 23, MR23) as an example, the mode register MR23 can be accessed through a mode register write (Mode Register Write, MRW) command to indicate the masking state of each segment. Table 1 shows an application example of segment masking.

[0046] Table 1

[0047]

[0048] Here, each storage bank can have up to 8 segments, and the 8 segments specifically include: Segment 0 (Segment0), Segment 1 (Segment 1), Segment 2 (Segment 2), ..., Segment 7 (Segment7). Among them, the segment mask (SegmentMask) is used to control whether a segment of the entire storage array is refreshed. When a segment is masked by the MRW command, the self-refresh operation of the entire segment is blocked, and the data retention of the segment cannot be guaranteed in the self-refresh mode. It can be seen from Table 1 that the segment mask corresponding to Segment 2 and Segment 7 is 1. At this time, in Bank0~Bank7, the refresh operations of Segment 2 and Segment 7 are masked (Masked, M).

[0049] In actual applications, whether to perform refresh shielding on the segments of the storage library, if a segment has not been accessed (i.e., no read or write operations have been performed, etc.), then the data in the segment is not of great value. At this time, the segment can not perform a refresh operation, that is, the segment can be refresh shielded.

[0050] Based on this, an embodiment of the present disclosure provides a control circuit, which includes a command decoding circuit, an address decoding circuit and a logic processing circuit. Among them, the storage array includes m storage banks, each storage bank includes n segments, and there is a corresponding relationship between the n segments and the n segment activation signals, and the segment activation signal is used to indicate whether there is at least one segment corresponding to the storage bank in the m storage banks that has been activated. In this way, if it can be determined according to the segment activation signal that the segments corresponding to some storage banks have been activated, it means that the segments corresponding to these storage banks have been accessed, then it is necessary to perform periodic refresh on the segments in the refresh operation stage; otherwise, if it can be determined according to the segment activation signal that the segments corresponding to some storage banks have not been activated, it means that the segments corresponding to these storage banks have not been accessed, then refresh shielding can be performed on the segments in the refresh operation stage; in this way, not only the data integrity in the storage bank can be maintained, but also the power consumption can be reduced to achieve the purpose of power saving, and ultimately the memory performance can be improved.

[0051] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0052] In one embodiment of the present disclosure, see Figure 1 , which shows a schematic diagram of the composition structure of a control circuit provided by an embodiment of the present disclosure. Figure 1As shown, the control circuit 10 may include a command decoding circuit 101, an address decoding circuit 102 and a logic processing circuit 103, the command decoding circuit 101 is connected to the address decoding circuit 102, and the address decoding circuit 102 is also connected to the logic processing circuit 103, wherein:

[0053] The command decoding circuit 101 is used to receive a command address signal, a chip select signal and a first clock signal, and perform command decoding processing on the first pulse of the chip select signal and the command address signal according to the first clock signal to obtain a first command signal; wherein the first command signal is used to indicate whether to activate m memory banks in the memory array, where m is a positive integer;

[0054] The address decoding circuit 102 is used to receive the first command signal, the first clock signal, the chip select signal and the command address signal, and perform row address decoding processing on the second pulse of the chip select signal and the command address signal according to the first command signal and the first clock signal to obtain n second command signals; wherein the second command signal is used to indicate whether to activate a certain segment of the m memory banks, and n is a positive integer;

[0055] The logic processing circuit 103 is used to receive n second command signals, perform logic processing according to the n second command signals, and obtain n segment activation signals, wherein the segment activation signal is used to indicate whether at least one segment corresponding to the storage library in the m storage libraries has been activated.

[0056] It should be noted that the control circuit 10 of the embodiment of the present disclosure is applied to a memory, which can solve the problem that the refresh operation has a great impact on the overall performance and power consumption of the memory. Specifically, in the embodiment of the present disclosure, the control circuit 10 can be a refresh control circuit, and in the refresh operation stage, it can reduce power consumption, thereby achieving the purpose of power saving.

[0057] It should also be noted that, in the embodiment of the present disclosure, the storage array may include m storage banks, each storage bank may include n segments, and there is a corresponding relationship between the n segments and the n segment activation signals. That is, the i-th segment activation signal is used to indicate whether the i-th segment of at least one storage bank among all storage banks has been activated; wherein i is an integer greater than or equal to 0 and less than n.

[0058] For example, assuming that m is equal to 16 and n is equal to 8, there are 16 storage banks in total, namely Bank0, Bank1, Bank2, ..., Bank15; each storage bank may include 8 segments, namely Segment 0, Segment 1, Segment 2, ..., Segment 7. Accordingly, there are also 8 segment activation signals generated here, and the i-th segment activation signal can be represented by ActSegMskIndicates; then the segment activation signals corresponding to the 8 segments are: ActSegMsk <0> 、ActSegMsk <1> 、ActSegMsk <2> , …, ActSegMsk <7> Here, if ActSegMsk The signal is in the first level state, indicating that the i-th segment of all memory banks in the storage array has not been activated; if ActSegMsk If the signal is in the second level state, it indicates that the i-th segment of at least one memory bank in the memory array has been activated.

[0059] It should also be noted that, in the embodiment of the present disclosure, since the segment activation signal can determine whether the segments corresponding to certain storage libraries have been activated, specifically, if the segments corresponding to these storage libraries have been activated, it means that the segment has been accessed and the data stored in the segment is valid. In order to ensure data integrity, this segment cannot be shielded and refreshed during the refresh operation phase; if the segments corresponding to these storage libraries have not been activated, it means that the segment has not been accessed and the data stored in the segment is not important. In this case, this segment can be shielded and refreshed during the refresh operation phase, thereby reducing the refresh current and refresh power consumption and achieving the purpose of power saving.

[0060] In some embodiments, the first command signal may include m first command sub-signals, and the m first command sub-signals have a corresponding relationship with the m storage banks, wherein:

[0061] If the first command sub-signal is in a first level state, determining that the storage bank corresponding to the first command sub-signal performs an activation operation;

[0062] If the first command sub-signal is in the second level state, it is determined that the memory bank corresponding to the first command sub-signal does not perform an activation operation.

[0063] It should be noted that, in the embodiment of the present disclosure, the first command signal can be used to indicate which storage bin is to be activated, and the first command signal can be represented by ActBnk1. In addition, the first command signal is not a signal, but represents a group of signals. Here, the number of first command sub-signals in the first command signal is the same as the number of storage bins, that is, each storage bin corresponds to a first command sub-signal. Among them, the lth first command sub-signal corresponding to the lth storage bin can be represented by ActBnk1. <l>It means that l is an integer greater than or equal to 0 and less than m.

[0064] It should also be noted that, in the embodiment of the present disclosure, the first level state may be a high level, such as logic 1; the second level state may be a low level, such as logic 0, but this is not specifically limited.

[0065] That is, in the embodiment of the present disclosure, if the lth first command sub-signal is at a high level, it can be determined that the lth storage bank performs an activation operation; if the lth first command sub-signal is at a low level, it can be determined that the lth storage bank does not perform an activation operation.

[0066] It can be understood that in the embodiment of the present disclosure, the command address signal can be represented by CA<6:0>. It should be noted that the command address signal here is not a signal, but represents a group of signals, specifically CA0, CA1, CA2, CA3, CA4, CA5 and CA6. The chip select signal can be represented by CS, and the chip select signal represents the signal that the target chip is selected. In this way, for the first command signal, it can be obtained by the command decoding circuit 101 performing command decoding processing on the first pulse of the chip select signal and the command address signal according to the first clock signal.

[0067] In some embodiments, the address decoding circuit 102 is further used to perform row address decoding processing on the second pulse of the chip selection signal and the command address signal according to the first command signal and the first clock signal to obtain n third command signals; wherein the second command signal and the third command signal are in anti-phase relationship with each other;

[0068] The logic processing circuit 103 is used to receive n second command signals and n third command signals, and perform logic processing according to the n second command signals and the n third command signals to obtain n segment activation signals.

[0069] It should be noted that, in the embodiment of the present disclosure, the third command signal is an inverted signal of the second command signal. That is, the third command signal can be obtained by inverting the second command signal; therefore, the third command signal can be generated in the address decoding circuit 102, or the third command signal can also be generated in the logic processing circuit 103, which is not specifically limited here.

[0070] In some embodiments, for the logic processing circuit 103, see Figure 2 , the logic processing circuit 103 may include n segment processing sub-circuits, wherein:

[0071] an i-th segment processing subcircuit, configured to receive an i-th second command signal and an i-th third command signal, and perform logic processing according to the i-th second command signal and the i-th third command signal to obtain an i-th segment activation signal;

[0072] The i-th segment activation signal is used to indicate whether the i-th segment corresponding to at least one storage bank in the m storage banks has been activated, and i is an integer greater than or equal to 0 and less than n.

[0073] It should be noted that, in the embodiment of the present disclosure, the i-th segment processing subcircuit can be represented by segment processing subcircuit i. Figure 2 In the embodiment, the n segment processing subcircuits may include: segment processing subcircuit 0, segment processing subcircuit 1, ..., segment processing subcircuit n-1. Each segment processing subcircuit may be used to process a certain segment corresponding to the m storage bins, and specifically, each segment activation signal may be used to indicate whether a certain segment corresponding to at least one storage bin in the m storage bins has been activated.

[0074] It should also be noted that in the embodiments of the present disclosure, the i-th second command signal is not a signal, but represents a group of signals, and the i-th third command signal is not a signal, but represents a group of signals. In some embodiments, for each second command signal and each third command signal, the second command signal may include m second command sub-signals, and the third command signal may include m third command sub-signals.

[0075] Among them, the second command sub-signal and the third command sub-signal are in anti-phase relationship with each other, and the kth second command sub-signal in the second command signal and the kth third command sub-signal in the third command signal both have a corresponding relationship with the kth storage memory, and k is an integer greater than or equal to 0 and less than m.

[0076] It can be understood that in the embodiment of the present disclosure, for the address decoding circuit 102, the second command signal and the third command signal generated are in anti-phase relationship with each other. <m-1:0>Indicates that the qth third command signal can be used with SegqActN <m-1:0>represents, "N" represents inversion, and q is an integer greater than or equal to 0 and less than n.

[0077] Exemplarily, assuming that the value of m is 16, then for the qth second command signal, it may include SegqAct <0> 、SegqAct <1> , …, SegqAct <15> For the qth third command signal, it may include SegqActN <0> 、SegqActN <1> , …, SegqActN <15> So, for Bank0, SegqAct <0> and SegqActN <0> It has a corresponding relationship with Bank0; for Bank1, SegqAct <1> and Segq ActN <1> It has a corresponding relationship with Bank1; and so on, for Bank15, SegqAct <15> and SegqActN <15> Corresponding to Bank15.

[0078] In some embodiments, for the segment processing subcircuit i, see Figure 3 , the i-th segment processing subcircuit may include m logic subcircuits 301 and control subcircuits 302, wherein:

[0079] In the m logic sub-circuits 301, the j-th logic sub-circuit is used to receive the ground signal, the j-th second command sub-signal and the j-th third command sub-signal, and the output end of the j-th logic sub-circuit is used to output the j-th first intermediate signal, where j is an integer greater than or equal to 0 and less than m;

[0080] The first input terminal of the control subcircuit 302 is connected to the output terminals of the m logic subcircuits 302 , the second input terminal of the control subcircuit 302 is used to receive a power-on signal, and the output terminal of the control subcircuit 302 is used to output the i-th segment activation signal.

[0081] It should be noted that, in the embodiment of the present disclosure, the chip select signal indicates that the target chip is selected, and the power-on signal indicates that all power supplies of the target chip have been started.

[0082] It should also be noted that in the embodiment of the present disclosure, in the m logic sub-circuits 301, the jth logic sub-circuit can be j It means that Figure 3 The logic subcircuit includes the 0th logic subcircuit (also called "logic subcircuit 0") U0, the 1st logic subcircuit (also called "logic subcircuit 1") U1, ..., the m-1th logic subcircuit (also called "logic subcircuit m-1") U m-1 There are a total of m logic sub-circuits.

[0083] In some embodiments, for the jth logic subcircuit U j For Figure 4 , the jth logic subcircuit U j The jth latch module A may be included j and the jth gated buffer module B j , the jth latch module A j The output end and the jth gate buffer module B j The input terminal of the jth gate buffer module B j The control terminal is used to receive the jth third command sub-signal; wherein:

[0084] The jth latch module A j , used to receive the ground signal and the jth second command sub-signal, and control the jth latch module A according to the jth second command sub-signal j The latch state of generates the jth second intermediate signal;

[0085] The jth gated buffer module B j , used to receive the jth second intermediate signal and the jth third command sub-signal, and control the jth gate buffer module B according to the jth third command sub-signal j is in a conducting state to generate the jth first intermediate signal.

[0086] It should be noted that, in the embodiment of the present disclosure, for each latch module, the latch module may include a clock terminal (CK), an input terminal (D), and an output terminal (Q). The latch module here is different from a D-type flip-flop. The D-type flip-flop is clock edge triggered, and the latch module controls whether to be turned on or not according to the level state. For example, the jth latch module A j For example, only when the jth second command sub-signal is in a high level state, can the jth latch module A be j The ground signal connected to the D terminal is transmitted to the jth latch module A j The Q terminal of the latch module is connected to the Q terminal, so that the Q terminal output is in a low level state. In addition, for each latch module, the initial value of the Q terminal is a high level state.

[0087] It should also be noted that, in the disclosed embodiment, for each gated buffer module, the gated buffer module may include an input terminal, an output terminal and a control terminal. Among them, the control terminal of the gated buffer module is used to receive a control signal. Only when the control signal is in a low level state, the gated buffer module can be turned on to transmit the signal received at the input terminal of the gated buffer module to the output terminal of the gated buffer module.

[0088] It should also be noted that, in the disclosed embodiment, each logic sub-circuit includes a gated buffer module. Since the gated buffer module has one more control signal than an ordinary buffer, it means that data is transmitted only when the control signal is at a low level. Thus, although the first input terminal of the control sub-circuit 302 is connected to the output terminals of m logic sub-circuits 302, so that a plurality of first intermediate signals are simultaneously connected to the input of the control sub-circuit 302, there will be a signal conflict at this time. However, this situation can be avoided by adding a gated buffer module, because for the segments of the storage library that have not been accessed, the corresponding gated buffer module is not turned on at this time, so that these first intermediate signals have no driving capability for the input of the connected control sub-circuit 302.

[0089] It can also be understood that in the embodiment of the present disclosure, since the gated buffer module is affected by its own control terminal, it may include two states, namely, conducting and non-conducting, which may result in different outputs of the gated buffer module. j The two output situations are described in detail.

[0090] In one possible implementation, the jth logic subcircuit U j , used to determine that the jth second intermediate signal is in the second level state and the jth gate buffer module B is in the second level state when the jth second command sub-signal is in the first level state and the jth third command sub-signal is in the second level state j is in a conducting state so that the jth first intermediate signal is in a second level state.

[0091] In another possible implementation, the j-th logic subcircuit U j , used to determine the jth gate buffer module B when the jth second command sub-signal is in the second level state and the jth third command sub-signal is in the first level state j In the off state, the jth gated buffer module B j The output is in high impedance state.

[0092] It should be noted that in the embodiment of the present disclosure, the first level state may be a high level, such as logic 1; the second level state may be a low level, such as logic 0, but this is not specifically limited.

[0093] It should also be noted that, in the embodiment of the present disclosure, the j-th logic sub-circuit U j For example, if the jth second command sub-signal is high, then latch module A j A logic 0 at its input can be transferred to latch module A j The output end of the gate buffer module B, that is, the jth second intermediate signal is at a low level; since the jth third command sub-signal is at a low level, the gate buffer module B j is in the on state, that is, the jth first intermediate signal is at a low level. Or, if the jth second command sub-signal is at a low level, then the latch module A j Failure to transmit a logic 0 at its input to latch module A j The output end of the gate buffer module B, that is, the j-th second intermediate signal maintains the initial state (at this time, it is a high level); since the j-th third command sub-signal is a high level, the gate buffer module B j Not conducting, i.e. gated buffer module B j The output is in high impedance state.

[0094] Exemplarily, assuming that m is 16, taking the 0th segment as an example, for 16 second command sub-signals, the following may be included: Seg0Act <0> 、Seg0Act <1> , …, Seg0Act <15> For the 16 third command sub-signals, they may include: Seg0ActN <0> 、Seg0ActN <1> , …, Seg0ActN <15> If Seg0Act <0> is low level, Seg0ActN <0> is high, which means that the 0th segment of the 0th memory bank has not been accessed, so the latch module A0 and the gated buffer module B0 do not transmit data. <0> There is a pulse, Seg0Act <0> is high, which means that the 0th segment of the 0th memory bank has been accessed. Then the latch module A0 can output logic 0, and the gated buffer module B0 will also be in Seg0ActN <0> The Seg0 Act is turned on under the control of a low level, and transmits a logic 0 to the first input terminal of the control subcircuit 302. In addition, for the 0th segment of the rth memory bank that has not been accessed, Seg0 Act <r>is low level, Seg0ActN <r>is high level, the gated buffer module is not turned on, the output is in high impedance state, and there is no driving capability for the first input terminal of the control subcircuit 302, thereby avoiding the signal conflict caused by 16 gated buffer modules controlling the first input terminal of the subcircuit 302 at the same time. Where r = 0, 1, 2, ..., 15.

[0095] In some embodiments, for the control subcircuit 302, see Figure 5 , the control subcircuit 302 may include a first OR gate 601, a first buffer 602 and an mth gated buffer module 603, wherein:

[0096] The first input end of the first OR gate 601 is respectively connected to the output end of the m logic sub-circuits 301 and the output end of the m-th gated buffer module 603, the second input end of the first OR gate 601 is used to receive a power-on signal, the output end of the first OR gate 601 is respectively connected to the input end of the m-th gated buffer module 603 and the input end of the first buffer 602, the control end of the m-th gated buffer module 603 is used to receive a power-on signal, and the output end of the first buffer 602 is used to output the i-th segment activation signal.

[0097] It should be noted that, in the disclosed embodiment, the power-on signal can be represented by PwrUp. The power-on signal indicates that all power supplies of the target chip have been started, or it can be said that the initialization of the target chip has been completed. For the power-on signal, if the power-on signal is at a high level, it can be said that the target chip is being powered on; if the power-on signal becomes a low level, it means that the target chip has been powered on.

[0098] It should also be noted that, in the disclosed embodiment, before power-on is completed and when power-on is just completed, the i-th segment activation signal is at a high level (i.e., logic 1). Specifically, before power-on is completed, the power-on signal is at a high level, and the power-on signal and the signal at the output end of the m logic sub-circuits 301 are subjected to an OR logic operation through the first OR gate 601, and the i-th segment activation signal finally output is at a high level; since power-on has not been completed at this time, no segment in the storage library will be activated. In addition, when power-on is just completed, since the power-on signal has just flipped to a low level, when the activation operation has not yet occurred, the i-th segment activation signal finally output at this time is also at a high level.

[0099] In short, before power-on is completed and just after power-on is completed, for all the segments in the memory bank (such as segment 0 to segment 7), each segment is not activated at this time, so all segment activation signals ActSegMsk<7:0> are at a high level.

[0100] In some embodiments, Figure 1 Based on the control circuit 10 shown, see Figure 6 , the control circuit 10 may further include a mode register 104 and an output circuit 105, wherein:

[0101] A mode register 104, used to output n initial segment mask signals, wherein the initial segment mask signal is used to indicate whether to perform mask refresh on a certain segment of the m memory banks set by the mode register;

[0102] The output circuit 105 is used to receive n segment activation signals and n initial segment mask signals, and perform OR logic processing on the n segment activation signals and the n initial segment mask signals to generate n target segment mask signals.

[0103] It should be noted that, in the embodiment of the present disclosure, the i-th initial segment mask signal can be represented by MRSeg Msk , the mode register 104 may be the mode register MR23. The i-th initial segment mask signal is specifically used to indicate whether the mode register MR23 is set to shield the refresh operation of the i-th segment, as can be seen in the aforementioned Table 1. If the mode register MR23 is set to shield the i-th segment, then the i-th segment will definitely shield the refresh operation. In this way, the i-th target segment mask signal can be generated by performing OR logic processing based on the i-th segment activation signal and the i-th initial segment mask signal.

[0104] In some embodiments, if the i-th target segment mask signal is in a first level state, then when a refresh operation is performed, the refresh operation of the i-th segment corresponding to at least one storage bank among the m storage banks is masked; if the i-th target segment mask signal is in a second level state, then when a refresh operation is performed, the refresh operation of the i-th segment corresponding to all storage banks among the m storage banks is not masked.

[0105] It should be noted that in the embodiment of the present disclosure, the first level state may be a high level, such as logic 1; the second level state may be a low level, such as logic 0, but this is not specifically limited.

[0106] It should also be noted that, in the embodiment of the present disclosure, for the target segment mask signal, the target segment mask signal is used to indicate whether to shield the refresh operation of a certain segment corresponding to at least one of the m storage banks. Specifically, in the refresh operation phase, if the target segment mask signal is at a high level, then the refresh operation of a certain segment corresponding to at least one of the m storage banks can be shielded; otherwise, if the target segment mask signal is at a low level, then there is no need to shield the refresh operation of a certain segment corresponding to all of the m storage banks, that is, at this time, it is necessary to perform a refresh operation on a certain segment corresponding to all of the m storage banks.

[0107] For example, taking the i-th segment as an example, the i-th target segment mask signal can be represented by SegMsk If SegMsk The signal is high, then the refresh operation of the i-th segment corresponding to at least one of the m memory banks can be shielded; if SegMsk If the signal is at a low level, a refresh operation needs to be performed on the i-th segment corresponding to all the memory banks in the m memory banks.

[0108] In one possible implementation, see Figure 7 , the output circuit 105 may include n second OR gates, wherein:

[0109] The first input end of the pth second OR gate is used to receive the pth segment activation signal, the second input end of the pth second OR gate is used to receive the pth initial segment mask signal; the output end of the pth second OR gate is used to output the pth target segment mask signal.

[0110] In the embodiment of the present disclosure, p is an integer greater than or equal to 0 and less than n.

[0111] It should also be noted that in Figure 7 In the example, the n second OR gates are respectively D0, D1, ..., D n-1 Indicates. For the pth segment, the pth second OR gate D p The first input terminal is used to receive the p-th segment activation signal ActSegMsk , the pth second OR gate D p The second input terminal is used to receive the pth initial segment mask signal MRSegMsk ; The pth second OR gate D p The output terminal is used to output the pth target segment mask signal SegMsk .

[0112] In another possible implementation, see Figure 8 , the output circuit 105 may include n second OR gates and n second buffers, and the input end of the pth second buffer is connected to the output end of the pth second OR gate, wherein:

[0113] a pth second OR gate, used for receiving the pth segment activation signal and the pth initial segment mask signal, performing an OR logic operation on the pth segment activation signal and the pth initial segment mask signal to obtain a pth intermediate segment mask signal;

[0114] The pth second buffer is used to perform drive enhancement processing on the pth intermediate segment mask signal to obtain the pth target segment mask signal.

[0115] In the embodiment of the present disclosure, p is an integer greater than or equal to 0 and less than n.

[0116] It should also be noted that in Figure 8 In the example, the n second OR gates are respectively D0, D1, ..., D n-1 Indicated, the n second buffers are denoted by F0, F1, ..., F n-1 Indicates. For the pth segment, the pth second OR gate D p The first input terminal is used to receive the p-th segment activation signal ActSegMsk , the pth second OR gate D p The second input terminal is used to receive the pth initial segment mask signal MRSeg Msk ; The pth second OR gate D p The output terminal of the pth second buffer F p The input terminal of the pth second buffer F p The output terminal is used to output the pth target segment mask signal SegMsk .

[0117] In simple terms, Figure 7 and Figure 8 Compared with the above, only a second buffer is added at the output end, so that it not only has a delay function, but also can enhance the signal driving ability. Specifically, for the p-th target segment mask signal and the p-th intermediate segment mask signal, the p-th target segment mask signal has a stronger driving ability than the p-th intermediate segment mask signal. In addition, it should be noted that if the second buffer is adjusted to a gated buffer (i.e., an additional control signal is added), then the control signal can also play a role in controlling transmission.

[0118] This embodiment provides a control circuit, in which a command decoding circuit is used to perform command decoding processing on the first pulse of a chip select signal and a command address signal according to a first clock signal to obtain a first command signal; an address decoding circuit is used to perform row address decoding processing on the second pulse of a chip select signal and a command address signal according to the first command signal and the first clock signal to obtain n second command signals and n third command signals; a logic processing circuit is used to perform logic processing on the n second command signals and the n third command signals to obtain n segment activation signals. There is a corresponding relationship between the n segments of each memory bank and the n segment activation signals, and the segment activation signal is used to indicate whether at least one segment corresponding to the memory bank has been activated in the m memory banks. In this way, if it can be determined based on the segment activation signal that the segments corresponding to some storage libraries have been activated, which means that the segments corresponding to these storage libraries have been accessed, then the segments need to be periodically refreshed during the refresh operation phase; otherwise, if it can be determined based on the segment activation signal that the segments corresponding to some storage libraries have not been activated, which means that the segments corresponding to these storage libraries have not been accessed, then refresh shielding can be performed on the segments during the refresh operation phase; in this way, not only the data integrity in the storage library can be maintained, but also the power consumption can be reduced to achieve the purpose of power saving.

[0119] In another embodiment of the present disclosure, see Fig. 9 , which shows a schematic diagram of the architecture of a memory provided by an embodiment of the present disclosure. Fig. 9 As shown, the memory 1000 may include a control circuit 10 and a storage array 1001, and the storage array 1001 may include multiple storage banks, specifically Bank0, Bank1, Bank2, ..., Bank15. Among them, the control circuit 10 is used to output the target segment mask signal SegMsk<7:0>, and then the target segment mask signal SegMsk<7:0> is sent to each storage bank in the storage array 1001 to control the refresh operation of each storage bank. Exemplarily, taking Table 1 as an example, if the segment mask signals corresponding to segment 2 and segment 7 are both 1, then the refresh operations of segment 2 and segment 7 in these storage banks are all masked.

[0120] Further, in the disclosed embodiment, the control circuit 10 here can be a power-saving refresh operation control circuit. Based on the description of the aforementioned embodiment, the control circuit 10 at least includes a logic processing circuit, a mode register, and an output circuit. Among them, the logic processing circuit is used to output the segment activation signal ActSeg Msk<7:0>, the mode register is used to output the initial segment mask signal MRSegMsk<7:0>, and the output circuit is used to perform OR logic processing on the segment activation signal ActSegMsk<7:0> and the initial segment mask signal MRSegMsk<7:0>, and finally generate a target segment mask signal SegMsk<7:0>, and then the target segment mask signal SegMsk<7:0> can be sent to each storage bank in the storage array 1001.

[0121] In a specific embodiment, assuming that the value of m is 16 and the value of n is 8, based on the refinement and integration of the above embodiments, Fig.10 FIG. 1 is a schematic diagram of a local detailed structure of a control circuit 10 provided in an embodiment of the present disclosure. Fig.10 As shown, a command decoding circuit 101 and an address decoding circuit 102 may be included. The input of the command decoding circuit 101 includes a command address signal CA<6:0>, a chip select signal CS and a first clock signal Clk, and the output of the command decoding circuit 101 is a first command signal ActBnk1; here, in the command decoding circuit 101, the first pulse of the chip select signal CS and the command address signal CA<6:0> are subjected to command decoding processing according to the first clock signal Clk, and the first command signal ActBnk1 may be obtained, and the first command signal ActBnk1 is used to indicate whether to activate the 16 memory banks in the memory array; the input of the address decoding circuit 102 may include a command address signal CA<6:0>, a chip select signal CS, a first command signal ActBnk1 and a first clock signal Clk In the address decoding circuit 102, the second pulse of the chip select signal CS and the command address signal CA<6:0> are processed by row address decoding according to the first command signal ActBnk1 and the first clock signal Clk, and 7 second command signals and 7 third command signals can be output; wherein the second command signal is used to indicate whether to activate a certain segment of the 16 memory banks, and the third command signal is an inverted signal of the second command signal; specifically, the second command signal Seg0Act<15:0>, Seg1Act<15:0>, ..., Seg7Act<15:0>, and the third command signal Seg0ActN<15:0>, Seg1ActN<15:0>, ..., Seg7ActN<15:0>. Exemplarily, taking Seg0Act<15:0> as an example, this signal indicates whether to activate the 0th segment of the 16 memory banks.

[0122] Further, taking the 0th segment as an example, for the logic processing circuit in the control circuit 10, Fig.11 FIG. 1 is a schematic diagram of a local detailed structure of a control circuit 10. Fig.11 As shown, 16 logic sub-circuits 301 and control sub-circuits 302 may be included, wherein each logic sub-circuit may be composed of a latch module and a gate buffer module, and the control sub-circuit 302 may be composed of a first OR gate 601, a first buffer 602 and an mth gate buffer module 603. For specific connection relationships, see Fig.11 .

[0123] In the disclosed embodiment, for the power-saving control circuit 10 in the refresh operation mode, on the one hand, according to the technical standards formulated by the Joint Electron Device Engineering Council (JEDEC), the segmentation can be performed according to different storage densities, and the access status of each segment of each storage memory bank can be obtained through the command decoding circuit 101 and the address decoding circuit 102. On the other hand, the SegxAct<15:0> / SegxActN<15:0> generated by the ActBnk1 command will be sent to the logic processing circuit in the control circuit 10 to generate a segment activation signal ActSegMsk<7:0>, where x=0,1,2,…,7. Among them, in the xth segment activation signal ActSegMsk <x>When it is low, it means that the xth segment of the 16 memory banks has been accessed. Then the refresh operation cannot be blocked during the refresh operation. At this time, the refresh operation needs to be performed on the xth segment of all the memory banks in the 16 memory banks. The xth segment activation signal ActSegMsk <x>When it is at a high level, it means that the xth segment corresponding to at least one memory bank has not been accessed. Therefore, when performing a refresh operation, the refresh operation of the xth segment of at least one memory bank among the 16 memory banks can be shielded, thereby achieving the purpose of power saving.

[0124] Based on the control circuit 10 of the aforementioned embodiment, Fig.12 A signal timing diagram provided by an embodiment of the present disclosure. Fig.12 As shown, Clk is the first clock signal, CS is the chip select signal, CA<6:0> is the command address signal, and PwrUp is the power-on signal. Here, taking the yth memory bank and the 0th segment as an example, based on the first pulse of the chip select signal CS, the first pulse of the chip select signal CS and the command address signal CA<6:0> can be command-decoded according to the first clock signal Clk to obtain the first command signal ActBnk1 to indicate whether the yth memory bank in the memory array is to be activated; then based on the second pulse of the chip select signal CS, the second pulse of the chip select signal CS and the command address signal CA<6:0> can be row-decoded according to the first command signal ActBnk1 and the first clock signal Clk to obtain the second command sub-signal Seg0Act. <y>and the third command sub-signal Seg0ActN <y>; Among them, the second command sub-signal Seg0Act <y>The third command sub-signal Seg0ActN is used to indicate whether to activate the 0th segment of the yth storage bank. <y>The second command sub-signal Seg0Act <y>Inverted signal; thus, after obtaining the second command sub-signal Seg0Act<15:0> and the third command sub-signal Seg0ActN<15:0> of all memory banks, the second command sub-signal Seg0Act<15:0> and the third command sub-signal Seg0ActN<15:0> are logically processed by the latch module and the gate buffer module to obtain the first intermediate signal; then, the segmented activation signal ActSegMsk is obtained by performing logical processing on the power-on signal PwrUp and the first intermediate signal. <0> , wherein the segment activation signal is used to indicate whether the 0th segment corresponding to the yth storage bank has been activated.

[0125] Specifically, in Fig.12 If the second command sub-signal Seg0Act <y>From low level to high level, the third command sub-signal Seg0ActN <y>Then it changes from high level to low level, at this time, the 0th segment of the yth storage bank has been accessed, that is, the 0th segment of the yth storage bank is activated. In this way, for the 0th segment of the 16 storage banks, if the second command sub-signal Seg0Act <y>The high level pulse means that the 0th segment of the yth memory bank has been accessed. Although the first input terminal of the control sub-circuit 302 is connected to the output terminals of the 16 gated buffer modules, only when the second command sub-signal Seg0Act <y>When a high-level pulse appears, the latch module corresponding to the yth storage memory outputs a low-level signal. At this time, the gated buffer module connected to the latch module can be turned on to transmit the low-level signal received at the input end of the gated buffer module to the output end of the gated buffer module. For the other segments of the storage memory that have not been visited, the corresponding gated buffer modules are not turned on at this time. Therefore, the first intermediate signal received at the first input end of the control subcircuit 302 is a low-level signal. According to the power-on signal PwrUp and the first intermediate signal, an OR logic process is performed. Since the power-on signal PwrUp and the first intermediate signal are both low-level, the segment activation signal ActSegMsk is finally obtained. <0> In addition, the segment activation signal ActSeg Msk <0> The falling edge of the second command signal Seg0Act <y>There is a slight delay time between the rising edges of , which is generated by logic devices such as the latch module, the gate buffer module, the first OR gate and the first buffer in the segment processing sub-circuit.

[0126] Thus, in the embodiment of the present disclosure, Fig. 9 For the memory 1000 shown in FIG. 1 , before power-on is completed and immediately after power-on is completed, the state of the segment activation signal ActSegMsk<7:0> is high. When the i-th segment of the corresponding memory bank is accessed, the corresponding segment activation signal ActSegMsk<7:0> is high. It will become a low level, and then the segment activation signal ActSegMsk<7:0> is logically ORed with the initial segment mask signal MRSegMsk<7:0> set by the mode register to obtain the final target segment mask signal SegMsk<7:0>; then the target segment mask signal SegMsk<7:0> is sent to the storage array 1001 for controlling the shield refresh operation, thereby reducing power consumption and achieving the purpose of power saving.

[0127] In another embodiment of the present disclosure, see Fig.13 , which shows a schematic diagram of the composition structure of a memory provided by an embodiment of the present disclosure. Fig.13 As shown, the memory 1000 at least includes the control circuit 10 as described in the above embodiment.

[0128] In some embodiments, the memory 1000 may include a DRAM chip. The DRAM chip may not only comply with memory specifications such as DDR, DDR2, DDR3, DDR4, DDR5, and DDR6, but may also comply with memory specifications such as LPDDR, LPDDR2, LPDDR3, LPDDR4, LPDDR5, and LPDDR6, which are not specifically limited here.

[0129] In the embodiment of the present disclosure, for the memory 1000, since the segment activation signal is used to indicate whether there is at least one segment corresponding to a storage library in multiple storage libraries that has been activated. In this way, if it can be determined according to the segment activation signal that the segments corresponding to some storage libraries have been activated, it means that the segments corresponding to these storage libraries have been accessed, then it is necessary to perform periodic refresh on the segments during the refresh operation phase; otherwise, if it can be determined according to the segment activation signal that the segments corresponding to some storage libraries have not been activated, it means that the segments corresponding to these storage libraries have not been accessed, then refresh shielding can be performed on the segments during the refresh operation phase; in this way, not only the data integrity in the storage library can be maintained, but also the power consumption can be reduced, so as to achieve the purpose of power saving, and ultimately the memory performance can be improved.

[0130] The above are only preferred embodiments of the present disclosure and are not intended to limit the protection scope of the present disclosure.

[0131] It should be noted that in the present disclosure, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0132] The serial numbers of the above-mentioned embodiments of the present disclosure are only for description and do not represent the advantages or disadvantages of the embodiments.

[0133] The methods disclosed in several method embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0134] The features disclosed in several product embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new product embodiments.

[0135] The features disclosed in several method or device embodiments provided in the present disclosure may be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0136] The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims. < / y> < / y> < / y> < / y> < / y> < / y> < / y> < / y> < / y> < / y> < / x> < / x> < / r> < / r> < / l>

Claims

1. A control circuit, characterized in that: The control circuit includes a command decoding circuit, an address decoding circuit and a logic processing circuit, wherein the command decoding circuit is connected to the address decoding circuit, and the address decoding circuit is also connected to the logic processing circuit, wherein: The command decoding circuit is used to receive a command address signal, a chip select signal and a first clock signal, and perform command decoding processing on the first pulse of the chip select signal and the command address signal according to the first clock signal to obtain a first command signal; wherein the first command signal is used to indicate whether to activate m memory banks in the memory array, and m is a positive integer; The address decoding circuit is used to receive the first command signal, the first clock signal, the chip select signal and the command address signal, and perform row address decoding processing on the second pulse of the chip select signal and the command address signal according to the first command signal and the first clock signal to obtain n second command signals; wherein the second command signal is used to indicate whether to activate a certain segment of the m memory banks, and n is a positive integer; The logic processing circuit is used to receive the n second command signals, perform logic processing according to the n second command signals, and obtain n segment activation signals, wherein the segment activation signals are used to indicate whether a segment corresponding to at least one storage bank in the m storage banks has been activated; The storage array includes m storage bins, each of which includes n segments, and there is a corresponding relationship between the n segments and the n segment activation signals.

2. The control circuit according to claim 1, characterized in that: The first command signal includes m first command sub-signals, and the m first command sub-signals have a corresponding relationship with the m storage bins, wherein: If the first command sub-signal is in a first level state, determining that the storage bank corresponding to the first command sub-signal performs an activation operation; If the first command sub-signal is in the second level state, it is determined that the storage memory corresponding to the first command sub-signal does not perform an activation operation.

3. The control circuit according to claim 1, characterized in that: The address decoding circuit is further used to perform row address decoding processing on the second pulse of the chip selection signal and the command address signal according to the first command signal and the first clock signal to obtain n third command signals; wherein the second command signal and the third command signal are in anti-phase relationship with each other; The logic processing circuit is used to receive the n second command signals and the n third command signals, and perform logic processing according to the n second command signals and the n third command signals to obtain n segment activation signals.

4. The control circuit according to claim 3, characterized in that: The logic processing circuit includes n segment processing sub-circuits, wherein: an i-th segment processing subcircuit, configured to receive an i-th second command signal and an i-th third command signal, and perform logic processing according to the i-th second command signal and the i-th third command signal to obtain an i-th segment activation signal; The i-th segment activation signal is used to indicate whether the i-th segment corresponding to at least one storage bank in the m storage banks has been activated, and i is an integer greater than or equal to 0 and less than n.

5. The control circuit according to claim 4, characterized in that: The second command signal includes m second command sub-signals; The third command signal includes m third command sub-signals; Among them, the second command sub-signal and the third command sub-signal are in anti-phase relationship with each other, and the kth second command sub-signal in the second command signal and the kth third command sub-signal in the third command signal both have a corresponding relationship with the kth storage memory, and k is an integer greater than or equal to 0 and less than m.

6. The control circuit according to claim 5, characterized in that: The i-th segment processing subcircuit comprises m logic subcircuits and control subcircuits, wherein: The jth logic sub-circuit is used to receive a ground signal, the jth second command sub-signal and the jth third command sub-signal, and the output end of the jth logic sub-circuit is used to output the jth first intermediate signal, where j is an integer greater than or equal to 0 and less than m; The first input terminal of the control subcircuit is connected to the output terminals of the m logic subcircuits, the second input terminal of the control subcircuit is used to receive a power-on signal, and the output terminal of the control subcircuit is used to output the i-th segment activation signal; The chip select signal indicates that the target chip is selected, and the power-on signal indicates that all power supplies of the target chip have been started.

7. The control circuit according to claim 6, characterized in that: The j-th logic sub-circuit comprises a j-th latch module and a j-th gate buffer module, the output end of the j-th latch module is connected to the input end of the j-th gate buffer module, and the control end of the j-th gate buffer module is used to receive the j-th third command sub-signal; wherein: the jth latch module is used to receive the ground signal and the jth second command sub-signal, and control the latch state of the jth latch module according to the jth second command sub-signal to generate a jth second intermediate signal; The jth gated buffer module is used to receive the jth second intermediate signal and the jth third command sub-signal, and control the conduction state of the jth gated buffer module according to the jth third command sub-signal to generate the jth first intermediate signal.

8. The control circuit according to claim 7, characterized in that: The jth logic sub-circuit is used to determine that the jth second intermediate signal is in the second level state and the jth gated buffer module is in the on state when the jth second command sub-signal is in the first level state and the jth third command sub-signal is in the second level state, so that the jth first intermediate signal is in the second level state.

9. The control circuit according to claim 7, characterized in that: The jth logic sub-circuit is used to determine that the jth gated buffer module is in the off state when the jth second command sub-signal is in the second level state and the jth third command sub-signal is in the first level state, so that the output of the jth gated buffer module is in a high impedance state.

10. The control circuit according to claim 7, characterized in that: The control subcircuit comprises a first OR gate, a first buffer and the mth gated buffer module, wherein: The first input end of the first OR gate is respectively connected to the output ends of the m logic sub-circuits and the output end of the m-th gated buffer module, the second input end of the first OR gate is used to receive the power-on signal, the output end of the first OR gate is respectively connected to the input end of the m-th gated buffer module and the input end of the first buffer, the control end of the m-th gated buffer module is used to receive the power-on signal, and the output end of the first buffer is used to output the i-th segmented activation signal.

11. The control circuit according to claim 1, characterized in that: The control circuit also includes a mode register and an output circuit, wherein: The mode register is used to output n initial segment mask signals, wherein the initial segment mask signal is used to indicate whether to perform mask refresh on a certain segment of the m memory banks set by the mode register; The output circuit is used to receive the n segment activation signals and the n initial segment mask signals, and perform OR logic processing on the n segment activation signals and the n initial segment mask signals to generate n target segment mask signals; wherein: If the i-th target segment mask signal is in the first level state, then when performing a refresh operation, the refresh operation of the i-th segment corresponding to at least one storage bank in the m storage banks is shielded; If the i-th target segment mask signal is in the second level state, then when a refresh operation is performed, the refresh operation of the i-th segment corresponding to all the storage banks in the m storage banks is not masked.

12. The control circuit according to claim 2, 8, 9 or 11, characterized in that: The first level state is a high level, and the second level state is a low level.

13. The control circuit according to claim 11, characterized in that: The output circuit includes n second OR gates, wherein: The first input end of the pth second OR gate is used to receive the pth segment activation signal, and the second input end of the pth second OR gate is used to receive the pth initial segment mask signal; the output end of the pth second OR gate is used to output the pth target segment mask signal; Here, p is an integer greater than or equal to 0 and less than n.

14. The control circuit according to claim 11, characterized in that: The output circuit includes n second OR gates and n second buffers, and the input end of the pth second buffer is connected to the output end of the pth second OR gate, wherein: a pth second OR gate, used for receiving the pth segment activation signal and the pth initial segment mask signal, performing an OR logic operation on the pth segment activation signal and the pth initial segment mask signal, to obtain a pth intermediate segment mask signal; The p-th second buffer is used to perform drive enhancement processing on the p-th intermediate segment mask signal to obtain the p-th target segment mask signal; Here, p is an integer greater than 0 and less than or equal to n.

15. A memory, characterized in that: The memory includes at least the control circuit according to any one of claims 1 to 14.

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