Page buffer, programming method, memory device and system

Abstract

The embodiment of the invention discloses a page buffer, a programming method, a memory device and a system, the page buffer is arranged corresponding to a bit line of a memory cell array of the memory device, and the page buffer comprises a first charging and discharging module, a second charging and discharging module and a memory cell array, the memory is configured to store first bit line forcing information and provide a first bit line forcing voltage to the bit line according to the first bit line forcing information; the second charging and discharging module is coupled with the bit line and is configured to be capable of storing second bit line forcing information and providing a second bit line forcing voltage different from the first bit line forcing voltage to the bit line according to the second bit line forcing information; wherein the first bit line forced voltage and the second bit line forced voltage are both larger than a normal programming bit line voltage and smaller than a forbidden programming bit line voltage.

Description

[0001] This application is a divisional application for a patent with an application date of March 14, 2022, application number 2022102484812, and invention name of page buffer, programming method, memory device and system. Technical Field

[0002] The embodiments of the present disclosure relate to semiconductor technology, and relate to but are not limited to a page buffer, a programming method, a memory device, and a system. Background Art

[0003] A nonvolatile memory cell, such as a NAND flash memory cell, is capable of program / erase operations, and performs the program and erase operations through a threshold voltage that varies when electrons are transferred by a strong electric field applied to a thin oxide layer.

[0004] When performing a programming operation on a non-volatile memory device, the threshold voltages of a plurality of memory cells may be programmed to different values, for example, the threshold voltages are distributed with a certain degree of variation. In the case where the threshold voltage distribution is wide, the read margin becomes narrow, thereby deteriorating the performance of the non-volatile memory device. In particular, in the case where there are threshold distributions corresponding to three or more different data states, such as in a multi-level cell programming method, it is more preferred that the threshold voltage distribution corresponding to each data state is limited to a narrow range. Summary of the invention

[0005] In view of this, embodiments of the present disclosure provide a page buffer, a programming method, a memory device, and a system.

[0006] In a first aspect, an embodiment of the present disclosure provides a page buffer, wherein the page buffer is arranged corresponding to a bit line of a memory cell array of a memory device, and the page buffer comprises:

[0007] A first charge-discharge module is coupled to the bit line and configured to store first bit line force information and provide a first bit line force voltage to the bit line according to the first bit line force information;

[0008] a second charge and discharge module coupled to the bit line and configured to store second bit line forcing information and provide a second bit line forcing voltage different from the first bit line forcing voltage to the bit line according to the second bit line forcing information;

[0009] Wherein, the first bit line forced voltage and the second bit line forced voltage are both greater than a normal programming bit line voltage and less than a programming inhibiting bit line voltage.

[0010] In some embodiments, the programming inhibit bit line voltage is applied to the bit line corresponding to the programming inhibited memory cell to inhibit programming of the memory cell;

[0011] The normal programming bit line voltage is applied to the bit line corresponding to the memory cell to be programmed, so as to allow the memory cell to be first programmed;

[0012] The first bit line forced voltage is applied to the bit line corresponding to the memory cell to be programmed to allow the memory cell to be second programmed;

[0013] The second bit line forced voltage is applied to the bit line corresponding to the memory cell to be programmed, so as to allow the memory cell to be third programmed;

[0014] The first programming degree is higher than the second programming degree, and the second programming degree is higher than the third programming degree.

[0015] In some embodiments, the first charge and discharge module includes: a first charge and discharge circuit, a first latch, and a first bit line voltage setting component;

[0016] The first charge and discharge circuit is connected to the power supply voltage and connected to the second sensing node of the page buffer via the first bit line voltage setting component and further connected to the bit line; the first charge and discharge circuit is configured to provide the power supply voltage to the first bit line voltage setting component;

[0017] The first latch is connected to the first charge and discharge circuit and the first sensing node connected to the page buffer so as to be connected to the bit line; the first latch is configured to store the first bit line forcing information;

[0018] The first bit line voltage setting component connects the first charge and discharge circuit and the second sensing node so as to connect the bit line; the first bit line voltage setting component is configured to: apply the first bit line forcing voltage to the second sensing node connected to the bit line based on the power supply voltage according to the first bit line forcing information stored in the first latch.

[0019] In some embodiments, the first charge and discharge circuit further includes:

[0020] A first charging switch is connected to a power supply and the first bit line voltage setting component; a control electrode of the first charging switch is connected to the first latch; and the first charging switch is configured to provide a power supply voltage to the first bit line voltage setting component according to a signal output by the first latch.

[0021] In some embodiments, the first latch comprises:

[0022] a first data latch unit configured to store corresponding program verification information according to a program verification result, or configured to store the first bit line forcing information;

[0023] The first data setting unit is connected to the first data latch unit, and the first data setting unit is configured to output the program verification information or the first bit line forcing information to be stored to the first data latch unit.

[0024] In some embodiments, the second charge and discharge module includes: a second charge and discharge circuit, a second latch, and a second bit line voltage setting component;

[0025] The second charge and discharge circuit is connected to the power supply voltage and connected to the second bit line voltage setting component via the first sensing node of the page buffer so as to be connected to the bit line, and the second charge and discharge circuit is configured to provide the power supply voltage to the second bit line voltage setting component;

[0026] the second latch is connected to the second charge and discharge circuit and to the first sensing node so as to be connected to the bit line, the second latch is configured to store the second bit line forcing information;

[0027] The second bit line voltage setting component is connected to the second charge and discharge circuit and the second sensing node connected to the page buffer so as to be connected to the bit line. The second bit line voltage setting component is configured to apply the second bit line forcing voltage to the second sensing node connected to the bit line based on the power supply voltage according to the second bit line forcing information stored in the second latch.

[0028] In some embodiments, the second charge and discharge circuit further includes:

[0029] A second charging switch connects the power supply and the second bit line voltage setting component; a control electrode of the second charging switch is connected to the second latch; and the second charging switch is configured to provide a power supply voltage to the first bit line voltage setting component according to a signal output by the second latch.

[0030] In some embodiments, the second latch comprises:

[0031] a second data latch unit configured to store the second bit line forcing information;

[0032] The second data setting unit is connected to the second data latch unit; the second data setting unit is configured to output the second bit line forcing information to be stored to the second data latch unit.

[0033] In some embodiments, the first charge and discharge module is further configured to store programming verification information; when the programming verification information is in a state that programming is allowed, the first charge and discharge module is configured to provide a normal programming bit line voltage to the bit line;

[0034] The page buffer further includes:

[0035] A dynamic latch is coupled to the first sensing node of the page buffer; the dynamic latch is configured to store the first bit line forcing information and is configured to transmit the first bit line forcing information to the first charge and discharge module after the first charge and discharge module provides the normal programming bit line voltage to the bit line.

[0036] In some embodiments, the dynamic latch comprises:

[0037] a third data latch unit configured to store the first bit line forcing information;

[0038] A third data setting unit is connected to the third data latch unit; the third data setting unit is configured to output the first bit line forcing information to be stored to the third data latch unit.

[0039] In some embodiments, when the program verification information indicates that program is prohibited, the first charge and discharge module is configured to provide a power supply voltage for prohibiting program to the bit line.

[0040] In a second aspect, an embodiment of the present disclosure further provides a method for programming a memory, wherein the memory includes a page buffer, the page buffer is arranged corresponding to a bit line of a memory array of a memory device, and the page buffer includes a first charge-discharge module and a second charge-discharge module coupled to the bit line; the programming method includes:

[0041] Providing a first bit line forced voltage to the bit line corresponding to the memory cell to be programmed according to the first bit line forced information stored in the first charge and discharge module;

[0042] Providing a second bit line forced voltage to a bit line corresponding to a memory cell to be programmed according to the second bit line forced information stored in the second charge and discharge module;

[0043] Wherein, the first bit line forced voltage and the second bit line forced voltage are both greater than the normal programming bit line voltage and less than the programming inhibiting bit line voltage;

[0044] The memory cells to be programmed are programmed to different degrees based on the first bit line forcing voltage and the second bit line forcing voltage.

[0045] In some embodiments, providing a first bit line forced voltage to the bit line corresponding to the memory cell to be programmed according to the first bit line forced information stored in the first charge and discharge module includes:

[0046] After verifying the first bit line sensing voltage of the memory cell to be programmed, storing the first bit line forcing information by using the first latch in the first charge and discharge module;

[0047] Using the first charge and discharge circuit in the first charge and discharge module to provide a power supply voltage to the first line voltage setting component in the first charge and discharge module;

[0048] The first bit line voltage setting unit is used to apply a first bit line forcing voltage to a second sensing node connected to the bit line corresponding to the memory cell to be programmed based on the power supply voltage according to the first bit line forcing information.

[0049] In some embodiments, using the first charge and discharge circuit in the first charge and discharge module to provide the first line voltage setting component with a power supply voltage includes:

[0050] A power supply voltage is provided to the first bit line voltage setting unit through a first charging switch in the first charging and discharging circuit according to a signal output by the first latch.

[0051] In some embodiments, providing a second bit line forcing voltage to a bit line corresponding to a memory cell to be programmed according to the second bit line forcing information stored in the second charging and discharging module includes:

[0052] After verifying the second bit line sensing voltage of the memory cell to be programmed, storing the second bit line forcing information by using a second latch;

[0053] Using a second charge and discharge circuit in the second charge and discharge module to provide a power supply voltage to a second bit line voltage setting component in the second charge and discharge module;

[0054] The second bit line voltage setting unit is used to apply a second bit line forcing voltage to a second sensing node connected to the bit line corresponding to the memory cell to be programmed based on the power supply voltage according to the second bit line forcing information.

[0055] In some embodiments, the using the second charge and discharge circuit in the second charge and discharge module to provide the second bit line voltage setting component with a power supply voltage includes:

[0056] A power supply voltage is provided to the second bit line voltage setting unit through a second charging switch in the second charging and discharging circuit according to a signal output by the second latch.

[0057] In some embodiments, the method further comprises:

[0058] Using a first charge and discharge module to store programming verification information, and providing a normal programming bit line voltage to the bit line when the programming verification information indicates that the first programming is allowed;

[0059] After the first charge and discharge module provides the normal programming bit line voltage to the bit line, the dynamic latch in the page buffer transmits the first bit line forcing information to the first charge and discharge module.

[0060] In some embodiments, the method further comprises:

[0061] In a state where the program verification information indicates program inhibition, a power supply voltage for program inhibition is supplied to the bit line.

[0062] In a third aspect, an embodiment of the present disclosure further provides a memory device, the memory device comprising:

[0063] a memory cell array having a plurality of memory cell strings and a plurality of bit lines connected to the plurality of memory cell strings; and

[0064] A peripheral circuit coupled to the memory cell array through the bit lines and used for the memory cell array to operate;

[0065] Wherein, a plurality of page buffers as described in any of the above embodiments are arranged in the peripheral circuit,

[0066] The page buffer is connected to a corresponding bit line via a sensing node, and is connected to the memory cell string via the bit line.

[0067] In a fourth aspect, an embodiment of the present disclosure provides a memory system, the memory system comprising:

[0068] A memory device as described in any of the above embodiments; and

[0069] A memory controller is coupled to the memory device and configured to control the memory device.

[0070] The disclosed embodiment sets up multiple charging and discharging modules in the page buffer circuit to provide different bit line forced voltages during the programming process. This allows flexible configuration of coarse programming and various degrees of fine programming, thereby making the threshold voltage distribution of the storage unit narrower and the read margin wider after programming, thereby improving the stability and read and write accuracy of the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0071] In the accompanying drawings, like reference numerals may describe similar components in different views. Like reference numerals with different letter suffixes may represent different examples of similar components. The accompanying drawings generally illustrate various embodiments discussed herein by way of example and not limitation.

[0072] Figure 1AA schematic diagram of the structure of an exemplary system provided for an embodiment of the present disclosure;

[0073] Figure 1B A schematic diagram of the structure of a memory card provided by an embodiment of the present disclosure;

[0074] Figure 1C A schematic diagram of the structure of a solid state disk (SSD) provided in accordance with an embodiment of the present disclosure;

[0075] Figure 1D and Figure 1E A schematic diagram of the structure of a memory device including a memory cell array and a peripheral circuit provided in one embodiment of the present disclosure;

[0076] Figure 1F A schematic structural diagram of a memory device including a page buffer provided in an embodiment of the present disclosure;

[0077] Figure 2 A schematic diagram of a page buffer provided in accordance with an embodiment of the present disclosure;

[0078] Figure 3 A schematic diagram of a charging and discharging module of a page buffer provided in an embodiment of the present disclosure;

[0079] Figure 4 A schematic diagram of a latch of a page buffer provided in yet another embodiment of the present disclosure;

[0080] Figure 5 A flowchart of a programming method for a page buffer provided in an embodiment of the present disclosure;

[0081] Figure 6 A schematic diagram of a memory device provided in accordance with an embodiment of the present disclosure;

[0082] Figure 7 A schematic diagram of a memory system provided in accordance with an embodiment of the present disclosure;

[0083] Figure 8 is a threshold voltage distribution diagram of an MLC flash memory in different threshold states;

[0084] Fig. 9 A threshold voltage distribution diagram provided for an embodiment of the present disclosure;

[0085] Fig.10 A schematic diagram of a page buffer provided in accordance with an embodiment of the present disclosure;

[0086] Fig.11 A schematic diagram of a page buffer provided in accordance with an embodiment of the present disclosure;

[0087] Fig.12A waveform diagram of various control signals applied during a bit line voltage setting operation of a nonvolatile memory device according to an embodiment;

[0088] Fig.13 FIG. 1 is a waveform diagram of various control signals applied during a bit line voltage setting operation of a nonvolatile memory device according to another embodiment. DETAILED DESCRIPTION

[0089] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present invention are shown in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present invention more thorough and comprehensive.

[0090] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0091] like Figure 1A As shown, an exemplary system 10 is shown in an embodiment of the present disclosure, and the exemplary system 10 may include a host 20 and a memory system 30. The exemplary system 10 may include, but is not limited to, a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory 34 therein; the host 20 may be a processor (e.g., a central processing unit (CPU)) or a system on chip (SoC) (e.g., an application processor (AP)) of the electronic device.

[0092] In an embodiment of the present disclosure, the host 20 may be configured to send data to or receive data from the memory system 30. Here, the memory system 30 may include a memory controller 32 and one or more memory devices 34. The memory device 34 may include, but is not limited to, NAND Flash Memory, Vertical NAND Flash Memory, NOR Flash Memory, Dynamic Random Access Memory (DRAM), Ferroelectric Random Access Memory (FRAM), Magnetic Random Access Memory (MRAM), Phase Change Random Access Memory (PCRAM), Resistive Random Access Memory (RRAM), Nano Random Access Memory (NRAM), etc.

[0093] In one embodiment of the present disclosure, a memory controller 32 may be coupled to a memory device 34 and a host 20 and used to control the memory device 34. Exemplarily, the memory controller 32 may be designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 32 may also be designed to operate in a high duty cycle environment, such as an SSD or an embedded multimedia card (eMMC), and the SSD or eMMC may be used as a data storage device for mobile devices such as smart phones, tablet computers, laptop computers, and enterprise storage arrays. Further, the memory controller 32 may manage data in the memory device 34 and communicate with the host. The storage controller 32 may be configured to control operations such as reading, erasing, and programming of the memory device 34; it may also be configured to manage various functions regarding data stored or to be stored in the memory device 34, including but not limited to bad block management, garbage collection, logical to physical address conversion, wear leveling, etc.; it may also be configured to process error correction codes (ECC) regarding data read from or written to the memory device 34. In addition, the storage controller 32 may also perform any other suitable functions, such as formatting the memory device 34, or communicating with an external device (e.g., Figure 1A The storage controller 32 may communicate with the external host 20. Exemplarily, the storage controller 32 may communicate with the external host through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a PCI Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer mini interface (SCSI) protocol, an enhanced minidisk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, etc.

[0094] In an embodiment of the present disclosure, the storage controller 32 and one or more memory devices 34 may be integrated into various types of storage devices, for example, included in the same package (for example, a universal flash storage (UFS) package or an eMMC package). That is, the memory system 30 may be implemented and packaged into different types of terminal electronic products. Figure 1BAs shown, the storage controller 32 and the single memory device 34 may be integrated together to form a memory card 40. The memory card 40 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 40 may also include a computer that connects the memory card 40 to a host (e.g., Figure 1A The memory card connector 42 is coupled to the host 20 in the embodiment. Figure 1C In another embodiment shown in FIG. 5 , the storage controller 32 and the plurality of memory devices 34 may be integrated together to form an SSD 50. The SSD 50 may also include a processor that connects the SSD 50 to a host (e.g., Figure 1A In some embodiments, the storage capacity and / or operating speed of the SSD 50 is greater than the storage capacity and / or operating speed of the memory card 40.

[0095] It should be noted that the memory device involved in an embodiment of the present disclosure may be a semiconductor memory device, which is a solid-state electronic device for storing data information manufactured using semiconductor integrated circuit technology. Figure 1D FIG. 6 is a schematic diagram of an optional memory device 60 in an embodiment of the present disclosure. The memory device 60 may be Figures 1A to 1C The memory device 34 in FIG. Figure 1D As shown, the memory device 60 may include a memory cell array 62 and a peripheral circuit 64 coupled to the memory cell array 62, etc. Here, the memory cell array may be a NAND flash memory cell array, wherein the memory cells are arranged in the form of an array of NAND memory strings 66, and each NAND memory string 66 extends vertically above the substrate. In some embodiments, each NAND memory string 66 may include a plurality of memory cells coupled in series and stacked vertically. Wherein, each memory cell is to maintain a continuous analog value, such as a voltage or charge, which depends on the number of electrons captured in the memory cell area. In addition, each memory cell in the above-mentioned memory cell array 62 may be a floating gate type memory cell including a floating gate transistor, or a charge capture type memory cell including a charge capture transistor.

[0096] In one embodiment of the present disclosure, the above-mentioned memory cell may be a single-level memory cell (Single Level Cell, SLC) having two possible storage states and thus can store one bit of data. For example, the first storage state "0" may correspond to a first threshold voltage range, and the second storage state "1" may correspond to a second threshold voltage range. In other embodiments, each memory cell may be a multi-level memory cell (Multi Level Cell, MLC) capable of storing more than a single bit of data in more than four storage states. For example, the MLC may store two bits per cell, three bits per cell (also known as a triple level cell (Triple Level Cell, TLC)), or four bits per cell (also known as a quad level cell (Quad Level Cell, QLC)). Each MLC may be programmed to take a range of possible nominal storage values. Exemplarily, if each MLC stores two bits of data, the MLC may be programmed to take one of three possible programming levels from an erased state by writing one of three possible nominal storage values ​​to the memory cell. Among them, the fourth nominal storage value may be used for an erased state.

[0097] In the embodiment of the present disclosure, the above-mentioned peripheral circuit can be coupled to the memory cell array through the bit line (Bit Line, BL), the word line (Word Line, WL), the source (Source Line), the source select gate (Source Select Gate, SSG) and the drain select gate (Drain Select Gate, DSG). Here, the peripheral circuit may include any suitable analog, digital and mixed signal circuits to facilitate the relevant operation of the memory cell array by applying a voltage signal and / or a current signal to each target memory cell via a bit line, a word line, a source, an SSG or a DSG, etc. and sensing a voltage signal and / or a current signal from each target memory cell. In addition, the peripheral circuit may also include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology. For example, as Figure 1E The peripheral circuit 70 may include a page buffer (PB) / sense amplifier 71, a column decoder / bit line driver 72, a row decoder / word line driver 73, a voltage generator 74, a control logic unit 75, a latch circuit 76, an interface 77 and a data bus 78. It should be understood that the above peripheral circuit 70 may be connected to Figure 1D The peripheral circuit 64 is the same as in FIG. 1 , and in some other embodiments, the peripheral circuit 70 may also include Figure 1E Additional peripheral circuits not shown.

[0098] like Figure 1FAs shown, a page buffer group 90 is shown in one embodiment of the present disclosure. The page buffer group 90 can be coupled to the memory cell array 80 via a plurality of bit lines BL1 to BLk. The page buffer group 90 can include page buffer 1 (PB1) to page buffer k (PBk), each of which is coupled to the memory cell array via a bit line. For example, the page buffers PB1 to PBk can be coupled to the memory cell array via corresponding bit lines BL1 to BLk, respectively.

[0099] The present disclosure provides a page buffer such as Figure 2 As shown, the page buffer is set corresponding to the bit line of the memory cell array of the memory device, and the page buffer includes:

[0100] A first charge-discharge module is coupled to the bit line and configured to store first bit line force information and provide a first bit line force voltage to the bit line according to the first bit line force information;

[0101] a second charge-discharge module different from the first charge-discharge module, coupled to the bit line and configured to store second bit line forcing information and provide a second bit line forcing voltage different from the first bit line forcing voltage to the bit line according to the second bit line forcing information;

[0102] Wherein, the first bit line forced voltage and the second bit line forced voltage are both greater than a normal programming bit line voltage and less than a programming inhibiting bit line voltage.

[0103] Figure 2 Will Figure 1F The page buffer 91 among the page buffers PB1 to PBk shown in FIG. 1 is described as an example. It should be noted that the remaining page buffers may have the same configuration as the page buffer 91. In some embodiments, the page buffer 91 has a charge and discharge module, which may be used to adjust the bit line voltage during programming. For example, a voltage is applied to the bit line to precharge the bit line; or the bit line is discharged to pull the bit line voltage down to the ground voltage, etc.

[0104] In some embodiments, during the process of programming the memory cell, a programming-inhabit voltage (Vinh) or a normal programming bit line voltage Vprog (e.g., Vss) may be applied to the bit line connected to the memory cell through a charge-discharge module. Exemplarily, a high level is applied to the bit line through the charging function of a charge-discharge module to achieve the effect of prohibiting programming, or the bit line is discharged through the discharge function of the charge-discharge module so that the voltage of the bit line is pulled down to the ground voltage to achieve the effect of allowing programming.

[0105] However, if the charge and discharge module is used to provide only a programming inhibit bit line voltage or a normal programming bit line voltage, it is difficult to narrow the threshold voltage distribution range of memory cells in corresponding storage states of a certain page after programming.

[0106] An embodiment of the present disclosure can provide two additional bit line forced voltages to the bit line through two charging and discharging modules. The two bit line forced voltages can be between the above-mentioned programming prohibited bit line voltage and the programming allowed voltage. Therefore, the corresponding storage cell to which the bit line forced voltage is applied will not be prohibited from programming, but the threshold voltage of the corresponding storage cell will change more slowly or more difficult during the programming process. It can be understood that the larger the bit line forced voltage, the more difficult it is for the corresponding storage cell to charge the charge into the charge storage layer of the storage cell during the programming process. Therefore, applying different bit line forced voltages to different bit lines during the programming process can achieve fine programming of the storage cells corresponding to different bit lines, thereby reducing over-programming or too wide a threshold voltage distribution.

[0107] like Figure 2 As shown, the page buffer 91 provided in one embodiment of the present disclosure includes a first charge and discharge module 201 and a second charge and discharge module 202 different from the first charge and discharge module 201. The first charge and discharge module 201 is coupled to the bit line and configured to store first bit line force information and provide a first bit line force voltage to the bit line according to the first bit line force information. The second charge and discharge module 202 is coupled to the bit line and configured to store second bit line force information and provide a second bit line force voltage different from the first bit line force voltage to the bit line according to the second bit line force information. In one embodiment of the present disclosure, two different bit line force voltages can be provided by using two charge and discharge modules. That is, during the programming process, two charge and discharge modules can be used to provide two bit line force voltages different from the programming prohibition bit line voltage or the normal programming bit line voltage based on the requirements of the programming fineness. The two bit line force voltages are the first bit line force voltage and the second bit line force voltage. In this way, the programming speed and the programming fineness can be balanced. For example, if the threshold voltage of the memory cell to be programmed is significantly different from the target threshold voltage and the programming degree needs to be increased, a smaller bit line forced voltage can be used to quickly increase the threshold voltage of the memory cell. If the threshold voltage of the memory cell to be programmed is already very close to the target threshold voltage, then the degree of programming needs to be reduced so that the threshold voltage is slightly increased but not too much to avoid over-programming. At this time, a relatively large bit line forced voltage can be used. In this way, when different bit lines corresponding to different memory cells of a certain page are respectively applied with different bit line forced voltages, when the same programming voltage is applied to the word lines corresponding to the page, the programming degrees of different memory cells are different, and the data state corresponding to a certain threshold range can be more consistently programmed.

[0108] The first bit line forcing information is information for distinguishing the memory cells to be subjected to the first bit line forcing operation, that is, distinguishing the memory cells to be subjected to the first bit line forcing operation from the memory cells not subjected to the first bit line forcing operation. The first bit line forcing information can use binary data "0" or "1" to indicate whether the first bit line forcing operation is to be performed.

[0109] Accordingly, the second bit line forcing information is information for distinguishing the memory cells to be subjected to the second bit line forcing operation, that is, distinguishing the memory cells to be subjected to the second bit line forcing operation from the memory cells not subjected to the second bit line forcing operation. The second bit line forcing information can use binary data "0" or "1" to indicate whether the second bit line forcing operation is to be performed.

[0110] Through the technical solution in one embodiment of the present disclosure, two charging and discharging modules are set in the page buffer 91 to provide two additional bit line forced voltages during the programming process, so that coarse programming and various degrees of fine programming can be flexibly configured, thereby making the threshold voltage distribution of the storage unit after programming narrower and the read margin wider, thereby improving the stability and read and write accuracy of the memory.

[0111] In some embodiments, more than two charging and discharging modules may be used to provide more than two different bit line forced voltages for the page buffer 91 to obtain finer programming accuracy.

[0112] In some embodiments, the programming inhibit bit line voltage is applied to the bit line corresponding to the programming inhibited memory cell to inhibit programming of the memory cell;

[0113] The normal programming bit line voltage is applied to the bit line corresponding to the memory cell to be programmed, so as to allow the memory cell to be first programmed;

[0114] The first bit line forced voltage is applied to the bit line corresponding to the memory cell to be programmed to allow the memory cell to be second programmed;

[0115] The second bit line forced voltage is applied to the bit line corresponding to the memory cell to be programmed, so as to allow the memory cell to be third programmed;

[0116] The first programming degree is higher than the second programming degree, and the second programming degree is higher than the third programming degree.

[0117] Here, the programming prohibition bit line voltage Vinh may be a power supply voltage VDD, and the programming prohibition bit line voltage is applied to the bit line corresponding to the programming prohibition memory cell, so as to prohibit the memory cell from being programmed. The normal programming bit line voltage Vprog may be a ground voltage Vss, and the normal programming bit line voltage is applied to the bit line corresponding to the memory cell to be programmed, so as to allow the memory cell to be first programmed.

[0118] The first bit line forced voltage may be a voltage between the power supply voltage VDD and the ground voltage Vss, and the first bit line forced voltage is applied to the bit line corresponding to the memory cell to be programmed to allow the memory cell to be second programmed. The degree of the first programming is higher than the degree of the second programming, that is, the threshold voltage of the same cell to be programmed increases faster when a normal programming bit line voltage is applied to it than when a first bit line forced voltage is applied to it.

[0119] The second bit line forced voltage may also be a voltage between the power supply voltage VDD and the first bit line forced voltage, and the second bit line forced voltage is greater than the first bit line forced voltage. The second bit line forced voltage is applied to the bit line corresponding to the memory cell to be programmed to allow the memory cell to be third programmed. The degree of the second programming is higher than the degree of the third programming, that is, the threshold voltage of the same cell to be programmed increases faster when the first bit line forced voltage is applied than when the second bit line forced voltage is applied.

[0120] In some embodiments, Figure 3 As shown, the first charge and discharge module 201 includes: a first charge and discharge circuit 310, a first latch 330 and a first bit line voltage setting component 320;

[0121] The first charge and discharge circuit 310 is connected to the power supply voltage and connected to the second sensing node SO2 of the page buffer via the first bit line voltage setting unit 320 so as to be connected to the bit line; the first charge and discharge circuit 310 is configured to provide the power supply voltage to the first bit line voltage setting unit 320;

[0122] The first latch 330 is connected to the first charge and discharge circuit 310 and the first sensing node SO connected to the page buffer so as to be connected to the bit line; the first latch 330 is configured to store the first bit line forcing information;

[0123] The first bit line voltage setting unit 320 connects the first charge and discharge circuit 310 and the second sensing node SO2 so as to connect the bit line; the first bit line voltage setting unit 320 is configured to: apply the first bit line forcing voltage to the second sensing node SO2 connected to the bit line based on the power supply voltage according to the first bit line forcing information stored in the first latch 330.

[0124] The power supply 340 is connected to the first charge and discharge circuit 310 and provides power to it. The first latch 330 can be configured to store at least data, which can be data indicating the verification result after programming and verification operations, or data read out by a read operation, etc. Here, as the verification result, binary data "0" or "1" can be used to indicate whether the verification is passed. The corresponding first latch 330 in the first charging module 201 in one embodiment of the present disclosure can be used to store the first bit line forced information, which is used to indicate the verification result after the first forced sensing voltage verifies the storage unit.

[0125] In some embodiments, storing "0" in the first latch indicates that the threshold voltage of the memory cell is greater than or equal to the first bit line sensing voltage; storing "1" in the first latch indicates that the threshold voltage of the memory cell is less than the first bit line sensing voltage.

[0126] In some embodiments, storing "0" in the first latch indicates that the threshold voltage of the memory cell is less than the first bit line sensing voltage; storing "1" in the first latch indicates that the threshold voltage of the memory cell is greater than or equal to the first bit line sensing voltage.

[0127] The first bit line voltage setting component 320 may be an NMOS transistor, a PMOS transistor, or a combination of multiple NMOS transistors and / or multiple PMOS transistors. The first bit line voltage setting component 320 may also be other components that can be used to clamp or adjust voltage, such as a Zener diode, a transient voltage suppressor, a varistor, etc.

[0128] The first bit line voltage setting component 320 can embed the voltage from the power supply at a suitable voltage value, for example, the first bit line force voltage (ground voltage < first bit line force voltage < power supply voltage), according to the verification result stored in the above-mentioned first latch circuit 330 (i.e., the stored first bit line force information, which is used to indicate the verification result after the first forced sensing voltage verifies the storage unit), and then apply it to the bit line.

[0129] According to the verification result stored in the first latch, the first bit line forcing voltage is applied to the bit line based on the power supply voltage so as to make a target threshold voltage distribution narrower.

[0130] In some embodiments, the first charge and discharge circuit 310 further includes:

[0131] The first charging switch connects the power supply 340 and the first bit line voltage setting component 320; the control electrode of the first charging switch is connected to the first latch 330; the first charging switch is configured to provide a power supply voltage to the first bit line voltage setting component 320 according to a signal output by the first latch 330.

[0132] The first charging switch includes a control electrode, that is, the on or off state of the first charging switch is determined by a signal input to the control electrode, and the input signal comes from the signal output by the first latch 330 .

[0133] In some embodiments, when the signal output by the first latch 330 causes the control electrode to control the first charging switch to be turned on, the power supply voltage is provided to the first bit line voltage setting unit 320 .

[0134] In some embodiments, the first latch 330 can be used to store first bit line force information, and the first bit line force information is used to indicate the verification result after the first forced sensing voltage verifies the storage unit. That is, the conduction of the first charging switch can be controlled by the first bit line force information, and when the first charging switch is turned on, the power supply voltage is provided to the first bit line voltage setting unit 320.

[0135] The first charging switch may provide a power supply voltage to the first bit line voltage setting unit 320 in a precharging stage and a bit line voltage setting stage.

[0136] In some embodiments, Figure 4 As shown, the first latch 330 includes:

[0137] A first data latch unit 420, configured to store corresponding program verification information according to a program verification result, or configured to store the first bit line forcing information;

[0138] The first data setting unit 410 is connected to the first data latch unit 420 , and the first data setting unit 410 is configured to output the program verification information or the first bit line forcing information to be stored to the first data latch unit 420 .

[0139] In some embodiments, the first data latch unit 420 may be reversely connected by an inverter 423 and an inverter 424 , and connection points of the two inverters are a first node 421 and a second node 422 , respectively.

[0140] In some embodiments, the first data setting unit 410 includes an NMOS transistor 412 and an NMOS transistor 411 , wherein the NMOS transistor 412 is connected to the second node 422 of the first data latch unit 410 , and the NMOS transistor 411 is connected to the first node 421 of the first data latch unit 410 .

[0141] The first latch may further include a first sensing switch 430. In some embodiments, the first sensing switch 430 is an NMOS tube, the control electrode of which is connected to the sensing node SO. The NMOS tube is turned on by the level of the sensing node SO and applies a ground voltage to the first data setting component 410.

[0142] The first data setting unit 410 selects the corresponding NMOS transistor 412 and NMOS transistor 411 to perform data setting according to the verification result after the memory cell is verified by the first forced sensing voltage.

[0143] The first data setting unit 410 transmits the ground voltage to the first node 421 or the second node 422 of the first data latch unit 420 according to the first bit line forcing information. In some embodiments, when the ground voltage is stored in the first node 421, it can be used to indicate that the data "0" is stored. For example, the data "0" can indicate that the memory cell to be programmed of the corresponding bit line will not perform the first bit line forcing operation.

[0144] The first node 421 can store the ground voltage in the following manner: after the first sensing switch 430 between the ground voltage and the first data setting unit 410 is turned on, the ground voltage is allowed to be transmitted to the first data setting unit 410 through the first sensing switch 430. The first data latch unit 410 includes an NMOS transistor 412 and an NMOS transistor 410, and the NMOS transistor 412 is configured to apply the ground voltage transmitted by the first sensing switch 430 to the second node 422 in response to the first data setting signal Sets. In addition, the NMOS transistor 411 is connected between the first sensing switch 430 and the first node 421, and is configured to apply the ground voltage transmitted by the first sensing switch 430 to the first node 421 in response to the second data setting signal Rsts.

[0145] In some embodiments, when the voltage of the first node 421 is at a high level, it can be used to indicate storage data "1". For example, data "1" can indicate that the memory cell to be programmed of the corresponding bit line will not perform a first bit line forced operation.

[0146] In some embodiments, when the voltage of the second node 422 is at a high level, it can be used to indicate storage of data "1", and data "1" can indicate that the memory cell to be programmed of the corresponding bit line will not perform a first bit line forced operation.

[0147] In some embodiments, the second charge and discharge module includes: a second charge and discharge circuit, a second latch, and a second bit line voltage setting component;

[0148] The second charge and discharge circuit is connected to the power supply voltage and connected to the second bit line voltage setting component via the first sensing node of the page buffer so as to be connected to the bit line, and the second charge and discharge circuit is configured to provide the power supply voltage to the second bit line voltage setting component;

[0149] the second latch is connected to the second charge and discharge circuit and to the first sensing node so as to be connected to the bit line, the second latch is configured to store the second bit line forcing information;

[0150] The second bit line voltage setting component is connected to the second charge and discharge circuit and the second sensing node connected to the page buffer so as to be connected to the bit line. The second bit line voltage setting component is configured to apply the second bit line forcing voltage to the second sensing node connected to the bit line based on the power supply voltage according to the second bit line forcing information stored in the second latch.

[0151] Different from the first charge and discharge module, the second bit line voltage setting component of the second charge and discharge module can be connected to the second charge and discharge circuit by connecting the first sensing node; while the first charge and discharge module can be directly connected to the first charge and discharge circuit.

[0152] The second latch can also be configured to store at least data, which can be data indicating verification results after programming and verification operations, or data read out by a read operation, etc. The corresponding second in the second charging module in one embodiment of the present disclosure can be used to store second bit line forcing information, and the second bit line forcing information is used to indicate the verification result after the second forced sensing voltage verifies the storage unit.

[0153] The second bit line voltage setting component may be the same as or different from the first bit line voltage setting component. The second bit line voltage setting component may clamp the voltage from the power supply to a suitable voltage value (eg, a second bit line forced voltage) and then apply it to the bit line.

[0154] In some embodiments, the second charge and discharge circuit further includes:

[0155] A second charging switch connects the power supply and the second bit line voltage setting component; a control electrode of the second charging switch is connected to the second latch; and the second charging switch is configured to provide a power supply voltage to the first bit line voltage setting component according to a signal output by the second latch.

[0156] The components used in the second charging switch may be the same as or different from those used in the first charging switch.

[0157] The second charging switch is controlled by a signal output by the second latch, and the second latch can be used to store second bit line forced information, and the second bit line forced information is used to indicate the verification result after the second forced sensing voltage verifies the storage unit. That is, the conduction of the second charging switch can be controlled by the second bit line forced information, and when the second charging switch is turned on, the power supply voltage is provided to the second bit line voltage setting component.

[0158] In some embodiments, the second latch comprises:

[0159] a second data latch unit configured to store the second bit line forcing information;

[0160] The second data setting unit is connected to the second data latch unit; the second data setting unit is configured to output the second bit line forcing information to be stored to the second data latch unit.

[0161] The components of the second latch may be the same as or different from those of the first latch.

[0162] The second latch may also include a second sensing switch. In some embodiments, the second sensing switch and the first sensing switch may be the same component, that is, the second sensing switch is the first sensing switch. In some embodiments, the second sensing switch and the first sensing switch may be the same but independent components. In some embodiments, the components used by the second sensing switch and the first sensing switch may be different, for example, the first sensing switch uses an NMOS tube and the second sensing switch uses a PMOS tube.

[0163] In some embodiments, the first charge and discharge module is further configured to store programming verification information; when the programming verification information is in a state that programming is allowed, the first charge and discharge module is configured to provide a normal programming bit line voltage to the bit line;

[0164] The page buffer further includes:

[0165] A dynamic latch is coupled to the first sensing node of the page buffer; the dynamic latch is configured to store the first bit line forcing information and is configured to transmit the first bit line forcing information to the first charge and discharge module after the first charge and discharge module provides the normal programming bit line voltage to the bit line.

[0166] The first charge and discharge module is further configured to store programming verification information. The programming verification information can be used to distinguish whether the storage cell is a programming-prohibited cell or a programming-allowed cell. When the programming verification information indicates that the storage cell is a programming-allowed cell, the first charge and discharge module can precharge the bit line first, and precharge the bit line to a normal programming bit line voltage (e.g., Vss).

[0167] When a verification voltage (e.g., a first forced sensing voltage, a second forced sensing voltage, and a programming verification voltage) is used to verify a storage cell, a verification result is obtained. For example, one verification result can be obtained after verification using one verification voltage; two verification results can be obtained after verification using two verification voltages; and N verification results can be obtained after verification using N verification voltages. Each verification result corresponding to a specific verification voltage can be represented by binary data "0" or "1". Part or all of the verification results representing a specific verification voltage can be stored in a dynamic latch.

[0168] In the disclosed embodiment, the verification result after the first forced sensing voltage verifies the storage unit, that is, the first bit line forced information, can be stored in the dynamic latch. When the first charge and discharge module stores the programming verification information, and the programming verification information indicates that the storage unit is a programming-allowed unit, the first charge and discharge module can use the programming verification information to precharge the bit line and precharge the bit line to a normal programming bit line voltage (e.g., Vss). Then, after the precharging action is completed, the first bit line forced information stored in the dynamic latch is transmitted to the first charge and discharge module. The first charge and discharge module then determines what voltage to provide to the bit line in the future according to the first bit line forced information.

[0169] In some embodiments, the dynamic latch comprises:

[0170] a third data latch unit configured to store the first bit line forcing information;

[0171] A third data setting unit is connected to the third data latch unit; the third data setting unit is configured to output the first bit line forcing information to be stored to the third data latch unit.

[0172] The dynamic latch may be composed of the same or different components as the second latch or the first latch.

[0173] Different from the first latch and the second latch, the dynamic latch may not belong to any charge and discharge module, and is only used to temporarily store the verification result after the first forced sensing voltage verifies the storage unit.

[0174] In some embodiments, when the program verification information indicates that program is prohibited, the first charge and discharge module is configured to provide a power supply voltage for prohibiting program to the bit line.

[0175] When the verification result (i.e., programming verification information) indicates that the threshold voltage of the memory cell to be programmed reaches the target threshold voltage, it is temporarily not necessary to continue programming the memory cell, so programming of the memory cell is prohibited. The memory cell can be prohibited from programming by precharging the bit line to a programming-prohibited voltage. The programming-prohibited voltage can come from the power supply voltage, that is, the power supply voltage is directly connected to the bit line. Exemplarily, at this time, the first bit line voltage setting component can be controlled not to clamp or divide the power supply voltage, that is, the first bit line voltage setting component is set to a fully conductive state. Of course, the power supply voltage can also be applied to the bit line as a programming-prohibited voltage through other paths connected to the power supply.

[0176] When the first bit line voltage setting component is an NMOS tube, a larger voltage value can be applied to the control electrode of the NMOS tube to make the first bit line voltage setting component fully turned on, so that the voltage from the power supply is not clamped. Therefore, the bit line can be provided with a power supply voltage for prohibiting programming.

[0177] The present disclosure provides a method for programming a memory, wherein the memory includes a page buffer, the page buffer is arranged corresponding to a bit line of a memory array of a memory device, and the page buffer includes a first charge-discharge module and a second charge-discharge module coupled to the bit line; Figure 5 As shown, the programming method includes:

[0178] Step S101, providing a first bit line forced voltage to the bit line corresponding to the memory cell to be programmed according to the first bit line forced information stored in the first charge and discharge module;

[0179] Step S102: providing a second bit line forced voltage to a bit line corresponding to a memory cell to be programmed according to second bit line forced information stored in the second charge and discharge module;

[0180] Wherein, the first bit line forced voltage and the second bit line forced voltage are both greater than the normal programming bit line voltage and less than the programming inhibiting bit line voltage;

[0181] Step S103 : programming the memory cells to be programmed to different degrees based on the first bit line forced voltage and the second bit line forced voltage.

[0182] In the embodiment of the present disclosure, an additional first bit line forced voltage and a second bit line forced voltage may be applied to the memory cell to be programmed, wherein the first bit line forced voltage is provided by the first charge and discharge module of the page buffer. The second bit line forced voltage is provided by the second charge and discharge module of the page buffer. Different charge and discharge modules may provide different bit line forced voltages. According to the first bit line forced information in the first charge and discharge module and the second bit line forced information in the second charge and discharge module, a suitable voltage may be selected from the voltages including the first bit line forced voltage and the second bit line forced voltage and applied to the bit line for programming the memory cell at different speeds. The larger the bit line forced voltage, the more difficult it is to charge the charge into the memory cell during programming. Therefore, during programming, the verification result (i.e., the first bit line forced information and the second bit line forced information) may be used to indicate the gap between the threshold voltage of the current memory cell and the target threshold voltage. Fine programming effect may be achieved by selecting to apply different bit line forced voltages to the bit line according to the size of the gap.

[0183] In some embodiments, providing a first bit line forced voltage to the bit line corresponding to the memory cell to be programmed according to the first bit line forced information stored in the first charge and discharge module includes:

[0184] After verifying the first bit line sensing voltage of the memory cell to be programmed, storing the first bit line forcing information by using the first latch in the first charge and discharge module;

[0185] Using the first charge and discharge circuit in the first charge and discharge module to provide a power supply voltage to the first line voltage setting component in the first charge and discharge module;

[0186] The first bit line voltage setting unit is used to apply a first bit line forcing voltage to a second sensing node connected to the bit line corresponding to the memory cell to be programmed based on the power supply voltage according to the first bit line forcing information.

[0187] The first bit line sensing voltage is used to verify the memory cell to be programmed and obtain a verification result, and the verification result is recorded by forcibly recording information using the first bit line.

[0188] When the first bitline forcing information indicates that the threshold voltage of the memory cell is greater than or equal to the first bitline sensing voltage, the first bitline forcing voltage is applied to the second sensing node of the bitline corresponding to the memory cell to be programmed based on the power supply voltage by using the first bitline voltage setting component.

[0189] When the first bit line forcing information indicates that the threshold voltage of the memory cell is less than the first bit line sensing voltage, the first bit line forcing voltage is not applied to the second sensing node.

[0190] In some embodiments, using the first charge and discharge circuit in the first charge and discharge module to provide the first line voltage setting component with a power supply voltage includes:

[0191] A power supply voltage is provided to the first bit line voltage setting unit through a first charging switch in the first charging and discharging circuit according to a signal output by the first latch.

[0192] The signal output by the first latch can control the conduction of the first charging switch. When the first charging switch is turned on, the power supply voltage can be provided to the first bit line voltage setting component in the pre-charging stage and the bit line voltage setting stage.

[0193] In the precharge phase, the first latch provides a power supply voltage to the first bit line voltage setting unit when the program verification information stored therein is in a state of prohibiting programming. In the bit line voltage setting phase, the first latch provides a power supply voltage to the first bit line voltage setting unit when the first bit line forcing information stored therein is that the threshold voltage of the cell to be programmed is greater than or equal to the first bit line sensing voltage.

[0194] In some embodiments, providing a second bit line forcing voltage to a bit line corresponding to a memory cell to be programmed according to the second bit line forcing information stored in the second charging and discharging module includes:

[0195] After verifying the second bit line sensing voltage of the memory cell to be programmed, storing the second bit line forcing information by using a second latch;

[0196] Using a second charge and discharge circuit in the second charge and discharge module to provide a power supply voltage to a second bit line voltage setting component in the second charge and discharge module;

[0197] The second bit line voltage setting unit is used to apply a second bit line forcing voltage to a second sensing node connected to the bit line corresponding to the memory cell to be programmed based on the power supply voltage according to the second bit line forcing information.

[0198] Similar to the step of providing the first bit line forced voltage, here, the second bit line sensing voltage can be used to verify the memory cell to be programmed and obtain the verification result, and the verification result is recorded using the second bit line forced information.

[0199] When the second bit line forcing information indicates that the threshold voltage of the memory cell is greater than or equal to the second bit line sensing voltage, a second bit line forcing voltage is applied to the second sensing node of the bit line corresponding to the memory cell to be programmed based on the power supply voltage by using a second bit line voltage setting component.

[0200] When the second bit line forcing information indicates that the threshold voltage of the memory cell is less than the second bit line sensing voltage, the second bit line forcing voltage is not applied to the second sensing node.

[0201] In some embodiments, the using the second charge and discharge circuit in the second charge and discharge module to provide the second bit line voltage setting component with a power supply voltage includes:

[0202] A power supply voltage is provided to the second bit line voltage setting unit through a second charging switch in the second charging and discharging circuit according to a signal output by the second latch.

[0203] The signal output by the second latch can control the conduction of the second charging switch, and when the second charging switch is turned on, a power supply voltage can be provided to the second bit line voltage setting component in the bit line voltage setting stage.

[0204] In the bit line voltage setting phase, the second latch provides a power supply voltage to the first bit line voltage setting unit when the second bit line forcing information stored therein indicates that the threshold voltage of the to-be-programmed cell is greater than or equal to the second bit line sensing voltage.

[0205] In some embodiments, the method further comprises:

[0206] Using a first charge and discharge module to store programming verification information, and providing a normal programming bit line voltage to the bit line when the programming verification information indicates that the first programming is allowed;

[0207] After the first charge and discharge module provides the normal programming bit line voltage to the bit line, the dynamic latch in the page buffer transmits the first bit line forcing information to the first charge and discharge module.

[0208] The first latch may store program verification information. In a precharge phase, the first latch provides a normal program bit line voltage to the bit line when the program verification information stored in the first latch indicates that programming is allowed.

[0209] After the first charge and discharge module provides the normal programming bit line voltage to the bit line, the dynamic latch in the page buffer transmits the first bit line forced information to the first charge and discharge module for setting the bit line voltage in the bit line voltage setting phase.

[0210] In some embodiments, the method further comprises:

[0211] In a state where the program verification information indicates program inhibition, a power supply voltage for program inhibition is supplied to the bit line.

[0212] The present disclosure also provides a memory device 1000, such as Figure 6 As shown, the memory device 1000 includes:

[0213] a memory cell array 1010 having a plurality of memory cell strings and a plurality of bit lines connected to the plurality of memory cell strings; and

[0214] A peripheral circuit 1020, which is coupled to the memory cell array 1010 through the bit line BL and is used for the memory cell array 1010 to operate;

[0215] The peripheral circuit 1020 is provided with a page buffer 1021 as described in any one of the above embodiments.

[0216] The page buffer 1021 is connected to a corresponding bit line via a sensing node, and is connected to the memory cell string via the bit line.

[0217] In some embodiments, the memory device 1000 may be a non-volatile memory product such as a NAND chip. The memory device 1000 includes a memory cell array 1010 and a peripheral circuit 1020 .

[0218] Among them, the memory cell array 1010 can be any suitable memory cell array 1010. For example, the memory cell array 1010 may include a plurality of memory cells arranged in a memory block. Each memory block may include a plurality of memory strings coupled between a bit line and a common source line. That is, the memory strings may be coupled to corresponding bit lines respectively. The memory strings may also be coupled to a common source line in common. Each memory string may include a source selection transistor, a plurality of memory cells, and a drain selection transistor coupled in series with each other.

[0219] The peripheral circuit 1020 is coupled to the memory cell array 1010 through one or more bit lines, and the peripheral circuit 1020 includes a page buffer group, and the page buffer group includes one or more page buffers 1021 as described in the above embodiment. The page buffer 1021 includes a sensing node SO for determining the state of the memory cell therein (for example, the data stored in the memory cell), and each of the page buffers 1021 is connected to the bit line via the sensing node. The state of the memory cell can be determined by detecting the current flowing through the sensing node SO.

[0220] The present disclosure also provides a memory system 1100, such as Figure 7 As shown, it is characterized in that the memory system 1100 includes:

[0221] The memory device 1000 as described in any of the above embodiments; and

[0222] A memory controller 1110 is coupled to the memory device 1000 and configured to control the memory device 1000 .

[0223] In some embodiments, the memory system 1100 may be a product such as an SSD, or may be an electronic device including the memory device 1000, such as a computer device.

[0224] The present disclosure also has the following examples:

[0225] Take MLC flash memory as an example (the same applies to TLC and QLC), Figure 8 This is the threshold voltage distribution diagram of MLC flash memory in different threshold states. MLC flash memory has four states, including the erase state E with the lowest threshold voltage (corresponding to the logical value of 11) and three programming states, which are P1, P2 and P3 from low to high in terms of threshold voltage, and the corresponding logical values ​​are 10, 01 and 00. For memories of different models and manufacturers, the corresponding relationship between the threshold state and the logical value of the memory can also have other corresponding relationships. Reference Figure 8 As shown, each threshold state corresponds to a threshold voltage distribution, the threshold voltage distribution is normally distributed, and ideally these threshold voltage distributions do not overlap. The non-overlapping parts between the threshold voltage distributions are called distribution margins. When reading a memory cell, the value of the read reference voltage (Ref1, Ref2, Ref3) is located in the distribution margin. Therefore, if the range of each threshold voltage distribution is narrower, the corresponding distribution margin is larger, and the read window between different threshold states is larger; conversely, the smaller the read window, the more likely it is to cause a read error.

[0226] In some embodiments, Fig. 9 As shown, three verification voltages are used to verify whether the memory cell reaches the target threshold voltage distribution. The three verification voltages are respectively the programming verification voltage Vry_f, the second forced sensing voltage Vry_c2 and the first forced sensing voltage from large to small. The three verification voltages are all within the current threshold voltage distribution range, and the current threshold voltage range is divided into four parts: a, b, c, and d.

[0227] When the threshold voltage of a memory cell is verified to be greater than or equal to the programming verification voltage Vry_f, it means that the current threshold voltage of the memory cell has been programmed into the range d of the target threshold voltage distribution. At this time, further programming of the memory cell is prohibited, that is, a programming prohibition bit line voltage (such as VDD voltage) is applied to the bit line connected to the memory cell.

[0228] When the threshold voltage of a certain memory cell is verified to be greater than or equal to the second forced sensing voltage Vry_c2 and less than the programming verification voltage Vry_f, it means that the threshold voltage of the memory cell has been programmed into the c range of the target threshold voltage distribution. Considering that the threshold voltage distribution of the memory cell is expected to converge within the range of the target threshold voltage distribution, the memory cell whose threshold voltage is distributed within the c range needs to continue to be programmed, but the step length of this programming needs to be shortened to prevent the step length of programming from being too long, causing the threshold voltage of the memory cell after the next programming to exceed the range of the target threshold voltage distribution. In order to shorten the step length of the next programming, a second bit line forced voltage Vmid2 is applied to the bit line voltage. The voltage value of Vmid2 is less than the VDD voltage and greater than the ground voltage.

[0229] When the threshold voltage of a certain memory cell is verified to be greater than or equal to the first forced sensing voltage Vry_c1 and less than the second forced sensing voltage Vry, it means that the threshold voltage of the memory cell is programmed into the b range of the current threshold voltage distribution. Considering that the threshold voltage distribution of the memory cell is expected to converge within the range of the target threshold voltage distribution, the memory cell whose threshold voltage is distributed within the b range needs to continue to be programmed, but the step length of this programming needs to be shortened to prevent the step length of programming from being too long (for example, over-programming) causing the threshold voltage of the memory cell to exceed the range of the target threshold voltage distribution after the next programming; it will be understood that the step length of this programming can be a little longer than the step length of programming for the memory cell whose current threshold voltage is in the c range. In order to shorten the step length of the next programming, the first bit line forced voltage Vmid1 is applied to the bit line voltage. The voltage value of Vmid1 is less than the voltage of Vmid2 and greater than the ground voltage.

[0230] When the threshold voltage of a certain memory cell is verified to be less than the first forced sensing voltage Vry_c1, it means that the threshold voltage of the memory cell is programmed into the range of a of the current threshold voltage distribution, which is far from the target threshold voltage distribution. This means that there is still a considerable distance from the target threshold voltage distribution range that is expected to converge. At this time, if Vmid2 or Vmid1 is used to program the memory cell, although the programming step size can be controlled, it will increase the programming time and affect the performance of the memory. Therefore, for the case where the threshold voltage is within the range of a of the current threshold voltage distribution or has not yet reached the range of a, the ground voltage, that is, the normal programming bit line voltage, can be applied to the bit line of the memory cell.

[0231] In summary, when three verification voltages are used for verification, the bit line voltage can adopt four bit line voltages to implement programming based on program inhibition and with three different step sizes according to the comparison results between the threshold voltage and the three verification voltages.

[0232] By adopting the above method, a narrow target threshold voltage distribution diagram can be obtained, which is beneficial to increase the read window.

[0233] In some embodiments, the page buffer is structured as follows: Fig.10 As shown, the page buffer 2200 is provided with a first charge and discharge module 2210 and a second charge and discharge module 2220, wherein the first charge and discharge module 2210 includes a first charge and discharge circuit 2211, a first latch 2212 and a first bit line voltage setting component 2213, wherein the first bit line voltage setting component 2213 may be an NMOS tube, which may be controlled by Vblbias to implement the clamping of the power supply voltage. The output information of the first latch 2212 may control the first charge and discharge circuit 2211 to provide the power supply voltage VDD to the first bit line voltage setting component 2213. The second charge and discharge module 2220 may include a second charge and discharge circuit 2221, a second latch 2222 and a second bit line voltage setting component 2223, wherein the second bit line voltage setting component 2223 may be an NMOS tube for clamping the power supply voltage. The second latch 2222 controls the second charge and discharge circuit 2221 to provide the power supply voltage VDD to the second bit line voltage setting component 2213. The page buffer 2200 further has a dynamic latch 2330 for recording at least one verification result (eg, program verification information and / or first bit line forcing information and / or second bit line forcing information).

[0234] The first charge and discharge module 2210 may charge the bit line voltage to a first bit line forcing voltage Vmid1 or a program inhibiting voltage (eg, Vdd), and the second charge and discharge module 2220 may charge the bit line voltage to a second bit line forcing voltage Vmid2.

[0235] Specifically, the first bit line voltage setting component 2213 may be used to clamp the power supply voltage provided by the first charge and discharge circuit 2211 to Vmid1; and the second bit line voltage setting component 2223 may be used to clamp the power supply voltage provided by the second charge and discharge circuit 2221 to Vmid2.

[0236] In one embodiment, if Fig.11As shown: the page buffer 2300 is provided with a first charge and discharge module 2310 and a second charge and discharge module 2320, the first charge and discharge module 2310 includes a first charge and discharge circuit 2311, a first latch 2312 and a first bit line voltage setting component (i.e., NMOS tube N5), the two ends of the first charge and discharge circuit 2311 are respectively connected to the power supply and the ground, and it is configured to provide the power supply voltage or the ground voltage to the first bit line voltage setting component N5. The first latch 2312 is connected to the first charge and discharge circuit 2311 and the bit line BL, and the first latch 2312 can store the verification result after the storage unit is verified by the first forced sensing voltage and the programming verification voltage. The source and drain of the first bit line voltage setting component N5 are respectively connected to the first charge and discharge circuit 2311 and the bit line BL, and its gate is controlled by the signal Vblbias2. The bit line voltage setting component N5 can be configured as follows: according to the verification result currently stored in the first latch 2312, during the programming process, the corresponding first bit line force voltage or programming prohibition voltage (for example, VDD) is applied to the bit line BL based on the power supply voltage transmitted from the first charge and discharge circuit 2321.

[0237] The second charge and discharge module 2320 includes a second charge and discharge circuit 2321, a second latch 2322 and a second bit line voltage setting component (i.e., NMOS tube N17). The two ends of the second charge and discharge circuit 2321 are respectively connected to the power supply and the ground, and are configured to provide the second bit line voltage setting component N17 with a power supply voltage or a ground voltage. The second latch 2322 is connected to the second charge and discharge circuit 2321 and the bit line BL, and the second latch 2322 is configured to store the verification result after the second forced sensing voltage verifies the storage unit. The source and drain of the second bit line voltage setting component N17 are respectively connected to the second charge and discharge circuit 2321 and the bit line BL, and its gate is controlled by the signal Vblbias3. The second bit line voltage setting component N17 can be configured to: according to the verification result currently stored in the second latch 2322, the second bit line forced voltage is applied to the bit line BL based on the power supply voltage transmitted from the second charge and discharge circuit 2321 during the programming process.

[0238] NMOS tube N18 and NMOS tube N19 are arranged in series on BL, and the bit line forced voltage transmitted by the first bit line voltage setting component N5 or the second bit line voltage setting component N17 can be applied to the bit line BL in sequence through NMOS tube N18 and NMOS tube N19 (when NMOS tube N18 and NMOS tube N19 are turned on); wherein, NMOS tube N18 is controlled by gate control signal Vblbias, and NMOS tube N19 is controlled by gate control signal VPASS_HV.

[0239] The first latch 2312 is provided with a first data latch unit, which is mainly formed by two inverters I1 and I2 connected in reverse parallel, and can store the verification result obtained by a verification operation after a certain programming (for example, a verification operation using a first forced sensing voltage and / or a verification operation using a programming voltage); the first latch 2312 is also provided with a first data setting unit connected to the first data latch unit, which includes an NMOS tube N3 and an NMOS tube N4. During a verification operation after a certain programming, the first data setting unit can output the verification result to be stored (for example, first bit line forced information and / or programming verification information) to the first data latch unit; the first latch is also provided with a first sensing switch, which is specifically composed of an NMOS tube N6, which is connected to a ground point and the first data setting unit, and the gate of the sensing switch N6 is connected to a sensing node SO. The first sensing switch N6 can be turned on under the control of the level of the sensing node SO and apply a ground voltage to the first node or the second node of the first data latch unit when either the NMOS tube N3 or the NMOS tube N4 of the first data setting unit is turned on.

[0240] The second latch 2322 is provided with a second data latch unit, which is mainly formed by two inverters I3 and I4 connected in reverse parallel, and can store the verification result obtained by a verification operation after a certain programming (for example, a verification operation using a second forced sensing voltage); the second latch 2322 is also provided with a second data setting unit connected to the second data latch unit, including an NMOS tube N9 and an NMOS tube N10. During the verification operation after a certain programming, the second data setting unit can output the verification result to be stored (for example, the second bit line forced information) to the second data latch unit; the second latch can also be provided with a second sensing switch. In the embodiment of the present disclosure, the second latch 2322 and the first latch 2312 share the first sensing switch N6.

[0241] The first data latch unit of the first latch 2312 temporarily stores data to be programmed into a specific cell or temporarily stores data read from a specific cell. To this end, the output terminal of the inverter I1 is connected to the input terminal of the inverter I2, and the output terminal I2 of the inverter is connected to the input terminal of the inverter I1. Here, the node at which the output terminal of the inverter I1 is connected to the input terminal of the inverter I2 is called the first node DS. The node at which the output terminal I2 of the inverter is connected to the input terminal of the inverter I1 is called the second node QDS.

[0242] The data latch unit of the second latch 2322 temporarily stores data to be programmed into a specific cell or temporarily stores data read from a specific cell. To this end, the output terminal of the inverter I3 is connected to the input terminal of the inverter I4, and the output terminal I3 of the inverter is connected to the input terminal of the inverter I1. Here, the node at which the output terminal of the inverter I3 is connected to the input terminal of the inverter I4 is called the first node D2, and the node at which the output terminal I3 of the inverter is connected to the input terminal of the inverter I1 is called the second node QD2.

[0243] The first data setting unit of the first latch 2312 includes an NMOS transistor N3 as a first data setting element and an NMOS transistor N4 as a second data setting element, wherein the NMOS transistor N3 is configured to apply a ground voltage to the second node QDS of the first data latch unit, and the NMOS transistor N4 is configured to apply a ground voltage to the first node DS. The NMOS transistor N3 is connected between the first sensing switch 2312 and the second node QDS, and is configured to apply the ground voltage transferred by the first sensing switch N6 to the second node QDS in response to the first data setting signal Sets. In addition, the NMOS transistor N4 is connected between the first sensing switch N6 and the first node DS, and is configured to apply the ground voltage transferred by the first sensing switch N6 to the first node DS in response to the second data setting signal Rsts.

[0244] The second data setting unit of the second latch 2322 includes an NMOS transistor N9 as a third data setting element and an NMOS transistor N10 as a fourth data setting element, the NMOS transistor N9 is configured to apply a ground voltage to the second node QD2 of the second data latch unit, and the NMOS transistor N10 is configured to apply a ground voltage to the first node D2 of the second data latch unit. The NMOS transistor N9 is connected between the first sensing switch N6 and the second node QD2, and is configured to apply the ground voltage transferred by the first sensing switch N6 to the second node QD2 of the second data latch unit in response to the third data setting signal Set2. In addition, the NMOS transistor N10 is connected between the first sensing switch N6 and the first node D2 of the second data latch unit, and is configured to apply the ground voltage transferred by the first sensing switch N6 to the first node DS2 of the second data latch unit in response to the fourth data setting signal Rst2.

[0245] The first sensing switch N6 applies a ground voltage to each data setting component according to the voltage level of the sensing node SO. In some embodiments, the first sensing switch N6 is an NMOS tube. When the voltage level of the sensing node SO is high, the first sensing switch is turned on and applies a ground voltage to each data setting component. When the first data setting signal Sets is applied at a high level, the ground voltage is applied to the second node QDS. In this case, it is determined that high-level data has been applied to the first node DS. When the second data setting signal Rsts is applied at a high level, the ground voltage is applied to the first node DS. In this case, it is determined that low-level data has been applied to the first node DS.

[0246] The page buffer further includes: a dynamic latch 2330, connected to at least one of the charge and discharge modules 2310 or 2320, the dynamic latch 2330 is configured to: store the first bit line forced information, and is configured to transfer the first bit line forced information to the first charge and discharge module after the first charge and discharge module provides the normal programming bit line voltage to the bit line. The dynamic latch can be composed of the same components as the first latch 2312 or the second latch 2322. The dynamic latch 23301 can share the first sensing switch N6 with the first latch 2312 and / or the second latch 2322.

[0247] The first charge and discharge module 2310 further includes: a first discharge circuit, including a discharge switch NMOS tube N7 and an NMOS tube N8 connected in series between a ground point and a sensing node SO of the bit line. The gate of the NMOS tube N7 is used to receive a discharge indication signal RDS; the gate of the NMOS tube N8 is controlled by the storage information of the first node DS of the first data latch unit. The first discharge circuit of the first charge and discharge module 2310 is configured to selectively ground the sensing node SO according to the data stored in the first node DS of the first data latch unit and in response to the discharge indication signal RDS.

[0248] The second charge and discharge module 2320 further includes: a second discharge circuit, including a discharge switch NMOS tube N11 and an NMOS tube N12 connected in series between a ground point and a sensing node SO of the bit line; wherein the gate of the NMOS tube N11 is used to receive a discharge indication signal RD2; and the gate of the NMOS tube N12 is controlled by the storage information of the second node QD2 of the second data latch unit. The second discharge circuit of the second charge and discharge module 2320 is configured to selectively ground the sensing node SO according to the data stored in the second node D2 of the second data latch unit 2325 and in response to the discharge indication signal RD2.

[0249] The page buffer 2300 may further include other charge and discharge modules for setting more bit line forced voltages.

[0250] By using the first forced sensing voltage, the second forced sensing voltage and the programming verification voltage to verify the memory cell, four verification results as shown in Table 1 can be obtained:

[0251]

[0252]

[0253] Table 1

[0254] Fig.12 The present invention is a waveform diagram of control signals applied to various components in a page buffer and a word line where a memory cell is located when a bit line forced voltage is applied to the bit line of the memory cell according to an embodiment. The waveform diagram reflects a partial programming method process of a memory device.

[0255] T1: Pre-charging stage: According to the verification result shown in Table 1, the initial bit line voltage is set using the value of the first node DS in the first charging and discharging module.

[0256] like Fig.12 In the T1 phase, the signal prech2 is at a high level, so the second charge-discharge module is disconnected from the bit line, that is, the second charge-discharge module may not be used to precharge the bit line.

[0257] When DS=1, QDS=0, QDS can control the first charging switch PMOS P1 of the first charging and discharging circuit to turn on. At the same time, a high voltage greater than Vdd+vth is applied to the first bit line voltage setting component N5, so that N5 is turned on, so that the power supply voltage is precharged to the bit line. When DS=0, QDS=1. QDS can control the NMOS tube N2 to turn on. N2 is connected to the ground voltage and directly connected to the bit line, so that the ground voltage can be directly precharged to the bit line.

[0258] In the T1 phase, the ground voltage is applied to both the selected word line and the unselected word lines.

[0259] In this way, the bit lines connected to the memory cells whose threshold voltages are greater than or equal to the programming verification voltage are precharged to the power supply voltage VDD for inhibiting programming; the bit lines connected to the memory cells whose threshold voltages are less than the programming verification voltage are precharged to the ground voltage.

[0260] T2: Data transmission stage. The signal disch1 is changed from high level to low level, and the precharging of the bit line is stopped. At this time, the bit line voltage is in a floating state. At the same time, the first bit line forced information stored in the dynamic latch 2331 is transmitted to the first latch 2312, that is, the first bit line forced information in the dynamic latch is used to replace the programming verification information in the first latch. The data in the dynamic latch 2331 and the second latch 2322 are kept unchanged.

[0261] At this time, the data stored in each latch, i.e., the target bit line voltage, is shown in Table 2 below:

[0262]

[0263] Table 2

[0264] T3: Bit line voltage setting stage: The bit line voltage is set according to the data stored in each latch in Table 2.

[0265] In the T3 phase, the Prech2 signal is at a low level, and the second charge and discharge module can be used to set the voltage of the bit line.

[0266] When setting the bit line voltage, gate voltages are applied to gate electrodes Vblbias2 and Vblbias3 of the bit line voltage setting parts N5 and N17, and the gate voltages are gradually increased from the ground voltage to Vmid1+vth and Vmid2+vth, respectively and simultaneously.

[0267] When the verification result is that the threshold voltage is greater than the first verification voltage, the data in the node DS of the first latch 2312 after transmission is 1, the data in the node D1 in the dynamic latch 2330 is 1, and the data in D2 in the second latch 2322 is 0 (see Table 2).

[0268] At this time, QDS=0, PMOS tube P1 is turned on, and after the power supply voltage passes through the first bit line voltage setting component N5, when N5 applies the VBLBIAS2 signal Vmid1+vth, the SO2 node voltage is (Vmid1+vth)-vth=Vmid1; the data of D2 in the second latch 2322 is 0, when the Prech2 signal is applied to turn on P4, the SO node voltage becomes VDD, and after the power supply voltage passes through the second bit line voltage setting component N17, when N17 applies the Vblbias3 signal Vmid2+vth, the SO2 node voltage is set to Vmid2, because in the pre-charging stage, the bit line voltage has been set to the power supply voltage VDD and programming is prohibited, so the bit line voltage is no longer affected by the voltage on the SO2 node.

[0269] When the verification result is that the threshold voltage is less than the programming verification voltage and the threshold voltage is greater than the first forced sensing voltage, the data in the node DS of the first latch 2312 after transmission is 1, the data in the node D1 in the dynamic latch 2330 is 1, and the data in D2 in the second latch 2322 is 0 (see Table 2).

[0270] At this time, QDS=0, P1 is turned on, and after the power supply voltage passes through the first bit line voltage setting component N5, when N5 applies the Vblbias2 signal Vmid1+vth, the SO2 node voltage is (Vmid1+vth)-vth=Vmid1; the data of D2 in the second latch 2322 is 0, when the Prech2 signal is applied to open P4, the SO node voltage becomes VDD, and after the power supply voltage passes through the second bit line voltage setting component N17, when N17 applies the Vblbias3 signal Vmid2+vth, the SO2 node voltage is set to Vmid2, because Vmid2 (provided by the second charge and discharge module) is greater than Vmid1 (provided by the first charge and discharge module) and because in the pre-charging stage, the bit line voltage has been set to the ground voltage Vss, so the bit line voltage is increased from the ground voltage (that is, the normal programming bit line voltage) to Vmid2.

[0271] When the verification result is that the threshold voltage is less than the first forced sensing voltage and the threshold voltage is greater than the second forced sensing voltage, the data in the node DS of the first latch 2312 after transmission is 1, the data in the node D1 in the dynamic latch 2330 is 1, and the data in D2 in the second latch 2322 is 1 (see Table 2).

[0272] At this time, QDS=0, P1 is turned on, and after the power supply voltage passes through the first bit line voltage setting component N5, when N5 applies the Vblbias2 signal of Vmid1+vth, the SO2 node voltage is set to (Vmid1+vth)-vth=Vmid1; when D2=1, the SO node is the ground voltage. Because Vmid1 (provided by the first charge and discharge module) is greater than the ground voltage (provided by the second charge and discharge module) and because the bit line voltage has been set to the ground voltage in the pre-charge stage, the bit line voltage is set to Vmid1.

[0273] When the verification result is that the threshold voltage is less than the third verification voltage, the data in the node DS of the first latch 2312 after transmission is 0, the data in the node D1 of the dynamic latch 2330 is 0, and the data in the D2 of the second latch 2322 is 1 (see Table 2).

[0274] The data of the node QDS of the first latch 2312 is 1, which turns on the NMOS transistor N2, which is connected to the ground voltage, so SO2 still maintains the ground voltage. When D2=1, the SO node is at the ground voltage and because the bit line voltage has been set to the ground voltage in the precharge stage, the bit line voltage remains unchanged at the ground voltage.

[0275] In the T3 phase, while setting the bit line voltage, a programming voltage is applied to the selected word line and a pass voltage is applied to the unselected word line. Then the next programming is performed on the memory cell. The disclosed embodiment also has the following examples:

[0276] Fig.13 The waveform diagram is a waveform diagram of various control signals applied to various components in a page buffer when a bit line forcing voltage is applied to a bit line of a memory cell according to another embodiment. The waveform diagram reflects a partial programming method process of a memory device.

[0277] In the case where the bit line voltage needs to be charged to Vmid2, that is, when the verification result is that the threshold voltage is less than the programming verification voltage and the threshold voltage is greater than or equal to the first forced sensing voltage, the bit line voltage setting phase T3 can be divided into two steps:

[0278] T3-1: first charge the gate voltage of the second bit line voltage setting component N17 to Vmid2-Vmid1+Vth. At this time, the bit line voltage is first charged to Vmid2-Vmid1.

[0279] T3-2: As in the aforementioned embodiment, the voltage of Vblbias2 is charged to Vmid1+vth-vth, and the voltage of Vblbias3 is charged from Vmid3-Vmid1+Vth to Vmid2+vth. The voltage settings of other components are the same as in the aforementioned embodiment.

[0280] By setting the bit line voltage in two steps, when the voltage of the control signal Vblbias2 applied to N5 rises to (Vmid1+vth), and when the voltage of the control signal Vblbias3 applied to N17 rises from Vmid3-Vmid1+Vth to Vmid2+vth, the voltage increases of the two are the same or similar, that is, the slope voltage intervals of the two are the same or similar, which can reduce the coupling between the bit lines.

[0281] The page buffer of the embodiment of the present disclosure may have one or more of the following advantages:

[0282] 1. The bit line voltage can be set to different levels and the sensing node still maintains sensing capability.

[0283] 2. The bit line voltage setting step can be divided into two or more steps, and the coupling between the bit lines can be reduced by precharging the bit line voltage to different intermediate voltages.

[0284] 3. During the programming process, one of at least four bit line voltages can be selected based on the verification result to perform bit line voltage biasing, so that the threshold voltage distribution range of multiple memory cells (for example, memory cells of a certain page being programmed) can be narrowed, so that there is more room for reading the memory cells, especially for TLC or QLC.

[0285] 4. It is also possible to add other data latch circuits and set more bit line forced voltages to make the target threshold voltage distribution range of the memory cell narrower until the programming requirements are met.

[0286] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial number of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0287] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0288] The above is only an embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A page buffer, characterized in that: The page buffer comprises: The first charge and discharge module comprises: a first charge and discharge circuit, a first latch and a first line voltage setting component; The first latch is connected to the first charge and discharge circuit and a first sensing node connected to the page buffer; The second charge and discharge module includes: a second charge and discharge circuit, a second latch and a second bit line voltage setting component; wherein the second charge and discharge circuit is connected to the second bit line voltage setting component via the first sensing node; and the second latch is connected to the second charge and discharge circuit.

2. The page buffer according to claim 1, wherein: The first latch and the second latch are of the same type.

3. The page buffer according to claim 1, wherein: The second latch comprises: a second data latch component; The second data setting unit is coupled to the second data latch unit.

4. The page buffer according to claim 3, wherein: The second data latch unit comprises a first inverter (I3) and a second inverter (I4) connected in parallel; The second data setting unit includes a first transistor (N9) coupled to an input terminal of the first inverter and a second transistor (N10) coupled to an input terminal of the second inverter.

5. The page buffer according to claim 1, wherein: The first charge and discharge module is configured to store first bit line forcing information and provide a first bit line forcing voltage to a bit line coupled to the page buffer according to the first bit line forcing information; The second charge and discharge module is configured to store second bit line forcing information and provide a second bit line forcing voltage different from the first bit line forcing voltage to the bit line according to the second bit line forcing information; Wherein, the first bit line forced voltage and the second bit line forced voltage are both greater than a normal programming bit line voltage and less than a programming inhibiting bit line voltage.

6. The page buffer according to claim 5, wherein: The page buffer further includes: The latch is coupled to the first sensing node and configured to temporarily store the first bit line forcing information.

7. The page buffer according to claim 5, wherein: The latch is of the same type as the first latch.

8. The page buffer according to claim 5, wherein: The programming prohibition bit line voltage is applied to the bit line corresponding to the programming prohibition memory cell, so as to prohibit the memory cell from being programmed; The normal programming bit line voltage is applied to the bit line corresponding to the memory cell to be programmed, so as to allow the memory cell to be first programmed; The first bit line forced voltage is applied to the bit line corresponding to the memory cell to be programmed to allow the memory cell to be second programmed; The second bit line forced voltage is applied to the bit line corresponding to the memory cell to be programmed, so as to allow the memory cell to be third programmed; The first programming degree is higher than the second programming degree, and the second programming degree is higher than the third programming degree.

9. The page buffer according to claim 5, wherein: The first charge and discharge circuit is connected to the power supply voltage and is connected to the second sensing node of the page buffer via the first bit line voltage setting unit and is connected to the bit line; the first charge and discharge circuit is configured to provide the power supply voltage to the first bit line voltage setting unit; the first latch being configured to store the first bit line forcing information; The first bit line voltage setting component connects the first charge and discharge circuit and the second sensing node so as to connect the bit line; the first bit line voltage setting component is configured to: apply the first bit line forcing voltage to the second sensing node connected to the bit line based on the power supply voltage according to the first bit line forcing information stored in the first latch.

10. The page buffer according to claim 9, wherein: The first charge and discharge circuit further includes: A first charging switch is connected to a power supply and the first bit line voltage setting component; a control electrode of the first charging switch is connected to the first latch; and the first charging switch is configured to provide a power supply voltage to the first bit line voltage setting component according to a signal output by the first latch.

11. The page buffer according to claim 9, wherein: The first latch comprises: a first data latch unit configured to store corresponding program verification information according to a program verification result, or configured to store the first bit line forcing information; The first data setting unit is connected to the first data latch unit, and the first data setting unit is configured to output the program verification information or the first bit line forcing information to be stored to the first data latch unit.

12. The page buffer according to claim 5, wherein: The second charge and discharge circuit is configured to provide a power supply voltage to the second bit line voltage setting unit; the second latch being configured to store the second bit line forcing information; The second bit line voltage setting component is connected to the second charge and discharge circuit and the second sensing node connected to the page buffer so as to be connected to the bit line. The second bit line voltage setting component is configured to apply the second bit line forcing voltage to the second sensing node connected to the bit line based on the power supply voltage according to the second bit line forcing information stored in the second latch.

13. The page buffer according to claim 12, wherein: The second charge and discharge circuit further includes: A second charging switch connects the power supply and the second bit line voltage setting component; the control electrode of the second charging switch is connected to the second latch; the second charging switch is configured to provide a power supply voltage to the second bit line voltage setting component according to a signal output by the second latch.

14. The page buffer according to claim 12, wherein: The second latch comprises: a second data latch unit configured to store the second bit line forcing information; The second data setting unit is connected to the second data latch unit; the second data setting unit is configured to output the second bit line forcing information to be stored to the second data latch unit.

15. The page buffer according to claim 6, wherein: The first charge and discharge module is further configured to store programming verification information; the first charge and discharge module is configured to provide a normal programming bit line voltage to the bit line when the programming verification information is in a state that programming is allowed; The latch is further configured to transfer the first bit line forcing information to the first charge and discharge module after the first charge and discharge module provides the normal programming bit line voltage to the bit line.

16. The page buffer according to claim 15, wherein: The latch comprises: a third data latch unit configured to store the first bit line forcing information; A third data setting unit is connected to the third data latch unit; the third data setting unit is configured to output the first bit line forcing information to be stored to the third data latch unit.

17. The page buffer according to claim 15, wherein: The first charge and discharge module is configured to provide a power supply voltage for prohibiting programming to the bit line when the program verification information indicates that programming is prohibited.

18. A method for operating a memory, characterized in that: The memory includes a page buffer, the page buffer is set corresponding to the bit line of the memory array of the memory device, and the page buffer includes a first charge and discharge module and a second charge and discharge module respectively connected to the first sensing node of the page buffer and connected to the bit line; the operation method includes: Providing a first bit line forced voltage to the bit line corresponding to the memory cell to be programmed according to the first bit line forced information stored in the first charge and discharge module; Providing a second bit line forcing voltage to a bit line corresponding to a memory cell to be programmed according to second bit line forcing information stored in the second latch in the second charging and discharging module; Wherein, the first bit line forced voltage and the second bit line forced voltage are both greater than the normal programming bit line voltage and less than the programming inhibiting bit line voltage; The memory cells to be programmed are programmed to different degrees based on the first bit line forcing voltage and the second bit line forcing voltage.

19. The programming method according to claim 18, characterized in that: The step of providing a first bit line forced voltage to the bit line corresponding to the memory cell to be programmed according to the first bit line forced information stored in the first charge and discharge module comprises: After verifying the first bit line sensing voltage of the memory cell to be programmed, storing the first bit line forcing information by using the first latch in the first charge and discharge module; Using the first charge and discharge circuit in the first charge and discharge module to provide a power supply voltage to the first line voltage setting component in the first charge and discharge module; The first bit line voltage setting unit is used to apply a first bit line forcing voltage to a second sensing node connected to the bit line corresponding to the memory cell to be programmed based on the power supply voltage according to the first bit line forcing information.

20. The programming method according to claim 19, characterized in that: The method of using the first charge-discharge circuit in the first charge-discharge module to provide a power supply voltage to the first line voltage setting component includes: A power supply voltage is provided to the first bit line voltage setting unit through a first charging switch in the first charging and discharging circuit according to a signal output by the first latch.

21. The programming method according to claim 18, characterized in that: The step of providing a second bit line forced voltage to a bit line corresponding to a memory cell to be programmed according to the second bit line forced information stored in the second charge and discharge module comprises: After verifying the second bit line sensing voltage of the memory cell to be programmed, storing the second bit line forcing information by using the second latch in the second charge and discharge module; Using a second charge and discharge circuit in the second charge and discharge module to provide a power supply voltage to a second bit line voltage setting component in the second charge and discharge module; The second bit line voltage setting unit is used to apply a second bit line forcing voltage to a second sensing node connected to the bit line corresponding to the memory cell to be programmed based on the power supply voltage according to the second bit line forcing information.

22. The programming method according to claim 21, characterized in that: The method of using the second charge and discharge circuit in the second charge and discharge module to provide a power supply voltage to the second bit line voltage setting component includes: A power supply voltage is provided to the second bit line voltage setting unit through a second charging switch in the second charging and discharging circuit according to a signal output by the second latch.

23. The method according to any one of claims 18 to 22, characterized in that: The method further comprises: Using a first charge and discharge module to store programming verification information, and providing a normal programming bit line voltage to the bit line when the programming verification information indicates that the first programming is allowed; After the first charge and discharge module provides the normal programming bit line voltage to the bit line, the latch in the page buffer transmits the first bit line forcing information to the first charge and discharge module.

24. The method according to claim 17, characterized in that The method further comprises: In a state where the program verification information indicates program inhibition, a power supply voltage for program inhibition is supplied to the bit line.

25. A memory device, characterized in that: The memory device comprises: a memory cell array having a plurality of memory cell strings and a plurality of bit lines connected to the plurality of memory cell strings; and A peripheral circuit coupled to the memory cell array through the bit lines and used for the memory cell array to operate; The peripheral circuit includes a plurality of page buffers according to any one of claims 1 to 17, and the page buffers are connected to corresponding bit lines via sensing nodes.

26. A memory system, characterized in that: The memory system comprises: One or more memory devices as claimed in claim 25; and A memory controller is coupled to the memory device and configured to control the memory device.

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