Packaging method and packaging structure

Abstract

The invention discloses a packaging method and a packaging structure, and the method comprises the steps: providing a substrate which comprises a chip region and a non-chip region, and comprises a first side and a second side which are opposite to each other; a chip is provided, the chip is arranged on the first side of the substrate, and the chip is located in the chip area; an isolation film is formed on the first side of the substrate, the isolation film covers the first side surface of the non-chip area and the side wall surface and the top surface of the chip, and the isolation film extends to the first side surface of the non-chip area from the side wall surface of the chip; a packaging layer is formed on the first side of the substrate, the packaging layer covers the surface of the isolation film, and the method for forming the packaging layer comprises the steps that the dosage of a packaging material is obtained according to the thickness of the chip and the thickness of the isolation film, and the packaging layer is formed through a compression molding technology. The thickness consistency of the packaging structure formed by the packaging method is improved, the reliability of the packaging structure is high, the size of the packaging structure can be regulated and controlled, and miniaturization of the packaging structure is facilitated.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a packaging method and a packaging structure. Background Art

[0002] The RF (Radio Frequency, referred to as RF) front-end chips of wireless communication equipment include power amplifiers, antenna switches, RF filters, multiplexers and low noise amplifiers, etc. Among them, RF filters include piezoelectric surface acoustic wave (Surface Acoustic Wave, referred to as SAW) filters, piezoelectric bulk acoustic wave (Bulk Acoustic Wave, referred to as BAW) filters, micro-electro-mechanical system (Micro-Electro-Mechanical System, referred to as MEMS) filters, integrated passive devices (Integrated Passive Devices, referred to as IPD) filters, etc.

[0003] As wireless communication technology gradually evolves, the scope of use of wireless communication equipment becomes wider and wider, and the requirements for the size and reliability of filters are becoming higher and higher. Piezoelectric surface acoustic wave filters are currently the most widely used filters in wireless communication equipment, and their small size and high reliability packaging form are becoming more and more widely used.

[0004] Therefore, there is a need for continuous improvement of filters with smaller sizes. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a packaging method and a packaging structure to improve the size of the filter.

[0006] To solve the above technical problems, the technical solution of the present invention provides a packaging method, comprising: providing a substrate, the substrate comprising a chip area and a non-chip area, the substrate comprising a first side and a second side opposite to each other; providing a chip, the chip being arranged on the first side of the substrate, the chip being located in the chip area; forming an isolation film on the first side of the substrate, the isolation film covering the first side surface of the non-chip area, the side wall surface and the top surface of the chip, the isolation film extending from the side wall surface of the chip to the first side surface of the non-chip area; forming a packaging layer on the first side of the substrate, the packaging layer covering the surface of the isolation film, the method for forming the packaging layer comprising: obtaining the amount of packaging material according to the thickness of the chip and the thickness of the isolation film, and forming the packaging layer by a molding process.

[0007] Optionally, forming an isolation film on the first side of the substrate includes: laminating an initial isolation film on the first side of the substrate; and curing the initial isolation film to form the isolation film.

[0008] Optionally, the material of the isolation film includes an organic material, and the organic material includes epoxy resin.

[0009] Optionally, the thickness of the isolation film ranges from 20 microns to 100 microns.

[0010] Optionally, the material of the encapsulation layer includes: an organic material containing inorganic particles, the organic material includes epoxy resin, and the material of the inorganic particles includes silicon oxide or carbon black.

[0011] Optionally, the first side surface of the substrate to the top surface of the packaging layer has a preset first thickness, and obtaining the amount of packaging material includes: obtaining the area of ​​the chip surface and the thickness of the chip; and obtaining the first mass of packaging material required for the chip area surface based on the area of ​​the chip, the thickness of the chip, the thickness of the isolation film and the preset first thickness.

[0012] Optionally, obtaining the amount of packaging material used also includes: obtaining the area of ​​the surface of the non-chip area, and obtaining the second mass of the required packaging material on the surface of the non-chip area based on the area of ​​the non-chip area, the thickness of the isolation film, and the preset first thickness.

[0013] Optionally, the chip includes at least a first chip and a second chip, and a thickness of the first chip is different from a thickness of the second chip.

[0014] Optionally, the flatness of the top surface of the packaging layer is within a preset range, including: the top surface of the packaging layer includes a first surface corresponding to the first chip and a second surface corresponding to the second chip, and the absolute value of the height difference between the first surface and the second surface is less than or equal to 1 micron.

[0015] Correspondingly, the technical solution of the present invention provides a packaging structure, including: a substrate, the substrate including a chip area and a non-chip area, the substrate including a first side and a second side opposite to each other; a chip arranged on the first side of the substrate, the chip being located in the chip area; an isolation film located on the first side of the substrate, the isolation film covering the first side surface of the non-chip area, the side wall surface and the top surface of the chip, the isolation film extending from the side wall surface of the chip to the first side surface of the non-chip area; an encapsulation layer located on the first side of the substrate, the encapsulation layer covering the surface of the isolation film, the encapsulation layer being formed by a molding process, and the thickness of the encapsulation layer being determined based on the thickness of the chip and the thickness of the isolation film.

[0016] Optionally, the material of the isolation film includes an organic material, and the organic material includes epoxy resin.

[0017] Optionally, the thickness of the isolation film ranges from 20 microns to 100 microns.

[0018] Optionally, the material of the encapsulation layer includes: an organic material containing inorganic particles, the organic material includes epoxy resin, and the material of the inorganic particles includes silicon oxide or carbon black.

[0019] Optionally, the chip includes at least a first chip and a second chip, and a thickness of the first chip is different from a thickness of the second chip.

[0020] Optionally, the flatness of the top surface of the packaging layer is within a preset range, including: the top surface of the packaging layer includes a first surface corresponding to the first chip and a second surface corresponding to the second chip, and the absolute value of the height difference between the first surface and the second surface is less than or equal to 1 micron.

[0021] Optionally, the chip includes a power amplifier chip, an antenna switch chip, a radio frequency filter chip, a multiplexer chip or a low noise amplifier chip; the radio frequency filter chip includes a piezoelectric surface acoustic wave filter chip, a piezoelectric bulk acoustic wave filter chip, a micro-electromechanical system filter chip or an integrated passive device filter chip.

[0022] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0023] The packaging method of the present invention first forms an isolation film covering the chip on the first side of the substrate, then obtains the amount of packaging material according to the thickness of the chip and the thickness of the isolation film, and adopts a molding process to form a packaging layer covering the isolation film, so that the flatness of the top surface of the formed packaging layer is within a preset range, the thickness consistency and controllability of the packaging structure are improved, the surface uniformity of the packaging structure is improved, and the application is more extensive; in addition, the isolation film extends from the side wall surface of the chip to the first side surface of the non-chip area, and the isolation film can protect the functional surface of the chip to prevent water vapor and the packaging layer from entering between the chip and the substrate, thereby causing damage to the functional surface of the chip.

[0024] Furthermore, the first mass of the packaging material required on the surface of the chip area is obtained according to the area of ​​the chip, the thickness of the chip, the thickness of the isolation film, and the preset first thickness, and the second mass of the packaging material required on the surface of the non-chip area is obtained according to the area of ​​the non-chip area, the thickness of the isolation film, and the preset first thickness. The amount of packaging material can be adjusted in real time according to the chip size and the preset packaging thickness to ensure that the thickness of the packaging structure in different chip areas is within a consistent range, so that the thickness of the packaging layer can be accurately controlled, the thickness uniformity of the packaging structure is improved, and the size of the packaging structure can be adjusted, which is conducive to the miniaturization of the packaging structure.

[0025] The packaging structure of the present invention has an isolation film covering the chip and an encapsulation layer covering the surface of the isolation film on the first side of the substrate. The flatness of the top surface of the encapsulation layer is within a preset range, the thickness consistency and controllability of the packaging structure are improved, the surface uniformity of the packaging structure is improved, and the application is more extensive; in addition, the isolation film extends from the side wall surface of the chip to the first side surface of the non-chip area, and the isolation film can protect the functional surface of the chip, preventing water vapor and the encapsulation layer from entering between the chip and the substrate, thereby causing damage to the functional surface of the chip. Under the dual protection of the isolation film and the encapsulation layer, the pressure resistance and waterproof performance of the packaging structure can be improved, and the reliability of the packaging structure is better. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 and Figure 2 is a structural schematic diagram of a packaging method in an embodiment;

[0027] Figures 3 to 7 It is a structural schematic diagram of the packaging method in an embodiment of the present invention. DETAILED DESCRIPTION

[0028] As described in the background art, it is necessary to continuously improve the filter to a smaller size. Now, an analysis and explanation will be given in conjunction with a specific embodiment.

[0029] Figure 1 and Figure 2 It is a structural schematic diagram of a packaging method in an embodiment.

[0030] Please refer to Figure 1 , providing a substrate 100, wherein the substrate 100 includes a chip area and a non-chip area, and the substrate 100 includes a first side and a second side opposite to each other; providing a chip, wherein the chip is arranged on the first side of the chip area, and the chip includes a first chip 101 and a second chip 102, and the thickness of the first chip 101 is less than the thickness of the second chip 102; providing a packaging pretreatment layer 103.

[0031] Please refer to Figure 2 A packaging pretreatment layer 103 is attached to the first side surface of the substrate 100 by a film attaching machine, and a packaging layer 104 is formed on the first side surface of the substrate 100. The top surface of the packaging layer 104 located on the second chip 102, the top surface located on the first chip 101, and the top surface located on the non-chip area have different distances from the first side surface of the substrate 100. The top surface of the packaging layer 104 located on the second chip 102 is higher than the top surface located on the first chip 101.

[0032] The material of the encapsulation pre-processing layer 103 includes epoxy resin. When the encapsulation pre-processing layer 103 is attached to the surface of the first side of the substrate 100 by a laminating machine, a soft silicone airbag is used to apply pressure to the encapsulation pre-processing layer 103. The encapsulation pre-processing layer 103 is deformed under the action of temperature and pressure and then attached to the first side of the substrate 100 to form the encapsulation layer 104. The pressure applied by the soft silicone airbag to the encapsulation pre-processing layer 103 will not be too large, so as to prevent the material of the encapsulation pre-processing layer 103 from entering between the chip and the first side of the substrate 100 and causing a backlog on the chip surface, thereby affecting the performance of the chip.

[0033] Therefore, the result of using a film laminating machine to laminate the encapsulation pretreatment layer 103 on the first side surface of the substrate 100 is that the top surface of the encapsulation layer 104 located on the second chip 102, the top surface located on the first chip 101, and the top surface located on the non-chip area are at different distances from the first side surface of the substrate 100, and the thickness of the chip encapsulation structure is not easy to control to a uniform value. There are height differences between different products, and the surface morphology is uneven, which is not conducive to the subsequent application of the chip. In addition, the encapsulation pretreatment layer 103 is an epoxy resin film layer with a certain thickness, and the material cost is relatively high.

[0034] In order to solve the above problems, the technical solution of the present invention provides a packaging method and a packaging structure, firstly, an isolation film covering the chip is formed on the first side of the substrate, and then the amount of packaging material is obtained according to the thickness of the chip and the thickness of the isolation film, and a packaging layer covering the isolation film is formed by a molding process, so that the flatness of the top surface of the formed packaging layer is within a preset range, the thickness consistency and controllability of the packaging structure are improved, the surface uniformity of the packaging structure is improved, and the application is more extensive; in addition, the isolation film extends from the side wall surface of the chip to the first side surface of the non-chip area, and the isolation film can protect the functional surface of the chip to prevent water vapor and the packaging layer from entering between the chip and the substrate, thereby causing damage to the functional surface of the chip.

[0035] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0036] Figures 3 to 7 It is a structural schematic diagram of the packaging method in an embodiment of the present invention.

[0037] Please refer to Figure 3 , providing a substrate 200, wherein the substrate 200 includes a chip region I and a non-chip region II, and the substrate 200 includes a first side and a second side opposite to each other.

[0038] The substrate 200 has a plurality of circuit structures therein, providing structural support and circuit connections for electrically connecting a plurality of chips together.

[0039] In this embodiment, the substrate 200 includes a PCB board. In other embodiments, the substrate may not include a circuit structure, and the substrate may be other implementable substrates.

[0040] Please continue to refer to Figure 3 , providing a chip, and disposing the chip on the first side of the substrate, wherein the chip is located in the chip area I. The chip is electrically connected to the substrate 200.

[0041] The chips include at least a first chip and a second chip, and a thickness of the first chip is different from a thickness of the second chip.

[0042] The chip includes a functional surface and a non-functional surface, wherein the functional surface faces the first side surface of the substrate 200 , and a gap exists between the functional surface and the first side of the substrate 200 .

[0043] In this embodiment, the chip includes a first chip 201 and a second chip 202 , and the thickness of the first chip 201 is smaller than the thickness of the second chip 202 .

[0044] In this embodiment, the difference between the thickness of the second chip 202 and the thickness of the first chip 201 ranges from 100 micrometers to 600 micrometers.

[0045] In this embodiment, a first distance exists between the functional surface of the first chip 201 and the first side surface of the substrate 200 ; a second distance exists between the functional surface of the second chip 202 and the first side surface of the substrate 200 .

[0046] Please continue to refer to Figure 3 , further comprising: forming a connection layer on the surface of the chip functional surface, wherein the chip is fixed to the first side of the substrate 200 through the connection layer.

[0047] In this embodiment, the first chip 201 is fixed and electrically connected to the first side of the substrate 200 through the first connecting layer 210, and there is a gap between the functional surface of the first chip 201 and the first side of the substrate 200; the second chip 202 is fixed and electrically connected to the first side of the substrate 200 through the second connecting layer 211, and there is a gap between the functional surface of the second chip 202 and the first side of the substrate 200.

[0048] In this embodiment, the material of the first connection layer 210 and the second connection layer 211 includes solder.

[0049] The chip includes a power amplifier chip, an antenna switch chip, a radio frequency filter chip, a multiplexer chip or a low noise amplifier chip; the radio frequency filter chip includes a piezoelectric surface acoustic wave filter chip, a piezoelectric bulk acoustic wave filter chip, a micro-electromechanical system filter chip or an integrated passive device filter chip.

[0050] In this embodiment, the first chip 201 includes one of the above chips, the second chip 202 includes one of the above chips, and the first chip 201 and the second chip 202 may be the same or different.

[0051] Please refer to Figure 4 An isolation film 203 is formed on the first side of the substrate 200, and the isolation film 203 covers the first side surface of the non-chip area II, the side wall surface and the top surface of the chip, and the isolation film 203 extends from the side wall surface of the chip to the first side surface of the non-chip area II.

[0052] In this embodiment, the isolation film 203 covers the first side surface of the non-chip area II, the side wall surface and the top surface of the first chip 201, and the side wall surface and the top surface of the second chip 202. The isolation film 203 extends from the side wall surface of the first chip 201 to the first side surface of the non-chip area II, and extends from the side wall surface of the second chip 202 to the first side surface of the non-chip area II.

[0053] The isolation film 203 extends from the side wall surface of the chip to the first side surface of the non-chip area II, that is, the isolation film 203 does not cover the gap between the chip and the first side of the substrate 200, so as to avoid the packaging layer formed subsequently being formed in the gap between the first side of the substrate 200, which may cause the packaging layer to squeeze the functional surface of the chip.

[0054] The isolation film 203 is formed on the first side surface of the substrate 200 , including: using a film laminating machine to laminate an initial isolation film (not shown) on the first side surface of the substrate 200 ; and curing the initial isolation film to form the isolation film 203 .

[0055] In this embodiment, the method of curing the initial isolation film includes heating treatment, and the temperature range of the heating treatment is: 100 degrees Celsius to 200 degrees Celsius.

[0056] The material of the isolation film 203 includes organic material. The initial isolation film is a material film with a certain thickness, which is easily deformed under pressure and solidifies under a preset temperature state, so that the initial isolation film can be applied to the occasion where it is needed by using a film sticking machine.

[0057] In this embodiment, the organic material includes epoxy resin. The epoxy resin has a certain degree of ductility, which facilitates the laminating machine to extrude and heat the initial isolation film, so that the initial isolation film is formed into an isolation film of a preset shape.

[0058] In other embodiments, the material of the isolation film includes other feasible organic materials.

[0059] In this embodiment, the thickness of the isolation film 203 is less than the thickness of the subsequently formed encapsulation layer. In other embodiments, the relative thickness of the isolation film and the encapsulation layer may have other situations, for example, the thickness of the isolation film is greater than or equal to the thickness of the encapsulation layer.

[0060] In this embodiment, the thickness of the isolation film 203 ranges from 20 micrometers to 100 micrometers.

[0061] In other embodiments, the isolation film may not be formed.

[0062] Next, a packaging layer is formed on the first side of the substrate 200, and the packaging layer covers the surface of the isolation film 203. The method for forming the packaging layer includes: obtaining the amount of packaging material according to the thickness of the chip and the thickness of the isolation film 203, and forming the packaging layer by a molding process. The formation process of the packaging layer can be found in Figures 5 to 7 .

[0063] There is a preset first thickness from the first side surface of the substrate 200 to the top surface of the packaging layer. The preset first thickness is the thickness from the top surface of the packaging layer to the first side of the substrate 200 of the packaging structure formed by subsequent demolding and curing. The preset first thickness can be set according to actual needs.

[0064] Please refer to Figure 5, providing a mold 300; filling a preset amount of packaging material 301 into the mold 300; heating the mold 300 to melt the packaging material 301 into a molten state.

[0065] In this embodiment, the material of the mold 300 includes steel or tungsten steel; the hardness of the material of the mold 300 is greater than the hardness of the molten packaging material 301. The bottom surface of the mold 300 is a plane.

[0066] In this embodiment, the temperature range for heating the mold 300 is 50 degrees Celsius to 300 degrees Celsius. Preferably, the temperature range for heating the mold 300 is 70 degrees Celsius.

[0067] In this embodiment, obtaining the amount of packaging material used includes: obtaining the area of ​​the chip surface and the thickness of the chip; and obtaining the first mass of packaging material required for the surface of the chip region I based on the area of ​​the chip, the thickness of the chip, the thickness of the isolation film 203 and the preset first thickness.

[0068] In this embodiment, the first quality of the packaging material required for the surface of the chip area I is obtained according to the area of ​​the chip, the thickness of the chip, the thickness of the isolation film 203 and the preset first thickness. The packaging material includes: a preset first thickness from the first side of the substrate 200 to the top surface of the packaging layer, the isolation film 203 has a second thickness, and there is a spacing between the functional surface of the chip and the first side of the substrate 200; the thickness of the packaging layer on the chip surface is obtained according to the difference between the preset first thickness and the second thickness, the thickness of the chip, and the spacing between the chip and the first side of the substrate 200; the first quality of the packaging material on the chip surface is obtained according to the thickness of the packaging layer on the chip surface, the area of ​​the chip and the density of the packaging material.

[0069] In this embodiment, obtaining the amount of packaging material used also includes: obtaining the area of ​​the surface of the non-chip area II, and obtaining the second mass of the required packaging material on the surface of the non-chip area II based on the area of ​​the non-chip area II, the thickness of the isolation film 203, and the preset first thickness.

[0070] The second mass of the required packaging material on the surface of the non-chip area II is obtained according to the area of ​​the non-chip area II, the thickness of the isolation film 203, and the preset first thickness, including: obtaining the thickness of the packaging layer on the surface of the non-chip area II according to the difference between the preset first thickness and the second thickness; obtaining the second mass of the packaging material on the surface of the non-chip area II according to the thickness of the packaging layer on the surface of the non-chip area II, the area of ​​the non-chip area II and the density of the packaging material.

[0071] In this embodiment, the area of ​​the surface of the non-chip region II and the area of ​​the chip surface are automatically scanned and measured using a scanner, so the degree of automation is improved and the result is more accurate.

[0072] Please refer to Figure 7 In this embodiment, the chip includes a first chip 201 and a second chip 202, and obtaining the first quality of the packaging material required on the surface of the chip area I includes: obtaining the quality of the packaging material required on the surface of the first chip 201, and obtaining the quality of the packaging material required on the surface of the second chip 202.

[0073] The thickness of the first chip 201 is less than that of the second chip 202. The first chip 201 has a thickness h1, and the second chip 202 has a thickness h2. An isolation film 203 is formed on the first side of the substrate 200. The first side surface of the substrate 200 to the top surface of the packaging layer has a preset first thickness d1 (reference Figure 7 ), the isolation film 203 on the surface of the first chip 201 has a second thickness d2 to the first side of the substrate 200; the surface of the first chip 201 has a first area S1 (corresponding to the surface area of ​​the first chip 201 covered with the isolation film 203), the surface of the second chip 202 has a second area S2 (corresponding to the surface area of ​​the second chip 202 covered with the isolation film 203), the surface of the non-chip area II has a third area S3 (corresponding to the surface area of ​​the non-chip area II covered with the isolation film 203), the packaging material has a density ρ, the first chip 201 functional surface and the first side surface of the substrate 200 have a first spacing t1, and the second chip 202 functional surface and the first side surface of the substrate 200 have a second spacing t2.

[0074] The thickness H1=d1-d2-h1-t1 of the packaging layer on the surface of the first chip 201 is obtained according to the first thickness d1, the second thickness d2 of the isolation film 203, the thickness h1 of the first chip 201, and the first spacing t1; the mass m of the packaging material required on the surface of the first chip 201 is obtained according to the first area S1 of the surface of the first chip 201, the thickness H1 of the packaging layer on the surface of the first chip 201, and the density ρ of the packaging material 11 =H1×s1×ρ.

[0075] The thickness H2=d1-d2-h2-t2 of the packaging layer on the surface of the second chip 202 is obtained according to the first thickness d1, the second thickness d2 of the isolation film 203, the thickness h2 of the second chip 202, and the second spacing t2; the mass m of the packaging material required on the surface of the second chip 202 is obtained according to the second area S2 of the surface of the second chip 202, the thickness H2 of the packaging layer on the surface of the second chip 202, and the density ρ of the packaging material12 =H2×s2×ρ.

[0076] According to the mass m of the packaging material required on the surface of the first chip 201 11 The mass m of the packaging material required for the surface of the second chip 202 12 Get the first mass m1 of the packaging material required on the surface of chip area I = m 11 +m 12 .

[0077] According to the difference between the preset first thickness and the second thickness, the thickness of the packaging layer on the surface of the non-chip area II is obtained; according to the thickness of the packaging layer on the surface of the non-chip area II, the area of ​​the non-chip area II and the first density, the second mass of the packaging material on the surface of the non-chip area II is obtained.

[0078] According to the difference between the first thickness d1 and the second thickness d2 of the isolation film 203, the thickness H3 = d1-d2 of the encapsulation layer on the surface of the non-chip area II is obtained; according to the thickness H3 of the encapsulation layer on the surface of the non-chip area II, the third area s3 of the surface of the non-chip area II and the density ρ of the encapsulation material, the second mass m2 = H3×s3×ρ of the encapsulation material on the surface of the non-chip area II is obtained.

[0079] The sum of the first mass m1 and the second mass m2 is the total mass of the packaging material subsequently formed on the first side of the substrate 200. The amount of packaging material 301 that actually needs to be filled in the mold 300 is obtained by conversion based on the correspondence between the deformation, mass loss, and volume curing shrinkage rate that occur when the packaging material 301 is melted and solidified to form a packaging layer.

[0080] The amount of mold packaging material 301 is adjusted in real time according to the chip size and the preset packaging thickness to ensure that the thickness of the packaging structure in different chip areas is within a consistent range, so that the thickness of the packaging layer can be accurately controlled, the thickness uniformity of the packaging structure is improved, and the size of the packaging structure can be controlled, which is conducive to the miniaturization of the packaging structure.

[0081] Please refer to Figure 6 , the mold 300 and the first side of the substrate 200 are pressed together under vacuum conditions so that the first side of the substrate 200 is immersed in the molten packaging material 301; pressure is applied to the substrate 200 and the mold 300 so that the first side of the substrate 200 and the mold 300 are tightly fitted under pressure to form an initial packaging layer 302.

[0082] In this embodiment, the first side of the substrate 200 is immersed in the molten packaging material 301 , that is, the isolation film 203 on the first side of the substrate 200 is in contact with the packaging material 301 , and the first chip 201 and the second chip 202 are both immersed in the molten packaging material 301 .

[0083] The hardness of the mold 300 material is greater than the hardness of the molten packaging material 301, so that when pressure is applied to the substrate 200 and the mold 300, the packaging material 301 is easily deformed under the pressure state, so that the packaging material 301 is leveled on the first side of the substrate 200, so that the top surface of the formed initial packaging layer 302 on the surface of each area on the first side of the substrate 200 is basically flat.

[0084] The material of the initial encapsulation layer 302 is different from the material of the isolation film 203 .

[0085] The material of the initial encapsulation layer 302 includes: an organic material containing inorganic particles. The organic material contains inorganic particles, and the inorganic particles can play a supporting role to prevent the initial encapsulation layer 302 from shrinking too much after subsequent solidification and cooling.

[0086] In this embodiment, the organic material includes epoxy resin, and the material of the inorganic particles includes silicon oxide or carbon black.

[0087] In this embodiment, the first side of the substrate 200 has an isolation film 203 covering the chip, and the initial packaging layer 302 covers the isolation film 203. The isolation film 203 can protect the functional surface of the chip, prevent water vapor from invading the functional surface of the chip, and avoid the initial packaging layer 302 from entering between the chip and the substrate under pressure, thereby causing damage to the functional surface of the chip. For example, when the chip is a SAW chip, the initial packaging layer 302 enters between the chip and the substrate under pressure, which will squeeze the fingers of the SAW chip and affect the performance of the SAW chip. In addition, the isolation film 203 and the subsequently formed packaging layer are formed on the first side of the substrate 200. Under the dual protection of the isolation film 203 and the packaging layer, the pressure resistance and waterproof performance of the packaging structure can be improved, and the formed packaging structure has better reliability.

[0088] Please refer to Figure 7 After the initial encapsulation layer 302 is formed, the substrate 200 is demolded; the demolded substrate 200 and the initial encapsulation layer 302 on the substrate 200 are cured to form the encapsulation layer 303.

[0089] The demolded substrate 200 and the initial encapsulation layer 302 on the substrate 200 are cured, including: heat treating the initial encapsulation layer 302, wherein the process parameters of the heat treatment include: a temperature range of 100 degrees Celsius to 200 degrees Celsius, and a heating time range of 1 hour to 5 hours.

[0090] In this embodiment, the flatness of the top surface of the encapsulation layer 303 is within a preset range. The thickness consistency and controllability of the encapsulation structure are improved, the surface uniformity of the encapsulation structure is improved, and the application is more extensive.

[0091] The flatness of the top surface of the packaging layer 303 is within a preset range, including: the top surface of the packaging layer 303 includes a first surface corresponding to the first chip 201 and a second surface corresponding to the second chip 202, and the absolute value of the height difference between the first surface and the second surface is less than or equal to 1 micron.

[0092] Accordingly, the embodiment of the present invention further provides a packaging structure, please continue to refer to Figure 7 , the packaging structure comprises:

[0093] A substrate 200, wherein the substrate 200 includes a chip region I and a non-chip region II, and the substrate 200 includes a first side and a second side opposite to each other;

[0094] A chip disposed on the first side of the substrate 200, wherein the chip is located in the chip area I;

[0095] An isolation film 203 located on the first side of the substrate 200, the isolation film 203 covers the first side surface of the non-chip region II, the side wall surface and the top surface of the chip, and the isolation film 203 extends from the side wall surface of the chip to the first side surface of the non-chip region II;

[0096] The encapsulation layer 303 is located on the first side of the substrate, and covers the surface of the isolation film 203 . The encapsulation layer 303 is formed by a compression molding process, and the thickness of the encapsulation layer 303 is determined based on the thickness of the chip and the thickness of the isolation film 203 .

[0097] In this embodiment, the material of the isolation film 203 includes an organic material, and the organic material includes epoxy resin.

[0098] In this embodiment, the thickness of the isolation film 203 ranges from 20 micrometers to 100 micrometers.

[0099] In this embodiment, the material of the encapsulation layer 303 includes: an organic material containing inorganic particles, the organic material includes epoxy resin, and the material of the inorganic particles includes silicon oxide or carbon black.

[0100] In this embodiment, the chip includes at least a first chip 201 and a second chip 202 , and the thickness of the first chip 201 is different from the thickness of the second chip 202 .

[0101] In this embodiment, the flatness of the top surface of the packaging layer 303 is within a preset range, including: the top surface of the packaging layer 303 includes a first surface corresponding to the first chip 201 and a second surface corresponding to the second chip 202, and the absolute value of the height difference between the first surface and the second surface is less than or equal to 1 micron.

[0102] In this embodiment, the chip includes a power amplifier chip, an antenna switch chip, a radio frequency filter chip, a multiplexer chip or a low noise amplifier chip; the radio frequency filter chip includes a piezoelectric surface acoustic wave filter chip, a piezoelectric bulk acoustic wave filter chip, a micro-electromechanical system filter chip or an integrated passive device filter chip.

[0103] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A packaging method, characterized in that: include: Providing a substrate, the substrate comprising a chip area and a non-chip area, the substrate comprising a first side and a second side opposite to each other; Providing a chip, and disposing the chip on the first side of the substrate, wherein the chip is located in the chip area; An isolation film is formed on the first side of the substrate, the isolation film covers the first side surface of the non-chip area, the side wall surface and the top surface of the chip, and the isolation film extends from the side wall surface of the chip to the first side surface of the non-chip area; A packaging layer is formed on the first side of the substrate, the packaging layer covers the surface of the isolation film, and the method for forming the packaging layer includes: obtaining the amount of packaging material according to the thickness of the chip and the thickness of the isolation film, and forming the packaging layer by a molding process.

2. The packaging method according to claim 1, characterized in that: Forming an isolation film on the first side of the substrate includes: laminating an initial isolation film on the first side of the substrate; and curing the initial isolation film to form the isolation film.

3. The packaging method according to claim 1, characterized in that: The material of the isolation film includes an organic material, and the organic material includes epoxy resin.

4. The packaging method according to claim 1, characterized in that: The thickness of the isolation film ranges from 20 micrometers to 100 micrometers.

5. The packaging method according to claim 1, characterized in that: The material of the encapsulation layer includes: an organic material containing inorganic particles, the organic material includes epoxy resin, and the material of the inorganic particles includes silicon oxide or carbon black.

6. The packaging method according to claim 1, characterized in that: The first side surface of the substrate to the top surface of the packaging layer has a preset first thickness, and obtaining the amount of packaging material includes: obtaining the area of ​​the chip surface and the thickness of the chip; and obtaining the first mass of packaging material required for the chip area surface based on the area of ​​the chip, the thickness of the chip, the thickness of the isolation film and the preset first thickness.

7. The packaging method according to claim 6, characterized in that: The method of obtaining the amount of packaging material used also includes: obtaining the area of ​​the non-chip area surface, and obtaining the second mass of the packaging material required on the non-chip area surface according to the area of ​​the non-chip area, the thickness of the isolation film, and the preset first thickness.

8. The packaging method according to claim 1, characterized in that: The chips include at least a first chip and a second chip, and a thickness of the first chip is different from a thickness of the second chip.

9. The packaging method according to claim 8, characterized in that: The flatness of the top surface of the packaging layer is within a preset range, including: the top surface of the packaging layer includes a first surface corresponding to the first chip and a second surface corresponding to the second chip, and the absolute value of the height difference between the first surface and the second surface is less than or equal to 1 micron.

10. A packaging structure, characterized in that: include: A substrate, the substrate comprising a chip area and a non-chip area, the substrate comprising a first side and a second side opposite to each other; A chip disposed on the first side of the substrate, the chip being located in the chip area; an isolation film located on the first side of the substrate, the isolation film covering the first side surface of the non-chip area, the side wall surface and the top surface of the chip, and the isolation film extending from the side wall surface of the chip to the first side surface of the non-chip area; The encapsulation layer is located on the first side of the substrate, the encapsulation layer covers the surface of the isolation film, the encapsulation layer is formed by a compression molding process, and the thickness of the encapsulation layer is determined based on the thickness of the chip and the thickness of the isolation film.

11. The packaging structure according to claim 10, characterized in that: The material of the isolation film includes an organic material, and the organic material includes epoxy resin.

12. The packaging structure according to claim 10, characterized in that: The thickness of the isolation film ranges from 20 micrometers to 100 micrometers.

13. The packaging structure according to claim 10, characterized in that: The material of the encapsulation layer includes: an organic material containing inorganic particles, the organic material includes epoxy resin, and the material of the inorganic particles includes silicon oxide or carbon black.

14. The packaging structure according to claim 10, characterized in that: The chips include at least a first chip and a second chip, and a thickness of the first chip is different from a thickness of the second chip.

15. The packaging structure according to claim 14, characterized in that: The flatness of the top surface of the packaging layer is within a preset range, including: the top surface of the packaging layer includes a first surface corresponding to the first chip and a second surface corresponding to the second chip, and the absolute value of the height difference between the first surface and the second surface is less than or equal to 1 micron.

16. The packaging structure according to claim 10, characterized in that: The chip includes a power amplifier chip, an antenna switch chip, a radio frequency filter chip, a multiplexer chip or a low noise amplifier chip; the radio frequency filter chip includes a piezoelectric surface acoustic wave filter chip, a piezoelectric bulk acoustic wave filter chip, a micro-electromechanical system filter chip or an integrated passive device filter chip.

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