Noise isolation device and chip
By laying a polysilicon POLY layer on the N-type and P-type protection rings of the chip to generate the target capacitor, the problem of low noise isolation efficiency of the chip is solved, the chip performance and electrostatic release performance are improved, and the impact of noise on sensitive modules is reduced.
Patent Information
- Application Number
- CN202310830342.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-07-06
- Publication Date
- 2025-01-10
AI Technical Summary
The noise propagation within the chip affects the chip performance, and the existing noise isolation methods are inefficient or affects the chip area and performance.
Polysitic POLY layers are laid on the N-type and P-type protection rings to generate target capacitors to isolate noise and enhance the noise isolation capability of the chip.
Effectively isolate external noise of sensitive modules with additional target capacitors, improve chip performance, enhance electrostatic discharge performance and reduce power rebound problems.
Smart Images
Figure CN119297175A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of chip technology, and in particular, to a noise isolation device and a chip. Background Art
[0002] As the scale of chip integration increases, the noise impact of chips has received widespread attention and has become an issue that cannot be ignored in integrated circuit design. The driver units on the various clock signals inside the chip are distributed throughout the chip and powered by the power network. The power network can easily become a medium for the spread of noise, spreading from one power source to other areas. Some sensitive modules are more susceptible to other signals and noise, thus affecting the performance of the chip. Summary of the invention
[0003] In order to solve the above problems, the present disclosure provides a noise isolation device and a chip.
[0004] In a first aspect, the present disclosure provides a noise isolation device, the device comprising:
[0005] An N-type guard ring, comprising an N-type active region and a first metal layer located above the N-type active region, wherein the first metal layer is used to connect to a target power source;
[0006] A P-type guard ring, comprising a P-type active region and a second metal layer located on the upper layer of the P-type active region, wherein the second metal layer is used to connect to a ground line;
[0007] A polysilicon POLY layer is laid between the N-type active area and the first metal layer, and between the P-type active area and the second metal layer to generate a target capacitor, wherein the target capacitor is used to isolate noise outside a sensitive module, and the sensitive module is a module surrounded by the noise isolation device.
[0008] Optionally, the POLY layer is laid between the N-type active area and the first metal layer, and extends to between the P-type active area and the second metal layer through an intermediate region, and the intermediate region includes a region between the N-type guard ring and the P-type guard ring.
[0009] Optionally, the device further comprises a plurality of third metal layers, wherein the third metal layers are laid on an upper layer of the first metal layer and extend to an upper layer of the second metal layer;
[0010] The third target metal layer is used to connect to the target power supply, and the third metal layer adjacent to the third target metal layer is used to connect to the ground line. The third target metal layer is any third metal layer among the plurality of third metal layers.
[0011] Optionally, the third target metal layer is connected to the first metal layer to be connected to the target power supply through the first metal layer, and the third metal layer adjacent to the third target metal layer is connected to the second metal layer to be connected to the ground line through the second metal layer.
[0012] Optionally, the POLY layer includes a first POLY layer and a second POLY layer, the first POLY layer is laid between the N-type active area and the first metal layer, and the second POLY layer is laid between the P-type active area and the second metal layer;
[0013] The first POLY layer is connected to the second metal layer;
[0014] The second POLY layer is connected to the first metal layer.
[0015] Optionally, the device further comprises a plurality of fourth metal layers, wherein the fourth metal layers are laid on an upper layer of the first metal layer and extend to an upper layer of the second metal layer;
[0016] The fourth target metal layer is used to connect to the target power supply, and the fourth metal layer adjacent to the fourth target metal layer is used to connect to the ground line. The fourth target metal layer is any fourth metal layer among the plurality of fourth metal layers.
[0017] Optionally, the fourth target metal layer is connected to the first metal layer to be connected to the target power supply through the first metal layer, and the fourth metal layer adjacent to the fourth target metal layer is connected to the second metal layer to be connected to the ground line through the second metal layer.
[0018] Optionally, the device further comprises a fifth metal layer and a sixth metal layer;
[0019] The fifth metal layer has the same level as the first metal layer and is laid below the first POLY layer;
[0020] The sixth metal layer has the same level as the second metal layer and is laid on top of the second POLY layer;
[0021] The fourth target metal layer is connected to the sixth metal layer, and the fourth metal layer adjacent to the fourth target metal layer is connected to the fifth metal layer.
[0022] Optionally, the target power supply is a power supply whose electrostatic discharge performance needs to be improved or a power supply with power rebound.
[0023] In a second aspect, the present disclosure provides a chip, comprising the noise isolation device described in the first aspect of the present disclosure.
[0024] Through the above technical solution, the noise isolation device includes: an N-type guard ring, including an N-type active area and a first metal layer located on the upper layer of the N-type active area, the first metal layer is used to connect to the target power supply; a P-type guard ring, including a P-type active area and a second metal layer located on the upper layer of the P-type active area, the second metal layer is used to connect to the ground line; a POLY layer, laid between the N-type active area and the first metal layer, and between the P-type active area and the second metal layer, to generate a target capacitor, the target capacitor is used to isolate the noise outside the sensitive module, and the sensitive module is the module surrounded by the noise isolation device. In other words, the noise isolation device adds a POLY layer to the P-type guard ring and the N-type guard ring, which can parasitize an additional target capacitor, through which the noise affecting the sensitive module can be isolated, thereby improving the performance of the chip.
[0025] Other features and advantages of the present disclosure will be described in detail in the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS
[0026] The accompanying drawings are used to provide a further understanding of the present disclosure and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the present disclosure but do not constitute a limitation of the present disclosure. In the accompanying drawings:
[0027] Figure 1 is a structural block diagram of a noise isolation device according to an exemplary embodiment of the present disclosure;
[0028] Figure 2 is a schematic diagram of a noise isolation device according to an exemplary embodiment of the present disclosure;
[0029] Figure 3 is a schematic diagram of another noise isolation device according to an exemplary embodiment of the present disclosure;
[0030] Figure 4 is a structural schematic diagram of a noise isolation device according to an exemplary embodiment of the present disclosure;
[0031] Figure 5 is a structural schematic diagram of another noise isolation device according to an exemplary embodiment of the present disclosure;
[0032] Figure 6 is a structural schematic diagram of another noise isolation device according to an exemplary embodiment of the present disclosure;
[0033] Figure 7 is a structural schematic diagram of another noise isolation device according to an exemplary embodiment of the present disclosure;
[0034] Figure 8It is a schematic structural diagram of another noise isolation device according to an exemplary embodiment of the present disclosure.
[0035] Description of Reference Numerals
[0036] 100 Noise Isolation Device 101 N-type Protection Ring
[0037] 102P type protection ring 103POLY layer
[0038] 104 third metal layer 105 fourth metal layer
[0039] 106 fifth metal layer 107 sixth metal layer
[0040] 1011N type active area 1012 first metal layer
[0041] 1013N-type well 1021P-type active area
[0042] 1022 second metal layer 1031 first POLY layer
[0043] 1032 Second POLY layer DETAILED DESCRIPTION
[0044] The specific implementation of the present disclosure is described in detail below in conjunction with the accompanying drawings. It should be understood that the specific implementation described herein is only used to illustrate and explain the present disclosure, and is not used to limit the present disclosure.
[0045] In the description below, words such as “first” and “second” are only used for the purpose of distinguishing the description and should not be understood as indicating or implying relative importance or order.
[0046] First, the application scenario of the present disclosure is explained. In the related art, the noise isolation methods of sensitive modules in chips include the following three methods: the first is to increase the distance between the sensitive module and the noise source, which consumes the chip area resources; the second is to add an additional noise isolation device between the sensitive module and the noise source, and the noise isolation device includes PSUB, deep well, N-type protection ring, P-type protection ring, etc. The isolation effect of this method is relatively poor; the third is to completely isolate the sensitive module in a deep well to avoid the influence of noise on the sensitive module. This method requires a new injection layer, which affects the performance and layout rules of the chip and has low usability.
[0047] In order to solve the above-mentioned technical problems, the present disclosure provides a noise isolation device and a chip. The noise isolation device adds a POLY layer on the P-type guard ring and the N-type guard ring, which can parasitize an additional target capacitor. The target capacitor can be used to isolate the noise affecting the sensitive module, thereby improving the performance of the chip.
[0048] The present disclosure is described below in conjunction with specific embodiments.
[0049] Figure 1 is a structural block diagram of a noise isolation device according to an exemplary embodiment of the present disclosure. Figure 1 As shown, the noise isolation device 100 includes:
[0050] An N-type guard ring 101 includes an N-type active region 1011 and a first metal layer 1012 located on the upper layer of the N-type active region, wherein the first metal layer 1012 is used to connect to a target power source;
[0051] A P-type guard ring 102, comprising a P-type active region 1021 and a second metal layer 1022 located on the upper layer of the P-type active region, wherein the second metal layer 1022 is used to connect to a ground line;
[0052] The POLY (Polysilicon) layer 103 is laid between the N-type active area 1011 and the first metal layer 1012, and between the P-type active area 1021 and the second metal layer 1022 to generate a target capacitor, which is used to isolate noise outside the sensitive module, which is the module surrounded by the noise isolation device 100.
[0053] The sensitive module may be a module in the chip that is easily interfered by noise, and the present disclosure may determine the sensitive module in advance through experiments. The noise isolation device 100 may be arranged around the sensitive module to surround the sensitive module.
[0054] It should be noted that the noise isolation device 100 may also be referred to as a noise isolation belt, which is not limited in the present disclosure.
[0055] Figure 2 is a schematic diagram of a noise isolation device according to an exemplary embodiment of the present disclosure. Figure 2 As shown, the middle area (rectangular area) represents the sensitive module, and the noise isolation device 100 is surrounded by the sensitive module.
[0056] Figure 3 is a schematic diagram of another noise isolation device according to an exemplary embodiment of the present disclosure, such as Figure 3 As shown, the middle area (polymorphic area) represents the sensitive module, and the noise isolation device 100 is surrounded by the sensitive module.
[0057] In a possible implementation, the target power supply may be any power supply in a chip.
[0058] In another possible implementation, the target power source may be a power source that needs to improve electrostatic discharge performance or a power source that has power rebound. For example, the target power source may be determined in advance through experimental tests.
[0059] In a possible implementation, the width of the noise isolation device 100 can be determined according to the sensitivity of the sensitive module to noise and the area cost of the chip. For example, the width of the noise isolation device 100 can be 2um or 200um, which is not limited in the present disclosure.
[0060] It should be noted that the width of the noise isolation device 100 is the distance between the first position and the second position, the first position is the position where the noise isolation device 100 is closest to the sensitive module, and the second position is the position where the noise isolation device 100 is closest to the sensitive module. The POLY layer 103 is between the N-type active area 1011 and the first metal layer 1012, and is not bonded to the N-type active area 1011 and the first metal layer 1012. An insulating material may be filled between the POLY layer 103 and the N-type active area 1011, and an insulating material may also be filled between the POLY layer 103 and the first metal layer 1012. The POLY layer 103 is between the P-type active area 1021 and the second metal layer 1022, and is not bonded to the P-type active area 1021 and the second metal layer 1022. An insulating material may be filled between the POLY layer 103 and the P-type active area 1021, and an insulating material may also be filled between the POLY layer 103 and the second metal layer 1022.
[0061] After determining the width of the noise isolation device 100, the N-type guard ring 101 and the P-type guard ring 102 may be arranged in the width direction. For example, the N-type guard ring 101 may be arranged above the noise isolation device 100 (closer to the sensitive module), and the P-type guard ring 102 may be arranged below the noise isolation device 100 (farther from the sensitive module).
[0062] Through the above-mentioned noise isolation device, a POLY layer is added to the P-type guard ring and the N-type guard ring, which can parasitize an additional target capacitor, through which the noise affecting the sensitive module can be isolated, thereby improving the performance of the chip. In addition, after the N-type guard ring 101 is connected to the target power supply, the target capacitor parasitic by the noise isolation device can improve the stability of the voltage and ground of the noise isolation device, improve the electrostatic release performance of the chip, and reduce the power rebound problem on the power supply track. The POLY layer in the noise isolation device will not be directly connected to the power supply or ground wire, which can avoid the risk of breakdown caused by the power supply or ground potential.
[0063] Figure 4is a structural schematic diagram of a noise isolation device according to an exemplary embodiment of the present disclosure. Figure 4 As shown, the POLY layer 103 is laid between the N-type active area 1011 and the first metal layer 1012 , and extends to between the P-type active area 1021 and the second metal layer 1022 through the middle area, and the middle area includes the area between the N-type guard ring 101 and the P-type guard ring 102 .
[0064] It should be noted that Figure 4 is a schematic diagram of the noise isolation device 100 in the width direction, which does not reflect the relationship between different levels, such as Figure 4 As shown, the POLY layer 103 is laid from the top of the noise isolation device 100 to the bottom of the noise isolation device 100 , the height of the POLY layer 103 is the same as the width of the noise isolation device 100 , and the POLY layer 103 is a whole.
[0065] Figure 4 The noise isolation device 100 shown sets a whole POLY layer 103 on the N-type guard ring 101, the P-type guard ring 102 and the area between the N-type guard ring 101 and the P-type guard ring 102, so as to generate potential floating. For example, the target capacitance parasitic by the noise isolation device 100 can be calculated by the following formula:
[0066] CAP=CAP1*CAP2 / (1+CAP2)(1)
[0067] Among them, CAP is the target capacitance, CAP1 includes the capacitance between the N-type active area 1011 and the POLY layer 103 and the capacitance between the first metal layer 1012 and the POLY layer 103 , and CAP2 includes the capacitance between the P-type active area 1021 and the POLY layer 103 and the capacitance between the second metal layer 1022 and the POLY layer 103 .
[0068] In a possible implementation, the N-type guard ring 101 may also include a deep well (N-type well, NWELL), such as Figure 4 As shown in 1013 (the rectangular area enclosed by the lines indicated by 1013).
[0069] Figure 5 is a schematic structural diagram of another noise isolation device according to an exemplary embodiment of the present disclosure, such as Figure 5 As shown, the noise isolation device 100 further includes a plurality of third metal layers 104 ( Figure 5Only four third metal layers are shown as an example), the third metal layer 104 is laid on the upper layer of the first metal layer 1012 and extends to the upper layer of the second metal layer 1022; the third target metal layer is used to connect to the target power supply, and the third metal layer adjacent to the third target metal layer is used to connect to the ground wire, and the third target metal layer is any third metal layer among the multiple third metal layers.
[0070] exist Figure 5 In the noise isolation device 100 shown, in order from left to right, the first third metal layer can be used as a third target metal layer and connected to a target power supply, the second third metal layer can be connected to a ground line, the third third metal layer can also be used as a third target metal layer and connected to a target power supply, and the fourth third metal layer is connected to a ground line.
[0071] In one possible implementation, the third target metal layer can also be connected to the first metal layer 1012 to be connected to the target power supply through the first metal layer 1012, and the third metal layer adjacent to the third target metal layer is connected to the second metal layer 1022 to be connected to the ground line through the second metal layer 1022.
[0072] by Figure 5 Taking the noise isolation device 100 shown as an example, in order from left to right, the first third metal layer can be used as the third target metal layer and connected to the first metal layer, the second third metal layer can be connected to the second metal layer, the third third metal layer can also be used as the third target metal layer and connected to the first metal layer, and the fourth third metal layer is connected to the second metal layer.
[0073] Figure 5 The noise isolation device 100 shown is in Figure 4 A third metal layer is added to the noise isolation device 100 shown in the figure, which can increase the parasitic capacitance. For example, Figure 5 The parasitic target capacitance of the noise isolation device 100 shown can be calculated by the following formula:
[0074] CAP=CAP1*CAP2 / (1+CAP2)+CAP3(2)
[0075] Among them, CAP3 is the parasitic capacitance between metal layers, and CAP3 may include the parasitic capacitance between the first metal layer 1012 and the second metal layer 1022, the parasitic capacitance between the first metal layer 1012 and the third metal layer 104, the parasitic capacitance between the second metal layer 1022 and the third metal layer 104, and the parasitic capacitance between two adjacent third metal layers 104.
[0076] By means of the noise isolation device, more capacitances between metal layers can be parasitized, thereby further improving the effect of noise isolation on sensitive modules.
[0077] Figure 6 is a schematic structural diagram of another noise isolation device according to an exemplary embodiment of the present disclosure, such as Figure 6 As shown, the POLY layer 103 includes a first POLY layer 1031 and a second POLY layer 1032, the first POLY layer 1031 is laid between the N-type active area 1011 and the first metal layer 1012, and the second POLY layer 1032 is laid between the P-type active area 1021 and the second metal layer 1022; the first POLY layer 1031 is connected to the second metal layer 1022; the second POLY layer 1032 is connected to the first metal layer 1012.
[0078] like Figure 6 As shown, the first metal layer 1012 and the second metal layer 1022 are both irregularly shaped, and two rectangles extending from the first metal layer 1012 are connected to the second POLY layer 1032, and two rectangles extending from the second metal layer 1022 are connected to the first POLY layer 1031. Since the second metal layer 1022 is connected to the ground line, the first POLY layer 1031 is also connected to the ground line after being connected to the second metal layer 1022; since the first metal layer 1012 is connected to the target power supply, the second POLY layer 1032 is also connected to the target power supply after being connected to the first metal layer 1012.
[0079] Figure 6 The parasitic target capacitance of the noise isolation device 100 shown can be calculated by the following formula:
[0080] CAP=CAP4+CAP5(3)
[0081] Among them, CAP4 includes the capacitance between the N-type active area 1011 and the first POLY layer 1031 and the capacitance between the first metal layer 1012 and the first POLY layer 1031 , and CAP2 includes the capacitance between the P-type active area 1021 and the second POLY layer 1032 and the capacitance between the second metal layer 1022 and the second POLY layer 1032 .
[0082] Figure 7 is a schematic structural diagram of another noise isolation device according to an exemplary embodiment of the present disclosure, such as Figure 7As shown, the noise isolation device 100 also includes a plurality of fourth metal layers 105, which are laid on the upper layer of the first metal layer 1012 and extend to the upper layer of the second metal layer 1022; the fourth target metal layer is used to connect to the target power supply, and the fourth metal layer adjacent to the fourth target metal layer is used to connect to the ground line, and the fourth target metal layer is any fourth metal layer among the plurality of fourth metal layers.
[0083] exist Figure 7 In the noise isolation device 100 shown, in order from left to right, the first fourth metal layer can be used as the fourth target metal layer and connected to the target power supply, the second fourth metal layer can be connected to the ground line, the third fourth metal layer can also be used as the fourth target metal layer and connected to the target power supply, and the fourth fourth metal layer is connected to the ground line.
[0084] In one possible implementation, the fourth target metal layer can be connected to the first metal layer 1012 to be connected to the target power supply through the first metal layer 1012, and the fourth metal layer adjacent to the fourth target metal layer is connected to the second metal layer 1022 to be connected to the ground line through the second metal layer 1022.
[0085] by Figure 7 Taking the noise isolation device 100 shown as an example, in order from left to right, the first fourth metal layer can be used as the fourth target metal layer and connected to the first metal layer 1012, the second fourth metal layer can be connected to the second metal layer 1022, the third fourth metal layer can also be used as the fourth target metal layer and connected to the first metal layer 1012, and the fourth fourth metal layer is connected to the second metal layer 1022.
[0086] Figure 7 The noise isolation device 100 shown is in Figure 6 A fourth metal layer is added to the noise isolation device 100 shown in the figure, which can increase the parasitic capacitance. For example, Figure 7 The parasitic target capacitance of the noise isolation device 100 shown can be calculated by the following formula:
[0087] CAP=CAP4+CAP5+CAP6(4)
[0088] Among them, CAP6 is the parasitic capacitance between metal layers, and CAP6 may include the parasitic capacitance between the first metal layer 1012 and the second metal layer 1022, the parasitic capacitance between the first metal layer 1012 and the fourth metal layer 105, the parasitic capacitance between the second metal layer 1022 and the fourth metal layer 105, and the parasitic capacitance between two adjacent fourth metal layers 105.
[0089] By means of the noise isolation device, more capacitances between metal layers can be parasitized, thereby further improving the effect of noise isolation on sensitive modules.
[0090] Figure 8 is a schematic structural diagram of another noise isolation device according to an exemplary embodiment of the present disclosure, such as Figure 8 As shown, the noise isolation device 100 also includes a fifth metal layer 106 and a sixth metal layer 107; the fifth metal layer 106 is at the same level as the first metal layer 1012, and is laid below the first POLY layer 1031; the sixth metal layer 107 is at the same level as the second metal layer 1022, and is laid above the second POLY layer 1032; the fourth target metal layer is connected to the sixth metal layer 107, and the fourth metal layer adjacent to the fourth target metal layer is connected to the fifth metal layer 106.
[0091] exist Figure 8 In the noise isolation device 100 shown, in order from left to right, the first fourth metal layer can be used as the fourth target metal layer, and the fourth target metal layer is respectively connected to the first metal layer 1012 and the sixth metal layer 107. When the first metal layer 1012 is connected to the target power supply, the sixth metal layer 107 is also connected to the target power supply through the fourth target metal layer. The second fourth metal layer is used as the fourth metal layer adjacent to the fourth target metal layer, and the second fourth metal layer is respectively connected to the second metal layer 1022 and the fifth metal layer 106. When the second metal layer 1022 is connected to the ground line, the fifth metal layer 106 is also connected to the ground line through the second fourth target metal layer.
[0092] Figure 8 The parasitic target capacitance of the noise isolation device 100 shown can be calculated by the following formula:
[0093] CAP=CAP4+CAP5+CAP7(5)
[0094] Among them, CAP7 is the parasitic capacitance between metal layers, and CAP7 may include the parasitic capacitance between the first metal layer 1012 and the second metal layer 1022, the parasitic capacitance between the first metal layer 1012 and the fifth metal layer 106, the parasitic capacitance between the second metal layer 1022 and the sixth metal layer 107, and the parasitic capacitance between two adjacent fourth metal layers 105.
[0095] It should be noted that the connection method of the first metal layer, the second metal layer, the third metal layer, the fourth metal layer, the fifth metal layer and the sixth metal layer in the present disclosure is for illustration only and is not limited in the present disclosure. In addition, in order to achieve a better isolation effect, a new metal layer may be added on the basis of the first metal layer, the second metal layer, the third metal layer, the fourth metal layer, the fifth metal layer and the sixth metal layer so as to parasitize more capacitance.
[0096] In another exemplary embodiment, the present disclosure further provides a chip, which includes the noise isolation device described in the above embodiment.
[0097] The preferred embodiments of the present disclosure are described in detail above in conjunction with the accompanying drawings. However, the present disclosure is not limited to the specific details in the above embodiments. Within the technical concept of the present disclosure, the technical solution of the present disclosure can be subjected to a variety of simple modifications, and these simple modifications all belong to the protection scope of the present disclosure. It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, the present disclosure will not further describe various possible combinations.
[0098] In addition, various embodiments of the present disclosure may be arbitrarily combined, and as long as they do not violate the concept of the present disclosure, they should also be regarded as the contents disclosed by the present disclosure.
Claims
1. A noise isolation device, characterized in that: The device comprises: An N-type guard ring, comprising an N-type active region and a first metal layer located above the N-type active region, wherein the first metal layer is used to connect to a target power source; A P-type guard ring, comprising a P-type active region and a second metal layer located on the upper layer of the P-type active region, wherein the second metal layer is used to connect to a ground line; A polysilicon POLY layer is laid between the N-type active area and the first metal layer, and between the P-type active area and the second metal layer to generate a target capacitor, wherein the target capacitor is used to isolate noise outside a sensitive module, and the sensitive module is a module surrounded by the noise isolation device.
2. The device according to claim 1, characterized in that The POLY layer is laid between the N-type active area and the first metal layer, and extends to between the P-type active area and the second metal layer through a middle area, and the middle area includes a region between the N-type guard ring and the P-type guard ring.
3. The device according to claim 2, characterized in that The device further comprises a plurality of third metal layers, wherein the third metal layers are laid on the upper layer of the first metal layer and extend to the upper layer of the second metal layer; The third target metal layer is used to connect to the target power supply, and the third metal layer adjacent to the third target metal layer is used to connect to the ground line. The third target metal layer is any third metal layer among the plurality of third metal layers.
4. The device according to claim 3, characterized in that The third target metal layer is connected to the first metal layer to be connected to the target power supply through the first metal layer, and the third metal layer adjacent to the third target metal layer is connected to the second metal layer to be connected to the ground line through the second metal layer.
5. The device according to claim 1, characterized in that The POLY layer includes a first POLY layer and a second POLY layer, the first POLY layer is laid between the N-type active area and the first metal layer, and the second POLY layer is laid between the P-type active area and the second metal layer; The first POLY layer is connected to the second metal layer; The second POLY layer is connected to the first metal layer.
6. The device according to claim 5, characterized in that The device further includes a plurality of fourth metal layers, the fourth metal layers being laid on an upper layer of the first metal layer and extending to an upper layer of the second metal layer; The fourth target metal layer is used to connect to the target power supply, and the fourth metal layer adjacent to the fourth target metal layer is used to connect to the ground line. The fourth target metal layer is any fourth metal layer among the plurality of fourth metal layers.
7. The device according to claim 6, characterized in that The fourth target metal layer is connected to the first metal layer to be connected to the target power source through the first metal layer, and the fourth metal layer adjacent to the fourth target metal layer is connected to the second metal layer to be connected to the ground line through the second metal layer.
8. The device according to claim 6 or 7, characterized in that The device also includes a fifth metal layer and a sixth metal layer; The fifth metal layer has the same level as the first metal layer and is laid below the first POLY layer; The sixth metal layer has the same level as the second metal layer and is laid on top of the second POLY layer; The fourth target metal layer is connected to the sixth metal layer, and the fourth metal layer adjacent to the fourth target metal layer is connected to the fifth metal layer.
9. The device according to claim 1, characterized in that The target power source is a power source whose electrostatic discharge performance needs to be improved or a power source with power rebound.
10. A chip, characterized in that: The chip comprises the noise isolation device according to any one of claims 1 to 9.