Voltage monitoring circuit

Abstract

The invention provides a voltage monitoring circuit. The voltage monitoring circuit comprises a voltage combining circuit and a monitoring filter circuit, the input end of the voltage combining circuit is connected with the power supply ends of at least two target chips, the output end of the voltage combining circuit is connected with the monitoring filter circuit, and the output end of the voltage combining circuit comprises an undervoltage output end and an overvoltage output end; the voltage combining circuit comprises an under-voltage branch circuit and an overvoltage branch circuit; the monitoring filter circuit comprises a combiner diode group, a comparator and a switch group, the positive input end of the comparator is connected with the reference voltage end of the comparator, the output end of the comparator is connected with the input end of the switch group, and the monitoring filter circuit is used for controlling the on-off of the switch group so as to maintain or close a power supply for supplying power to the at least two target chips. According to the voltage monitoring circuit disclosed by the invention, undervoltage and overvoltage monitoring of the power supply end of the target chip can be realized with relatively low cost.

Description

Technical Field

[0001] The present disclosure relates to the technical field of electronic circuits, and in particular to a voltage monitoring circuit. Background Art

[0002] For functional safety products that need to meet the requirements of IEC61508, the relevant standard for the electrical and electronic components industry officially released by the International Electrotechnical Commission in May 2000, when the product reaches the safety integrity level SIL3 or even SIL4, the power supply usually uses non-redundant power supply, and the fault diagnosis coverage must reach the High level requirement. Correspondingly, the power supply voltage of key chips such as processor chips is required to be monitored for over-voltage and under-voltage, so as to shut down the power supply after the voltage exceeds the chip's operating voltage range.

[0003] Over-voltage and under-voltage monitoring include over-voltage monitoring and under-voltage monitoring. In the related art, over-voltage and under-voltage monitoring can be implemented by an over-voltage and under-voltage monitoring circuit including an integrated multi-channel voltage monitoring chip and a CPLD (Complex Programmable Logic Device). Among them, the over-voltage and under-voltage monitoring circuit needs to use CPLD for filtering and a voltage monitoring chip for combining and over-voltage and under-voltage monitoring.

[0004] The above-mentioned over-voltage and under-voltage monitoring circuit uses an integrated multi-channel voltage monitoring chip and CPLD, and the circuit cost is relatively high. Among them, the multi-channel voltage monitoring chip is a niche product, and there are few domestic suppliers involved, and most of them are foreign suppliers, which is not conducive to realizing domestic design. Summary of the invention

[0005] In view of this, an embodiment of the present disclosure provides a voltage monitoring circuit to solve the technical problem of high cost of voltage monitoring circuits in the prior art.

[0006] To achieve the above objectives, the technical solution adopted by the present disclosure is:

[0007] The voltage monitoring circuit provided by the embodiment of the present disclosure includes: the voltage monitoring circuit includes a voltage combining circuit and a monitoring filter circuit, wherein: the input end of the voltage combining circuit is connected to the power supply ends of at least two target chips, the output end of the voltage combining circuit is connected to the monitoring filter circuit, and the output end of the voltage combining circuit includes an undervoltage output end and an overvoltage output end; the voltage combining circuit includes an undervoltage branch circuit and an overvoltage branch circuit, the input end of each undervoltage branch circuit is connected to the power supply end of a target chip, the output end of each undervoltage branch circuit is connected to the undervoltage output end, and the input end of each overvoltage branch circuit is connected to the power supply end of a target chip. The output end of each overvoltage branch circuit is connected to the overvoltage output end; the monitoring filter circuit includes a combined diode group, a comparator and a switch group, the combined diode group includes a first diode and a second diode, the positive terminal of the first diode is connected to the undervoltage output end, the positive terminal of the second diode is connected to the overvoltage output end, the cathode terminal of the first diode and the cathode terminal of the second diode are connected to the negative input end of the comparator, the positive input end of the comparator is connected to the reference voltage end of the comparator, and the output end of the comparator is connected to the input end of the switch group, which is used to control the on and off of the switch group to maintain or turn off the power supply for at least two target chips.

[0008] In one embodiment, the undervoltage branch circuit includes a first resistor, a second resistor and an undervoltage diode connected at one point, one end of the first resistor is connected to the combined reference voltage terminal, one end of the second resistor is connected to the power supply terminal of a target chip, and one end of the undervoltage diode is connected to the undervoltage output terminal; the overvoltage branch circuit includes a third resistor, a fourth resistor and an overvoltage diode connected at one point, one end of the third resistor is connected to the power supply terminal of a target chip, one end of the fourth resistor is connected to the ground terminal, and one end of the overvoltage diode is connected to the overvoltage output terminal.

[0009] In one embodiment, the comparator reference voltage terminal is a connection point of a first voltage-dividing resistor and a second voltage-dividing resistor, and the first voltage-dividing resistor and the second voltage-dividing resistor are connected in series and connected between an external power supply and a ground terminal.

[0010] In one embodiment, the voltage monitoring circuit further includes a buffer amplifier circuit, which is connected to the undervoltage output terminal and the overvoltage output terminal respectively, and is used to: when the undervoltage output terminal outputs an undervoltage signal, generate an undervoltage alarm signal according to the undervoltage signal to alarm the system; and when the overvoltage output terminal outputs an overvoltage signal, generate an overvoltage alarm signal according to the overvoltage signal to alarm the system.

[0011] In one embodiment, the switch group includes a PMOS tube and a PNP transistor, the source of the PMOS tube is connected to an external power supply, the drain of the PMOS tube is connected to a power supply terminal of a target chip, the gate of the PMOS tube is connected to the collector of the PNP transistor, the emitter of the PNP transistor is connected to the ground terminal, and the base of the PNP transistor is connected to the output terminal of the comparator.

[0012] In one embodiment, the voltage monitoring circuit also includes a filtering circuit, which includes a first filtering resistor, a second filtering resistor and a filtering capacitor, the first filtering resistor is connected between the gate and the source of the PMOS tube, the second filtering resistor is connected between the gate of the PMOS tube and the collector of the PNP transistor, and the filtering capacitor is connected between the emitter and the collector of the PNP transistor.

[0013] In one embodiment, the values ​​of the first resistor and the second resistor meet the following restrictions:

[0014]

[0015] Wherein, Vduv0 is the undervoltage diode voltage drop, R0_1 is the first resistor, R0_2 is the second resistor, Vin0_uv is the undervoltage threshold, Vcom_ref is the reference voltage of the positive input terminal of the comparator, and Vref is the combined reference voltage.

[0016] In one embodiment, the values ​​of the third resistor and the fourth resistor meet the following restrictions:

[0017]

[0018] Among them, Vdov0 is the overvoltage diode voltage drop, R0_3 is the third resistor, R0_4 is the fourth resistor, Vin0_ov is the overvoltage threshold, and Vcom_ref is the reference voltage of the positive input terminal of the comparator.

[0019] In one embodiment, the switch group is connected between the external power supply and at least two DC modules, and the at least two DC modules are connected to the power supply terminals of at least two target chips in a one-to-one correspondence.

[0020] In one embodiment, a first voltage-dividing resistor and a second voltage-dividing resistor are connected in series and connected between a DC converter and a ground terminal, the DC converter is connected between an external power supply and the first voltage-dividing resistor, and the second voltage-dividing resistor is connected between the first voltage-dividing resistor and the ground terminal, wherein the DC converter outputs a comparator reference voltage.

[0021] Compared with the prior art, the embodiments of the present disclosure have the following beneficial effects: the voltage monitoring circuit in the embodiments of the present disclosure includes a voltage combining circuit and a monitoring filter circuit; the undervoltage branch circuit and the overvoltage branch circuit in the voltage combining circuit are composed of simple discrete devices such as resistors and diodes; the combining diode group, comparator and switch group in the monitoring filter circuit can also be implemented using simple discrete devices, thereby making it easier to obtain the components of the undervoltage and overvoltage monitoring circuits, which is conducive to the localized design of the product and has lower circuit costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0023] Figure 1 It is a structural schematic diagram of a voltage monitoring circuit in the related art;

[0024] Figure 2 is a schematic diagram of the structure of a voltage monitoring circuit provided by an embodiment of the present disclosure;

[0025] Figure 3 is a schematic diagram of the structure of a voltage combining circuit provided by an embodiment of the present disclosure;

[0026] Figure 4 It is a structural schematic diagram of a monitoring filter circuit provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0027] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present disclosure more clearly understood, the present disclosure is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present disclosure and are not used to limit the present disclosure.

[0028] In related technologies, such as Figure 1As shown, the supply voltage of the CPLD and the power monitoring chip in a voltage monitoring circuit is U0, which comes from the independent power conversion chip DC-DC_a0. The voltage monitoring chip monitors the supply voltages Vout0, Vout1 and Vout2 of the key chips through the monitoring ports VM0, VM1 and VM2. Among them, the supply voltages Vout0, Vout1 and Vout2 of the key chips come from the independent power conversion chips DC-DC_b0, DC-DC_b1 and DC-DC_b2 respectively. When the supply voltage of the voltage monitoring chip exceeds the power supply range, the OV / UV (overvoltage / undervoltage) terminal output signal of the voltage monitoring chip is sent to the CPLD. After filtering by the CPLD, the control switch turns off the power supply path for the key chip. The voltage monitoring chip may have only a limited number, for example, 3, of monitoring ports. Therefore, when monitoring the input voltage of all key chips, multiple voltage monitoring chips may be required. In addition to the cost of the CPLD and the independent power conversion chip DC-DC_a0, it can be seen that the cost of the voltage monitoring circuit is relatively high.

[0029] In order to solve the above technical problems, the technical solution of the embodiment of the present disclosure provides a voltage monitoring circuit.

[0030] The voltage monitoring circuit according to the embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0031] Figure 2 is a schematic diagram of the structure of a voltage monitoring circuit provided by an embodiment of the present disclosure; Figure 3 is a schematic diagram of the structure of a voltage combining circuit provided by an embodiment of the present disclosure; Figure 4 This is a schematic diagram of the structure of a monitoring filter circuit provided by an embodiment of the present disclosure. Figure 2 , Figure 3 and Figure 4 The voltage monitoring circuit provided by the embodiments of the present disclosure is described together.

[0032] like Figure 2 As shown, the voltage output by the independent power conversion chips DC-DC_0 to DC-DC_n is combined by the voltage combining circuit and then output to the monitoring filter circuit. When the voltage output by any of the independent power conversion chips DC-DC_0 to DC-DC_n is abnormal, for example, overvoltage or undervoltage, and exceeds the voltage operating range of the key chip, the voltage combining circuit will send the output overvoltage or undervoltage signal to the monitoring filter circuit. After the monitoring filter circuit processes, the control switch is turned off, the output voltage Vout becomes 0, the power supply voltage Vout0 to Voutn of the key chip is 0V, the system loses power, and leads to safety.

[0033] like Figure 2 , Figure 3 and Figure 4As shown, an embodiment of the present disclosure provides a voltage monitoring circuit, which includes a voltage combining circuit and a monitoring filter circuit, wherein: the input end of the voltage combining circuit is connected to the power supply end of at least two target chips, the output end of the voltage combining circuit is connected to the monitoring filter circuit, and the output end of the voltage combining circuit includes an undervoltage output end and an overvoltage output end; the voltage combining circuit includes an undervoltage branch circuit and an overvoltage branch circuit, and the undervoltage branch circuit and the overvoltage branch circuit are both composed of resistors and diodes, the input end of each undervoltage branch circuit is connected to the power supply end of a target chip, the output end of each undervoltage branch circuit is connected to the undervoltage output end, and the output end of each overvoltage branch circuit is connected to the undervoltage output end. The input end is connected to the power supply end of a target chip, and the output end of each overvoltage branch circuit is connected to the overvoltage output end; the monitoring filter circuit includes a combined diode group, a comparator and a switch group, the combined diode group includes a first diode and a second diode, the positive terminal of the first diode is connected to the undervoltage output end, the positive terminal of the second diode is connected to the overvoltage output end, the cathode terminal of the first diode and the cathode terminal of the second diode are connected to the negative input end of the comparator, the positive input end of the comparator is connected to the reference voltage end of the comparator, and the output end of the comparator is connected to the input end of the switch group, which is used to control the on and off of the switch group to maintain or turn off the power supply for powering at least two target chips.

[0034] like Figure 2 As shown, the input terminals 0, 1, ..., n of the voltage combining circuit are connected to the power supply terminals of n+1 target chips one by one, wherein n is a natural number and n≥3. The power supply voltages Vout0, Vout1, ..., Voutn of the power supply terminals of the key chips come from independent power conversion chips DC-DC_0, DC-DC_1, ..., DC-DC_n, respectively. The undervoltage output terminal of the voltage combining circuit outputs a Vuv_sum signal, i.e., an undervoltage summary signal, to the monitoring filter circuit, and the overvoltage output terminal of the monitoring filter circuit outputs a Vov_sum signal, i.e., an overvoltage summary signal, to the monitoring filter circuit.

[0035] In the embodiment of the present disclosure, the switch group is connected between the external power supply and at least two DC modules, and the at least two DC modules are connected to the power supply terminals of at least two target chips in a one-to-one correspondence.

[0036] like Figure 3As shown, a voltage combining circuit includes n undervoltage branch circuits and n overvoltage branch circuits. One undervoltage branch circuit and one overvoltage branch circuit are connected to the power supply end of a target chip. The undervoltage branch circuit is used to detect the undervoltage condition of the power supply end of the target chip, and the overvoltage branch circuit is used to detect the overvoltage condition of the power supply end of the target chip. The n undervoltage branch circuits corresponding to the n target chips are connected to the same undervoltage output end to realize the combining of multiple undervoltage branch circuits; the n overvoltage branch circuits corresponding to the n target chips are connected to the same overvoltage output end to realize the combining of multiple overvoltage branch circuits.

[0037] Among them, the undervoltage output end is the port for the summary output of the undervoltage branch circuit, and the output signal of this port is the undervoltage summary signal. The overvoltage output end is the port for the summary output of the overvoltage branch circuit, and the output signal of this port is the overvoltage summary signal.

[0038] In an embodiment of the present disclosure, the undervoltage branch circuit includes a first resistor, a second resistor and an undervoltage diode connected at one point, the first end of the first resistor is connected to the combined reference voltage terminal, the first end of the second resistor is connected to the power supply terminal of a target chip, the first end of the undervoltage diode is connected to the undervoltage output terminal, and the first resistor, the second resistor and the second end of the undervoltage diode are connected to one point; the overvoltage branch circuit includes a third resistor, a fourth resistor and an overvoltage diode connected at one point, the first end of the third resistor is connected to the power supply terminal of a target chip, the first end of the fourth resistor is connected to the ground terminal, the first end of the overvoltage diode is connected to the overvoltage output terminal, and the third resistor, the fourth resistor and the second end of the overvoltage diode are connected to one point.

[0039] Specifically, Figure 3 As shown, the first resistor R0_1, the second resistor R0_2 and the undervoltage diode Duv_0 form an undervoltage branch circuit, the first resistor Rn_1, the second resistor Rn_2 and the undervoltage diode Duv_n form another undervoltage branch circuit, these two undervoltage branch circuits and other undervoltage branch circuits are summarized at the undervoltage output terminal, and the undervoltage output terminal outputs a signal Vuv_sum. The first resistor R0_3, the second resistor R0_4 and the overvoltage diode Dov_0 form an overvoltage branch circuit, the first resistor Rn_3, the second resistor Rn_4 and the overvoltage diode Dov_n form another overvoltage branch circuit, these two overvoltage branch circuits and other overvoltage branch circuits are summarized at the overvoltage output terminal, and the overvoltage output terminal outputs a signal Vov_sum. Among them, Vin_0 to Vin_n are input voltages from the power supply terminal of a key chip to be voltage monitored. Here, Vin_0 to Vin_n can correspond to inputs such as Figure 2 The supply voltages shown are Vout0, Vout1, ..., Voutn.

[0040] In the embodiment of the present disclosure, it is assumed that the power supply terminals of the key chips from 1 to n are included, and the values ​​of the first resistor and the second resistor meet the restriction conditions defined by the following formula (1):

[0041]

[0042] Among them, Vduv0 is the undervoltage diode voltage drop, R0_1 is the first resistor, R0_2 is the second resistor, Vin0_uv is the undervoltage threshold, Vcom_ref is the reference voltage of the positive input terminal of the comparator, that is, the comparator reference voltage, and Vref is the combined reference voltage.

[0043] The voltage Vduv0_out after the undervoltage diode Duv_0 can be expressed by the following formula (2):

[0044]

[0045] Wherein, Vin0 is the voltage currently input to the input terminal of the undervoltage branch circuit.

[0046] It can be seen from formula (1) and formula (2) that when Vin_0 is not undervoltage, that is, Vin_0 is greater than Vin0_uv, Vduv0_out will be smaller than Vcom_ref; when Vin_0 is undervoltage, that is, Vin_0 is less than Vin0_uv, Vduv0_out will be larger than Vcom_ref.

[0047] Due to the combining effect of the undervoltage diodes Duv_0 to Duv_n, the undervoltage summary signal Vuv_sum=max{Vduv0_out, Vduv1_out, ..., Vduvn_out}.

[0048] In the embodiment of the present disclosure, it is assumed that the power supply terminals of the key chips from 0 to n are included, and the values ​​of the third resistor and the fourth resistor meet the restriction conditions defined by the following formula (3):

[0049]

[0050] Among them, Vdov0 is the overvoltage diode voltage drop, R0_3 is the third resistor, R0_4 is the fourth resistor, Vin0_ov is the overvoltage threshold, and Vcom_ref is the reference voltage of the positive input terminal of the comparator.

[0051] The voltage Vdov0_out after the overvoltage diode Dov_0 can be expressed by the following formula (4):

[0052]

[0053] Wherein, Vin0 is the voltage currently input to the input terminal of the overvoltage branch circuit.

[0054] Due to the combining effect of the overvoltage diodes Duv_0 to Duv_n, the overvoltage summary signal Vov_sum=max{Vdov0_out, Vdov1_out, ..., Vdovn_out}.

[0055] When Vin0 is not over-voltage, that is, Vin0 does not exceed Vin0_ov, Vdov0_out will be smaller than Vcom_ref; when Vin0 is over-voltage, that is, Vin0 exceeds Vin0_ov, Vdov0_out will be larger than Vcom_ref.

[0056] To ensure the accuracy of the monitored voltage, the first resistor, the second resistor, the third resistor and the fourth resistor should be high-precision resistors. Furthermore, the undervoltage summary signal Vuv_sum and the overvoltage summary signal Vov_sum are combined in the branch circuit and input to the negative input terminal of the comparator, and the reference voltage of the positive input terminal of the comparator is set to Vcom_ref, so that the judgment of whether the power supply is undervoltage or overvoltage can be realized.

[0057] For example, when there is an undervoltage condition at the power supply end of any target chip, the undervoltage branch circuit corresponding to the power supply end of the target chip will output a signal indicating that the power supply end of the target chip is undervoltage. After combining the output signals of the undervoltage branch circuits corresponding to the power supply ends of other target chips, the undervoltage output end can output a signal indicating whether the power supply end of a certain target chip in the circuit is undervoltage. The power supply end undervoltage signal can only indicate whether the power supply end of at least one target chip is undervoltage, but cannot indicate which target chip has the undervoltage.

[0058] Similarly, when there is an overvoltage at the power supply end of any target chip, the overvoltage branch circuit corresponding to the power supply end of the target chip will output a signal indicating that the power supply end of the target chip is overvoltage. After combining the output signals of the overvoltage branch circuits corresponding to the power supply ends of other target chips, the overvoltage output end can output a signal indicating whether the power supply end of a certain target chip in the circuit is overvoltage. The power supply end overvoltage signal can only indicate whether the power supply end of at least one target chip is overvoltage, but cannot indicate which target chip has overvoltage.

[0059] like Figure 4As shown, the combined diode group includes a first diode D1 and a second diode D2, the positive terminal of the first diode is connected to the undervoltage output terminal to receive the Vuv_sum signal, the positive terminal of the second diode is connected to the overvoltage output terminal to receive the Vov_sum signal, and the cathode terminal of the first diode and the cathode terminal of the second diode are connected to the negative input terminal of the comparator. The combined diode group realizes the combination of the branch circuits where the undervoltage summary signal Vuv_sum and the overvoltage summary signal Vov_sum are located. The output signal of the combined diode group can indicate whether there is an undervoltage or overvoltage condition at the power supply end of the target chip. The output signal of the combined diode group can only indicate whether there is an undervoltage or overvoltage condition at the power supply end of at least one target chip, and cannot indicate which power supply end of the target chip is undervoltage or overvoltage.

[0060] In the disclosed embodiment, a comparator with high input impedance may be selected to ensure that the leakage current on the diode is very small, the voltage drop on the diode is very small, and the voltage monitoring accuracy is improved.

[0061] like Figure 4 As shown, the negative input terminal of comparator A is connected to the output terminal of the combiner diode group, the positive input terminal of the comparator is connected to the reference voltage terminal of the comparator, and the output terminal of the comparator is connected to the input terminal of the switch group. A Switch off signal can be sent to the input terminal of the switch group to control the on and off of the switch group including a MOS (Metal Oxide Semiconductor) switch and a transistor Q1 to maintain or turn off the power supply for at least two target chips.

[0062] The comparator compares the current or voltage at the negative input and positive input, and outputs different voltage results at the output. The input of the comparator is connected to an analog signal, and the output is a digital signal. The output is a high level or a low level. The specific high level amplitude is arbitrarily determined by the external voltage amplitude. Figure 4 As shown, the comparator is powered by a single power supply, and the two power supply ports are respectively combined with a reference voltage Vref and a ground terminal, and the voltage amplitude of the combined reference voltage Vref is the amplitude of the high level output by the output terminal of the comparator.

[0063] In practical applications, one of the input terminals of the comparator can be selected as a reference point for comparison, such as Figure 4 As shown, the positive input terminal can be selected as the reference voltage input terminal. When the input voltage of the negative input terminal is greater than the input reference voltage, the output terminal of the comparator outputs a low level. When the input voltage of the negative input terminal is less than the input reference voltage, the output terminal of the comparator outputs a high level.

[0064] like Figure 2As shown, the Switch off signal output by the monitoring filter circuit is the Switch off signal output by the comparator.

[0065] In an embodiment of the present disclosure, a first voltage-dividing resistor and a second voltage-dividing resistor are connected in series and connected between a DC converter and a ground terminal, the DC converter is connected between an external power supply and the first voltage-dividing resistor, and the second voltage-dividing resistor is connected between the first voltage-dividing resistor and the ground terminal, wherein the DC converter outputs a comparator reference voltage.

[0066] Specifically, the comparator reference voltage terminal is a connection point of a first voltage-dividing resistor R5 and a second voltage-dividing resistor R6, and the first voltage-dividing resistor and the second voltage-dividing resistor are connected in series and connected between an external power supply and a ground terminal.

[0067] Specifically, the reference voltage is obtained by dividing the high-precision voltage generated by the high-precision independent power conversion chip DC-DC_c0 through the resistors R5 and R6. To ensure accurate voltage division, R5 and R6 are selected from high-precision resistors. The reference voltage value of the positive terminal of the comparator can be controlled by R5 and R6.

[0068] In one embodiment of the present disclosure, the voltage monitoring circuit also includes a buffer amplifier circuit, which is respectively connected to the undervoltage output terminal and the overvoltage output terminal, and is used to: when the undervoltage output terminal outputs an undervoltage signal, generate an undervoltage alarm signal according to the undervoltage signal to alarm the system; and when the overvoltage output terminal outputs an overvoltage signal, generate an overvoltage alarm signal according to the overvoltage signal to alarm the system.

[0069] Specifically, Figure 4 As shown, after the undervoltage summary signal Vuv_sum and the overvoltage summary signal Vov_sum are driven by a buffer (buffer amplifier circuit), an undervoltage alarm signal Vuv_alarm and an overvoltage alarm signal Vov_alarm can be generated to warn the system.

[0070] In one embodiment, the switch group includes a PMOS (Positive Channel Metal Oxide Semiconductor) tube and a PNP transistor, the source of the PMOS tube is connected to an external power supply, the drain of the PMOS tube is connected to a power supply terminal of a target chip, the gate of the PMOS tube is connected to the collector of the PNP transistor, the emitter of the PNP transistor is connected to the ground terminal, and the base of the PNP transistor is connected to the output terminal of the comparator.

[0071] Specifically, the Swith_off signal output by the comparator is used to turn off the switch MOS tube to achieve the purpose of cutting off the power supply voltage of the target chip. Figure 4As shown, the input voltage of the switch group including the MOS switch and the transistor Q1 is Vin, and the output voltage is Vout. When Vin0 to Vinn in the voltage combining circuit is normal, the voltage after the undervoltage summary signal Vuv_sum and the overvoltage summary signal Vov_sum after the first diode D1 and the second diode D2 are combined is lower than the positive terminal voltage of the comparator, the comparator outputs a high level, the transistor Q1 is turned on, the MOS tube source voltage Vs is greater than the source voltage Vg, the MOS tube is turned on, the power supply is normally supplied, and the switch group outputs a voltage Vout=Vin. When Vin0 to Vinn in the voltage combining circuit is abnormal, that is, there is an overvoltage or undervoltage situation, the voltage after the undervoltage summary signal Vuv-sum and the overvoltage summary signal Vov-sum after the first diode D1 and the second diode D2 are combined is higher than the positive terminal voltage of the comparator, the comparator outputs a low level, the transistor Q1 is not turned on, the MOS tube Vs=Vg, the MOS tube is not turned on, the power supply is turned off, and the switch group outputs a voltage Vout=0.

[0072] In one embodiment, the voltage monitoring circuit also includes a filtering circuit, which includes a first filtering resistor, a second filtering resistor and a filtering capacitor, the first filtering resistor is connected between the gate and the source of the PMOS tube, the second filtering resistor is connected between the gate of the PMOS tube and the collector of the PNP transistor, and the filtering capacitor is connected between the emitter and the collector of the PNP transistor.

[0073] like Figure 4 As shown, the first filter resistor R7 is connected between the gate and source of the MOS switch, the second filter resistor R8 is connected between the drain of the MOS switch and the collector of the transistor Q1, and the filter capacitor C1 is connected between the emitter and collector of the transistor Q1.

[0074] Specifically, to avoid voltage fluctuations causing false shutdowns, the shutdown circuit needs to be filtered. Resistors R7, R8 and capacitor C1 form a filter circuit. When the monitored voltage fluctuates, causing the Switch_off signal to fluctuate, which in turn causes Q1 to be disconnected instantly, the discharge circuit composed of R7, R8 and C1 can still keep the MOS tube turned on. Reasonable selection of R7, R8 and C1 can filter out voltage fluctuations of the corresponding frequency.

[0075] When the system is powered on, due to the presence of R7, R8, and C1, the MOS tube Vs>Vg, the MOS tube is turned on, and Vout has output. The presence of R7, R8, and C1 avoids the situation where Vout has no output, Vout0~Voutn has no output, and undervoltage is detected, resulting in failure to supply power normally. It can be seen that the filter circuit can ensure that the switch cannot be turned off when the output is undervoltage at power-on.

[0076] According to the voltage monitoring circuit provided by the embodiment of the present disclosure, the voltage monitoring circuit includes a voltage combining circuit and a monitoring filter circuit. The undervoltage branch circuit and the overvoltage branch circuit in the voltage combining circuit are composed of simple discrete devices such as resistors and diodes. The combining diode group, comparator and switch group in the monitoring filter circuit can also be implemented with simple discrete devices, thereby making the components of the undervoltage and overvoltage monitoring circuits easier to obtain, which is conducive to the localized design of the product and has lower circuit costs.

[0077] The above are only preferred embodiments of the present disclosure and are not intended to limit the present disclosure. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present disclosure should be included in the protection scope of the present disclosure.

Claims

1. A voltage monitoring circuit, characterized in that: The voltage monitoring circuit includes a voltage combining circuit and a monitoring filter circuit, wherein: The input end of the voltage combining circuit is connected to the power supply ends of at least two target chips, the output end of the voltage combining circuit is connected to the monitoring filter circuit, and the output end of the voltage combining circuit includes an undervoltage output end and an overvoltage output end; The voltage combining circuit comprises an undervoltage branch circuit and an overvoltage branch circuit, the input end of each undervoltage branch circuit is connected to a power supply end of the target chip, the output end of each undervoltage branch circuit is connected to the undervoltage output end, the input end of each overvoltage branch circuit is connected to a power supply end of the target chip, and the output end of each overvoltage branch circuit is connected to the overvoltage output end; The monitoring filter circuit includes a combined diode group, a comparator and a switch group. The combined diode group includes a first diode and a second diode. The positive terminal of the first diode is connected to the undervoltage output terminal, the positive terminal of the second diode is connected to the overvoltage output terminal, the negative terminal of the first diode and the negative terminal of the second diode are connected to the negative input terminal of the comparator, the positive input terminal of the comparator is connected to the reference voltage terminal of the comparator, and the output terminal of the comparator is connected to the input terminal of the switch group, so as to control the on and off of the switch group to maintain or turn off the power supply for the at least two target chips.

2. The voltage monitoring circuit according to claim 1, characterized in that: The undervoltage branch circuit includes a first resistor, a second resistor and an undervoltage diode connected to one point, one end of the first resistor is connected to the combined reference voltage terminal, one end of the second resistor is connected to the power supply terminal of the target chip, and one end of the undervoltage diode is connected to the undervoltage output terminal; The overvoltage branch circuit includes a third resistor, a fourth resistor and an overvoltage diode connected at one point, one end of the third resistor is connected to the power supply end of the target chip, one end of the fourth resistor is connected to the ground end, and one end of the overvoltage diode is connected to the overvoltage output end.

3. The voltage monitoring circuit according to claim 1, characterized in that: The comparator reference voltage terminal is a connection point of a first voltage-dividing resistor and a second voltage-dividing resistor, and the first voltage-dividing resistor and the second voltage-dividing resistor are connected in series and connected between an external power supply and a ground terminal.

4. The voltage monitoring circuit according to claim 1, characterized in that: The voltage monitoring circuit further includes a buffer amplifier circuit, which is connected to the undervoltage output terminal and the overvoltage output terminal respectively, and is used to: When the undervoltage output terminal outputs an undervoltage signal, an undervoltage alarm signal is generated according to the undervoltage signal to alarm the system; and When the overvoltage output terminal outputs an overvoltage signal, an overvoltage alarm signal is generated according to the overvoltage signal to alarm the system.

5. The voltage monitoring circuit according to claim 1, characterized in that: The switch group includes a P-channel metal oxide semiconductor (PMOS) tube and a PNP transistor, the source of the PMOS tube is connected to an external power supply, the drain of the PMOS tube is connected to a power supply terminal of a target chip, the gate of the PMOS tube is connected to the collector of the PNP transistor, the emitter of the PNP transistor is connected to the ground terminal, and the base of the PNP transistor is connected to the output terminal of the comparator.

6. The voltage monitoring circuit according to claim 5, characterized in that: The voltage monitoring circuit also includes a filtering circuit, which includes a first filtering resistor, a second filtering resistor and a filtering capacitor, wherein the first filtering resistor is connected between the gate and the source of the PMOS tube, the second filtering resistor is connected between the gate of the PMOS tube and the collector of the PNP transistor, and the filtering capacitor is connected between the emitter and the collector of the PNP transistor.

7. The voltage monitoring circuit according to claim 1, characterized in that: The values ​​of the first resistor and the second resistor meet the following restrictions: Wherein, Vduv0 is the undervoltage diode voltage drop, R0_1 is the first resistor, R0_2 is the second resistor, Vin0_uv is the undervoltage threshold, Vcom_ref is the reference voltage of the positive input terminal of the comparator, and Vref is the combined reference voltage.

8. The voltage monitoring circuit according to claim 7, characterized in that: The values ​​of the third resistor and the fourth resistor meet the following restrictions: Among them, Vdov0 is the overvoltage diode voltage drop, R0_3 is the third resistor, R0_4 is the fourth resistor, Vin0_ov is the overvoltage threshold, and Vcom_ref is the reference voltage of the positive input terminal of the comparator.

9. The voltage monitoring circuit according to claim 1, characterized in that: The switch group is connected between an external power supply and at least two DC modules, and the at least two DC modules are connected to power supply terminals of the at least two target chips in a one-to-one correspondence.

10. The voltage monitoring circuit according to claim 3, characterized in that: The first voltage-dividing resistor and the second voltage-dividing resistor are connected in series between a DC converter and a ground terminal, the DC converter is connected between the external power supply and the first voltage-dividing resistor, and the second voltage-dividing resistor is connected between the first voltage-dividing resistor and the ground terminal, wherein the DC converter outputs a comparator reference voltage.

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