Soft start circuit with fixed slope

Abstract

The invention belongs to the field of integrated circuit power supply chip design, and relates to a soft start circuit with a fixed slope, which comprises a soft start circuit, an external voltage division circuit and a digital signal, the soft start circuit comprises a capacitor array, a digital signal is accessed to the capacitor array, and the soft start time of the soft start circuit is controlled by controlling the capacitance in the capacitor array; the external voltage division circuit comprises a resistor array, a digital signal is accessed to the resistor array, and the magnitude of the output voltage of the external voltage division circuit is controlled by controlling the magnitude of effective resistance in the resistor array; according to the soft start circuit disclosed by the invention, the capacitance of the capacitor array of the soft start circuit and the effective resistance of the resistor array of the external voltage division circuit are controlled through digital signals, so that the soft start time is correspondingly changed under different output voltages, and the output voltage with fixed slope rising is realized; and large current impact caused by too short starting time is avoided, so that the power consumption of the whole circuit is reduced, and the system efficiency is improved.

Description

Technical Field

[0001] The invention belongs to the field of integrated circuit power chip design and relates to a soft start circuit with a fixed slope. Background Art

[0002] The soft start circuit is a basic protection module in many integrated circuit chips and is widely used in analog integrated circuits. It can smooth the current impact during the startup process and reduce the impact on the power supply and load. The design goal of the soft start circuit is to achieve a smooth startup by gradually increasing the current, thereby reducing current impact and equipment damage.

[0003] Figure 1 This is a traditional fixed rise time soft start circuit. This soft start mode means that the output voltage gradually rises from zero to the set value within a preset time period. The fixed rise time soft start circuit consists of an error amplifier EA, a power PMOS tube P1, a resistor feedback network R1, R2, and a load resistor R L , load capacitance C L and capacitor C, where I REF is the zero-temperature current of the bandgap reference output, V REF is the bandgap reference output voltage. Before starting, the output voltage V OUT is low level, after the power is turned on, I REF The capacitor C is charged, and the voltage V across the capacitor C C will rise slowly. C <V REF , the output voltage of the error amplifier will also rise slowly, thus making the output voltage V OUT After charging capacitor C for a certain period of time, V C Will rise to a value greater than or equal to V REF , at this time the feedback voltage V FB will switch to V REF The error amplifier outputs a stable voltage, and the soft start circuit outputs a voltage V OUT Stable, soft start completed.

[0004] Since the bandgap reference output voltage V REF and zero temperature current I REF Fixed, so the startup time T SS It is only determined by the capacitance of capacitor C. Figure 2 This is a schematic diagram of the output voltage of a traditional fixed rise time soft start circuit. As the output voltage increases, the soft start becomes steeper and steeper. When the output voltage is high, the fixed rise time soft start circuit is prone to cause surge current, causing the output voltage to be too high instantly, thereby damaging the application equipment.

[0005] Therefore, the soft start circuit with a fixed rise time cannot adjust the soft start time according to the variation range of the output voltage. When the output voltage varies greatly, the soft start circuit with a fixed rise time may have an overshoot phenomenon, making the effect of the soft start circuit not obvious. Summary of the invention

[0006] In order to solve the above-mentioned problems in the prior art, the present invention adopts a soft start circuit with a fixed slope, including: a soft start circuit, an external voltage divider circuit and a digital signal; the soft start circuit includes a capacitor array, the digital signal is connected to the capacitor array, and the soft start time of the soft start circuit is controlled by controlling the size of the capacitor in the capacitor array; the external voltage divider circuit includes a resistor array, the digital signal is connected to the resistor array, and the size of the output voltage of the external voltage divider circuit is controlled by controlling the size of the effective resistance in the resistor array.

[0007] The external voltage divider circuit also includes: an error amplifier EA, a PMOS tube P1 and a resistor R; the negative input terminal of the error amplifier EA is connected to the soft start circuit, the source of the PMOS tube P1 is connected to the power supply, the gate is connected to the output terminal of the error amplifier EA, the drain is connected to one end of the resistor array, the other end of the resistor array is connected to the positive input terminal of the error amplifier EA and one end of the resistor R, and the other end of the resistor R is grounded.

[0008] The external voltage divider circuit also includes: load resistor R L and load capacitance C L , load resistance R L and load capacitance C L One end of each is connected to the drain of the PMOS tube P1, and the other end is grounded.

[0009] The resistor array includes: multiple resistors R connected in series NCi And its control circuit S R,i ; Control circuit S R,i Including: NMOS tube NM R,i and inverter INV R,i ; Resistance R NCi The two ends of the NMOS tube NM R,i The source and drain of NMOS tube NM R,i The gate of the inverter INV R,i The output terminal of the inverter INV is connected R,i The input terminal is connected to the digital signal NC i ; Where i is the index of the digital signal.

[0010] The soft start circuit also includes: an error amplifier A1, a MOS tube M1, a MOS tube M2, a MOS tube M3, a resistor R, a bias current source, and a reference voltage V REFOne end of the bias current source is connected to the power supply, and the other end is connected to the drain of the MOS tube M1. The drain of the MOS tube M1 is connected to the gate. The source of the MOS tube M1 is connected to one end of the capacitor array, and the other end of the capacitor array is grounded. The drain of the MOS tube M2 is connected to the power supply, the gate is connected to the gate of the MOS tube M1, the source is connected to the negative input end of the error amplifier A1 and one end of the resistor R, and the other end of the resistor R is grounded. The positive input end of the error amplifier A1 is connected to the reference voltage V REF , the output end is connected to the gate of the MOS tube M3, the source of the MOS tube M3 is connected to the power supply, and the drain is connected to the drain of the MOS tube M1.

[0011] The capacitor array includes: a plurality of parallel capacitor circuits S C,i , capacitor circuit S C,i Including: Capacitor C NCi And NMOS tube NM C,i ; Capacitor C NCi One end of the NMOS tube NM R,i The source of the NMOS tube is connected and the other end is grounded; R,i The gate access digital signal NC i , the drain is connected to the source of the MOS tube M1; wherein i is the index of the digital signal.

[0012] The soft start circuit also includes: an inverter I1 and an inverter I2; the input end of the inverter I1 is connected to the output end of the error amplifier A1, and the output end is connected to the input end of the inverter I2; the output end of the inverter I2 is connected to the gate of the MOS tube M3.

[0013] Beneficial effects:

[0014] The soft start circuit of the present invention controls the charging capacitance of the capacitor array of the soft start circuit and the effective resistance of the resistor array of the external voltage divider circuit through digital signals to achieve corresponding changes in the soft start time under different output voltages, thereby achieving an output voltage with a fixed slope increase, avoiding the generation of a large current shock due to a too short start time, thereby reducing the power consumption of the overall circuit, improving system efficiency, and better protecting power devices and extending the service life of the devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 This is a traditional soft start circuit diagram with fixed on-time;

[0016] Figure 2 It is a schematic diagram of the output voltage of a traditional fixed on-time soft start circuit;

[0017] Figure 3 A soft start circuit diagram with a fixed slope provided by an embodiment of the present invention;

[0018] Figure 4 An internal circuit diagram of a resistor array provided by an embodiment of the present invention;

[0019] Figure 5 A soft start circuit diagram provided by an embodiment of the present invention;

[0020] Figure 6 This is a simulation diagram of soft-start fixed slope power-on under different output voltages provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0021] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0022] In response to the problems of soft-start circuits with fixed rise time, the present invention proposes a fixed slope soft-start circuit. Compared with fixed time soft start, fixed slope soft start can adapt to different output voltages and load conditions, provide a smoother starting process, and reduce the impact on the load.

[0023] The fixed slope soft start circuit designed by the present invention uses a digital signal to control an external voltage divider circuit to control the output voltage. The topology of the external voltage divider circuit is as follows: Figure 3 As shown, it specifically includes: error amplifier EA, power tube PMOS tube P1, load resistor R L , load capacitance C L and a resistor feedback network consisting of a resistor R and a resistor array;

[0024] The negative input terminal of the error amplifier EA is connected to the soft start circuit, the source of the PMOS tube P1 is connected to the power supply VDD, the gate is connected to the output terminal of the error amplifier EA, the drain is connected to one end of the resistor array, the other end of the resistor array is connected to the positive input terminal of the error amplifier EA and one end of the resistor R, and the other end of the resistor R is grounded R NCi , load resistance R L and load capacitance C L One end of each is connected to the drain of the power tube P1, and the other end is connected to the ground GND.

[0025] The internal circuit of the resistor array is as follows Figure 4 As shown, it specifically includes: a plurality of resistors R connected in series NCi And its control circuit S R,i ; Control circuit S R,i Including: NMOS tube NM R,i and inverter INV R,i; Resistance R NCi The two ends of the NMOS tube NM R,i The source and drain of NMOS tube NM R,i The gate of the inverter INV R,i The output terminal of the inverter INV is connected R,i The input terminal is connected to the digital signal NC i ; Where i is the index of the digital signal.

[0026] Combination Figure 3 , Figure 4 It can be seen that different V outputs can be achieved by simply changing the digital signal that controls the resistor array. OUT , digital signal NC1~NC 13 Control the output voltage to output different voltage values, namely V1~V 13 If you want to make V OUT =V1, just connect the digital signal NC1 to a high level, and the other digital signals to a low level. After the inverter is reversed, NC1 is at a low level, and the gate of the NMOS tube connected to the inverter is input to turn it off, while the other NMOS tubes are all turned on, and the resistance controlled by them is short-circuited, so that the effective resistance of the access circuit is only the resistance controlled by the NC1 signal. Therefore, the output voltage can be adjusted by adjusting the digital signal. Correspondingly, these control signals will also be introduced into the soft start circuit to control the start time.

[0027] The soft start circuit structure designed by the present invention is as follows Figure 5 As shown, it specifically includes: a capacitor array, an error amplifier A1, MOS tubes M1-M3, a resistor R, a bias current source, and a reference voltage V REF ; The current output by the bias current source is the bias current I BIAS One end of the bias current source is connected to the power supply, and the other end is connected to the drain of the MOS tube M1. The drain of the MOS tube M1 is connected to the gate. The source of the MOS tube M1 is connected to one end of the capacitor array, and the other end of the capacitor array is grounded. The drain of the MOS tube M2 is connected to the power supply, the gate is connected to the gate of the MOS tube M1, the source is connected to the negative input end of the error amplifier A1 and one end of the resistor R, and the other end of the resistor R is grounded. The positive input end of the error amplifier A1 is connected to the reference voltage V REF The output end is connected to the gate of the MOS tube M3, the source of the MOS tube M3 is connected to the power supply, and the drain is connected to the drain of the MOS tube M1; the source of the MOS tube M2 is also connected to the negative input end of the error amplifier EA of the external voltage divider circuit.

[0028] The capacitor array includes: a plurality of parallel capacitor circuits S C,i , capacitor circuit S C,i Including: Capacitor C NCiAnd NMOS tube NM C,i ; Capacitor C NCi One end of the NMOS tube NM R,i The source of the NMOS tube is connected and the other end is grounded; R,i The gate access digital signal NC i , the drain is connected to the source of the MOS tube M1.

[0029] When the digital signal NC1 is high and the others are low, only the NMOS tube controlled by NC1 is turned on, and the NMOS tubes controlled by the other digital signals are all turned off, so the bias current I BIAS Only for capacitor C NC1 Since MOS tubes M1 and M2 form a current mirror, the source voltages of MOS tubes M1 and M2 are the same. When the soft start output voltage SS_OUT rises to the reference voltage V REF When the error amplifier A1 outputs a low level, after passing through the inverters I1 and I2, the PMOS tube M3 is turned on, and the power supply voltage VDD is immediately supplied to the capacitor C through M3. NC1 A large current is injected, causing the soft-start output voltage SS_OUT to immediately rise to the power supply voltage VDD. After the soft-start output voltage SS_OUT is pulled high, the control of the error amplifier in the loop is lost, and the soft-start ends. Different digital signals can achieve the bias current I BIAS Different capacitors are charged. When multiple control signals are at a high level, the soft start charging capacitors are connected in parallel. Therefore, this part can increase or decrease the soft start power-on time. Therefore, with the cooperation of the resistor array and the soft start circuit, different output voltages V OUT In this case, a soft start function with a fixed slope is realized.

[0030] like Figure 6 As shown in the figure, compared with the traditional fixed rise time soft start circuit, the fixed slope soft start circuit can better protect the power device. When the output voltage changes, the current and voltage of the device will change smoothly at startup, reducing the possibility of startup shock and mutation, which helps to extend the life of the power device and improve the reliability of the system. In addition, when a large output voltage is generated, this soft start circuit can avoid the generation of large current shocks due to too short startup time, thereby reducing power consumption and improving system efficiency.

[0031] The above embodiments further illustrate the purpose, technical solutions and advantages of the present invention in detail. It should be understood that the above embodiments are only preferred implementation modes of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made to the present invention within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A fixed slope soft start circuit, characterized in that: include: A soft start circuit, an external voltage divider circuit and a digital signal; the soft start circuit includes a capacitor array, the digital signal is connected to the capacitor array, and the soft start time of the soft start circuit is controlled by controlling the size of the capacitor in the capacitor array; the external voltage divider circuit includes a resistor array, the digital signal is connected to the resistor array, and the size of the output voltage of the external voltage divider circuit is controlled by controlling the size of the effective resistance in the resistor array.

2. A fixed slope soft start circuit according to claim 1, characterized in that: The external voltage divider circuit also includes: an error amplifier EA, a PMOS tube P1 and a resistor R; the negative input terminal of the error amplifier EA is connected to the soft start circuit, the source of the PMOS tube P1 is connected to the power supply, the gate is connected to the output terminal of the error amplifier EA, the drain is connected to one end of the resistor array, the other end of the resistor array is connected to the positive input terminal of the error amplifier EA and one end of the resistor R, and the other end of the resistor R is grounded.

3. A fixed slope soft start circuit according to claim 2, characterized in that: The external voltage divider circuit also includes: load resistor R L and load capacitance C L , load resistance R L and load capacitance C L One end of each is connected to the drain of the PMOS tube P1, and the other end is grounded.

4. The fixed slope soft start circuit according to claim 1, characterized in that: The resistor array includes: multiple resistors R connected in series NCi And its control circuit S R,i ; Control circuit S R,i Including: NMOS tube NM R,i and inverter INV R,i ; Resistance R NCi The two ends of the NMOS tube NM R,i The source and drain of NMOS tube NM R,i The gate of the inverter INV R,i The output terminal of the inverter INV is connected R,i The input terminal is connected to the digital signal NC i ; Where i is the index of the digital signal.

5. The fixed slope soft start circuit according to claim 1, characterized in that: The soft start circuit also includes: an error amplifier A1, a MOS tube M1, a MOS tube M2, a MOS tube M3, a resistor R, a bias current source, and a reference voltage V REF One end of the bias current source is connected to the power supply, and the other end is connected to the drain of the MOS tube M1. The drain of the MOS tube M1 is connected to the gate. The source of the MOS tube M1 is connected to one end of the capacitor array, and the other end of the capacitor array is grounded. The drain of the MOS tube M2 is connected to the power supply, the gate is connected to the gate of the MOS tube M1, the source is connected to the negative input end of the error amplifier A1 and one end of the resistor R, and the other end of the resistor R is grounded. The positive input end of the error amplifier A1 is connected to the reference voltage V REF , the output end is connected to the gate of the MOS tube M3, the source of the MOS tube M3 is connected to the power supply, and the drain is connected to the drain of the MOS tube M1.

6. A fixed slope soft start circuit according to claim 5, characterized in that: The capacitor array includes: a plurality of parallel capacitor circuits S C,i , capacitor circuit S C,i Including: Capacitor C NCi And NMOS tube NM C,i ; Capacitor C NCi One end of the NMOS tube NM R,i The source of the NMOS tube is connected and the other end is grounded; R,i The gate access digital signal NC i , the drain is connected to the source of the MOS tube M1; wherein i is the index of the digital signal.

7. The fixed slope soft start circuit according to claim 5, characterized in that: The soft start circuit also includes: an inverter I1 and an inverter I2; the input end of the inverter I1 is connected to the output end of the error amplifier A1, and the output end is connected to the input end of the inverter I2; the output end of the inverter I2 is connected to the gate of the MOS tube M3.

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