Follower for adjusting voltage mismatch

Abstract

The invention relates to the technical field of integrated circuits, and discloses a follower for adjusting voltage mismatch, which comprises a first-stage follower, an error amplifier EA and a second-stage follower which are electrically connected in sequence. The problem that voltage mismatch is difficult to adjust in the prior art is solved.

Description

Technical Field

[0001] The invention relates to the technical field of integrated circuits, in particular to a follower for adjusting voltage mismatch. Background Art

[0002] In analog integrated circuits, common drain amplifiers have large bandwidth, low output impedance, and voltage gain close to one, so they are widely used as circuit output buffer driver stages, also known as source followers. Source followers have the characteristics of simple circuit structure, high speed, and high linearity. Their output voltage can change with the input voltage, showing good AC following characteristics.

[0003] However, the output voltage and input voltage of the basic source follower always produce a fixed voltage difference, resulting in an inconsistency in the DC levels of the two. The output voltage of the source follower based on the NMOS tube is the input voltage minus the gate-source voltage, and the output voltage of the source follower based on the PMOS tube is the input voltage plus the gate-source voltage.

[0004] In the prior art, PMOS and NMOS complementary source follower structures are often used to make the DC level of the input voltage consistent with the output voltage. There are two complementary source follower structures in the prior art. Figure 1 As shown, the input signal VIN first passes through the first-stage PMOS source follower MP1, raising the voltage |VGS_P|, and then passes through the second-stage NMOS source follower MN1, reducing the voltage VGS_N, making the voltage values ​​of |VGS_P| and VGS_N the same, and the output voltage with a DC level consistent with the input voltage can be obtained. Figure 2 As shown, the input signal VIN first passes through the first-stage NMOS source follower MN1, the voltage is reduced to VGS_N, and then passes through the second-stage PMOS source follower MP1, the voltage is raised |VGS_P|, so that the voltage values ​​of VGS_N and |VGS_P| are the same, and an output voltage with a DC level consistent with the input voltage can be obtained.

[0005] However, the deviation of the manufacturing process may cause mismatch of the threshold voltage, etc., which will result in the inability of the traditional PMOS and NMOS complementary source follower structure to completely eliminate the DC level deviation between the input voltage and the output voltage.

[0006] At the same time, if Figure 3As shown, the basic source follower also has the problem of inconsistent capabilities of pulling current (I_Up) and sinking current (I_Down). Taking the basic source follower with a current source as a load as an example, its current sinking capability (I_Down) depends on the current flowing through MN4. When the source follower needs to drive a larger load capacitor CL, a larger bias current needs to be set to meet the current sinking requirement. A large bias current also means higher power consumption. MN4 working in the saturation region is used as a current source load, and the output impedance is limited, which greatly limits the output swing of the source follower.

[0007] How to adjust the DC level mismatch between the input voltage and output voltage of the source follower and ensure that the sink current and source current capabilities of the output are consistent is of great significance for reducing power consumption and increasing output swing. Therefore, it is urgent to design a wide-swing source follower with voltage mismatch adjustment. Summary of the invention

[0008] In order to overcome the deficiencies of the prior art, the present invention provides a follower for adjusting voltage mismatch, which solves the problem that the prior art is difficult to adjust voltage mismatch.

[0009] The technical solution adopted by the present invention to solve the above problems is:

[0010] A follower for adjusting voltage mismatch comprises a first-stage follower, an error amplifier EA and a second-stage follower which are electrically connected in sequence.

[0011] As a preferred technical solution, the first-stage follower and the second-stage follower are both source followers.

[0012] As a preferred technical solution, the first-stage follower is a PMOS source follower, and the second-stage follower is an NMOS source follower.

[0013] As a preferred technical solution, the first-stage follower includes a current source IB1 and a PMOS tube MP1, and the second-stage follower includes an NMOS tube MN1 and an NMOS tube MN2. The first input terminal of EA is used to connect to the voltage input terminal, and the second input terminal of EA is used to connect to the voltage output terminal; the gate (g pole) of MP1 is electrically connected to the first input terminal of EA, the source (s pole) of MP1, IB1, and the drain (d pole) of MN1 are electrically connected in sequence, the s pole of MP1 is electrically connected (coupled) to the g pole of MN1, and the d pole of MP1 is grounded; the s pole of MN1 is electrically connected to the in-phase input terminal of EA and the d pole of MN2 respectively; the g pole of MN2 is electrically connected (coupled) to the output terminal of EA, and the s pole of MN2 is grounded.

[0014] As a preferred technical solution, the error amplifier EA is a single-power supply operational amplifier with dual-end input and single-end output.

[0015] As a preferred technical solution, the model of the error amplifier EA is AD8531, OPA343 or TSL6201.

[0016] As a preferred technical solution, the first-stage follower is an NMOS source follower, and the second-stage follower is a PMOS source follower.

[0017] As a preferred technical solution, the first-stage follower includes an NMOS tube MN1 and a current source IB1, and the second-stage follower includes a PMOS tube MP1 and a PMOS tube MP2. The first input terminal of EA is used to connect to the voltage input terminal, and the second input terminal of EA is used to connect to the voltage output terminal; the g pole of MN1 is electrically connected to the first input terminal of EA, the d pole of MN1 and the s pole of MP2 are electrically connected to each other, the s pole of MN1 is electrically connected to the g pole of MP1, and the s pole of MN1, IB1, and ground are electrically connected in sequence; the g pole of MP2 is electrically connected to the output terminal of EA, the d pole of MP2 is electrically connected to the in-phase input terminal of EA, and the d pole of MP2 is electrically connected to the s pole of MP1; the d pole of MP1 is grounded.

[0018] As a preferred technical solution, the error amplifier EA is a single-power supply operational amplifier with dual-end input and single-end output.

[0019] As a preferred technical solution, it also includes a bias circuit electrically connected to the first-stage follower.

[0020] Compared with the prior art, the present invention has the following beneficial effects:

[0021] The source follower structure proposed in the present invention is simple and has the ability to adjust voltage mismatch without affecting the high speed and high stability of the source follower, which can ensure that the DC levels of the input voltage and the output voltage are consistent. At the same time, the source follower structure proposed in the present invention has consistent current pulling and current sinking capabilities for the load, and has a wider output swing than traditional source followers. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 A schematic diagram of a structure of an existing PMOS and NMOS complementary source follower;

[0023] Figure 2 Another structural schematic diagram of an existing PMOS and NMOS complementary source follower;

[0024] Figure 3 It is a schematic diagram of the structure of a basic NMOS source follower with a current source as a load;

[0025] Figure 4 A schematic diagram of a wide swing source follower with voltage mismatch adjustment according to the present invention;

[0026] Figure 5 A circuit diagram of a wide swing source follower with voltage mismatch adjustment according to the present invention;

[0027] Figure 6 Another structural diagram of the wide swing source follower with voltage mismatch adjustment of the present invention. DETAILED DESCRIPTION

[0028] The present invention will be further described in detail below in conjunction with embodiments and drawings, but the embodiments of the present invention are not limited thereto.

[0029] Example 1

[0030] like Figures 1 to 6 As shown, the wide swing source follower architecture with voltage mismatch adjustment of the present invention is as follows Figure 4 shown.

[0031] like Figure 5 As shown, the present invention provides a wide swing source follower with voltage mismatch adjustment, including: a bias circuit, a first-stage PMOS source follower, a second-stage NMOS source follower, and an error amplifier with dual-end input and single-end output.

[0032] The bias circuit provides a reasonable bias voltage for the first-stage source follower and error amplifier, including the cascode PMOS tubes MP8, MP9 and the bias current IBIAS. The cascode PMOS tubes MP8, MP9 and the first source follower MP2, MP3, and the error amplifier MP6, MP7 form two sets of cascode structures, which can achieve a more accurate proportional "copy" of the current IBIAS.

[0033] The first-stage PMOS source follower is used to receive the input voltage signal VIN and output voltage to the second-stage NMOS source follower. MP1 serves as a PMOS tube with a common drain, and MP2 and MP3 form a common-source and common-gate current source as the load of the source follower.

[0034] The second-stage NMOS source follower is used to receive the output voltage of the first-stage PMOS source follower, the output voltage is the output terminal VOUT, MN1 serves as a common drain NMOS tube, and MN2 serves as a current source load.

[0035] In one embodiment, the amplifier EA in FIG. 4 is implemented using MP4, MP5, MN3, MN4, and MN2. The error amplifier with dual-end input and single-end output is used to form a closed-loop feedback structure to ensure that the DC level of the input voltage VIN is consistent with the output voltage VOUT. MP6 and MP7 constitute a common source and common gate current source, which provides a bias current as a tail current source of the error amplifier. MP3 and MP4 serve as a differential input pair of tubes, the gate of MP4 receives the input voltage VIN, and the gate of MP5 receives the output voltage VOUT. MN3 and MN4 are diode-connected NMOS transistors, which serve as loads of the differential input pair of the error amplifier. The drain end of MP4 serves as the output end of the error amplifier, connected to the gate of MN2, and can dynamically adjust the current size of MN2, thereby stabilizing the output voltage VOUT and ensuring that the current sinking capability of the VOUT end is consistent with the current sourcing capability.

[0036] Figure 4 , Figure 6 Middle: The substrates of PMOS tubes are connected to VCC, and the substrates of NMOS tubes are connected to GND.

[0037] Figure 5 Middle: Except that the substrates of the PMOS tubes MP4 and MP5 are connected to their corresponding sources; the substrates of the PMOS tubes MP1-MP3, MP6-MP9 are all connected to VCC; and the substrates of the NMOS tubes MN1-MN4 are all connected to GND.

[0038] It is worth noting that the error amplifier EA can use a single-supply operational amplifier with dual-end input and single-end output. Figure 5 In addition to the specific structure of the error amplifier EA shown in , other operational amplifier structures of a sleeve type or folded common source and common gate structure can also be used. If the circuit of the present invention is constructed using discrete devices, the error amplifier EA can also use existing chips such as ADI's AD8531, TI's OPA343, ST's TSL6201, etc.

[0039] In one embodiment, the first input terminal is an inverting terminal, and the second input terminal is a non-inverting terminal. In other embodiments, those skilled in the art can set the first input terminal to a non-inverting terminal and the second input terminal to a reverse terminal according to system requirements.

[0040] The wide-swing source follower with voltage mismatch adjustment proposed in the present invention adopts a PMOS and NMOS complementary source follower structure and introduces a dual-end input and single-end output error amplifier to ensure that the DC levels of the input voltage and the output voltage are consistent on the one hand, and to form a closed-loop negative feedback structure on the other hand to dynamically adjust the bias current of the second-stage NMOS source follower, thereby achieving consistency between the pull current and the sink current of the load and increasing the output voltage swing.

[0041] In summary, the source follower structure proposed in the present invention is simple, and has the ability to adjust voltage mismatch without affecting the high speed and high stability of the source follower, which can ensure that the DC levels of the input voltage and the output voltage are consistent; at the same time, the source follower structure proposed in the present invention has consistent current pulling and current sinking capabilities for the load, and has a wider output swing compared to traditional source followers.

[0042] The following will refer to Figure 5 The working principle of the present invention is described in more detail with reference to an example.

[0043] Figure 5 In the figure, VCC is connected to the s-pole of MP3, the s-pole of MP7, and the d-pole of MN1 respectively, the g-pole of MP3 is connected to the g-pole of MP7, and the d-pole of MP3 is connected to the s-pole of MP2; the g-pole of MP2 is connected to the g-pole of MP6, and the d-pole of MP2 is connected to the s-pole of MP1 and the g-pole of MN1 respectively; the g-pole of MP1 is connected to the input signal VIN and the g-pole of MP4 respectively, and the d-pole of MP1 is grounded; the d-pole of MP7 is connected to the s-pole of MP6; the d-pole of MP6 is connected to the s-pole of MP4 and the s-pole of MP5 respectively; the d-pole of MP4 is connected to the d-pole of MN4, the g-pole of MN4, and the g-pole of MN2 respectively; the s-pole of MN4 is grounded; the d-pole of MP5 is connected to the d-pole of MN3 and the g-pole of MN3 respectively, and the g-pole of MP5 is connected to the signal output terminal VOUT, the d-pole of MN2, and the s-pole of MN1 respectively; the s-pole of MN3 is grounded; the s-pole of MN2 is grounded.

[0044] Analysis on how to ensure that the DC level of input voltage and output voltage remain consistent:

[0045] like Figure 5 As shown in the figure, when the input voltage VIN is greater than the output voltage VOUT, the voltage at the output of the error amplifier, i.e., the gate voltage of MN2, decreases, which reduces the current flowing through MN1 and MN2, thereby reducing the gate-source voltage difference VGS_N of MN1. The output voltage VOUT is equal to the gate voltage of MN1 minus the gate-source voltage difference VGS_N of MN1, so the output voltage VOUT increases. Finally, the system will stabilize in a state where the output voltage VOUT is equal to the input voltage VIN.

[0046] like Figure 5 As shown in the figure, when the input voltage VIN is less than the output voltage VOUT, the voltage at the output of the error amplifier, i.e., the gate voltage of MN2, increases, which increases the current flowing through MN1 and MN2, thereby increasing the gate-source voltage difference VGS_N of MN1. The output voltage VOUT is equal to the gate voltage of MN1 minus the gate-source voltage difference VGS_N of MN1, so the output voltage VOUT decreases. Finally, the system will stabilize in a state where the output voltage VOUT is equal to the input voltage VIN.

[0047] Analysis on how to ensure that the current sourcing capability and current sinking capability of the load remain consistent:

[0048] like Figure 5 As shown, the source of MN1 is the output terminal VOUT, which has a strong ability to pull current (I_Up) to the load. The ability to sink current (I_Down) to the load, that is, the pull-down ability of the output terminal VOUT, depends on the current flowing through the MN2 tube.

[0049] When the output voltage VOUT is high, the output end is in a current sourcing state, and the MN1 tube provides the output current required by the load to source current. Its capability is strong and is not affected by the MN2 tube.

[0050] When the output voltage VOUT is at the intermediate voltage, the magnitude of the current flowing through MN1 is proportional to the width-to-length ratio of MN2 to MN4, and the circuit is in a typical working state.

[0051] When the output voltage VOUT is low, the source voltage of MP4 and MP5 is also low, the bias current of the branch where MP6 and MP7 are located becomes larger, the current of the MN4 tube increases, thereby increasing the gate voltage of the MN2 tube and increasing the current of the MN1 tube, ensuring that the pull-down capability of the load remains unchanged.

[0052] like Figure 6 As shown, another architecture of the wide swing source follower with voltage mismatch adjustment of the present invention can also adopt a first stage of NMOS source follower and a second stage of PMOS source follower. This similar structure is also within the protection scope of the present invention.

[0053] The wide swing source follower with voltage mismatch adjustment of the present invention is also applicable to the emitter follower in the bipolar transistor circuit.

[0054] As described above, the present invention can be preferably implemented.

[0055] All features disclosed in all embodiments in this specification, or steps in all methods or processes implicitly disclosed, except for mutually exclusive features and / or steps, can be combined and / or expanded or replaced in any manner.

[0056] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form. According to the technical essence of the present invention, within the spirit and principles of the present invention, any simple modification, equivalent replacement and improvement made to the above embodiment still falls within the protection scope of the technical solution of the present invention.

Claims

1. A follower for adjusting voltage mismatch, characterized in that: It includes a first-stage follower, an error amplifier EA, and a second-stage follower which are electrically connected in sequence.

2. The voltage mismatch adjusting follower according to claim 1, characterized in that: The first-stage follower and the second-stage follower are both source followers.

3. The voltage mismatch adjusting follower according to claim 2, characterized in that: The first-stage follower is a PMOS source follower, and the second-stage follower is an NMOS source follower.

4. The voltage mismatch adjusting follower according to claim 3, characterized in that: The first-stage follower includes a current source IB1 and a PMOS tube MP1, and the second-stage follower includes an NMOS tube MN1 and an NMOS tube MN2. The first input terminal of EA is used to connect to the voltage input terminal, and the second input terminal of EA is used to connect to the voltage output terminal; the g pole of MP1 is electrically connected to the first input terminal of EA, the s pole of MP1, IB1, and the d poles of MN1 are electrically connected in sequence, the s pole of MP1 is electrically connected to the g pole of MN1, and the d pole of MP1 is grounded; the s pole of MN1 is electrically connected to the in-phase input terminal of EA and the d pole of MN2 respectively; the g pole of MN2 is electrically connected to the output terminal of EA, and the s pole of MN2 is grounded.

5. The voltage mismatch adjusting follower according to claim 3, characterized in that: The error amplifier EA is a single-supply operational amplifier with dual-end input and single-end output.

6. The voltage mismatch adjusting follower according to claim 5, characterized in that: The model of the error amplifier EA is AD8531, OPA343 or TSL6201.

7. The voltage mismatch adjusting follower according to claim 2, characterized in that: The first-stage follower is an NMOS source follower, and the second-stage follower is a PMOS source follower.

8. The voltage mismatch adjusting follower according to claim 7, characterized in that: The first-stage follower includes an NMOS tube MN1 and a current source IB1, and the second-stage follower includes a PMOS tube MP1 and a PMOS tube MP2. The first input terminal of EA is used to connect to the voltage input terminal, and the second input terminal of EA is used to connect to the voltage output terminal; the g pole of MN1 is electrically connected to the first input terminal of EA, the d pole of MN1 and the s pole of MP2 are electrically connected to each other, the s pole of MN1 is electrically connected to the g pole of MP1, and the s pole of MN1, IB1, and the ground are electrically connected in sequence; the g pole of MP2 is electrically connected to the output terminal of EA, the d pole of MP2 is electrically connected to the in-phase input terminal of EA, and the d pole of MP2 is electrically connected to the s pole of MP1; the d pole of MP1 is grounded.

9. The voltage mismatch adjusting follower according to claim 7, characterized in that: The error amplifier EA is a single-supply operational amplifier with dual-end input and single-end output.

10. A follower for adjusting voltage mismatch according to any one of claims 1 to 9, characterized in that: Also included is a bias circuit electrically connected to the first-stage follower.

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