High-energy-efficiency Pipelined-SAR hybrid ADC circuit based on time residual voltage amplifier
By using time-based residual voltage amplifiers and delay alignment circuits in Pipelined-SAR ADCs, the problems of high power consumption and PVT sensitivity are solved, and a low-power, high-precision ADC design is achieved.
Patent Information
- Application Number
- CN202411625634.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-14
- Publication Date
- 2025-01-10
AI Technical Summary
The existing Pipelined-SAR ADC intermediate inter-amplifiers have high power consumption and are sensitive to PVT, resulting in increased design complexity and making it difficult to achieve low-power, high-precision ADCs.
The time-based residual voltage amplifier is used as the interstage amplifier, and the time-residual voltage amplifier circuit and the delay alignment circuit are used to reduce the overall power consumption of the system and reduce the sensitivity to PVT changes.
A low-power, high-precision Pipelined-SAR ADC is realized, which significantly reduces system power consumption and reduces system gain errors caused by the amplifier.
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Figure CN119298911A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of integrated circuits, and more specifically, to a high-energy-efficiency Pipelined-SAR hybrid ADC circuit based on a time residual voltage amplifier. Background Art
[0002] In the current design of ADC (Analog-to-Digital Converter, A / D Converter), the trade-off between speed, accuracy and power consumption has attracted much attention. In order to meet the demand for higher accuracy and lower power consumption ADC in future application scenarios, hybrid architecture ADC combining the advantages of different architectures has become a research hotspot. Pipeline SAR ADC is a hybrid architecture ADC that combines the advantages of SAR ADC and Pipeline ADC. SAR ADC is an architecture with high energy efficiency ratio, but with the improvement of accuracy, the number of capacitors in the CDAC (charge redistribution digital-to-analog converter) array increases exponentially, and the comparator noise will also have a great impact on the performance, so it is only suitable for medium-precision fields. Pipeline ADC cascades multiple sub-ADCs and works in a pipeline manner. It has a good compromise in accuracy and speed, but due to the large number of active circuits such as its sub-level comparators, its power consumption is relatively large, which is not suitable for low-power application scenarios. Pipelined-SAR ADC inherits the low power consumption advantage of SAR ADC, while alleviating the problem of exponential growth of the number of capacitors in the capacitor array with the improvement of resolution brought by high-precision SAR ADC. It also reduces the number of active circuits such as sub-stage comparators in pipeline ADC, greatly reducing the overall power consumption and area of the circuit, making it a good choice for high-performance ADC.
[0003] One of the main challenges in achieving high-performance pipelined-SAR ADCs is the design of interstage amplifiers. As a bridge connecting the two-stage sub-SAR ADCs, the performance of the interstage amplifier will directly affect the performance of the entire ADC. At present, interstage amplifiers are mainly divided into two categories: one is an OTA-based amplifier and the other is a dynamic amplifier. In traditional pipeline ADCs, OTA-based amplifiers are usually used as interstage residual amplifiers. They have stable output, are insensitive to interference and noise, and have a controllable output signal range. However, the problem is that the exponential form of the establishment leads to slower speed, increased power consumption, and the existence of static power consumption. Compared with OTA-based operational amplifiers, dynamic amplifiers have significant advantages in speed and power consumption. However, when using dynamic amplifiers, it is necessary to consider issues such as gain nonlinearity and gain stability with PVT changes. Additional calibration techniques are required, which increases the hardware expenditure of the circuit and greatly increases the overall design complexity of the pipelined-SAR ADC. Summary of the invention
[0004] The purpose of the present invention is to provide a high-energy-efficiency Pipelined-SAR hybrid ADC circuit based on a time residual voltage amplifier in view of the above-mentioned deficiencies in the prior art, so as to solve the technical problems of high power consumption and PVT sensitivity of the inter-stage amplifier in the existing Pipelined-SAR ADC, thereby realizing a low-power, high-precision Pipelined-SAR ADC.
[0005] The technical solution of the present invention is:
[0006] The present invention provides a high-energy-efficiency Pipelined-SAR hybrid ADC circuit based on a time residual voltage amplifier, comprising the following circuits: a first-stage SAR ADC circuit, a time-based residual voltage amplifier circuit, a second-stage SAR ADC circuit, and a delay alignment circuit; wherein the time-based residual voltage amplifier circuit and the second-stage SAR ADC circuit simultaneously include a third capacitor array and a fourth capacitor array;
[0007] The two input signal ports V IP and V IN The two voltage output ports V of the first-stage SAR ADC circuit are connected to the differential input signals respectively. OUT1 and V OUT2 The two input signal ports V of the time-based residual voltage amplifier circuit are respectively IN1 and V IN2 The digital output port D of the first stage SAR ADC circuit is connected to OUT The input port D of the delay alignment circuit IN1 The digital output port D of the second-stage SAR ADC circuit is connected to OUT The input port D of the delay alignment circuit IN2 connected to the output port D of the delay alignment circuit OUT Output the final quantization result.
[0008] Furthermore, the first-stage SAR ADC circuit adopts a fully differential structure, including a first gate voltage bootstrap switch, a second gate voltage bootstrap switch, a first switch, a second switch, a first DAC module, a second DAC module, a first comparator, and a first SARLogic module, wherein the first DAC module includes a first capacitor array, and the second DAC module includes a second capacitor array; wherein the two input signal ports V IP and V INIt is also the input end of the first gate voltage bootstrap switch and the input end of the second gate voltage bootstrap switch. The two voltage output ports V OUT1 and V OUT2 The digital output port D of the first-stage SAR ADC circuit is OUT It is also the output 2 port of the first SAR Logic module; the input end of the first gate voltage bootstrap switch is connected to V IP signal, whose output end is connected to the lower plate of the first capacitor array; the input end of the first switch is connected to the common mode voltage V CM , whose output end is connected to the upper plate of the first capacitor array and the positive input end of the first comparator; the input end of the second gate voltage bootstrap switch is connected to V in the differential input signal IN signal, the output end of which is connected to the lower plate of the second capacitor array; the input end of the second switch is connected to the common mode voltage V CM , its output end is connected to the upper plate of the second capacitor array and the inverting input end of the first comparator; the output end of the first comparator is connected to the input end of the first SAR Logic module; the output 1 end of the first SAR Logic module is connected to the first DAC module, and the output 2 end of the first SAR Logic module is connected to the second DAC module.
[0009] Furthermore, the time-based residual voltage amplifier circuit includes a first capacitor, a second capacitor, a third DAC capacitor array, a fourth DAC capacitor array, 10 switches (φ3, φ4, φ5, φ6, φ7, φ8, φ9, φ10, φ11, φ12), a first current source, a second current source, a third current source, a fourth current source, a first decision circuit, a second decision circuit, and a third decision circuit; wherein the time-based residual voltage amplifier circuit has two input signal ports V IN1 and V IN2 It is also the input end of the switch φ3 and the input end of the switch φ4; the input end of the switch φ3 is connected to the upper plate of the first capacitor array in the first-stage SARADC, and its output end is connected to the upper plate of the first capacitor, the output end of the switch φ5, the input end of the switch φ7 and the input 2 end IN2 of the first decision circuit; the lower plate of the first capacitor and the input end of the switch φ5 are both connected to the voltage V CM; The output end of the switch φ7 is connected to the input end of the first current source, and the output end of the first current source is connected to the ground; the input end of the switch φ11 is connected to the power supply, and the output end of the switch φ11 is connected to the input end of the switch φ9, the upper board of the third DAC capacitor array and the input 1 end of the third decision circuit; the output end of the switch φ9 is connected to the input end of the third current source, and the output end of the third current source is connected to the ground; the input end of the switch φ4 is connected to the upper board of the second capacitor array in the first-stage SAR ADC, and its output end is connected to the upper board of the second capacitor, the output end of the switch φ6, the input end of the switch φ8 and the input 2 end IN2 of the second decision circuit; the lower plate of the second capacitor and the input end of the switch φ6 are both connected to the voltage V CM ; The output end of the switch φ8 is connected to the input end of the second current source, and the output end of the second current source is connected to the ground; the input end of the switch φ12 is connected to the power supply, the output end of the switch φ12 is connected to the input end of the switch φ10, the upper board of the fourth DAC capacitor array and the input 2 end of the third judgment circuit, the output end of the switch φ10 is connected to the input end of the fourth current source, and the output end of the fourth current source is connected to the ground; the output end of the third judgment circuit is connected to the input 1 end of the first judgment circuit and the input 1 end of the second judgment circuit.
[0010] Furthermore, the second-stage SAR ADC adopts a fully differential structure, including a third DAC module, a fourth DAC module, a second comparator, and a second SAR logic module, wherein the third DAC module includes a third capacitor array, and the fourth DAC module includes a fourth capacitor array; wherein the digital output port D of the second-stage SAR ADC circuit is OUT It is also the output 2 port of the second SARLogic module; the non-inverting input end of the second comparator is connected to the upper board of the third DAC capacitor array, the inverting input end is connected to the upper board of the fourth DAC capacitor array, and the output end is connected to the input end of the second SARlogic module; the output OUT1 end of the second SAR logic module is connected to the third DAC module, and the output OUT2 end of the second SAR logic module is connected to the fourth DAC module.
[0011] Compared with the prior art, the present invention has the following advantages:
[0012] The present invention realizes a high-energy-efficiency Pipelined-SAR ADC. Compared with the traditional solution, the present invention uses a time-residual voltage amplifier as an inter-stage amplifier, which greatly reduces the overall power consumption of the system; and because the gain of the amplifier is not sensitive to changes in PVT, this characteristic significantly reduces the system gain error caused by the amplifier, thereby realizing a low-power and high-precision Pipelined-SAR ADC. BRIEF DESCRIPTION OF THE DRAWINGS
[0013] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0014] Figure 1 It is a circuit diagram of a Pipelined-SAR ADC based on a time residual voltage amplifier of the present invention;
[0015] Figure 2 It is a working timing diagram of a Pipelined-SAR ADC based on a time residual voltage amplifier of the present invention;
[0016] Figure 3 It is a simulation result diagram of a Pipelined-SAR ADC based on a time residual voltage amplifier of the present invention. DETAILED DESCRIPTION
[0017] In order to make the purpose, technical scheme and advantages of the present invention more clearly understood, the specific embodiments of the present invention are described in detail below in conjunction with the accompanying drawings. Examples of these embodiments are illustrated in the accompanying drawings. The embodiments of the present invention shown in the accompanying drawings and described according to the accompanying drawings are merely exemplary and are not limited to these embodiments.
[0018] In addition, it should be noted that, in order to avoid obscuring the present invention due to unnecessary details, only structures and / or processing steps closely related to the solutions according to the present invention are shown in the drawings, while other details that are not closely related to the present invention are omitted. In addition, the terms "first" and "second" are used only for descriptive purposes and should not be understood as indicating or implying relative importance.
[0019] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0020] In order to illustrate the technical solution of the present invention, a specific embodiment is used below for description, and only the parts related to the embodiment of the present invention are shown.
[0021] See also Figure 1 A high-efficiency Pipelined-SAR hybrid ADC circuit based on a time residual voltage amplifier mainly includes: a first-stage SAR ADC circuit (SAR ADC 1), a time-based residual voltage amplifier circuit, a second-stage SAR ADC circuit (SAR ADC 2), and a delay alignment circuit; wherein the time-based residual voltage amplifier circuit and the second-stage SAR ADC circuit (SAR ADC 2) both include a third capacitor array (C DAC3 ) and the fourth capacitor array (C DAC4 ).
[0022] The two input signal ports V IP and V IN The two voltage output ports V of the first-stage SAR ADC circuit (SAR ADC 1) are respectively connected to the differential input signal. OUT1 and V OUT2 The two input signal ports V of the time-based residual voltage amplifier circuit are respectively IN1 and V IN2 The digital output port D of the first stage SAR ADC circuit (SAR ADC 1) is connected to OUT The input port D of the delay alignment circuit IN1 The digital output port D of the second-stage SAR ADC circuit (SAR ADC 2) is connected to OUT The input port D of the delay alignment circuit IN2 connected to the output port D of the delay alignment circuit OUT Output the final quantization result.
[0023] Specifically, the first-stage SAR ADC circuit (SAR ADC 1) adopts a fully differential structure, including a first gate voltage bootstrap switch (φS1), a second gate voltage bootstrap switch (φS2), a first switch (φ1), a second switch (φ2), a first DAC module (DAC1), a second DAC module (DAC2), a first comparator (COMP1), and a first SAR Logic module (SAR Logic1), wherein the first DAC module (DAC1) includes a first capacitor array (C DAC1 ), the second DAC module (DAC2) includes a second capacitor array (C DAC2 ); wherein the two input signal ports V IP and V IN are respectively the input end of the first gate voltage bootstrap switch (φS1) and the input end of the second gate voltage bootstrap switch (φS2), and the two voltage output ports V of the first stage SAR ADC circuit (SAR ADC 1) OUT1 and V OUT2 At the same time, the first capacitor array (C DAC1 ) and the upper plate voltage of the second capacitor array (C DAC2 ), the digital output port D of the first-stage SAR ADC circuit (SAR ADC 1) OUT It is also the output 2 port of the first SAR Logic module (SAR Logic1); the input end of the first gate voltage bootstrap switch (φS1) is connected to V in the differential input signal IP signal, whose output end is connected to the first capacitor array (C DAC1 ) lower plate; the input end of the first switch (φ1) is connected to the common mode voltage V CM , whose output end is connected to the first capacitor array (C DAC1 ) and the positive phase input terminal of the first comparator (COMP1); the input terminal of the second gate voltage bootstrap switch (φS2) is connected to V in the differential input signal IN signal, whose output end is connected to the second capacitor array (C DAC2 ) lower plate; the input end of the second switch (φ2) is connected to the common mode voltage V CM , whose output end is connected to the second capacitor array (C DAC2) and the inverting input terminal of the first comparator (COMP1); the output terminal of the first comparator (COMP1) is connected to the input terminal of the first SAR Logic module (SAR Logic1); the output 1 terminal of the first SAR Logic module (SAR Logic1) is connected to the first DAC module (DAC1), and the output 2 terminal of the first SAR Logic module (SAR Logic1) is connected to the second DAC module (DAC2).
[0024] Specifically, the time residual voltage amplifier circuit comprises a first capacitor (C1), a second capacitor (C2), a third DAC capacitor array (C DAC3 ), the fourth DAC capacitor array (C DAC4 ), 10 switches (φ3, φ4, φ5, φ6, φ7, φ8, φ9, φ10, φ11, φ12), a first current source (I1), a second current source (I2), a third current source (I3), a fourth current source (I4), a first decision circuit (Judge1), a second decision circuit (Judge2), and a third decision circuit (Judge3); wherein the time-based residual voltage amplifier circuit has two input signal ports V IN1 and V IN2 It is also the input end of the switch φ3 and the input end of the switch φ4; the input end of the switch φ3 is connected to the first capacitor array (C DAC1 ) is connected to the upper plate of the first capacitor (C1), and its output end is connected to the upper plate of the first capacitor (C1), the output end of the switch φ5, the input end of the switch φ7 and the input 2 end IN2 of the first judgment circuit (Judge1); the lower plate of the first capacitor (C1) and the input end of the switch φ5 are both connected to the voltage V CM The output end of the switch φ7 is connected to the input end of the first current source (I1), and the output end of the first current source (I1) is connected to the ground; the input end of the switch φ11 is connected to the power supply, and the output end of the switch φ11 is connected to the input end of the switch φ9, the third DAC capacitor array (C DAC3 ) and the input 1 end of the third judgment circuit (Judge3); the output end of the switch φ9 is connected to the input end of the third current source (I3), and the output end of the third current source (I3) is connected to the ground; the input end of the switch φ4 is connected to the second capacitor array (C DAC2) is connected to the upper plate of the second capacitor (C2), and its output end is connected to the upper plate of the second capacitor (C2), the output end of the switch φ6, the input end of the switch φ8 and the input 2 end IN2 of the second judgment circuit (Judge2); the lower plate of the second capacitor (C2) and the input end of the switch φ6 are both connected to the voltage V CM The output end of the switch φ8 is connected to the input end of the second current source (I2), and the output end of the second current source (I2) is connected to the ground; the input end of the switch φ12 is connected to the power supply, and the output end of the switch φ12 is connected to the input end of the switch φ10, the fourth DAC capacitor array (C DAC4 )'s upper board and the input 2 end of the third judgment circuit (Judge3), the output end of the switch φ10 is connected to the input end of the fourth current source (I4), and the output end of the fourth current source (I4) is connected to the ground; the output end of the third judgment circuit (Judge3) is connected to the input 1 end of the first judgment circuit (Judge1) and the input 1 end of the second judgment circuit (Judge2).
[0025] Specifically, the second-stage SAR ADC adopts a fully differential structure, including a third DAC module (DAC3), a fourth DAC module (DAC4), a second comparator (COMP2), and a second SAR logic module (SAR Logic2), wherein the third DAC module (DAC3) includes a third capacitor array (C DAC3 ), the fourth DAC module (DAC4) includes a fourth capacitor array (C DAC4 ); wherein the digital output port DOUT of the second-stage SAR ADC circuit (SAR ADC 2) is also the output 2 port of the second SAR Logic module (SARLogic2); the non-inverting input terminal of the second comparator (COMP2) is connected to the third DAC capacitor array (C DAC3 ) is connected to the upper board, and its inverting input terminal is connected to the fourth DAC capacitor array (C DAC4 ), and its output end is connected to the input end of the second SAR logic module (SAR Logic2); the output OUT1 end of the second SAR logic module (SARLogic2) is connected to the third DAC module (DAC3), and the output OUT2 end of the second SAR logic module (SARLogic2) is connected to the fourth DAC module (DAC4).
[0026] See also Figure 2The working timing of a high-efficiency Pipelined-SAR hybrid ADC circuit based on a time residual voltage amplifier includes: a sampling clock fs, a working clock comp1 of a first comparator (COMP1), a reset clock rst based on the time residual voltage amplifier, a residual transfer clock share, an amplification clock start based on the time residual voltage amplifier, an enable clock EN based on the time residual voltage amplifier, and a working clock comp2 of a second comparator (COMP2).
[0027] When the sampling clock fs is high, the sampling phase begins. The first gate voltage bootstrap switch (φS1) and the second gate voltage bootstrap switch (φS2) are closed, and the differential input signal is sampled into the first capacitor array (C DAC1 ) and the second capacitor array (C DAC2 ), and at the same time, the first switch (φ1) and the second switch (φ2) are also closed, so that the first capacitor array (C DAC1 ) and the second capacitor array (C DAC2 ) is charged to the common-mode voltage V CM .
[0028] The first comparator (COMP1) enters the holding phase before the sampling clock fs is low and the working clock comp1 is high. At this time, the first gate voltage bootstrap switch (φS1) and the second gate voltage bootstrap switch (φS2) are disconnected, and the first capacitor array (C DAC1 ) and the second capacitor array (C DAC2 ) and the common-mode voltage V CM The first switch (φ1) and the second switch (φ2) are disconnected, so that the first capacitor array (C DAC1 ) and the second capacitor array (C DAC2 ) is in a suspended state, and the sampled signal is transferred to the first capacitor array (C DAC1 ) and the second capacitor array (C DAC2 )'s upper plate.
[0029] When the working clock comp1 of the first comparator (COMP1) is high, the first comparator (COMP1) starts to detect the first capacitor array (C DAC1 ) and the second capacitor array (C DAC2), the first SAR Logic module (SAR Logic1) is used to control the first DAC module (DAC1) and the second DAC module (DAC2) to work according to the comparison result of the comparator to complete the process of successive approximation; the first SAR Logic module (SAR Logic1) obtains the first level quantization result Dout[M:N] after quantization, and the unquantized residual voltage is still maintained at the first capacitor array (C DAC1 ) and the second capacitor array (C DAC2 ) on the upper plate.
[0030] When the reset clock rst of the time-based residual voltage amplifier is high, the switches φ5 and φ6 are closed, so that the upper plates of the first capacitor (C1) and the second capacitor (C2) are reset to the common mode voltage V CM .
[0031] When the residual transfer clock share is high, the third judgment circuit (Judge3) outputs EN as a high level, entering the residual voltage amplification stage. At this time, the switches φ3 and φ4 are closed, so that the upper plate of the first capacitor (C1) and the first capacitor array (C DAC1 ) is connected to the upper plate of the second capacitor (C2), and the upper plate of the second capacitor array (C DAC2 ) is connected to the upper board, and the residual transfer is completed by charge sharing; at the same time, the switches φ11 and φ12 are closed, and the third capacitor array (C DAC3 ) and the fourth capacitor array (C DAC4 )’s upper plate is pre-charged to the supply voltage.
[0032] When the amplification clock start of the time-based residual voltage amplifier is high, the switches φ7 and φ8 are closed, allowing the first capacitor (C1) to discharge to the ground through the first current source (I1), and the second capacitor (C2) to discharge to the ground through the second current source (I2); when the voltage on the upper board of the first capacitor (C1) reaches the threshold voltage of the first judgment circuit (Judge1), the first judgment circuit (Judge1) outputs a high level TP; when the voltage on the upper board of the second capacitor (C2) reaches the threshold voltage of the second judgment circuit (Judge2), the second judgment circuit (Judge2) outputs a high level TN, wherein the threshold voltage of the first judgment circuit (Judge1) is equal to the threshold voltage of the second judgment circuit (Judge2); when the first judgment circuit (Judge1) outputs a high level TP, the switch φ9 is closed, and the third capacitor array (C DAC3) discharges to the ground through the third current source (I3), and when the second judgment circuit (Judge2) outputs a high level TN, the switch φ10 is closed, and the fourth capacitor array (C DAC4 ) discharges to ground through the fourth current source (I4), when the third capacitor array (C DAC3 ) or the fourth capacitor array (C DAC4 ) reaches the threshold voltage of the third judgment circuit (Judge3), the third judgment circuit (Judge3) outputs EN as a low level, completing the amplification of the residual voltage, and the amplified residual voltage is maintained at the third capacitor array (C DAC3 ) and the fourth capacitor array (C DAC4 )'s superior board.
[0033] When the working clock comp2 of the second comparator (COMP2) is high, the second comparator (COMP2) starts to detect the third capacitor array (C DAC3 ) and the fourth capacitor array (C DAC4 ) is compared with the holding signal on the upper plate, the second SAR Logic module (SAR Logic2) is used to control the third DAC module (DAC3) and the fourth DAC module (DAC4) to work according to the comparison result of the second comparator (COMP2), so as to complete the process of successive approximation; the second SARLogic module (SAR Logic2) obtains the second-level quantization result Dout[0:M-1] after quantization, and when the third sampling clock fs comes, the delay alignment combines the first-level quantization result Dout[M:N] and the second-level quantization result Dout[0:N-1] obtained by the first sampling into the final quantization result Dout[0:N] for output.
[0034] See also Figure 3 , a 14-bit high-efficiency pipelined-SAR hybrid ADC transient simulation FFT result based on time residual voltage amplifier. Set the first stage to 8-bits SAR ADC and the second stage to 6-bits SAR ADC; C DAC1 , C DAC2 , C1 and C2 have the same capacitance value, C DAC3 and C DAC4 The capacitance value is the same, C DAC1 and C DAC3The ratio is 4:1; the currents of current source I1 and current source I2 are the same, the currents of current source I3 and current source I4 are the same, and the current ratio of current source I1 to current source I3 is 1:4. The Pipelined-SAR ADC of the present invention has an effective number of bits (ENOB) of 13.76 bits, a signal-to-noise-distortion ratio (SNDR) of 84.61 dB, a spurious-free dynamic range (SFDR) of 98.7 dB, a power consumption of only 1.52 mW, and a quality factor FoMs value of 179.78 dB under an operating voltage of 1.8 V, a sampling frequency of 10 MS / s, an input signal frequency of 19.3 KHz, and a bandwidth of 5 MHz.
[0035] Although the preferred embodiments of the present invention have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.
[0036] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.
Claims
1. A high energy efficiency Pipelined-SAR hybrid ADC circuit based on a time residual voltage amplifier, characterized in that: The invention comprises the following circuits: a first-stage SAR ADC circuit, a time-based residual voltage amplifier circuit, a second-stage SAR ADC circuit, and a delay alignment circuit; wherein the time-based residual voltage amplifier circuit and the second-stage SAR ADC circuit simultaneously comprise a third capacitor array and a fourth capacitor array; The two input signal ports V IP and V IN The two voltage output ports V of the first-stage SAR ADC circuit are connected to the differential input signals respectively. OUT1 and V OUT2 The two input signal ports V of the time-based residual voltage amplifier circuit are respectively IN1 and V IN2 The digital output port D of the first stage SAR ADC circuit is connected to OUT The input port D of the delay alignment circuit IN1 The digital output port D of the second-stage SAR ADC circuit is connected to OUT The input port D of the delay alignment circuit IN2 connected to the output port D of the delay alignment circuit OUT Output the final quantization result.
2. The high energy efficiency Pipelined-SAR hybrid ADC circuit based on the time residual voltage amplifier according to claim 1, characterized in that: The first-stage SAR ADC circuit adopts a fully differential structure, including a first gate voltage bootstrap switch, a second gate voltage bootstrap switch, a first switch, a second switch, a first DAC module, a second DAC module, a first comparator, and a first SARLogic module, wherein the first DAC module includes a first capacitor array, and the second DAC module includes a second capacitor array; wherein the two input signal ports V IP and V IN It is also the input end of the first gate voltage bootstrap switch and the input end of the second gate voltage bootstrap switch. The two voltage output ports V OUT1 and V OUT2 The digital output port D of the first-stage SAR ADC circuit is OUT It is also the output 2 port of the first SAR Logic module; the input end of the first gate voltage bootstrap switch is connected to V IP signal, whose output end is connected to the lower plate of the first capacitor array; the input end of the first switch is connected to the common mode voltage V CM , whose output end is connected to the upper plate of the first capacitor array and the positive input end of the first comparator; the input end of the second gate voltage bootstrap switch is connected to V in the differential input signal IN signal, the output end of which is connected to the lower plate of the second capacitor array; the input end of the second switch is connected to the common mode voltage V CM , its output end is connected to the upper plate of the second capacitor array and the inverting input end of the first comparator; the output end of the first comparator is connected to the input end of the first SAR Logic module; the output 1 end of the first SAR Logic module is connected to the first DAC module, and the output 2 end of the first SAR Logic module is connected to the second DAC module.
3. The high energy efficiency Pipelined-SAR hybrid ADC circuit based on the time residual voltage amplifier according to claim 1, characterized in that: The time-based residual voltage amplifier circuit comprises a first capacitor, a second capacitor, a third DAC capacitor array, a fourth DAC capacitor array, 10 switches (φ3, φ4, φ5, φ6, φ7, φ8, φ9, φ10, φ11, φ12), a first current source, a second current source, a third current source, a fourth current source, a first decision circuit, a second decision circuit, and a third decision circuit; wherein the time-based residual voltage amplifier circuit has two input signal ports V IN1 and V IN2 It is also the input end of the switch φ3 and the input end of the switch φ4; the input end of the switch φ3 is connected to the upper plate of the first capacitor array in the first-stage SAR ADC, and its output end is connected to the upper plate of the first capacitor, the output end of the switch φ5, the input end of the switch φ7 and the input 2 end IN2 of the first decision circuit; the lower plate of the first capacitor and the input end of the switch φ5 are both connected to the voltage V CM ; The output end of the switch φ7 is connected to the input end of the first current source, and the output end of the first current source is connected to the ground; the input end of the switch φ11 is connected to the power supply, and the output end of the switch φ11 is connected to the input end of the switch φ9, the upper board of the third DAC capacitor array and the input 1 end of the third decision circuit; the output end of the switch φ9 is connected to the input end of the third current source, and the output end of the third current source is connected to the ground; the input end of the switch φ4 is connected to the upper board of the second capacitor array in the first-stage SAR ADC, and its output end is connected to the upper board of the second capacitor, the output end of the switch φ6, the input end of the switch φ8 and the input 2 end IN2 of the second decision circuit; the lower plate of the second capacitor and the input end of the switch φ6 are both connected to the voltage V CM ; The output end of the switch φ8 is connected to the input end of the second current source, and the output end of the second current source is connected to the ground; the input end of the switch φ12 is connected to the power supply, the output end of the switch φ12 is connected to the input end of the switch φ10, the upper board of the fourth DAC capacitor array and the input 2 end of the third judgment circuit, the output end of the switch φ10 is connected to the input end of the fourth current source, and the output end of the fourth current source is connected to the ground; the output end of the third judgment circuit is connected to the input 1 end of the first judgment circuit and the input 1 end of the second judgment circuit.
4. The high energy efficiency Pipelined-SAR hybrid ADC circuit based on the time residual voltage amplifier according to claim 1, characterized in that: The second-stage SAR ADC adopts a fully differential structure, including a third DAC module, a fourth DAC module, a second comparator, and a second SAR logic module, wherein the third DAC module includes a third capacitor array, and the fourth DAC module includes a fourth capacitor array; wherein the digital output port D of the second-stage SAR ADC circuit OUT It is also the output 2 port of the second SARLogic module; the non-inverting input end of the second comparator is connected to the upper board of the third DAC capacitor array, the inverting input end is connected to the upper board of the fourth DAC capacitor array, and the output end is connected to the input end of the second SARlogic module; the output OUT1 end of the second SAR logic module is connected to the third DAC module, and the output OUT2 end of the second SAR logic module is connected to the fourth DAC module.