A parallel amplification and quantization ADC based on pipeline structure

Abstract

The present invention belongs to the field of digital analog hybrid integrated circuits, and specifically relates to a parallel amplification quantization ADC based on a pipeline structure. The present invention adopts a closed-loop interstage amplifier as an interstage amplifier, and the corresponding secondary quantization sub-ADC of the interstage amplifier adopts a parallel amplification quantization sub-ADC to form the architecture of the entire pipeline ADC, and its secondary quantization timing uses the CTADC in the parallel amplification quantization sub-ADC to perform low-power and low-precision quantization tasks, while the high-precision quantization tasks are completed by the DTADC. In the present invention, the secondary quantization timing changes the discrete time quantization that is usually performed after the interstage amplifier is fully established, adds a part of the continuous time quantization, allows amplification and quantization to be performed in parallel, greatly improves the speed, and takes into account power consumption and precision; and the present invention can also cascade the interstage amplifier of the f stage and the secondary parallel amplification quantization sub-ADC to form an f+2 stage pipeline structure to achieve higher performance requirements.

Description

Technical Field

[0001] The invention belongs to the field of digital analog hybrid integrated circuits, and in particular relates to a parallel amplification and quantization ADC based on a pipeline structure. Background Art

[0002] The pipeline ADC is a commonly used ADC structure that can meet the requirements of high speed and high precision at the same time. This structure splits the multi-bit long-term high-precision quantization into a multi-stage pipeline form of low-precision short-time quantization, and uses inter-stage amplifiers to connect each stage, amplifying the quantization residual after low-precision short-time quantization step by step.

[0003] The current pipeline structure ADC has developed a variety of hybrid architectures, not only limited to the basic pipeline-FLASH ADC, but also pipeline-successive approximation ADC and other structures. Due to the high hardware overhead of FLASH ADC, the single-stage quantization bit number of traditional pipeline ADCs is relatively small, and the inter-stage amplification factor is not very large, which means that the quantization and amplification time are relatively short. However, in hybrid architecture ADCs, such as successive approximation ADCs, the hardware overhead and power consumption are very small, and the quantization bit number of each stage is no longer limited to 1.5 bits or 2 or 3 bits, and can be more bits and longer quantization. The inter-stage amplification factor is therefore increased, and the inter-stage amplification time will also increase.

[0004] In a pipeline ADC, the subsequent stage is in the sampling process during inter-stage amplification, which means that during the amplification process, the subsequent sub-ADC (secondary) cannot perform quantization operations. For a long amplification time, this part of the speed loss is very wasteful. Summary of the invention

[0005] In view of the above-mentioned problems or shortcomings, in order to solve the problem of speed loss caused by the inability of the secondary stage to perform quantization during the amplification process of the existing pipeline ADC, the present invention provides a parallel amplification and quantization ADC based on a pipeline structure, which optimizes the timing of quantization after inter-stage amplification, and parallel amplification and quantization timing, thereby shortening the total working time of the secondary ADC.

[0006] A parallel amplification quantization ADC based on a pipeline structure comprises a first-stage sub-ADC, an inter-stage amplifier and a secondary parallel amplification quantization sub-ADC which are cascaded in sequence.

[0007] The first-stage sub-ADC is an ADC with any structure.

[0008] The interstage amplifier uses a closed-loop interstage amplifier and satisfies that the amplification accuracy increases as the amplification time becomes longer, so that the sub-ADC of this stage can continuously perform quantization with continuously improved accuracy from low bits to high bits as the amplification accuracy increases.

[0009] The secondary parallel amplification quantization sub-ADC is a parallel amplification quantization sub-ADC, which consists of a continuous time quantization CTADC and a discrete time quantization DTADC, and its secondary quantization timing uses the CTADC to perform the quantization task during amplification and the DTADC to perform the quantization task after the amplification. Among them, continuous time quantization refers to the quantization of the continuously changing voltage during the second-level sampling; discrete time quantization refers to the quantization of the unchanged discrete voltage obtained after the second-level sampling is completed.

[0010] Furthermore, the secondary parallel amplification quantization sub-ADC is composed of CTADC and DTADC, each of which contains a capacitor array DAC. Compared with the two, the capacitor array DAC of CTADC has a smaller capacitance and lower precision, so it is faster and consumes less power. During the inter-stage amplifier amplification process, CTADC completes the low-bit quantization part of the secondary sub-ADC for the continuously changing input signal, and DTADC completes the remaining high-bit quantization task of the secondary sub-ADC for the discrete and stable input signal after the inter-stage amplifier finishes amplification; the first M bits of the entire secondary sub-ADC quantization process are low bits, a total of K bits, and the KMth bit is a high bit, where K>M≥1.

[0011] The sampling and quantization process of DTADC is based on a high-precision large capacitor array DAC that is not affected by CTADC quantization, while the quantization process of CTADC is based on a low-precision small capacitor array. Among them, due to the limitations of capacitor mismatch and kT / C noise on ADC accuracy, the unit capacitance of the two capacitor array DACs is constrained. The high-precision large capacitor array DAC needs to meet the secondary full K-bit quantization accuracy; the low-precision small capacitor array DAC only needs to meet the accuracy required by the first M bits of the K-bit quantization in the secondary parallel amplification quantization sub-ADC.

[0012] After the first-stage sub-ADC completes quantization, the inter-stage amplifier amplifies the quantization residual voltage of the first-stage sub-ADC to the secondary parallel amplification quantization sub-ADC, and the DTADC starts sampling; after the inter-stage amplifier has passed the CT precision establishment time, the CTADC starts CT quantization. After the inter-stage amplifier finishes amplification, the CTADC loads the quantization result onto the DTADC, and the DTADC starts DT quantization.

[0013] In order to ensure the requirements of high precision and low power consumption at the same time, if the secondary parallel amplification and quantization sub-ADC uses CTADC to perform all quantization tasks, the accuracy of the secondary parallel amplification and quantization sub-ADC will be deteriorated due to the mismatch between the two ADCs; at the same time, since CTADC is required to perform all quantization, CTADC needs to use a high-precision capacitor array DAC that meets all K-bit quantization of the secondary, and power consumption cannot be reduced; in addition, the inter-stage amplifier is always in an amplification state, which increases power consumption, so CTADC only performs low-bit quantization tasks, and the inter-stage amplifier can enter a reset state after amplifying to the accuracy required by the secondary sub-ADC so as not to increase power consumption; the secondary parallel quantization sub-ADC can perform DT quantization with higher accuracy after the inter-stage amplifier finishes amplification.

[0014] Furthermore, the combination form of the DTADC and the CTADC is an isolation capacitor connection.

[0015] Furthermore, the combination of the DTADC and the CTADC is a sampling switch that is turned off successively.

[0016] Furthermore, the combination of the DTADC and the CTADC is a sharing of a four-input comparator.

[0017] Furthermore, after the secondary parallel amplification and quantization sub-ADC, f-stage inter-stage amplifiers and secondary parallel amplification and quantization sub-ADCs are sequentially cascaded to form a parallel amplification and quantization ADC with an f+2-stage pipeline structure.

[0018] In summary, the present invention adopts a closed-loop interstage amplifier as the interstage amplifier, and the corresponding secondary quantization sub-ADC of the interstage amplifier adopts a parallel amplification quantization sub-ADC; and the parallel amplification quantization sub-ADC performs low-power, low-precision quantization tasks with CTADC, and the high-precision quantization tasks are completed by DTADC; thus forming the architecture of the entire pipeline ADC. In the present invention, the secondary quantization timing changes the discrete time quantization that is usually performed after the interstage amplifier is fully established, and adds a part of continuous time quantization, so that amplification and quantization are performed in parallel, which greatly improves the speed and takes into account power consumption and accuracy; and the present invention can also cascade f-level interstage amplifiers and secondary parallel amplification quantization sub-ADCs to form an f+2-level pipeline structure to achieve higher performance requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a structural block diagram of the present invention.

[0020] Figure 2 This is the traditional secondary quantization timing.

[0021] Figure 3 The invention provides a secondary quantization timing sequence of a secondary parallel amplification quantization sub-ADC.

[0022] Figure 4 This is the secondary parallel amplification and quantization sub-ADC structure of embodiment 1 of the present invention.

[0023] Figure 5 This is the secondary parallel amplification and quantization sub-ADC structure of embodiment 2 of the present invention.

[0024] Figure 6 This is the secondary parallel amplification and quantization sub-ADC structure of embodiment 3 of the present invention.

[0025] Figure numerals: first-stage sub-ADC-100, inter-stage amplifier-101, secondary parallel amplification and quantization sub-ADC-102, amplification time-200, quantization time-201, CT accuracy establishment time-300, CT quantization time-301, DT quantization time-302, CT-DT isolation capacitor-401, CTADC-402, DTADC-403, sampling switch-404, CT sampling switch-501, four-input comparator-601, CT quantized capacitor array DAC-602, DT quantized capacitor array DAC-603. DETAILED DESCRIPTION

[0026] The present invention is further described in detail below with reference to the accompanying drawings and embodiments.

[0027] The present invention provides a parallel amplification quantization ADC based on a pipeline structure, the overall structure block diagram is as follows: Figure 1 As shown: it includes a first-stage sub-ADC 100, an inter-stage amplifier 101 (RA) and a secondary parallel amplification and quantization sub-ADC 102 which are cascaded in sequence.

[0028] The secondary parallel amplification quantization sub-ADC 102 is composed of CTADC and DTADC. The secondary quantization timing is composed of three parts: CT precision establishment time, CT quantization time and DT quantization time. Figure 3 As shown, this is the relationship between input voltage and time.

[0029] During the CT accuracy establishment time of 300, the interstage amplifier completes the M-bit amplification accuracy required for continuous-time CT quantization; in fact, the CTADC does not need to wait for the amplifier to establish the M-bit accuracy before starting quantization, but only needs to ensure that the n-bit accuracy has been established when the n-bit quantization is currently being performed. After that, the interstage amplifier will continue to amplify during the CT quantization time, and the M-bit CT quantization will be performed synchronously. After the CT quantization is completed, the interstage amplifier completes the K-bit accuracy amplification; since the M-bit quantization has been completed at this time, the KM-bit discrete-time DT quantization can be directly performed according to the CT quantization result.

[0030] The traditional secondary quantization timing, such as Figure 2As shown, it consists of two parts: amplification time 200 and quantization time 201. The secondary ADC needs to wait until the interstage amplifier fully amplifies to the accuracy required by the second stage quantization before starting quantization. Example 1

[0031] A parallel amplification quantization ADC based on a pipeline structure, a specific combination of CTADC and DTADC is as follows Figure 4 As shown, it is an isolation capacitor connection, and only a single-ended structure is shown in the figure; it is composed of an inter-stage amplifier 101, a CT-DT isolation capacitor 401, an M-bit CTADC 402, a KM-bit DTADC 403, a DAC switching logic and a sampling switch 404. The output of the inter-stage amplifier 101 is connected to the input of the KM-bit DTADC 403 via the sampling switch 404, and is connected to the input of the M-bit CTADC 402 via the CT-DT isolation capacitor 401. Example 2

[0032] A parallel amplification quantization ADC based on a pipeline structure, a specific combination of CTADC and DTADC is as follows Figure 5 As shown, the sampling switches are turned off successively, and only the single-ended structure is shown in the figure; it is composed of an interstage amplifier 101, a CT sampling switch 501, an M-bit CTADC402, a KM-bit DTADC403, a DAC switching logic, and a sampling switch 404. The output of the interstage amplifier 101 is connected to the input of the KM-bit DTADC403 via the sampling switch 404, and is connected to the input of the M-bit CTADC402 via the CT sampling switch 501. The CT sampling switch 501 is turned off after the M-bit accuracy is fully established. Example 3

[0033] A parallel amplification quantization ADC based on a pipeline structure, a specific combination of CTADC and DTADC is as follows Figure 6 As shown, it is a sharing of a four-input comparator, and the structure only shows a single-ended structure; it is composed of an interstage amplifier 101, a DT-quantized capacitor array DAC 603, a DAC switching logic, a four-input comparator 601, a CT-quantized capacitor array DAC 602, and a sampling switch 404. The output of the interstage amplifier 101 is connected to the input of the DT-quantized capacitor array DAC 603 via the sampling switch 404. The DT-quantized capacitor array DAC 603, the four-input comparator 601, and the CT-quantized capacitor array DAC 602 together constitute a CTADC; the DT-quantized capacitor array DAC 603 and the four-input comparator 601 together constitute a DTADC.

[0034] The above three embodiments are based on the parallel amplification quantization ADC of the pipeline structure. In the working sequence, the interstage amplifier 101 starts amplification first, and after the CT precision amplification is completed, the M-bit CTADC starts the quantization operation, and the interstage amplifier 101 continues to amplify. After the interstage amplifier 101 completes the amplification within the CT quantization time 301, the quantization result of the M-bit CTADC is transferred to the KM-bit DTADC after code value loading, and the KM-bit DTADC continues to complete quantization within the DT quantization time 302.

[0035] For the traditional secondary quantization timing, the time required for the interstage amplifier to amplify K bits of accuracy is recorded as t amp , the time required to convert 1 bit of precision is t conv , then t is needed to quantize K bits amp +K*t conv The present invention is based on a parallel amplification quantization ADC with a pipeline structure and adopts a secondary quantization timing of parallel amplification quantization, which only requires t amp +(KM)*t conv .

[0036] It can be seen from the above embodiments that the present invention adopts a closed-loop interstage amplifier as an interstage amplifier, and the corresponding secondary quantization sub-ADC of the interstage amplifier adopts a parallel amplification quantization sub-ADC; the CTADC in the parallel amplification quantization sub-ADC is used to perform low-power, low-precision quantization tasks, while the high-precision quantization tasks are completed by the secondary quantization timing of DTADC. The secondary quantization timing in the present invention changes the usual discrete time quantization after the interstage amplifier is fully established, adds a part of continuous time quantization, allows amplification and quantization to be performed in parallel, shortens the total working time of the secondary ADC, greatly improves the speed, and takes into account power consumption and precision; and the present invention can also cascade f-level interstage amplifiers and secondary parallel amplification quantization sub-ADCs to form an f+2-level pipeline structure to achieve more and higher pipeline ADC performance and design possibilities.

Claims

1. A parallel amplification quantization ADC based on a pipeline structure, characterized in that: It includes a first-stage sub-ADC, an inter-stage amplifier and a secondary parallel amplification and quantization sub-ADC which are cascaded in sequence; The first-stage sub-ADC is an ADC of any structure; The inter-stage amplifier uses a closed-loop inter-stage amplifier, and the amplification accuracy becomes higher as the amplification time becomes longer; The secondary parallel amplification quantization sub-ADC is composed of a continuous time quantization CTADC and a discrete time quantization DTADC, and its secondary quantization timing adopts CTADC to perform the quantization task during amplification and DTADC to perform the quantization task after amplification; wherein continuous time quantization refers to the quantization of the continuously changing voltage during the second-level sampling; discrete time quantization refers to the quantization of the unchanged discrete voltage obtained after the second-level sampling is completed; Specifically, the CTADC and DTADC of the secondary parallel amplification quantization sub-ADC each include a capacitor array DAC. Compared with the two, the capacitor array DAC of the CTADC has a smaller capacitance and lower precision; the CTADC completes the low-bit quantization task of the secondary sub-ADC for the continuously changing input signal during the amplification process of the inter-stage amplifier, and the DTADC completes the remaining high-bit quantization task of the secondary sub-ADC for the discrete and stable input signal after the inter-stage amplifier finishes amplification; the first M bits of the entire secondary sub-ADC quantization process are low bits, a total of K bits, and the KMth bit is a high bit, K>M≥1; After the first-stage sub-ADC completes quantization, the inter-stage amplifier amplifies the quantization residual voltage of the first-stage sub-ADC to the secondary parallel amplification quantization sub-ADC, and the DTADC starts sampling; after the inter-stage amplifier has passed the CT accuracy establishment time, the CTADC starts CT quantization; after the inter-stage amplifier finishes amplification, the CTADC loads the quantization result onto the DTADC, and the DTADC starts DT quantization.

2. The parallel amplification quantization ADC based on pipeline structure as claimed in claim 1, characterized in that: The secondary quantization timing is composed of three parts: CT accuracy establishment time, CT quantization time and DT quantization time; During the CT accuracy establishment time, the interstage amplifier completes the M-bit amplification accuracy required for continuous-time CT quantization; after that, the interstage amplifier continues to amplify within the CT quantization time, and synchronously, the M-bit CT quantization is carried out together; after the CT quantization is completed, the interstage amplifier completes the K-bit accuracy amplification, and then directly performs KM-bit discrete-time DT quantization according to the CT quantization result.

3. The parallel amplification and quantization ADC based on pipeline structure as claimed in claim 1, characterized in that: The combination form of the DTADC and the CTADC is an isolation capacitor connection.

4. The parallel amplification and quantization ADC based on pipeline structure as claimed in claim 1, characterized in that: The combination of the DTADC and the CTADC is a sampling switch that is turned off successively.

5. The parallel amplification quantization ADC based on pipeline structure as claimed in claim 1, characterized in that: The combination of the DTADC and the CTADC is a shared four-input comparator.

6. The parallel amplification quantization ADC based on pipeline structure as claimed in claim 1, characterized in that: After the secondary parallel amplifying and quantizing sub-ADC, f-stage inter-stage amplifiers and secondary parallel amplifying and quantizing sub-ADCs are sequentially cascaded, where f≥1, to form a parallel amplifying and quantizing ADC with an f+2-stage pipeline structure.

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