Memory and preparation method thereof

Abstract

The invention discloses a memory and a preparation method of the memory, and belongs to the technical field of semiconductors. The memory includes: a write transistor including a first channel layer; the read transistor comprises a second channel layer, and the read transistor and the write transistor are connected to a storage node; wherein the mobility of the second channel layer is greater than that of the first channel layer, and the threshold voltage of the first channel layer is greater than that of the second channel layer. The stability of the memory can be improved, and the overall performance of the memory is optimized.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor technology, and in particular, relates to a memory and a method for preparing the memory. Background Art

[0002] The storage unit in the dynamic volatile memory can be a capacitor-free memory (such as a 2T0C memory). The performance of the memory is determined by the performance of the write transistor and the read transistor. However, the performance requirements of the write transistor and the read transistor are different. The write transistor and the read transistor in the related art use the same material, composition and thickness of the channel layer to comprehensively balance and optimize the overall performance of the memory, but it is impossible to take into account the performance requirements of the write transistor and the read transistor at the same time, which affects the stability of the memory under long-term operation. Summary of the invention

[0003] The present application aims to solve at least one of the technical problems existing in the prior art. To this end, the present application proposes a memory and a method for preparing the memory, which can improve the stability of the memory and optimize the overall performance of the memory.

[0004] In a first aspect, the present application provides a memory, including:

[0005] a write transistor including a first channel layer;

[0006] a read transistor, the read transistor and the write transistor being connected to a storage node, the read transistor comprising a second channel layer;

[0007] The mobility of the second channel layer is greater than the mobility of the first channel layer, and the threshold voltage of the first channel layer is greater than the threshold voltage of the second channel layer.

[0008] According to the memory of the present application, by directionally regulating the first channel layer in the write transistor and the second channel layer in the read transistor, the threshold voltage of the first channel layer is made greater than the threshold voltage of the second channel layer, the leakage current of the write transistor is reduced, and the stability of the write transistor under negative voltage stress is improved. The mobility of the second channel layer is made greater than the mobility of the first channel layer, the on-state current of the read transistor is increased, and the stability of the read transistor under positive voltage stress is improved, thereby optimizing the overall performance of the memory.

[0009] According to one embodiment of the present application, a doping ratio of conductive ions in the second channel layer is greater than a doping ratio of conductive ions in the first channel layer.

[0010] According to an embodiment of the present application, the first channel layer and the second channel layer respectively include any one of IGZO, ITO and IWO;

[0011] The conductive ions in the IGZO, the ITO, and the IWO all include In ions.

[0012] According to one embodiment of the present application, the first channel layer and the second channel layer respectively include IGZO;

[0013] The doping ratio of In ions in the first channel layer is 25%-35%, and the doping ratio of In ions in the second channel layer is 45%-55%.

[0014] According to an embodiment of the present application, a doping ratio of the conductive inhibition ions in the second channel layer is smaller than a doping ratio of the conductive inhibition ions in the first channel layer.

[0015] According to an embodiment of the present application, the first channel layer and the second channel layer respectively include any one of IGZO, ITO and IWO;

[0016] The conductive inhibitory ions in the IGZO include Ga ions, the conductive inhibitory ions in the ITO include Sn ions, and the conductive inhibitory ions in the IWO include W ions.

[0017] According to one embodiment of the present application, the first channel layer and the second channel layer respectively include IGZO;

[0018] The doping ratio of Ga ions in the first channel layer is 45%-55%, and the doping ratio of Ga ions in the second channel layer is 20%-30%.

[0019] According to one embodiment of the present application, the thickness of the first channel layer is greater than the thickness of the second channel layer.

[0020] According to one embodiment of the present application, the first channel layer and the second channel layer respectively include IGZO;

[0021] The thickness of the first channel layer is 15-20 nm, and the thickness of the second channel layer is 8-12 nm.

[0022] In a second aspect, the present application provides a method for preparing a memory, comprising:

[0023] providing a substrate;

[0024] forming a first gate and a second gate on the substrate;

[0025] forming a gate oxide layer covering the first gate and the second gate;

[0026] forming a second channel layer on the gate oxide layer, wherein the second channel layer corresponds to a position of the second gate;

[0027] forming a second source and a second drain on the second channel layer to obtain a read transistor;

[0028] covering the second channel layer with a second passivation layer;

[0029] forming a first channel layer on the gate oxide layer, wherein the first channel layer corresponds to a position of the first gate;

[0030] forming a first source electrode and a first drain electrode on the first channel layer to obtain a write transistor, wherein the first source electrode is connected to the second gate electrode;

[0031] covering the first channel layer with a first passivation layer;

[0032] The mobility of the second channel layer is greater than the mobility of the first channel layer, and the threshold voltage of the first channel layer is greater than the threshold voltage of the second channel layer.

[0033] The above one or more technical solutions in the embodiments of the present application have at least one of the following technical effects:

[0034] By directionally regulating the first channel layer in the write transistor and the second channel layer in the read transistor, the threshold voltage of the first channel layer is made greater than the threshold voltage of the second channel layer, the leakage current of the write transistor is reduced, and the stability of the write transistor under negative voltage stress is improved. The mobility of the second channel layer is made greater than the mobility of the first channel layer, the on-state current of the read transistor is increased, and the stability of the read transistor under positive voltage stress is improved, thereby optimizing the overall performance of the memory.

[0035] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0037] Figure 1 is a circuit diagram of a memory provided in an embodiment of the present application;

[0038] Figure 2 is a schematic diagram of the structure of a memory provided in an embodiment of the present application;

[0039] Figure 3 is a cross-sectional schematic diagram of a write transistor and a read transistor in a memory provided by an embodiment of the present application;

[0040] Figure 4It is a schematic diagram of the process of preparing the memory provided in the embodiment of the present application. DETAILED DESCRIPTION

[0041] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0042] The memory and the method for manufacturing the memory provided in the embodiments of the present application are described below with reference to the accompanying drawings.

[0043] Figure 1 A circuit diagram of a memory provided in an embodiment of the present application. The memory may be a capacitor-free memory (such as a 2T0C memory). The memory may be applied to a memory, which may be a dynamic volatile memory.

[0044] like Figure 1 As shown, the memory provided by the embodiment of the present application includes a write transistor 1 and a read transistor 2. The read transistor 2 and the write transistor 1 are connected to a storage node SN, that is, the read transistor 2 and the write transistor 1 are connected, and the connection point is the storage node SN. The storage node SN is used to store data (logic 1 or logic 0).

[0045] The write transistor 1 has a first source S1, a first drain D1, and a first gate G1. The first source S1 of the write transistor 1 may be connected to the storage node SN, the first drain D1 of the write transistor 1 may be connected to the write bit line WBL, and the first gate G1 of the write transistor 1 may be connected to the write word line WWL.

[0046] The read transistor 2 has a second source S2, a second drain D2, and a second gate G2. The second gate G2 of the read transistor 2 can be connected to the storage node SN, the second drain D2 of the read transistor 2 can be connected to the read word line RWL, and the second source S2 of the read transistor 2 can be connected to the read bit line RBL.

[0047] Among them, the write bit line WBL, the write word line WWL, the read bit line RBL and the read word line RWL are all operation lines. The read bit line RBL guarantees the ground potential.

[0048] When writing data to the memory, the first gate G1 of the write transistor 1 is turned on, and a voltage (high level or low level) is applied to the first drain D1 of the write transistor 1. At this time, the data is stored in the form of charge at the storage node SN, that is, in the gate parasitic capacitance of the read transistor 2. When reading data, a voltage is applied to the second drain D2 of the read transistor 2, and the drain current I of the read transistor 2 is measured. RWLThe size of is used to determine whether charge is stored at the storage node SN.

[0049] Combination Figure 2 As shown, the write transistor 1 includes a first channel layer 11 and the read transistor 2 includes a second channel layer 21 . The mobility of the second channel layer 21 is greater than that of the first channel layer 11 , and the threshold voltage of the first channel layer 11 is greater than that of the second channel layer 21 .

[0050] It should be noted that the performance of the memory is determined by the performance of the write transistor 1 and the read transistor 2, including retention time, operating voltage, data switching ratio, reliability, etc. In order to optimize the performance of the memory, the electrical characteristics of the write transistor 1 and the read transistor 2 can be adjusted by adjusting the performance of the first channel layer 11 and the second channel layer 21.

[0051] The performance requirements of the write transistor 1 and the read transistor 2 are different. For the write transistor 1, the threshold voltage of the first channel layer 11 is increased, thereby increasing the threshold voltage of the write transistor 1, so that when the gate voltage of the write transistor 1 is 0 (i.e., WWL=0V), the write transistor 1 has a lower leakage current, and the on-state current of the write transistor 1 is not a major concern. For the read transistor 2, the mobility of the second channel layer 21 is increased, thereby increasing the on-state current and switching ratio of the read transistor 2, so that the 1 / 0 state can be accurately distinguished when reading the state, and the threshold voltage of the read transistor 2 is not a major concern.

[0052] In addition, for stability, the write transistor 1 is more concerned with stability under negative voltage stress (Negative Bias Sress, NBS). By increasing the thickness of the first channel layer 11 in the write transistor 1, the stability of the write transistor 1 under NBS can be improved. The read transistor 2 is more concerned with stability under positive voltage stress (Positive Bias Stress, PBS). By increasing the doping concentration of the conductive ions in the second channel layer 12 in the read transistor 2, the mobility of the read transistor 2 is increased, the on-state current of the read transistor 2 is increased, and the stability of the read transistor 2 under PBS is improved.

[0053] This embodiment is compatible with the performance requirements of the write transistor 1 and the read transistor 2 at the same time, and performs directionally regulated control on the first channel layer 11 in the write transistor 1 and the second channel layer 21 in the read transistor 2, thereby increasing the threshold voltage of the write transistor 1, reducing the leakage current of the write transistor, and improving the stability of the write transistor 1 under NBS, and increasing the mobility of the read transistor 2, increasing the on-state current of the read transistor, and improving the stability of the read transistor 2 under PBS, thereby optimizing the overall performance of the memory.

[0054] In some embodiments, the first channel layer 11 and the second channel layer 21 include any one of IGZO (Indium Gallium Zinc Oxide), ITO (Indium Tin Oxide) and IWO (Indium Tungsten Oxide). The materials of the first channel layer 11 and the second channel layer 21 can be the same or different.

[0055] Transistors made with IGZO as the channel material have a lower off-state leakage current (e.g., off-state leakage current I off <10 -19 ), lower process temperature (such as process temperature less than 300°C), higher mobility (such as mobility greater than 10cm 2 / V·s), and good uniformity. The transistor made of ITO as the channel material has good electrical conductivity, high light transmittance, and high thermal conductivity. The transistor made of IWO as the channel material has high mobility and good stability.

[0056] By adjusting the material, composition and / or thickness of the first channel layer 11 and the second channel layer 21, the performance of the first channel layer 11 and the second channel layer 21 can be adjusted so that the mobility of the second channel layer 21 is greater than the mobility of the first channel layer 11, and the threshold voltage of the first channel layer 11 is greater than the threshold voltage of the second channel layer 21.

[0057] In some embodiments, the doping ratio of the conductive ions in the second channel layer 21 is greater than the doping ratio of the conductive ions in the first channel layer 11. The conductive ions refer to ions that can increase the conductivity of the channel layer.

[0058] By adjusting the doping concentration or doping ratio of the conductive ions in the channel layer, the mobility and threshold voltage of the channel layer can be adjusted to optimize the performance of the transistor. The threshold voltage formula of the transistor is: Among them, V th is the threshold voltage, N ch is approximately the doping concentration of conductive ions (such as In ions) in the channel layer, t ch is the thickness of the channel layer, is the gate metal work function, χ s is the electron affinity of the channel material, C G is the gate capacitance, and q is the charge of the electron. From this formula, we can see that by adjusting the doping concentration N of the conductive ions in the channel layer ch , the threshold voltage of the transistor can be adjusted. The stability of the read transistor 2 under PBS can be improved by increasing the doping concentration N of the conductive ions in the channel layer. ch to achieve.

[0059] Increasing the doping concentration or doping ratio of the conductive ions in the second channel layer 21 can increase the mobility of the second channel layer 21 and reduce the threshold voltage of the second channel layer 21, thereby improving the stability of the read transistor 2 under PBS. Reducing the doping concentration or doping ratio of the conductive ions in the first channel layer 11 can reduce the mobility of the first channel layer 11 and increase the threshold voltage of the first channel layer 11, thereby improving the stability of the write transistor 1 under NBS.

[0060] In some embodiments, the conductive ions in IGZO, ITO, and IWO all include In ions. When the first channel layer 11 includes IGZO, ITO, or IWO, and the second channel layer 21 includes IGZO, ITO, or IWO, the doping ratio of In ions in the first channel layer 11 can be reduced, and the doping ratio of In ions in the second channel layer 21 can be increased, so that the doping ratio of In ions in the second channel layer 21 is greater than the doping ratio of In ions in the first channel layer 11.

[0061] In some embodiments, the first channel layer 11 and the second channel layer 21 include IGZO, respectively. The doping ratio of In ions in the first channel layer 11 is 25%-35%, and the doping ratio of In ions in the second channel layer 21 is 45%-55%.

[0062] In some embodiments, the doping ratio of the conductive inhibitory ions in the second channel layer 21 is less than the doping ratio of the conductive inhibitory ions in the first channel layer 11. The conductive inhibitory ions refer to ions that can suppress the electron concentration in the channel layer.

[0063] By adjusting the doping concentration or doping ratio of the conductive inhibitory ions in the channel layer, the mobility and threshold voltage of the channel layer can be adjusted. Reducing the doping concentration or doping ratio of the conductive inhibitory ions in the second channel layer 21 can increase the mobility of the second channel layer 21 and reduce the threshold voltage of the second channel layer 21, thereby improving the stability of the read transistor 2 under PBS. Increasing the doping concentration or doping ratio of the conductive inhibitory ions in the first channel layer 11 can reduce the mobility of the first channel layer 11 and increase the threshold voltage of the first channel layer 11, thereby improving the stability of the write transistor 1 under NBS.

[0064] In some embodiments, the conductive inhibitory ions in IGZO include Ga ions, the conductive inhibitory ions in ITO include Sn ions, and the conductive inhibitory ions in IWO include W ions. When the first channel layer 11 includes IGZO, ITO or IWO, and the second channel layer 21 includes IGZO, ITO or IWO, the doping ratio of Ga ions, Sn ions or W ions in the first channel layer 11 can be increased, and the doping ratio of Ga ions, Sn ions or W ions in the second channel layer 21 can be reduced, so that the doping ratio of the conductive inhibitory ions in the second channel layer 21 is less than the doping ratio of the conductive inhibitory ions in the first channel layer 11.

[0065] In some embodiments, the first channel layer 11 and the second channel layer 21 include IGZO, respectively. The doping ratio of Ga ions in the first channel layer 11 is 45%-55%, and the doping ratio of Ga ions in the second channel layer 21 is 20%-30%.

[0066] It should be noted that the doping concentration / doping ratio of the conductive ions and the conductive inhibitory ions in the channel layer can also be adjusted at the same time to adjust the mobility and threshold voltage of the channel layer. For example, the doping concentration / doping ratio of the conductive ions (such as In ions) in the second channel layer 21 is increased, and the doping concentration / doping ratio of the conductive inhibitory ions (such as Ga ions, Sn ions or W ions) in the second channel layer 21 is reduced to increase the mobility of the second channel layer 21 and reduce the threshold voltage of the second channel layer 21, thereby improving the stability of the read transistor 2 under PBS. The doping concentration / doping ratio of the conductive ions (such as In ions) in the first channel layer 11 is reduced, and the doping concentration / doping ratio of the conductive inhibitory ions (such as Ga ions, Sn ions or W ions) in the first channel layer 11 is increased to reduce the mobility of the first channel layer 11 and increase the threshold voltage of the first channel layer 11, thereby improving the stability of the write transistor 1 under NBS.

[0067] In some embodiments, the thickness of the first channel layer 11 is greater than the thickness of the second channel layer 21. By adjusting the thickness of the channel layer, the turn-on current and threshold voltage of the channel layer can be adjusted to optimize the performance of the transistor. It can be seen from the threshold voltage formula of the transistor that by adjusting the thickness of the channel layer t ch , the threshold voltage of the transistor can be adjusted. The stability of the write transistor 1 under NBS can be improved by increasing the thickness t of the first channel layer 11. ch to achieve.

[0068] In some embodiments, the first channel layer 11 and the second channel layer 21 include IGZO, respectively. The thickness of the first channel layer 11 is 15-20 nm, and the thickness of the second channel layer 21 is 8-12 nm. For example, the thickness of the first channel layer 11 is 16 nm, and the thickness of the second channel layer 21 is 10 nm.

[0069] In some embodiments, the first channel layer 11 and the second channel layer 21 include ITO, respectively. The thickness of the first channel layer 11 is 4 nm, and the thickness of the second channel layer 21 is 2 nm.

[0070] It should be noted that the thickness of the channel layer and the doping concentration / doping ratio of the conductive ions / conductive inhibitory ions in the channel layer can also be adjusted at the same time to adjust the mobility and threshold voltage of the channel layer. For example, the thickness of the second channel layer 21 is reduced, and the doping concentration / doping ratio of the conductive ions (such as In ions) in the second channel layer 21 is increased, and the doping concentration / doping ratio of the conductive inhibitory ions (such as Ga ions, Sn ions or W ions) in the second channel layer 21 is reduced to increase the mobility of the second channel layer 21 and reduce the threshold voltage of the second channel layer 21, thereby improving the stability of the read transistor 2 under PBS. The thickness of the first channel layer 11 is increased, and the doping concentration / doping ratio of the conductive ions (such as In ions) in the first channel layer 11 is reduced, and the doping concentration / doping ratio of the conductive inhibitory ions (such as Ga ions, Sn ions or W ions) in the first channel layer 11 is increased to reduce the mobility of the first channel layer 11 and increase the threshold voltage of the first channel layer 11, thereby improving the stability of the write transistor 1 under NBS.

[0071] In some embodiments, the memory may further include a substrate 3, a gate oxide layer 4, a first passivation layer 5, and a second passivation layer 6. The first gate G1 of the write transistor 1 and the second gate G2 of the read transistor 2 are spaced apart and located on the substrate 3. The gate oxide layer 4 covers the first gate G1 of the write transistor 1 and the second gate G2 of the read transistor 2. The first channel layer 11 and the second channel layer 21 are located on the gate oxide layer 4, and the position of the first channel layer 11 corresponds to the position of the first gate G1, and the position of the second channel layer 21 corresponds to the position of the second gate G2. The first source S1 and the first drain D1 of the write transistor 1 are located on the first channel layer 11, and the second source S2 and the second drain D2 of the read transistor 2 are located on the second channel layer 21. The first passivation layer 5 covers the first channel layer 11, and the second passivation layer 6 covers the second channel layer 21. Among them, the substrate 3 may include silicon and silicon oxide, etc. The first gate G1 and the second gate G2 may include 1nm of titanium (Ti) and 20nm of palladium (Pd), etc. The gate oxide layer 4 may include hafnium dioxide (HfO2). The first source S1 and the first drain D1 may include 1 nm of Ti and 45 nm of Pd, respectively. The second source S2 and the second drain D2 may include 1 nm of Ti and 45 nm of Pd, respectively. The first passivation layer 5 and the second passivation layer 6 may include Y2O3, respectively.

[0072] It should be noted that the structures of the write transistor 1 and the read transistor 2 may be the same, but the materials, components and / or thicknesses of the first channel layer 11 in the write transistor 1 and the second channel layer 21 in the read transistor 2 are different.

[0073] In summary, according to the memory provided by the embodiment of the present application, the threshold voltage of the first channel layer 11 in the write transistor 1 and the second channel layer 21 in the read transistor 2 are directionally regulated so that the threshold voltage of the first channel layer 11 is greater than the threshold voltage of the second channel layer 21, thereby reducing the leakage current of the write transistor 1, improving the stability of the write transistor 1 under negative voltage stress, and making the mobility of the second channel layer 21 greater than the mobility of the first channel layer 11, thereby improving the on-state current of the read transistor 2 and improving the stability of the read transistor 2 under positive voltage stress, thereby optimizing the overall performance of the memory.

[0074] Correspondingly, an embodiment of the present application also provides a method for preparing a memory, which can prepare the memory in the above embodiment.

[0075] like Figure 4 As shown, the method for preparing a memory provided in an embodiment of the present application includes steps 110 to 170.

[0076] Step 110: Provide a substrate.

[0077] Combination Figure 3 , first provide a substrate 3. The substrate 3 may include silicon, silicon oxide, etc.

[0078] Step 120: forming a first gate and a second gate on a substrate.

[0079] Combination Figure 2 As shown, a thin film deposition process (such as an electron beam evaporation process) is used to form a first gate G1 and a second gate G2 on a substrate 3. The first gate G1 and the second gate G2 are arranged at intervals. The first gate G1 and the second gate G2 may include 1 nm of titanium (Ti) and 20 nm of palladium (Pd), respectively.

[0080] Step 130 : forming a gate oxide layer covering the first gate and the second gate.

[0081] Combination Figure 2 As shown, a thin film deposition process (such as an atomic layer deposition process) is used to form a gate oxide layer 4 covering the first gate G1 and the second gate G2, and the gate oxide layer 4 also covers the substrate 3 not covered by the first gate G1 and the second gate G2. The gate oxide layer 4 may include hafnium dioxide (HfO2). The thickness of the gate oxide layer 4 may be 10 nm.

[0082] Step 140: forming a second channel layer on the gate oxide layer, wherein the second channel layer corresponds to a position of the second gate.

[0083] Combination Figure 2 As shown, a thin film deposition process (such as an atomic layer deposition process) is used to form a second channel layer 21 on the gate oxide layer 4, and the second channel layer 21 corresponds to the position of the second gate G2. According to the performance requirements of the read transistor, the components and cycles of the atomic layer deposition process are adjusted to adjust the performance of the second channel layer 21. Among them, the second channel layer 21 can include any one of IGZO (indium gallium zinc oxide), ITO (indium tin oxide) and IWO (indium tungsten oxide).

[0084] Step 150 : forming a second source and a second drain on the second channel layer to obtain a read transistor.

[0085] Combination Figure 2 As shown, a thin film deposition process (such as an electron beam evaporation process) is used to form a second source S2 and a second drain D2 on the second channel layer 21. The second source S2 and the second drain D2 include 1nm Ti and 45nm Pd, respectively. The second gate G2, the second channel layer 21, the second source S2 and the second drain D2 constitute the read transistor 2.

[0086] Step 160 : Covering the second channel layer with a second passivation layer.

[0087] Combination Figure 2 As shown, a second passivation layer 6 is deposited on the second channel layer 21 as a passivation protection layer of the second channel layer 21 to prevent the second channel layer 21 from being affected when the first channel layer 11 is subsequently formed. For example, PVD75E-beam (growth rate of 0.5A / s) is used, and oxidation is performed at 250°C for 30 minutes to obtain a 7nm second passivation layer 6. The second passivation layer 6 may include Y2O3.

[0088] Step 170: forming a first channel layer on the gate oxide layer, wherein the first channel layer corresponds to a position of the first gate.

[0089] Combination Figure 2 As shown, a thin film deposition process (such as an atomic layer deposition process) is used to form a first channel layer 11 on the gate oxide layer 4, and the first channel layer 11 corresponds to the position of the first gate G1. According to the performance requirements of the write transistor, the components and cycles of the atomic layer deposition process are adjusted to adjust the performance of the first channel layer 11. Among them, the first channel layer 11 may include any one of IGZO, ITO and IWO. The materials of the first channel layer 11 and the second channel layer 21 may be the same or different.

[0090] Step 180, forming a first source and a first drain on the first channel layer to obtain a write transistor, wherein the first source is connected to the second gate; wherein the mobility of the second channel layer is greater than the mobility of the first channel layer, and the threshold voltage of the first channel layer is greater than the threshold voltage of the second channel layer.

[0091] Combination Figure 2 As shown, a thin film deposition process (such as an electron beam evaporation process) is used to form a first source S1 and a first drain D1 on the first channel layer 11, and the first source S1 is connected to the second gate G2. The first source S1 and the first drain D1 include 1nm of Ti and 45nm of Pd, respectively. The first gate G1, the first channel layer 11, the first source S1, and the first drain D1 constitute a write transistor 1.

[0092] Step 190 : Covering the first channel layer with a first passivation layer.

[0093] Combination Figure 2 As shown, a first passivation layer 5 is deposited on the first channel layer 11 as a passivation protection layer of the first channel layer 11. For example, PVD75 E-beam (growth rate of 0.5 A / s) is used, and oxidation is performed at 250° C. for 30 minutes to obtain a 7 nm second passivation layer 6. The first passivation layer 5 may include Y2O3.

[0094] By directionally regulating the first channel layer 11 in the write transistor 1 and the second channel layer 21 in the read transistor 2, the threshold voltage of the write transistor 1 is increased, the leakage current of the write transistor is reduced, the stability of the write transistor 1 under NBS is improved, and the mobility of the read transistor 2 is increased, the on-state current of the read transistor is increased, and the stability of the read transistor 2 under PBS is improved, thereby optimizing the overall performance of the memory.

[0095] In some embodiments, the first channel layer 11 includes IGZO. The first channel layer 11 may include 50 periodic structures, each of which includes two indium oxide layers, four gallium oxide layers, and one zinc oxide layer arranged in sequence. The second channel layer 21 includes IGZO. The second channel layer 21 may include 50 periodic structures, each of which includes two indium oxide layers, two gallium oxide layers, and one zinc oxide layer arranged in sequence.

[0096] By controlling the gas flow rate, gas pressure, time and number of deposition cycles of each element deposited in the first channel layer 11 and the second channel layer 21 during the ALD deposition process, the element doping concentration and film thickness in the first channel layer 11 and the second channel layer 21 can be controlled, thereby adjusting the performance of the first channel layer 11 and the second channel layer 21.

[0097] In some embodiments, the doping ratio of the conductive ions in the second channel layer 21 is greater than the doping ratio of the conductive ions in the first channel layer 11 .

[0098] In some embodiments, the first channel layer 11 and the second channel layer 21 include any one of IGZO, ITO and IWO, respectively. The conductive ions in IGZO, ITO and IWO all include In ions.

[0099] In some embodiments, the first channel layer 11 and the second channel layer 21 include IGZO, respectively. The doping ratio of In ions in the first channel layer 11 is 25%-35%, and the doping ratio of In ions in the second channel layer 21 is 45%-55%.

[0100] In some embodiments, the doping ratio of the conductive inhibiting ions in the second channel layer 21 is less than the doping ratio of the conductive inhibiting ions in the first channel layer 11 .

[0101] In some embodiments, the first channel layer 11 and the second channel layer 21 include any one of IGZO, ITO and IWO, respectively. The conductive inhibitory ions in IGZO include Ga ions, the conductive inhibitory ions in ITO include Sn ions, and the conductive inhibitory ions in IWO include W ions.

[0102] In some embodiments, the first channel layer 11 and the second channel layer 21 include IGZO, respectively. The doping ratio of Ga ions in the first channel layer 11 is 45%-55%, and the doping ratio of Ga ions in the second channel layer 21 is 20%-30%.

[0103] In some embodiments, the thickness of the first channel layer 11 is greater than the thickness of the second channel layer 21 .

[0104] In some embodiments, the first channel layer 11 and the second channel layer 21 include IGZO, respectively. The thickness of the first channel layer 11 is 15-20 nm, and the thickness of the second channel layer 21 is 8-12 nm.

[0105] According to the preparation method of the memory provided in the embodiment of the present application, by directionally controlling the first channel layer in the write transistor and the second channel layer in the read transistor, the threshold voltage of the first channel layer is made greater than the threshold voltage of the second channel layer, thereby reducing the leakage current of the write transistor, improving the stability of the write transistor under negative voltage stress, and making the mobility of the second channel layer greater than the mobility of the first channel layer, thereby increasing the on-state current of the read transistor and improving the stability of the read transistor under positive voltage stress, thereby optimizing the overall performance of the memory.

[0106] The terms "first", "second", etc. in the specification and claims of this application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of the same type, and the number of objects is not limited. For example, the first object can be one or more.

[0107] In the description of the present application, “plurality” means two or more.

[0108] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0109] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present application, and that the scope of the present application is defined by the claims and their equivalents.

Claims

1. A memory, characterized in that: include: a write transistor including a first channel layer; a read transistor including a second channel layer, the read transistor and the write transistor being connected to a storage node; The mobility of the second channel layer is greater than the mobility of the first channel layer, and the threshold voltage of the first channel layer is greater than the threshold voltage of the second channel layer.

2. The memory according to claim 1, characterized in that: The doping ratio of the conductive ions in the second channel layer is greater than the doping ratio of the conductive ions in the first channel layer.

3. The memory according to claim 2, characterized in that: The first channel layer and the second channel layer respectively include any one of IGZO, ITO and IWO; The conductive ions in the IGZO, the ITO, and the IWO all include In ions.

4. The memory according to claim 3, characterized in that: The first channel layer and the second channel layer include IGZO respectively; The doping ratio of In ions in the first channel layer is 25%-35%, and the doping ratio of In ions in the second channel layer is 45%-55%.

5. The memory according to claim 1, characterized in that: A doping ratio of the conductive inhibiting ions in the second channel layer is smaller than a doping ratio of the conductive inhibiting ions in the first channel layer.

6. The memory according to claim 5, characterized in that: The first channel layer and the second channel layer respectively include any one of IGZO, ITO and IWO; The conductive inhibitory ions in the IGZO include Ga ions, the conductive inhibitory ions in the ITO include Sn ions, and the conductive inhibitory ions in the IWO include W ions.

7. The memory according to claim 6, characterized in that: The first channel layer and the second channel layer include IGZO respectively; The doping ratio of Ga ions in the first channel layer is 45%-55%, and the doping ratio of Ga ions in the second channel layer is 20%-30%.

8. The memory according to any one of claims 1 to 7, characterized in that: The thickness of the first channel layer is greater than the thickness of the second channel layer.

9. The memory according to claim 8, characterized in that: The first channel layer and the second channel layer include IGZO respectively; The thickness of the first channel layer is 15-20 nm, and the thickness of the second channel layer is 8-12 nm.

10. A method for preparing a memory, characterized in that: include: providing a substrate; forming a first gate and a second gate on the substrate; forming a gate oxide layer covering the first gate and the second gate; forming a second channel layer on the gate oxide layer, wherein the second channel layer corresponds to a position of the second gate; forming a second source and a second drain on the second channel layer to obtain a read transistor; covering the second channel layer with a second passivation layer; forming a first channel layer on the gate oxide layer, wherein the first channel layer corresponds to a position of the first gate; forming a first source electrode and a first drain electrode on the first channel layer to obtain a write transistor, wherein the first source electrode is connected to the second gate electrode; covering the first channel layer with a first passivation layer; The mobility of the second channel layer is greater than the mobility of the first channel layer, and the threshold voltage of the first channel layer is greater than the threshold voltage of the second channel layer.

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