Three-dimensional memory, memory system and manufacturing method of three-dimensional memory

Abstract

The embodiment of the invention provides a three-dimensional memory, a memory system and a manufacturing method of the three-dimensional memory. The three-dimensional memory comprises a first peripheral circuit chip; the storage array chip is bonded with the first peripheral circuit chip; the second peripheral circuit chip is bonded with the storage array chip on one side, far away from the first peripheral circuit chip, of the storage array chip; the memory array chip comprises a stacking structure, a first electrode and a second electrode, the channel structure penetrates through the stacking structure, and the first end, close to the first peripheral circuit chip, of the channel structure is connected with the first peripheral circuit chip; and the word line contact structure at least partially penetrates through the stacking structure, and the second end, close to the second peripheral circuit chip, of the word line contact structure is connected with the second peripheral circuit chip.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and more specifically, to a three-dimensional memory, a memory system, and a method for manufacturing the three-dimensional memory. Background Art

[0002] As the demand for the operating speed and capacity of three-dimensional memory (e.g., 3D NAND memory) continues to increase, multi-chip integration has gradually become one of the mainstream directions of three-dimensional memory research and development. However, due to the internal structure of three-dimensional memory, the feasibility and flexibility of multi-chip integration are greatly limited. Summary of the invention

[0003] The present application provides a three-dimensional memory, a memory system, and a method for manufacturing a three-dimensional memory that can at least partially solve the above-mentioned problems existing in the related art or other problems in the art.

[0004] Some embodiments of the present application provide a three-dimensional memory. The three-dimensional memory includes: a first peripheral circuit chip; a memory array chip bonded to the first peripheral circuit chip; a second peripheral circuit chip bonded to the memory array chip on a side of the memory array chip away from the first peripheral circuit chip; wherein the memory array chip includes: a stacking structure; a channel structure penetrating the stacking structure, the channel structure being connected to the first peripheral circuit chip near the first end of the first peripheral circuit chip; and a word line contact structure at least partially penetrating the stacking structure, the word line contact structure being connected to the second peripheral circuit chip near the second end of the second peripheral circuit chip.

[0005] In some embodiments, the memory array chip further includes a bit line, which is located on a side of the stacked structure close to the first peripheral circuit chip, and the first end of the channel structure is connected to the first peripheral circuit chip through the bit line.

[0006] In some embodiments, the first peripheral circuit chip includes a page buffer, and the second peripheral circuit chip includes a word line driver.

[0007] In some embodiments, the stack structure includes a plurality of dielectric layers and a plurality of gate layers alternately stacked, and the word line contact structure extends from a side of the stack structure close to the second peripheral circuit chip to a target gate layer among the plurality of gate layers.

[0008] In some embodiments, a cross-sectional dimension of the word line contact structure in a direction perpendicular to a first direction gradually increases along the first direction, wherein the first direction is a stacking direction from the first peripheral circuit chip toward the second peripheral circuit chip.

[0009] In some embodiments, the stacked structure includes a plurality of dielectric layers and a plurality of gate layers alternately stacked, each word line contact structure includes a first word line contact portion and a second word line contact portion, the first word line contact portion extends from a side of the stacked structure close to the first peripheral circuit chip to a target gate layer among the plurality of gate layers, and the second word line contact portion extends from a side of the stacked structure close to the second peripheral circuit chip to the target gate layer.

[0010] In some embodiments, the cross-sectional dimension of the first word line contact portion in a direction perpendicular to the first direction gradually decreases along the first direction, and the cross-sectional dimension of the second word line contact portion in a direction perpendicular to the first direction gradually increases along the first direction, wherein the first direction is the stacking direction of the first peripheral circuit chip toward the second peripheral circuit chip.

[0011] In some embodiments, a contact area between the second word line contact portion and the target gate layer is smaller than a contact area between the first word line contact portion and the target gate layer.

[0012] In some embodiments, the memory array chip further includes a common semiconductor layer, which is located on a side of the stacked structure close to the second peripheral circuit chip, and the second ends of the plurality of channel structures are connected to the second peripheral circuit chip through the common semiconductor layer.

[0013] In some embodiments, the word line contact structure includes a conductive filler and an insulating layer, wherein the insulating layer at least partially surrounds an outer sidewall of the conductive filler.

[0014] In some embodiments, the stacked structure includes an array region and a connection region, the gate layer extends in the array region and at least a portion of the connection region, a plurality of word line contact structures at least partially penetrate the stacked structure in the connection region and are connected to respective corresponding plurality of target gate layers, and the heights of the plurality of target gate layers in the stacking direction are different from each other.

[0015] Some other embodiments of the present application provide a memory system, which includes: a three-dimensional memory, the three-dimensional memory including the semiconductor device mentioned in any of the above embodiments; and a controller coupled to the three-dimensional memory to control the three-dimensional memory to store data.

[0016] Some embodiments of the present application provide a method for manufacturing a three-dimensional memory. The method for manufacturing the three-dimensional memory includes: forming a memory array chip and a first peripheral circuit chip bonded to each other, so that the first end of the channel structure in the memory array chip is connected to the first peripheral circuit chip; and bonding the second peripheral circuit chip to the memory array chip, so that the word line contact structure in the memory array chip is close to the second end of the second peripheral circuit chip and is connected to the second peripheral circuit chip.

[0017] In some embodiments, the manufacturing method further includes: forming a first peripheral circuit chip having a page buffer; and forming a second peripheral circuit chip having a word line driver.

[0018] In some embodiments, forming a memory array chip and a first peripheral circuit chip bonded to each other includes: forming a bit line connected to a first end of a channel structure on a first side of an initial stacking structure to form an initial memory array chip, wherein the initial stacking structure includes an array area and a connection area, the initial stacking structure includes a plurality of dielectric layers and a plurality of gate layers alternately stacked in the array area, and includes a plurality of dielectric layers and a plurality of sacrificial layers alternately stacked in the connection area, and the channel structure penetrates the initial stacking structure in the array area; and bonding the initial memory array chip to the first peripheral circuit chip.

[0019] In some embodiments, after the initial memory array chip is bonded to the first peripheral circuit chip, the method further includes: forming a first word line contact hole in a connection area extending to a target sacrificial layer among multiple sacrificial layers in the initial stacking structure from a side of the initial stacking structure away from the first peripheral circuit chip; replacing at least a portion of the target sacrificial layer with a portion of the target gate layer using the first word line contact hole to form a stacking structure; and forming a conductive filler in the first word line contact hole to form a word line contact structure, thereby forming a memory array chip.

[0020] In some embodiments, the plurality of word line contact structures extend in the connection region to the plurality of target gate layers corresponding to each other, and the heights of the plurality of target gate layers in the stacking direction are different from each other.

[0021] In some embodiments, forming a bit line connected to the channel structure on the first side of the initial stacking structure to form an initial storage array chip includes: forming a second word line contact hole in a connection area extending to a target sacrificial layer among multiple sacrificial layers in the initial stacking structure from the first side of the initial stacking structure; replacing at least a portion of the target sacrificial layer with a portion of the target gate layer using the second word line contact hole to form a stacking structure; forming a conductive filler in the second word line contact hole to form a first word line contact portion; forming a bit line connected to the channel structure on the first side of the stacking structure to form an initial storage array chip; wherein, after bonding the initial storage array chip to the first peripheral circuit chip, the method further includes: forming a second word line contact portion extending to the target gate layer from a side of the stacking structure away from the first peripheral circuit chip, so that the first word line contact portion and the second word line contact portion form a word line contact structure.

[0022] In some embodiments, forming a second word line contact portion extending to a target gate layer from a side of the stack structure away from the first peripheral circuit chip includes: forming a third word line contact hole extending to the target gate layer from a side of the stack structure away from the first peripheral circuit chip; and forming a conductive filler in the third word line contact hole to form a second word line contact portion.

[0023] In some embodiments, a plurality of second word line contact portions extend to respective corresponding plurality of target gate layers within the connection region, and the plurality of target gate layers have different heights in the stacking direction, wherein a third word line contact hole extending to the target gate layer is formed from a side of the stack structure away from the first peripheral circuit chip, comprising: in the same process, etching the stack structure to the plurality of target gate layers respectively to form a plurality of third word line contact holes.

[0024] In some implementations, a central axis of the first word line contact and a central axis of the second word line contact are at least partially aligned.

[0025] In some embodiments, an initial stacked structure is formed on a substrate, and a channel structure extends toward the substrate, and the channel structure includes a functional layer and a channel layer from the outside to the inside, wherein after forming an initial memory array chip and a first peripheral circuit chip bonded to each other, the method further includes: removing a portion of the substrate and the functional layer; and forming a common semiconductor layer connected to the channel layers of multiple channel structures.

[0026] According to at least one embodiment of the present application, the three-dimensional memory, memory system and manufacturing method of the three-dimensional memory provided by the present application, by connecting the first end of the channel structure close to the first peripheral circuit chip to the first peripheral circuit chip, and connecting the second end of the word line contact structure close to the second peripheral circuit chip to the second peripheral circuit chip, that is, connecting the opposite ends of the channel structure and the word line contact structure to different peripheral circuit chips respectively, is conducive to reducing the difficulty of back-end winding, improving the layout flexibility of the circuits in the first peripheral circuit chip and the second peripheral circuit chip, and optimizing the circuit layout in the first peripheral circuit chip and the second peripheral circuit chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Other features, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings, in which:

[0028] Figure 1 is a cross-sectional schematic diagram of a three-dimensional memory according to an exemplary embodiment of the present application;

[0029] Figure 2 is a schematic top view of a memory array chip according to an exemplary embodiment of the present application;

[0030] Figure 3 is a cross-sectional schematic diagram of a channel structure according to an exemplary embodiment of the present application;

[0031] Figure 4 is a cross-sectional schematic diagram of a three-dimensional memory according to another exemplary embodiment of the present application;

[0032] Figure 5 is a flow chart of a method for manufacturing a three-dimensional memory according to an exemplary embodiment of the present application;

[0033] FIG. 6A to FIG. 6D is a cross-sectional schematic diagram of a three-dimensional memory device according to an exemplary embodiment of the present application during a manufacturing process;

[0034] 7A to 7D is a cross-sectional schematic diagram of a three-dimensional memory device during a manufacturing process according to another exemplary embodiment of the present application;

[0035] Figure 8 is a cross-sectional schematic diagram of a three-dimensional memory in the related art;

[0036] Fig. 9 is a system block diagram of a memory system according to an exemplary embodiment of the present application; and

[0037] Fig. 10A and Fig. 10B is a schematic diagram of a memory system according to an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0038] In order to better understand the present application, a more detailed description will be made of various aspects of the present application with reference to the accompanying drawings. It should be understood that these detailed descriptions are only descriptions of exemplary embodiments of the present application, and are not intended to limit the scope of the present application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0039] It should be noted that in this specification, the expressions first, second, third, etc. are only used to distinguish one feature from another feature, and do not represent any limitation on the features, especially do not represent any order of precedence. Therefore, without departing from the teaching of this application, the first peripheral circuit chip discussed in this application may also be referred to as the second peripheral circuit chip, and vice versa.

[0040] In the drawings, the thickness, size and shape of the components have been slightly adjusted for ease of illustration. The drawings are for illustration only and are not drawn strictly to scale. As used herein, the terms "substantially," "approximately," and similar terms are used as terms of approximation, not as terms of degree, and are intended to account for the inherent deviations in measurements or calculations that would be recognized by one of ordinary skill in the art.

[0041] It should also be understood that expressions such as "include", "including", "have", "contain" and / or "comprising" are open rather than closed expressions in this specification, which indicate the presence of the stated features, elements and / or components, but do not exclude the presence of one or more other features, elements, components and / or combinations thereof. In addition, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features rather than just the individual elements in the list. In addition, when describing embodiments of the present application, "may" is used to mean "one or more embodiments of the present application". And, the term "exemplary" is intended to refer to an example or illustration.

[0042] Unless otherwise specified, all words (including engineering terms and scientific and technological terms) used in this article have the same meaning as those commonly understood by ordinary technicians in the field to which this application belongs. It should also be understood that, unless clearly stated in this application, words defined in common dictionaries should be interpreted as having the same meaning as their meaning in the context of the relevant technology, and should not be interpreted in an idealized or overly formal sense.

[0043] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments in this application can be combined with each other. In addition, unless explicitly limited or contradictory to the context, the specific steps included in the method recorded in this application are not necessarily limited to the recorded order, but can be performed in any order or in parallel.

[0044] In addition, in the present application, when “connected” or “coupled” is used, it may indicate direct contact or indirect contact between corresponding components, unless otherwise clearly defined or inferred from the context.

[0045] The present application will be described in detail below with reference to the accompanying drawings and in combination with implementation modes.

[0046] Some embodiments of the present application provide a three-dimensional memory. Figure 1 1 is a cross-sectional schematic diagram of a three-dimensional memory 100 according to an exemplary embodiment of the present application. It should be noted that, in the following, the x-direction, y-direction, and z-direction in each figure show the spatial relationship of the components in the three-dimensional memory. For example, the z-direction is the stacking direction of the stacking structure (or the initial stacking structure), and the x-direction and the y-direction are two directions perpendicular to each other on a plane perpendicular to the stacking direction. The same concept will be used throughout the present application to describe the spatial relationship of the components in the three-dimensional memory.

[0047] like Figure 1As shown, the three-dimensional memory 100 includes a first peripheral circuit chip 110, a second peripheral circuit chip 120 and a memory array chip 130. The memory array chip 130 is bonded to the first peripheral circuit chip 110, and the second peripheral circuit chip 120 is bonded to the memory array chip 130 on a side of the memory array chip 130 away from the first peripheral circuit chip 110. For example, the first peripheral circuit chip 110, the memory array chip 130 and the second peripheral circuit chip 120 are arranged in sequence along the z direction. It should be noted that the bonding referred to in the present application can be any appropriate bonding technology, such as hybrid bonding, anodic bonding, melt bonding, transfer bonding, adhesive bonding, eutectic bonding, etc. The memory array chip 130 can be used to provide a memory cell array composed of a plurality of memory cells to realize data storage. The first peripheral circuit chip 110 and the second peripheral circuit chip 120 can be used to provide a peripheral circuit for controlling the memory cell array to realize various operations such as writing, reading, erasing, etc.

[0048] Figure 2 1 is a schematic top view of a memory array chip 130 according to an exemplary embodiment of the present application.

[0049] in, Figure 1 Can be along Figure 2 The cross-sectional schematic diagram shown is taken along the section line II'. Figure 1 and Figure 2 As shown, the memory array chip 130 includes a stacked structure 131. In some embodiments, the stacked structure 131 is divided into an array area A and a connection area B in a plane perpendicular to the z direction. The array area A and the connection area B are arranged along the x direction. Figure 2 As shown, the two array regions A may be located on both sides of the connection region B in the x direction. In other examples, the two connection regions B may be located on both sides of the array region A in the x direction (not shown). In some embodiments, the connection region B may be divided into a first region B1 and a second region B2. The first region B1 and the second region B2 are arranged along the y direction. For example, the two first regions B1 are located on both sides of the second region B2 in the y direction.

[0050] In some embodiments, the stacked structure 131 is located in a portion of the second region B2 (eg, Figure 2 The stacked structure 131 may include a plurality of dielectric layers 1311 and a plurality of sacrificial layers 1313 alternately stacked in the z direction. The materials of the dielectric layers 1311 and the sacrificial layers 1313 may have different etching selectivities with respect to the same etchant. For example, the material of the dielectric layer 1311 may include silicon oxide, and the material of the sacrificial layer 1313 may include silicon nitride. The stacked structure 131 is located in the array region A, the first region B1, and another portion of the second region B2 (for example, Figure 2The portion of the second region B2 shown in gray) may include a plurality of dielectric layers 1311 and a plurality of gate layers 1312 alternately stacked in the z direction. In other words, the gate layer 1312 extends in the array area A, the first region B1, and a portion of the second region B2. The extension ranges of the gate layers 1312 of different layers in the second region B2 are different from each other. The extension range of the gate layer 1312 in the second region B2 is related to the word line contact structure 133, which will be described in detail below. The gate layer 1312 can be used as a word line of a three-dimensional memory. For example, a plurality of gate layers 1312 and a plurality of sacrificial layers 1313 may correspond one to one in the z direction. It should be noted that the present application does not impose specific restrictions on the number of stacked layers of the dielectric layer 1311 and the gate layer 1312 (or the sacrificial layer 1313). The more stacked layers of the dielectric layer 1311 and the gate layer 1132 (or the sacrificial layer 1313), the higher the integration of the memory cell, that is, the greater the unit storage density.

[0051] In some embodiments, the gate layer 1312 may be made of a conductive material. The conductive material may include, but is not limited to, metal (e.g., tungsten, cobalt, copper, aluminum), polysilicon, or any other suitable conductive material. For example, the material of the gate layer 1312 is tungsten. In other embodiments, the gate layer may include a high dielectric constant layer, an adhesive layer, and a conductive layer (not shown) arranged sequentially from the outside to the inside. The material of the high dielectric constant layer may include, but is not limited to, aluminum oxide, zirconium oxide, hafnium oxide, or any other suitable high dielectric constant material. The material of the adhesive layer may include, but is not limited to, titanium, titanium nitride, tantalum, tantalum nitride, or any other suitable material. It should be noted that the portions of the gate layer 1312 located in different regions may have different internal structures, and this application does not limit this.

[0052] The memory array chip 130 further includes a channel structure 132. For example, a plurality of channel structures 132 are arranged in an array in the array area A. Figure 1 As shown, the channel structure 132 penetrates the stack structure 131. For example, the channel structure 132 may be a columnar structure. The channel structure 132 is connected to the first peripheral circuit chip 110 near the first end of the first peripheral circuit chip 110, so as to electrically connect the functional circuit for controlling the first end of the channel structure 132 in the first peripheral circuit chip 110 to the channel structure 132.

[0053] Figure 3 is a schematic cross-sectional view of a channel structure 132 according to an exemplary embodiment of the present application. In some embodiments, as Figure 3As shown, the channel structure 132 may include a blocking layer 1321, a charge trapping layer 1322, a tunneling layer 1323, and a channel layer 1324, which are sequentially arranged from the outside to the inside. The blocking layer 1321, the charge trapping layer 1322, and the tunneling layer 1323 may be referred to as a functional layer 1326. For example, the materials of the blocking layer 1321, the charge trapping layer 1322, and the tunneling layer 1323 may sequentially include silicon oxide, silicon nitride, and silicon oxide. The material of the channel layer 1324 may include any other appropriate semiconductor material such as silicon (e.g., amorphous silicon, polycrystalline silicon, or single crystal silicon).

[0054] In some embodiments, a portion of the channel structure 132 surrounded by a gate layer 1312 and a portion of the gate layer 1312 constitute a memory cell MC. A plurality of memory cells MC are arranged in series along the extension direction (e.g., z direction) of the channel structure 132 to constitute a memory string, and share the channel layer 1324. The remaining portion of the gate layer 1312 can be used as a word line connecting a plurality of memory cells MC at the same height in different memory strings. For example, by applying a voltage to the gate layer 1312, the memory cell MC can cause the charge in the channel layer 1324 to enter the charge trapping layer 1322, or cause the charge in the charge trapping layer 1322 to return to the channel layer 1324, thereby placing the memory cell MC in a programmed state or an erased state (unprogrammed state).

[0055] like Figure 1 As shown, the memory array chip 130 further includes a word line contact structure 133. For example, a plurality of word line contact structures 133 are arranged, for example, in the second region B2 of the connection region B. The word line contact structure 133 at least partially penetrates the stacked structure 131, and the word line contact structure 133 is connected to the second peripheral circuit chip 120 near the second end of the second peripheral circuit chip 120, so as to electrically connect the functional circuit for controlling the gate layer (word line) in the second peripheral circuit chip 120 with the plurality of gate layers 1312.

[0056] In some embodiments, the word line contact structure 133 extends from one side of the stack structure 131 close to the second peripheral circuit chip 120 to one gate layer among the plurality of gate layers 1312 (the target gate layer corresponding to the word line contact structure 133). Figure 2As shown, in the projection plane perpendicular to the z direction, the projection of the word line contact structure 133 is located within the projection of the gate layer 1312 corresponding to the word line contact structure 133 in the second region B2. In other words, in the projection plane perpendicular to the z direction, the projection area of ​​the gate layer 1312 corresponding to the word line contact structure 133 in the second region B2 is larger than the projection area of ​​the word line contact structure 133. For example, in the projection plane perpendicular to the z direction, the projection shape of the word line contact structure 133 and the projection shape of the gate layer 1312 corresponding to the word line contact structure 133 in the second region B2 are substantially concentric circles. The projection of the gate layer 1312 corresponding to the word line contact structure 133 in the second region B2 contacts the projection of the gate layer 1312 in the first region B1. Since the multiple word line contact structures 133 are discretely distributed at different positions in the second region B2, the extension ranges of the multiple gate layers 1312 corresponding to the multiple word line contact structures 133 in the second region B2 are different from each other. Different word line contact structures 133 can be electrically connected to different layers of gate layers 1312 by having different extension distances in the z direction, and lead out different layers of gate layers 1312. The material of the word line contact structure 133 may include, but is not limited to, tungsten, cobalt, copper, aluminum, titanium nitride, polysilicon, or any other appropriate conductive material. For example, the material of the word line structure 133 may be tungsten.

[0057] In some embodiments, the cross-sectional dimension of the word line contact structure 133 in the perpendicular direction to the z direction gradually increases along the positive z direction (e.g., the stacking direction of the first peripheral circuit chip 110 toward the second peripheral circuit chip 120). For example, the word line contact structure 133 may be a substantially cylindrical structure. The diameter of the word line contact structure 133 gradually increases along the positive z direction. In other embodiments, the cross-sectional dimension of the word line contact structure in the perpendicular direction to the z direction is substantially the same along the positive z direction, and the present application does not limit this.

[0058] In some embodiments, the word line contact structure 133 may include an insulating layer and a conductive filler (not shown). The insulating layer surrounds at least a portion of the outer sidewall of the conductive filler. The material of the insulating layer may include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any other suitable insulating material. For example, the material of the insulating layer may be silicon oxide.

[0059] Figure 8 Schematic diagram of a cross-section of a three-dimensional memory in the related art. Figure 8As shown, in the related art, the memory array chip 430 is located between the first peripheral circuit chip 410 and the second peripheral circuit chip 420, and is bonded to the first peripheral circuit chip 410 and the second peripheral circuit chip 420 respectively. The second end of the channel structure 432 close to the second peripheral circuit chip 420 and the second end of the word line contact structure 433 close to the second peripheral circuit chip 420 are both connected to the second peripheral circuit chip 420. If the functional circuit for controlling the second end of the channel structure 432 and the functional circuit for controlling the gate layer (word line) are arranged in the two peripheral circuit chips. It is usually necessary to additionally set up a through contact structure 441 to electrically connect the two functional circuits. However, this layout method will increase the difficulty of the back-end winding, make the circuit design in the two peripheral circuit chips more complicated, and is not conducive to optimizing the functional circuits of the first peripheral circuit chip and the second peripheral circuit chip into a reasonable layout.

[0060] In an embodiment of the present application, when the three-dimensional memory includes a first peripheral circuit chip, a second peripheral circuit chip and a memory array chip, and the memory array chip is located between the first peripheral circuit chip and the second peripheral circuit chip, by connecting the first end of the channel structure close to the first peripheral circuit chip to the first peripheral circuit chip, and connecting the second end of the word line contact structure close to the second peripheral circuit chip to the second peripheral circuit chip, that is, connecting the opposite ends of the channel structure and the word line contact structure to different peripheral circuit chips, respectively, it is helpful to reduce the difficulty of back-end winding, improve the layout flexibility of the circuits in the first peripheral circuit chip and the second peripheral circuit chip, and optimize the circuit layout in the first peripheral circuit chip and the second peripheral circuit chip.

[0061] In some embodiments, Figure 1 As shown, the memory array chip 130 may further include a bit line (not shown). The bit line is located on one side of the stacked structure 131 close to the first peripheral circuit chip 110. For example, the first ends (e.g., drain ends) of the plurality of channel structures 132 arranged along the y direction are connected to the same bit line. In other words, the first end of the channel structure 132 is connected to the first peripheral circuit chip 110 through the bit line.

[0062] In some embodiments, Figure 1 As shown, the memory array chip 130 may further include a common semiconductor layer 134. The common semiconductor layer 134 is located on one side of the stacked structure 131 close to the second peripheral circuit chip 120. For example, the common semiconductor layer 134 is located in the array region A. The second ends (for example, source ends) of the plurality of channel structures 132 are connected to the second peripheral circuit 120 through the common semiconductor layer 134. For example, the channel layer 1324 (refer to Figure 3) extends from the stacked structure 131 into the common semiconductor layer 134 and contacts the common semiconductor layer 134. The material of the common semiconductor layer 134 may include but is not limited to silicon (e.g., amorphous silicon, polycrystalline silicon, or single crystal silicon) or any other suitable semiconductor material. For example, the material of the common semiconductor layer 134 and the material of the channel layer 1324 may be the same.

[0063] In some embodiments, the functional circuits in the first peripheral circuit chip 110 and the second peripheral circuit chip 120 together constitute a peripheral circuit for controlling the memory cell array to implement various operations such as writing, reading, erasing, etc. For example, the peripheral circuit can control the memory cell array through word lines and bit lines. The peripheral circuit may include one or more of a page buffer / sense amplifier, a decoder (e.g., a row decoder or a column decoder), a word line driver, an input / output (I / O) circuit, a charge pump, a voltage source or a voltage generator, a current or voltage reference, any part of the functional circuit (e.g., a subcircuit) or any active or passive device of the functional circuit (e.g., a transistor, a diode, a resistor, or a capacitor).

[0064] In some embodiments, the first peripheral circuit chip 110 may include a page buffer, and the second peripheral circuit chip 120 may include a word line driver. For example, the word line driver may be a functional circuit for controlling a gate layer (word line), and the page buffer may be a functional circuit for controlling a first end (e.g., a drain end) of a channel structure. In some examples, the word line driver may be configured to apply a programming voltage (Vprog) or a pass voltage (Vpass) in a range of, for example, between 5V and 30V to the gate layer (word line) during a programming operation. In some examples, the page buffer may include a bit line driver and a latch. For example, the bit line driver in the page buffer may be configured to apply an erase voltage (Veras) in a range of, for example, between 5V and 30V to the bit line during an erase operation. For example, the latch in the page buffer may be configured to buffer data read from a memory cell array or data to be programmed to the memory cell array. In this embodiment, when the page buffer and the word line driver have their own independent control circuits, the page buffer and the word line driver are respectively arranged in the first peripheral circuit chip and the second peripheral circuit chip, without the need to add an additional through-contact structure, which is conducive to reducing the plane size of the three-dimensional memory and reducing the difficulty of back-end winding. When the page buffer and the word line driver have a common control circuit, for example, the circuits in the page buffer other than the common control circuit can be arranged in the first peripheral circuit chip, and the circuits in the word line driver other than the common control circuit can be arranged in the second peripheral circuit chip, and the common control circuit is arranged in one of the first peripheral circuit chip and the second peripheral circuit chip, so that the number of required through-contact structures can be reduced as a whole, which is conducive to reducing the plane size of the three-dimensional memory and reducing the difficulty of back-end winding.

[0065] In some embodiments, the three-dimensional memory 100 further includes a first bonding layer 101 and a second bonding layer 102. The first bonding layer 101 is located between the first peripheral circuit chip 110 and the memory array chip 130, and the second bonding layer 102 is located between the memory array chip 130 and the second peripheral circuit chip 120. The first bonding layer 101 and the second bonding layer 102 each include a plurality of bonding contacts (not shown). The material of the bonding contacts may include, but is not limited to, tungsten, cobalt, copper, aluminum, titanium nitride, polysilicon, or any other suitable conductive material.

[0066] Figure 4 FIG. 2 is a cross-sectional schematic diagram of a three-dimensional memory 200 according to another exemplary embodiment of the present application. Figure 4 As shown, Figures 1 to 3 The difference of the three-dimensional memory 100 shown is the word line contact structure 233. For the purpose of brevity, the same components as those in the three-dimensional memory 100 are not described in detail in this application.

[0067] like Figure 4 As shown, the memory array chip 230 includes a word line contact structure 233. For example, a plurality of word line contact structures 233 are arranged in the second region B2 of the connection region B (see Figure 2 The word line contact structure 233 penetrates the stack structure 231 and is connected to the second peripheral circuit chip 220 at a second end thereof close to the second peripheral circuit chip 220, so as to electrically connect the functional circuit for controlling the gate layer (word line) in the second peripheral circuit chip 220 with the plurality of gate layers 2312.

[0068] In some embodiments, each word line contact structure 233 includes a first word line contact portion 2331 and a second word line contact portion 2332. The first word line contact portion 2331 and the second word line contact portion 2332 may be at least partially aligned. The first word line contact portion 2331 extends from a side of the stacked structure 231 close to the first peripheral circuit chip 210 to one of the plurality of gate layers 2312 (the target gate layer corresponding to the word line contact structure 233). The second word line contact portion 2332 extends from a side of the stacked structure 231 close to the second peripheral circuit chip 220 to its corresponding gate layer 2132. Figure 2As shown, in the projection plane perpendicular to the z direction, the projection of the word line contact structure 233 (for example, the first word line contact portion 2331) is located within the projection of the gate layer 2132 corresponding to the word line contact structure 233 in the second region B2. In other words, in the projection plane perpendicular to the z direction, the projection area of ​​the gate layer 2132 corresponding to the word line contact structure 233 in the second region B2 is larger than the projection area of ​​the word line contact structure 233 (for example, the first word line contact portion 2331). The materials of the first word line contact portion 2331 and the second word line contact portion 2332 may include, but are not limited to, tungsten, cobalt, copper, aluminum, titanium nitride, polysilicon or any other appropriate conductive material. For example, the material of the first word line contact portion 2331 and the second word line contact portion 2332 may be tungsten. In this embodiment, the gate layer 2312 may also be connected to the first peripheral circuit chip 210 through the first end of the first word line contact portion 2331 close to the first peripheral circuit chip 210, further improving the layout flexibility of the circuits in the first peripheral circuit chip 210 and the second peripheral circuit chip 220.

[0069] In some embodiments, the cross-sectional dimension of the first word line contact portion 2331 in the direction perpendicular to the z direction gradually decreases along the positive z direction (for example, the stacking direction of the first peripheral circuit chip 210 toward the second peripheral circuit chip 220). The cross-sectional dimension of the second word line contact portion 2332 in the direction perpendicular to the z direction gradually increases along the positive z direction. For example, the first word line contact portion 2331 and the second word line contact portion 2332 may be approximately cylindrical structures. The diameter of the first word line contact portion 2331 gradually decreases along the positive z direction, and the diameter of the second word line contact portion 2332 gradually increases along the positive z direction. In other embodiments, the cross-sectional dimensions of the first word line contact portion and the second word line contact portion in the direction perpendicular to the z direction are approximately the same along the positive z direction, and the present application does not limit this.

[0070] In some embodiments, the contact area between the second word line contact 2332 and its corresponding gate layer 2312 is smaller than the contact area between the first word line contact 2331 and the gate layer 2312. The gate layer 2312 can be used as a stop layer for the second word line contact 2332 during the manufacturing process, so that multiple second word line contacts 2332 can be formed in the same process, which is conducive to improving manufacturing efficiency.

[0071] In some embodiments, the first word line contact portion 2331 in the word line contact structure 233 may include an insulating layer and a conductive filler (not shown). The insulating layer surrounds at least a portion of the outer sidewall of the conductive filler. The material of the insulating layer may include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any other suitable insulating material. For example, the material of the insulating layer may be silicon oxide.

[0072] In some embodiments, the first peripheral circuit chip 210 may include a page buffer, and the second peripheral circuit chip 220 may include a word line driver. In this embodiment, when the page buffer and the word line driver have their own independent control circuits, the page buffer and the word line driver are respectively arranged in the first peripheral circuit chip and the second peripheral circuit chip, without the need to add an additional through-contact structure, which is conducive to reducing the plane size of the three-dimensional memory and reducing the difficulty of back-end winding. When the page buffer and the word line driver have a common control circuit, for example, the circuits in the page buffer other than the common control circuit can be arranged in the first peripheral circuit chip, and the circuits in the word line driver other than the common control circuit can be arranged in the second peripheral circuit chip, and the common control circuit is arranged in one of the first peripheral circuit chip and the second peripheral circuit chip, and the word line contact structure composed of the first word line contact portion and the second word line contact portion can play the role of a through-contact structure, without the need to add an additional through-contact structure, which is conducive to reducing the number of required through-contact structures as a whole, and is conducive to reducing the plane size of the three-dimensional memory and reducing the difficulty of back-end winding.

[0073] Some embodiments of the present application also provide a method for manufacturing a three-dimensional memory. Figure 5 FIG. 3 is a flow chart of a method 300 for manufacturing a three-dimensional memory according to an exemplary embodiment of the present application. Figure 5 As shown, a method 300 for manufacturing a three-dimensional memory (hereinafter referred to as manufacturing method 300 ) includes steps S310 and S320 .

[0074] S310, forming a memory array chip and a first peripheral circuit chip bonded to each other, so that a first end of a channel structure in the memory array chip is connected to the first peripheral circuit chip.

[0075] S320, bonding the second peripheral circuit chip to the memory array chip, so that the word line contact structure in the memory array chip is close to the second end of the second peripheral circuit chip and is connected to the second peripheral circuit chip.

[0076] According to the manufacturing method of the three-dimensional memory provided in this embodiment, by connecting the first end of the channel structure in the memory array chip to the first peripheral circuit chip, and connecting the second end of the word line contact structure in the memory array chip close to the second peripheral circuit chip to the second peripheral circuit chip, that is, connecting the opposite ends of the channel structure and the word line contact structure to different peripheral circuit chips respectively, it is helpful to reduce the difficulty of back-end winding, improve the layout flexibility of the circuits in the first peripheral circuit chip and the second peripheral circuit chip, and optimize the circuit layout in the first peripheral circuit chip and the second peripheral circuit chip.

[0077] FIG. 6A to FIG. 6Dis a schematic cross-sectional view of an intermediate structure of a three-dimensional memory device in a manufacturing process according to an exemplary embodiment of the present application. Figure 5 The manufacturing method 300 shown may form FIG. 6A to FIG. 6D The intermediate structure of the three-dimensional memory is shown, and Figures 1 to 3 The three-dimensional memory 100 is shown. FIG. 6A to FIG. 6D as well as Figures 1 to 3 The above steps S310 and S320 are explained by way of example.

[0078] S310 forms a memory array chip and a first peripheral circuit chip bonded to each other, so that a first end of a channel structure in the memory array chip is connected to the first peripheral circuit chip.

[0079] In some implementations, step S310 may include steps S311a to S316a. Steps S311a to S316a are exemplarily described below with reference to the accompanying drawings.

[0080] S311a forms a first peripheral circuit chip having a page buffer.

[0081] In step S311a, Fig. 6A As shown, a plurality of peripheral devices 112 may be formed on one side of the first substrate 111. The material of the first substrate 111 may include, but is not limited to, silicon (e.g., single crystal silicon c-Si), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), or any other appropriate material. For example, the first substrate 111 may be a silicon substrate.

[0082] In some embodiments, the type of peripheral device 112 may include a metal oxide semiconductor field effect transistor (MOSFET), a fin field effect transistor (FINFET), a bipolar junction transistor (BJT), a diode, a resistor, an inductor, a capacitor, or any other suitable semiconductor device. Several peripheral devices 112 may constitute a digital, analog, and / or mixed digital-analog functional circuit for implementing various functions. For example, multiple peripheral devices 112 in the first peripheral circuit chip 110 may be used to constitute a page buffer.

[0083] In some embodiments, the trench isolation structure 113 may be formed at the periphery of the peripheral device 112 to achieve electrical isolation between adjacent peripheral devices 112. The trench isolation structure 113 may be formed by patterning the first substrate 111 through photolithography and etching processes, filling the insulating material, and polishing the insulating material. Exemplarily, the insulating material used to form the trench isolation structure 113 may include silicon oxide, silicon nitride, silicon oxynitride, low temperature oxide (LTO), high temperature oxide (HTO), or any other suitable insulating material. Exemplarily, the insulating material may be filled by processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), sputtering, thermal oxidation / nitridation, or any combination thereof.

[0084] In some embodiments, after forming a plurality of peripheral devices 112, a thin film deposition process such as CVD, PVD, ALD or any combination thereof may be used to form an insulating material layer 114 on one side of the plurality of peripheral devices 112 away from the first substrate 111, and a plurality of interconnection line structures 115 and a plurality of contact via structures 116 may be formed in the insulating material layer 114 to form a first interconnection layer. The interconnection line structure 115 may extend laterally in a plane perpendicular to the z direction, and the contact via structure 116 may extend longitudinally in the z direction. The plurality of contact via structures 116 and the plurality of interconnection line structures 115 are alternately arranged in layers in the z direction. The contact via structures 116 and the interconnection line structures 115 interconnect the plurality of peripheral devices 112 to form a functional circuit with, for example, a page buffer. The material of the insulating material layer 114 may include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride or any other suitable insulating material. The materials of the interconnection line structure 115 and the contact via structure 116 may include, but are not limited to, tungsten, cobalt, copper, aluminum, polysilicon, titanium, titanium nitride or any other suitable conductive material.

[0085] S312a forms a bit line connected to the first end of the channel structure on the first side of the initial stacking structure to form an initial storage array chip, wherein the initial stacking structure includes an array area and a connection area, the initial stacking structure includes a plurality of alternatingly stacked dielectric layers and a plurality of gate layers in the array area, and includes a plurality of alternatingly stacked dielectric layers and a plurality of sacrificial layers in the connection area, and the channel structure runs through the initial stacking structure in the array area.

[0086] In step S312a, if Figure 6B As shown, the initial stacked structure 131' may be formed on one side of the third substrate 135. The material of the third substrate 135 may include, but is not limited to, silicon (e.g., single crystal silicon c-Si), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), or any other appropriate material. For example, the third substrate 135 may be a composite substrate having a multilayer structure. Figure 2, the initial stacking structure 131' is divided into an array area A and a connection area B in a plane perpendicular to the z direction. The array area A and the connection area B are arranged along the x direction. The connection area B is divided into a first area B1 and a second area B2. The first area B1 and the second area B2 are arranged along the y direction. For example, the two first areas B1 are located on both sides of the second area B2 in the y direction. The portion of the initial stacking structure 131' located in the array area A and the first area B1 has a plurality of dielectric layers 1311 and a plurality of gate layers 1312 alternately stacked in the z direction. The portion of the initial stacking structure 131' located in the second area B2 has a plurality of dielectric layers 1311 and a plurality of sacrificial layers 1313 alternately stacked in the z direction.

[0087] In some embodiments, the plurality of gate layers 1312 in the portion of the initial stacked structure 131' located in the array region A and the first region B1 may be formed by a "replacement" process. For example, before the "replacement" process is performed, the portion of the initial stacked structure (not shown) located in the array region A and the connection region B includes a plurality of dielectric layers 1311 and a plurality of sacrificial layers 1313 alternately stacked in the z direction. For example, the initial stacked structure 131' may be formed by the manufacturing method described below. Figure 2 , a first gate line gap corresponding to the first gate gap structure 1361 and a second gate line gap corresponding to the second gate line gap structure 1362 can be formed by photolithography and etching processes. The first gate line gap and the second gate line gap can be grooves in which the first gate line gap structure 1361 and the second gate line gap structure 1362 are in an unfilled state, respectively. The first gate line gap and the second gate line gap penetrate the unreplaced initial stacking structure in the z direction. The first gate line gap extends continuously along the x direction in the array area A and the connection area B, and the second gate line gap extends discontinuously along the x direction in the array area A. The second gate line gap is located between two adjacent first gate line gaps. In other words, the first gate line gap and the second gate line gap are arranged along the y direction.

[0088] Further, a thin film deposition process may be used to fill a sacrificial material in the portion of the first gate line gap located in the array region A, and the portion of the first gate line gap located in the connection region B is left unfilled. For example, the sacrificial material may have different etching selectivities with the dielectric layer 1311 and the sacrificial layer 1313 relative to the same etchant. For example, the sacrificial material may include, but is not limited to, polysilicon or carbon. Further, a wet etching process may be used to remove the portion of the first region B1 of each sacrificial layer 1313 located in the connection region B via the portion of the first gate line gap located in the connection region B. It should be noted that the first region B1 may be a region having a predetermined distance from the first gate line gap. For example, the area and range of the first region B1 may be determined by controlling the etching rate and / or etching time of the wet etching. Further, the sacrificial material in the portion of the first gate line gap located in the array region A may be removed by a wet etching process to remove the portion of each sacrificial layer 1313 located in the connection region A via the portion of the first gate line gap located in the array region A and / or the second gate gap.

[0089] Further, a gate layer 1312 may be formed in a gap formed by removing the sacrificial layer 1313 in the first region B1 located in the array region A and the connection region B by using a thin film deposition process such as CVD, PVD, ALD or any combination thereof. In some examples, a high dielectric constant layer and a conductive layer may be sequentially formed in the gap to form the gate layer 1312. For example, the material of the high dielectric constant layer may include aluminum oxide, zirconium oxide, hafnium oxide or any other suitable high dielectric constant material, and the material of the conductive layer may include tungsten, cobalt, copper, aluminum, polysilicon or any other suitable conductive material. In other examples, a conductive layer may be directly formed in the gap and used as the gate layer 1312.

[0090] Further, the first gate line gap and the second gate line gap may be filled to form a first gate line gap structure 1361 and a second gate line gap structure 1362. For example, the filling material in the first gate line gap and the second gate line gap may include silicon oxide, silicon nitride, silicon oxynitride or any other appropriate insulating material. Thus, an initial stacked structure 131' may be formed. The portion of the initial stacked structure 131 located in the array area A and the first area B1 includes a plurality of dielectric layers 1311 and a plurality of gate layers 1312 alternately stacked, and the portion of the initial stacked structure 131' located in the second area B2 includes a plurality of sacrificial layers 1313 of a plurality of dielectric layers 1311 alternately stacked.

[0091] It should be noted that the above exemplary steps of forming the initial stacking structure 131' are described. In other embodiments, the sacrificial layer 1313 in the portion of the initial stacking structure that is not replaced and located in the array area A may be removed first, and then the sacrificial layer 1313 in the portion of the initial stacking structure that is not replaced and located in the first area B1 may be removed, and the present application does not limit this.

[0092] In some embodiments, Figure 6B As shown, the channel structure 132 may penetrate the initial stacking structure 131'. To form the channel structure 132, a channel hole (not shown) may be first formed that penetrates, for example, the initial stacking structure that is not replaced and extends into the third substrate 135, and then, Figure 3 A blocking layer 1321 , a charge trapping layer 1322 , a tunneling layer 1323 and a channel layer 1324 are sequentially formed on the inner wall of the channel hole, and a channel plug 1325 is formed on the top of the channel hole, thereby forming a channel structure 132 .

[0093] In some embodiments, Figure 6B As shown, after the initial stack structure 131' is formed, a channel plug 1325 (see FIG. 1 ) connected to the channel structure 132 can be formed on the side of the initial stack structure 131' away from the third substrate 135 by using photolithography and etching processes and thin film deposition processes. Figure 3 ) is connected to the trench contact 137. For example, the material of the trench contact 137 may include but is not limited to tungsten, cobalt, copper, aluminum, polysilicon, titanium, titanium nitride or any other suitable conductive material.

[0094] Further, a bit line (not shown) connected to the channel contact 137 may be formed on a side of the initial stacked structure 131' away from the third substrate 135 (e.g., a side of the channel contact 137 away from the initial stacked structure 131') by using a photolithography and etching process and a thin film deposition process. In other words, the bit line is connected to the first end (e.g., the drain end) of the channel structure 132 through the channel contact 137. For example, the first ends (e.g., the drain ends) of a plurality of channel structures 132 arranged along the y direction are connected to the same bit line.

[0095] In some embodiments, a third interconnect layer (not shown) may be formed on a side of the bit line away from the initial stacked structure 131' using a photolithography and etching process and a thin film deposition process. For example, the third interconnect layer may include a plurality of interconnect line structures and a plurality of contact via structures. The interconnect line structure may extend laterally in a plane perpendicular to the z direction, and the contact via structure may extend longitudinally in the z direction. The plurality of contact via structures and the plurality of interconnect line structures are alternately arranged in layers in the z direction.

[0096] After the above process, Figure 6B As shown, an initial memory array chip 130' may be formed.

[0097] S313a bonds the initial memory array chip to the first peripheral circuit chip.

[0098] In step S313a, if Figure 6CAs shown, the initial memory array chip 130' and the first peripheral circuit chip 110 may be connected in the z direction, for example, by bonding (e.g., hybrid bonding), thereby forming a first bonding layer 101 between the initial memory array chip 130' and the first peripheral circuit chip 110. Hybrid bonding may perform data transmission between the initial memory array chip 130' and the first peripheral circuit chip 110 through bonding contacts.

[0099] In some embodiments, after bonding the initial memory array chip 130' to the first peripheral circuit chip 110, the manufacturing method 300 may further include a step of forming a common semiconductor layer 134. Figure 6B and 6C As shown, firstly, mechanical chemical polishing (CMP) and / or wet etching process can be used to remove the third substrate 135 and the functional layer 1326 extending from the channel structure 132 to the third substrate 135 (refer to Figure 3 ) so that the channel layer 1324 (reference Figure 3 ) is exposed. Then, a thin film deposition process such as CVD, PVD, ALD or any combination thereof may be used to form a common semiconductor layer 134 connected to the channel layer 1324 at the portion of the initial stacked structure 131' located in the array region A. An insulating capping layer 138 is formed at the portion of the initial stacked structure 131' located in the connection region B. The material of the insulating capping layer 138 may include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride or any other appropriate insulating material.

[0100] S314a: forming a first word line contact hole in the connection region from a side of the initial stack structure away from the first peripheral circuit chip to a target sacrificial layer among the plurality of sacrificial layers in the initial stack structure.

[0101] In step S314a, if Figure 6C and 6D As shown, as described above, the portion of the initial stacked structure 131' located in the second region B2 includes a plurality of dielectric layers 1311 and a plurality of sacrificial layers 1313 alternately stacked. For example, a photolithography and etching (e.g., dry etching or wet etching) process may be used to form a first word line contact hole penetrating the insulating cover layer 138 and extending in the initial stacked structure 131' from the side of the initial stacked structure 131' away from the first peripheral circuit chip 110 in the second region B2 of the connection region B. For example, the first word line contact hole corresponds to Fig.6D The outer contour of the word line contact structure 133 is shown. The first word line contact hole may extend in the z direction and extend to one sacrificial layer (the target sacrificial layer corresponding to the first word line contact hole) among the plurality of sacrificial layers 1313 to expose the sacrificial layer 1313 corresponding to it.

[0102] It should be noted that since the first word line contact hole is formed by etching the initial stack structure 131' from the side of the initial stack structure 131' away from the first peripheral circuit chip 110, due to the limitations of the etching process, the cross-sectional size (e.g., diameter) of the first word line contact hole on a plane perpendicular to the z direction gradually increases along the positive z direction.

[0103] S315a: Using the first word line contact hole, at least a portion of the target sacrificial layer is replaced with a portion of the target gate layer to form a stacked structure.

[0104] In step S315a, as shown in FIG6, since the first word line contact hole exposes the corresponding sacrificial layer 1313, the first word line contact hole can be used to remove at least a portion of the corresponding sacrificial layer by, for example, a wet etching process to form a gap. The gap can expose the gate layer (the gate layer can be a target gate layer) that is located in the same layer as the sacrificial layer 1313 and located in the first region B1. Optionally, a thin film deposition process can be used to form an insulating layer on the sidewall of the first word line contact hole to protect other dielectric layers 1311 and other sacrificial layers 1313 exposed by the sidewall of the first word line contact hole.

[0105] Further, in some examples, a thin film deposition process may be used to fill the gap with a conductive material to form a portion of the gate layer 1312. In another exemplary embodiment, a high dielectric constant layer, an adhesion layer, and a conductive layer may be sequentially formed in the gap using a thin film deposition process as a portion of the gate layer 1312.

[0106] After the above process, Fig.6D As shown, the initial stacking structure 131 '(reference Figure 6C ) is converted into a stacked structure 131. The stacked structure 131 is located in the array area A, the first area B1 (reference Figure 2 ) and a portion of the second area B2 include multiple dielectric layers 1311 and multiple gate layers 1312 stacked alternately, and a portion of the stacked structure 131 located in another portion of the second area B2 includes multiple dielectric layers 1311 and multiple sacrificial layers 1313 stacked alternately.

[0107] S316a: forming a conductive filler in the first word line contact hole to form a word line contact structure, thereby forming a memory array chip.

[0108] In step S316a, if Fig.6D As shown, a thin film deposition process such as CVD, PVD, ALD or any combination thereof may be used to form a conductive filler in the first word line contact hole to form a word line contact structure 133. For example, in the case where an insulating layer is formed on the sidewall of the first word line contact hole, a thin film deposition process may be used to form a conductive filler in the space surrounded by the insulating layer.

[0109] It should be noted that the multiple word line contact structures 133 extend to their respective corresponding multiple gate layers in the second region B2 of the connection region B, and the heights of the multiple gate layers in the stacking direction are different from each other, thereby leading out the multiple gate layers in the stacking structure 131.

[0110] In some embodiments, the manufacturing method 300 may further include the step of forming a fourth interconnect layer (not shown). For example, a fourth interconnect layer (not shown) may be formed on a side of the common semiconductor layer 134 and the insulating cover layer 138 away from the stacked structure 131 using a photolithography and etching process and a thin film deposition process. For example, the fourth interconnect layer may include a plurality of interconnect line structures and a plurality of contact through hole structures. The interconnect line structure may extend laterally in a plane perpendicular to the z direction, and the contact through hole structure may extend longitudinally in the z direction. The plurality of contact through hole structures and the plurality of interconnect line structures are alternately arranged in layers in the z direction.

[0111] After the above process, Fig.6D As shown, the initial storage array chip 130' (reference Figure 6C ) is converted into a memory array chip 130, thereby forming a memory array chip 130 and a first peripheral circuit chip 110 bonded to each other.

[0112] S320: Bonding the second peripheral circuit chip to the memory array chip, so that the word line contact structure in the memory array chip is close to the second end of the second peripheral circuit chip and is connected to the second peripheral circuit chip.

[0113] In step S320, Figure 1 As shown, a plurality of peripheral devices 122 may be formed on one side of the second substrate 121. The material of the second substrate 121 may include, but is not limited to, silicon (e.g., single crystal silicon c-Si), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), or any other appropriate material. For example, the second substrate 121 may be a silicon substrate.

[0114] In some embodiments, the type of the peripheral device 122 may include a metal oxide semiconductor field effect transistor (MOSFET), a fin field effect transistor (FINFET), a bipolar junction transistor (BJT), a diode, a resistor, an inductor, a capacitor, or any other suitable semiconductor device. Several peripheral devices 122 may constitute a digital, analog, and / or mixed digital-analog functional circuit for implementing various functions. For example, a plurality of peripheral devices 122 in the second peripheral circuit chip 120 may be used to constitute a word line driver.

[0115] In some embodiments, after forming the plurality of peripheral devices 122, a second interconnect layer may be formed on a side of the plurality of peripheral devices 122 away from the second substrate 121. The second interconnect layer may include a plurality of interconnect line structures 125 and a plurality of contact via structures 126. The interconnect line structures 125 may extend laterally in a plane perpendicular to the z-direction, and the contact via structures 126 may extend longitudinally in the z-direction. The plurality of contact via structures 126 and the plurality of interconnect line structures 125 are alternately arranged in layers in the z-direction.

[0116] It should be noted that the initial memory array chip 130 ′, the first peripheral circuit chip 110 , and the second peripheral circuit chip 120 may be manufactured in parallel so that the thermal budget of manufacturing one of the chips does not impose a limitation on the process of manufacturing another.

[0117] In step S320, Figure 1 As shown, the second peripheral circuit chip 120 and the memory array chip 130 may be connected in the z direction, for example, by bonding (e.g., hybrid bonding), so as to form a second bonding layer 102 between the second peripheral circuit chip 120 and the memory array chip 130. Hybrid bonding may perform data transmission between the memory array chip 130 and the second peripheral circuit chip 120 through bonding contacts. For example, data transmission between the second end of the word line contact structure 133 in the memory array chip 130 close to the second peripheral circuit chip 120 and the second peripheral circuit chip 120.

[0118] According to the manufacturing method of the three-dimensional memory of the embodiment of the present application, the opposite ends of the channel structure and the word line contact structure are respectively connected to different peripheral circuit chips, which is beneficial to reduce the difficulty of back-end winding, improve the layout flexibility of the circuits in the first peripheral circuit chip and the second peripheral circuit chip, and optimize the circuit layout in the first peripheral circuit chip and the second peripheral circuit chip.

[0119] 7A to 7D is a cross-sectional schematic diagram of an intermediate structure of a three-dimensional memory in a manufacturing process according to another exemplary embodiment of the present application. Figure 5 The manufacturing method 300 shown may also form 7A to 7D The intermediate structure of the three-dimensional memory is shown as well as Figure 4 The three-dimensional memory 200 is shown. 7A to 7D as well as Figure 4 The above steps S310 and S320 are exemplarily described. For the purpose of brevity, the same steps as those in the above embodiments are not described in detail in this application.

[0120] S310 forms a memory array chip and a first peripheral circuit chip bonded to each other, so that a first end of a channel structure in the memory array chip is connected to the first peripheral circuit chip.

[0121] In some implementations, step S310 may include steps S311b to S316b. Steps S311b to S316b are exemplarily described below with reference to the accompanying drawings.

[0122] S311b: forming a second word line contact hole in the connection region from the first side of the initial stack structure, extending to a target sacrificial layer among the plurality of sacrificial layers in the initial stack structure.

[0123] In step S311b, if Fig. 7A As shown, the initial stacking structure (not shown) may be formed on one side of the third substrate 235. For example, the third substrate 235 may be a composite substrate having a multilayer structure. The portion of the initial stacking structure located in the second region B2 of the connection region B includes a plurality of dielectric layers 2311 and a plurality of sacrificial layers 2313 that are alternately stacked. For example, a photolithography and etching (e.g., dry etching or wet etching) process may be used to form a second word line contact hole in the second region B2 of the connection region B from a side (first side) of the initial stacking structure that is away from the third substrate 235. For example, the second word line contact hole corresponds to Fig. 7A The outer contour of the first word line contact portion 2331 is shown. The second word line contact hole may extend in the z direction and extend to one sacrificial layer (the target sacrificial layer corresponding to the second word line contact hole) among the plurality of sacrificial layers 2313 to expose the corresponding sacrificial layer 2313 .

[0124] It should be noted that since the second word line contact hole is formed by etching the initial stack structure from the first side of the initial stack structure, limited by the etching process, the cross-sectional size (e.g., diameter) of the second word line contact hole on a plane perpendicular to the z direction gradually decreases along the positive z direction.

[0125] S312b utilizes the second word line contact hole to replace at least a portion of the target sacrificial layer with a portion of the target gate layer to form a stacked structure.

[0126] In step S312b, if Fig. 7A As shown, since the second word line contact hole exposes its corresponding sacrificial layer 2313, the second word line contact hole can be used to remove at least a portion of its corresponding sacrificial layer by, for example, a wet etching process to form a gap. The gap can expose the gate layer (the gate layer can be a target gate layer) that is located in the same layer as the sacrificial layer 2313 and located in the first region B1. Optionally, a thin film deposition process can be used to form an insulating layer on the sidewall of the second word line contact hole to protect other dielectric layers 2311 and other sacrificial layers 2313 exposed by the sidewall of the second word line contact hole.

[0127] Further, in some examples, a thin film deposition process may be used to fill the gap with a conductive material as part of the gate layer 2312. In another exemplary embodiment, a high dielectric constant layer, an adhesion layer, and a conductive layer may be sequentially formed in the gap as part of the gate layer 2312 using a thin film deposition process.

[0128] After the above process, Fig. 7A As shown, the initial stacking structure can be converted into a stacking structure 231. The stacking structure 231 is located in the array area A, the first area B1 (reference Figure 2 ) and a portion of the second area B2 include multiple dielectric layers 2311 and multiple gate layers 2312 stacked alternately, and a portion of the stacked structure 231 located in another portion of the second area B2 includes multiple dielectric layers 2311 and multiple sacrificial layers 2313 stacked alternately.

[0129] S313b forms a conductive filling in the second word line contact hole to form a first word line contact portion.

[0130] In step S313b, if Fig. 7A As shown, a thin film deposition process such as CVD, PVD, ALD or any combination thereof may be used to form a conductive filler in the second word line contact hole to form the first word line contact portion 2331. For example, in the case where an insulating layer is formed on the sidewall of the second word line contact hole, a thin film deposition process may be used to form a conductive filler in the space surrounded by the insulating layer.

[0131] It should be noted that the multiple first word line contact portions 2331 extend to the corresponding multiple gate layers 2312 in the second region B2 of the connection area B, and the heights of the multiple gate layers in the stacking direction are different from each other, thereby leading out the multiple gate layers 2312 in the stacking structure 231.

[0132] S314b forms a bit line connected to the channel structure on the first side of the stack structure, thereby forming an initial memory array chip.

[0133] In step S314b, as shown in FIG. 7 , the channel structure 232 may penetrate the stacked structure 231 and extend into the third substrate 235. After forming the first word line contact portion 2331, a channel plug (see FIG. 20 ) may be formed on the first side of the stacked structure 231 by using a photolithography and etching process and a thin film deposition process to connect the channel structure 232. Figure 3 The trench plug 1325 is shown connected to the trench contact 237.

[0134] Further, a bit line (not shown) connected to the channel contact 237 may be formed on a first side of the stacked structure 231 (e.g., a side of the channel contact 237 away from the stacked structure 231) by using a photolithography and etching process and a thin film deposition process. In other words, the bit line is connected to a first end (e.g., a drain end) of the channel structure 232 through the channel contact 237. For example, the first ends (e.g., drain ends) of a plurality of channel structures 232 arranged along the y direction are connected to the same bit line.

[0135] In some embodiments, a third interconnect layer (not shown) may be formed on a side of the bit line away from the stacked structure 231 using a photolithography and etching process and a thin film deposition process. For example, the third interconnect layer may include a plurality of interconnect line structures and a plurality of contact via structures. The interconnect line structure may extend laterally in a plane perpendicular to the z direction, and the contact via structure may extend longitudinally in the z direction. The plurality of contact via structures and the plurality of interconnect line structures are alternately arranged in layers in the z direction.

[0136] After the above process, Fig. 7A As shown, an initial memory array chip 230' may be formed.

[0137] S315b bonds the initial memory array chip to the first peripheral circuit chip.

[0138] In step S315b, if Figure 7B As shown, the initial memory array chip 230' and the first peripheral circuit chip 210 may be connected in the z direction, for example, by bonding (e.g., hybrid bonding), thereby forming a first bonding layer 201 between the initial memory array chip 230' and the first peripheral circuit chip 210. Hybrid bonding may perform data transmission between the initial memory array chip 230' and the first peripheral circuit chip 210 through bonding contacts.

[0139] In some embodiments, after bonding the initial memory array chip 230' to the first peripheral circuit chip 210, the manufacturing method 300 may further include a step of forming a common semiconductor layer 234. Figure 7B and 7C As shown, first, the third substrate 235 and the functional layer extending from the channel structure 232 to the third substrate 235 can be removed by CMP and / or wet etching process (refer to Figure 3 The functional layer 1326 shown is used to make the channel layer (refer to Figure 3 Then, a thin film deposition process such as CVD, PVD, ALD or any combination thereof may be used to form a channel layer (see FIG. 14 ) in the portion of the stacked structure 231 located in the array region A. Figure 3The channel layer 1324 is shown as a common semiconductor layer 234 connected to the stack structure 231. An insulating cap layer 238 is formed on the portion of the stack structure 231 located in the connection region B.

[0140] S316b forms a second word line contact extending to the target gate layer from a side of the stack structure away from the first peripheral circuit chip, so that the first word line contact and the second word line contact form a word line contact structure.

[0141] In step S316, Fig.7D As shown, in some embodiments, an etching (e.g., wet etching or dry etching) process may be first used to form a third word line contact hole extending to the corresponding gate layer 2312 from the side of the stacked structure 231 away from the first peripheral circuit chip 210. For example, the third word line contact hole corresponds to Fig.7D The outer contour of the second word line contact 2332 is shown. Then, a thin film deposition process such as CVD, PVD, ALD or any combination thereof may be used to form a conductive filler in the third word line contact hole to form the second word line contact 2332. Among them, the first word line contact 2331 and the second word line contact 2332 together constitute the word line contact structure 233. The material of the conductive filler in the third word line contact hole may include, but is not limited to, tungsten, cobalt, copper, aluminum, polysilicon, titanium, titanium nitride or any other suitable conductive material. Optionally, the central axis of the first word line contact 2331 and the central axis of the second word line contact 2332 are at least partially aligned, so that the gate layer 2312 can be led out along the negative z direction and the positive z direction respectively through the first word line contact 2331 and the second word line contact 2332. For example, the positive z direction is the stacking direction of the first peripheral circuit chip 210 toward the memory array chip 230, and the negative z direction is the stacking direction of the memory array chip 230 toward the first peripheral circuit chip 210.

[0142] It should be noted that since the third word line contact hole is formed by etching the stack structure 231 from the side of the stack structure 231 away from the first peripheral circuit chip 210, due to the limitations of the etching process, the cross-sectional size (for example, diameter) of the third word line contact hole on a plane perpendicular to the z direction gradually increases along the positive z direction.

[0143] In some embodiments, in the step of forming the third word line contact hole from the side of the stacked structure 231 away from the first peripheral circuit chip 210, the gate layer can be used as an etching stop layer for the third word line contact hole, and in the same etching process, the stacked structure 231 can be etched from the side of the stacked structure 231 away from the first peripheral circuit chip 210 to the multiple gate layers 2312 to form multiple third word line contact holes. For example, multiple third word line contact holes can be formed in the same etching process by designing a mask pattern, which is conducive to simplifying the process and improving manufacturing efficiency.

[0144] According to the manufacturing method of the three-dimensional memory of the embodiment of the present application, the word line contact structure composed of the first word line contact portion and the second word line contact portion can be connected to the first peripheral circuit chip and the second peripheral circuit chip from two opposite directions, further improving the layout flexibility of the circuits in the first peripheral circuit chip and the second peripheral circuit chip. At the same time, the word line contact structure can play the role of a through contact structure, which is beneficial to reduce the number of through contact structures required as a whole, which is conducive to reducing the plane size of the three-dimensional memory and reducing the difficulty of back-end winding.

[0145] Some embodiments of the present application also provide a memory system. Fig. 9 is a block diagram of a system 10 having a memory system 12 according to an exemplary embodiment of the present application.

[0146] The system 10 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a car computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device (the electronic device having the memory system 12 located therein). Fig. 9 As shown, the system 10 may include a host 18 and a memory system 12, the memory system 12 having one or more three-dimensional memories 14 and a controller 16. The host 18 may be a processor of an electronic device, such as a central processing unit (CPU), or may be a system-on-chip (SoC), such as an application processor (AP). The host 18 may be configured to send or receive data to or from the three-dimensional memory 14.

[0147] The three-dimensional memory 14 may include the three-dimensional memory described in any embodiment of the present application, for example, Figures 1 to 3 The three-dimensional memory 100 or Figure 43D memory 200 is shown. According to some embodiments, the controller 16 is coupled to the 3D memory 14 and the host 18, and is configured to control the 3D memory 14. The controller 16 can manage data stored in the 3D memory 14 and communicate with the host 18. In some embodiments, the controller 16 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact Flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the controller 16 is designed to operate in a high duty cycle environment, such as an SSD or an embedded multi-media-card (eMMC) used as a data storage device for mobile devices, and an enterprise storage array, and the mobile device is a smart phone, a tablet computer, a laptop computer, etc. The controller 16 can be configured to control the operation of the 3D memory 14, such as read, erase, and program operations. The controller 16 may also be configured to manage various functions related to data stored in or to be stored in the three-dimensional memory 14, including but not limited to bad block management, garbage collection, logical to physical address conversion, wear leveling, etc. In some embodiments, the controller 16 is further configured to process error correction code (ECC) related to data read from or written to the three-dimensional memory 14. Any other appropriate functions may also be performed by the controller 16, for example, formatting the three-dimensional memory 14. The controller 16 may communicate with an external device (e.g., a host 18) according to a specific communication protocol. For example, the controller 16 may communicate with an external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a high-speed PCI (PCI-express, PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, etc.

[0148] The controller 16 and the one or more three-dimensional memories 14 may be integrated into various types of memory systems, for example, included in the same package (such as a universal flash storage (UFS) package or an eMMC package). That is, the memory system 12 may be implemented and packaged into different types of final electronic products. Fig. 10AIn one example shown in FIG, the controller 16 and the single three-dimensional memory 14 may be integrated into a memory card 22. The memory card 22 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 22 may further include a memory card 22 that connects to a host (e.g., Fig. 9 The memory card connector 24 is coupled to the host 18 in the embodiment. Fig. 10B In another example shown in FIG. 1 , the controller 16 and the plurality of three-dimensional memories 14 may be integrated into the SSD 26. The SSD 26 may further include a processor that connects the SSD 26 to a host (e.g., Fig. 9 In some embodiments, the storage capacity and / or operating speed of the SSD 26 is higher than the storage capacity and / or operating speed of the memory card 22.

[0149] The above description is only an implementation method of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of protection involved in the present application is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the technical concept. For example, the above features are replaced with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A three-dimensional memory, characterized in that: include: a first peripheral circuit chip; A memory array chip bonded to the first peripheral circuit chip; A second peripheral circuit chip is bonded to the memory array chip on a side of the memory array chip away from the first peripheral circuit chip; Wherein, the storage array chip comprises: Stacked structure; a channel structure, penetrating the stacked structure, wherein the first end of the channel structure close to the first peripheral circuit chip is connected to the first peripheral circuit chip; and A word line contact structure at least partially penetrates the stack structure, and the word line contact structure is connected to the second peripheral circuit chip near the second end of the second peripheral circuit chip.

2. The three-dimensional memory according to claim 1, wherein: The memory array chip further includes a bit line, and the bit line is located at a side of the stack structure close to the first peripheral circuit chip, and the first end of the channel structure is connected to the first peripheral circuit chip through the bit line.

3. The three-dimensional memory according to claim 1, wherein: The first peripheral circuit chip includes a page buffer, and the second peripheral circuit chip includes a word line driver.

4. The three-dimensional memory according to claim 1, wherein: The stack structure includes a plurality of dielectric layers and a plurality of gate layers alternately stacked, and the word line contact structure extends from a side of the stack structure close to the second peripheral circuit chip to a target gate layer among the plurality of gate layers.

5. The three-dimensional memory according to claim 4, wherein: The cross-sectional dimension of the word line contact structure in a direction perpendicular to a first direction gradually increases along the first direction, wherein the first direction is a stacking direction from the first peripheral circuit chip toward the second peripheral circuit chip.

6. The three-dimensional memory according to claim 1, wherein: The stacked structure includes a plurality of dielectric layers and a plurality of gate layers alternately stacked, and each of the word line contact structures includes a first word line contact portion and a second word line contact portion, wherein the first word line contact portion extends from a side of the stacked structure close to the first peripheral circuit chip to a target gate layer among the plurality of gate layers, and the second word line contact portion extends from a side of the stacked structure close to the second peripheral circuit chip to the target gate layer.

7. The three-dimensional memory according to claim 6, wherein: The cross-sectional dimension of the first word line contact portion in a direction perpendicular to a first direction gradually decreases along the first direction, and the cross-sectional dimension of the second word line contact portion in a direction perpendicular to the first direction gradually increases along the first direction, wherein the first direction is the stacking direction of the first peripheral circuit chip toward the second peripheral circuit chip.

8. The three-dimensional memory according to claim 7, wherein: A contact area between the second word line contact portion and the target gate layer is smaller than a contact area between the first word line contact portion and the target gate layer.

9. The three-dimensional memory according to any one of claims 1 to 8, wherein: The memory array chip further comprises a common semiconductor layer, which is located on a side of the stacked structure close to the second peripheral circuit chip, and the second ends of the plurality of channel structures are connected to the second peripheral circuit chip through the common semiconductor layer.

10. The three-dimensional memory according to any one of claims 1 to 8, wherein: The word line contact structure includes a conductive filler and an insulating layer, wherein the insulating layer at least partially surrounds an outer sidewall of the conductive filler.

11. The three-dimensional memory according to any one of claims 4 to 8, wherein: The stacking structure includes an array area and a connection area, the gate layer extends in the array area and at least part of the connection area, a plurality of word line contact structures at least partially penetrate the stacking structure in the connection area and are connected to respective corresponding plurality of target gate layers, and the heights of the plurality of target gate layers in the stacking direction are different from each other.

12. A memory system, characterized in that: include: The three-dimensional memory as claimed in any one of claims 1 to 11; The controller is coupled to the three-dimensional memory to control the three-dimensional memory to store data.

13. A method for manufacturing a three-dimensional memory, characterized in that: include: forming a memory array chip and a first peripheral circuit chip bonded to each other, so that a first end of a channel structure in the memory array chip is connected to the first peripheral circuit chip; as well as The second peripheral circuit chip is bonded to the memory array chip so that the word line contact structure in the memory array chip is close to the second end of the second peripheral circuit chip and is connected to the second peripheral circuit chip.

14. The manufacturing method according to claim 13, wherein: The method further comprises: forming the first peripheral circuit chip having a page buffer; and The second peripheral circuit chip is formed to have a word line driver.

15. The manufacturing method according to claim 13, wherein: The memory array chip and the first peripheral circuit chip bonded to each other include: forming a bit line connected to the first end of the channel structure on a first side of an initial stacked structure to form an initial memory array chip, wherein the initial stacked structure comprises an array region and a connection region, the initial stacked structure comprises a plurality of dielectric layers and a plurality of gate layers alternately stacked in the array region, and comprises a plurality of dielectric layers and a plurality of sacrificial layers alternately stacked in the connection region, and the channel structure penetrates the initial stacked structure in the array region; and The initial memory array chip is bonded to the first peripheral circuit chip.

16. The manufacturing method according to claim 15, wherein: After bonding the initial memory array chip to the first peripheral circuit chip, the method further comprises: forming a first word line contact hole extending from a side of the initial stack structure away from the first peripheral circuit chip in the connection region to a target sacrificial layer among the plurality of sacrificial layers in the initial stack structure; replacing at least a portion of the target sacrificial layer with a portion of the target gate layer by using the first word line contact hole to form the stacked structure; and A conductive filler is formed in the first word line contact hole to form the word line contact structure, thereby forming the memory array chip.

17. The manufacturing method according to claim 16, wherein: The multiple word line contact structures extend in the connection region to the multiple corresponding target gate layers respectively, and the heights of the multiple target gate layers in the stacking direction are different from each other.

18. The manufacturing method according to claim 15, wherein: Forming a bit line connected to the channel structure on a first side of the initial stack structure to form an initial memory array chip includes: forming, from the first side of the initial stack structure, in the connection region, a second word line contact hole extending to a target sacrificial layer among the plurality of sacrificial layers in the initial stack structure; replacing at least a portion of the target sacrificial layer with a portion of the target gate layer by using the second word line contact hole to form the stacked structure; forming a conductive filler in the second word line contact hole to form a first word line contact portion; forming a bit line connected to the channel structure on the first side of the stack structure, thereby forming the initial memory array chip; After bonding the initial memory array chip to the first peripheral circuit chip, the method further comprises: A second word line contact portion extending to the target gate layer is formed from a side of the stack structure away from the first peripheral circuit chip, so that the first word line contact portion and the second word line contact portion form the word line contact structure.

19. The manufacturing method according to claim 18, wherein: Forming a second word line contact extending to the target gate layer from a side of the stack structure away from the first peripheral circuit chip comprises: forming a third word line contact hole extending to the target gate layer from a side of the stack structure away from the first peripheral circuit chip; and A conductive filler is formed in the third word line contact hole to form the second word line contact portion.

20. The manufacturing method according to claim 18, wherein: The plurality of second word line contact portions extend in the connection region to the plurality of target gate layers corresponding to the respective ones, and the plurality of target gate layers have different heights from each other in the stacking direction. Wherein, forming a third word line contact hole extending to the target gate layer from a side of the stack structure away from the first peripheral circuit chip comprises: In the same process, the stacked structure is etched to the plurality of target gate layers respectively to form a plurality of the third word line contact holes.

21. The manufacturing method according to claim 18, wherein: A central axis of the first word line contact and a central axis of the second word line contact are at least partially aligned.

22. The manufacturing method according to claim 15, wherein: The initial stacking structure is formed on a substrate, the channel structure extends toward the substrate, and the channel structure includes a functional layer and a channel layer from outside to inside, wherein after forming the initial memory array chip and the first peripheral circuit chip bonded to each other, the method further includes: removing a portion of the substrate and the functional layer; and A common semiconductor layer connected to the channel layers of the plurality of channel structures is formed.

Images