Three-dimensional memory and manufacturing method thereof

Abstract

The invention relates to the technical field of semiconductor manufacturing, in particular to a three-dimensional memory and a manufacturing method thereof. The manufacturing method of the three-dimensional memory comprises the following steps of forming a substrate, wherein the substrate comprises a substrate, a first dielectric layer located on the substrate and a first contact structure penetrating through the first dielectric layer; forming a storage hole which at least exposes the side wall of the first contact structure in the first dielectric layer; forming a storage structure which at least continuously covers the inner wall of the storage hole, the side wall of the first contact structure and the top surface of the first contact structure, wherein the storage structure is electrically connected with the first contact structure in a contact manner; forming a conductive filling layer which fills the storage hole and covers the surface of the storage structure, wherein the conductive filling layer is electrically connected with the storage structure; and forming a first lead-out structure which is positioned above the substrate and is electrically connected with the conductive filling layer. According to the invention, the area of the storage structure is increased, and the size of the three-dimensional memory can be reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a three-dimensional memory and a manufacturing method thereof. Background Art

[0002] Phase change memory or ferroelectric memory (FeRAM) and other memories are devices that integrate memory cells (Cells) in the back-end process (BEOL for short), which is a structure in which the memory cell is inserted between two adjacent metal layers. The memory cell is generally composed of an upper and lower electrode layer and a ferroelectric memory layer in the middle. The storage performance of the ferroelectric memory is proportional to the effective area of ​​the ferroelectric memory layer and the electrode layer in the memory cell. The traditional two-dimensional structure memory is composed of a vertically stacked upper electrode layer, a lower electrode layer, and a ferroelectric material layer or a phase change material layer located between the upper electrode layer and the lower electrode layer. However, as the size of the memory continues to shrink, the effective area of ​​the storage structure in the traditional two-dimensional structure memory continues to shrink, thereby limiting the further improvement of the memory performance. Moreover, after the traditional two-dimensional memory forms the storage structure, when a lead-out structure electrically connected to the storage structure is formed above the storage structure, it is easy to cause damage to the storage structure, thereby affecting the performance of the memory.

[0003] Therefore, how to increase the effective area of ​​the storage structure while reducing the damage to the storage structure when forming the lead-out structure, thereby improving the performance and manufacturing yield of the memory, is a technical problem that needs to be solved urgently. Summary of the invention

[0004] The present invention provides a three-dimensional memory and a manufacturing method thereof, which are used to increase the effective area of ​​the memory structure while reducing the damage to the memory structure when forming a lead-out structure, thereby improving the performance and manufacturing yield of the memory.

[0005] According to some embodiments, the present invention provides a method for manufacturing a three-dimensional memory, comprising the following steps:

[0006] Forming a substrate, the substrate comprising a substrate, a first dielectric layer located on the substrate, and a first contact structure penetrating the first dielectric layer along a first direction, the substrate comprising a top surface and a bottom surface that are relatively distributed, and the first direction perpendicularly intersects with the top surface of the substrate;

[0007] forming a storage hole in the first dielectric layer to expose at least a side wall of the first contact structure;

[0008] forming a storage structure that continuously covers at least the inner wall of the storage hole, the side wall of the first contact structure and the top surface of the first contact structure, and the storage structure is in electrical contact with the first contact structure;

[0009] forming a conductive filling layer that fills the storage hole and covers the surface of the storage structure, wherein the conductive filling layer is electrically connected to the storage structure;

[0010] A first lead-out structure is formed which is located above the substrate and is electrically connected to the conductive filling layer.

[0011] In some embodiments, the specific steps of forming the substrate include:

[0012] Providing a substrate, wherein the substrate includes an active region;

[0013] forming a first dielectric layer on the top surface of the substrate;

[0014] A first contact structure is formed that penetrates the first dielectric layer along a first direction and is electrically connected to the active area in the substrate.

[0015] In some embodiments, the active region includes a channel region and a source region and a drain region located on opposite sides of the channel region along a second direction, wherein the second direction is parallel to the top surface of the substrate; the first contact structure is electrically connected to the drain region, and the substrate further includes a second contact structure that penetrates the first dielectric layer and is electrically connected to the source region; the specific steps of forming a storage hole in the first dielectric layer that exposes at least a sidewall of the first contact structure include:

[0016] forming a second dielectric layer covering the first dielectric layer, the first contact structure and the second contact structure;

[0017] The second dielectric layer and the first dielectric layer are etched to form the storage hole penetrating the second dielectric layer and extending into the first dielectric layer.

[0018] In some embodiments, the specific step of forming a storage hole in the first dielectric layer to expose at least a sidewall of the first contact structure includes:

[0019] The first dielectric layer and the second dielectric layer are etched to form the storage holes symmetrically distributed about the first contact structure.

[0020] In some embodiments, the specific steps of forming a storage structure that continuously covers at least the inner wall of the storage hole, the side wall of the first contact structure, and the top surface of the first contact structure include:

[0021] forming a lower electrode layer that continuously covers the inner wall of the storage hole, the side wall of the first contact structure, the top surface of the first contact structure, and the top surface of the second dielectric layer;

[0022] forming a storage layer covering the lower electrode layer;

[0023] An upper electrode layer covering the storage layer is formed, and the lower electrode layer, the storage layer and the upper electrode layer together constitute the storage structure.

[0024] In some embodiments, after forming the conductive filling layer that fills the storage holes and covers the surface of the storage structure, the following steps are further included:

[0025] The conductive filling layer, the storage structure and the second dielectric layer on the top surface of the first dielectric layer are removed to expose the second contact structure.

[0026] In some embodiments, the specific steps of removing the conductive filling layer, the storage structure and the second dielectric layer on the top surface of the first dielectric layer include:

[0027] forming a third dielectric layer covering the conductive filling layer;

[0028] The third dielectric layer, the conductive filling layer, the storage structure and the second dielectric layer on the top surface of the first dielectric layer are etched to expose the second contact structure.

[0029] In some embodiments, the specific steps of forming a first lead-out structure located above the substrate and electrically connected to the conductive filling layer include:

[0030] forming a fourth dielectric layer covering the top surfaces of the third dielectric layer and the first dielectric layer;

[0031] forming a first lead-out hole that continuously penetrates the fourth dielectric layer and the third dielectric layer and exposes the conductive filling layer, and forming a second lead-out hole that penetrates the fourth dielectric layer and exposes the second contact structure;

[0032] A first lead-out structure is formed to be filled in the first lead-out hole, and a second lead-out structure is formed to be filled in the second lead-out hole.

[0033] According to some other embodiments, the present invention further provides a three-dimensional memory, comprising:

[0034] A base, comprising a substrate, a first dielectric layer located above the substrate, and a first contact structure penetrating the first dielectric layer along a first direction, wherein the substrate comprises a top surface and a bottom surface that are relatively distributed, and the first direction intersects the top surface of the substrate perpendicularly;

[0035] A storage hole, located in the first dielectric layer, wherein the storage hole at least exposes a side wall of the first contact structure;

[0036] a storage structure, continuously covering an inner wall of the storage hole, a side wall of the first contact structure and a top surface of the first contact structure, and the storage structure is electrically connected to the first contact structure;

[0037] A conductive filling layer, which fills the storage hole and covers the surface of the storage structure, and the conductive filling layer is electrically connected to the storage structure;

[0038] The first lead-out structure is located above the substrate and is electrically connected to the conductive filling layer.

[0039] In some embodiments, the storage holes are symmetrically distributed about the first contact structure.

[0040] In some embodiments, the storage structure includes:

[0041] a lower electrode layer, continuously covering an inner wall of the storage hole, a side wall of the first contact structure, and a top surface of the first contact structure;

[0042] A storage layer continuously covers the surface of the lower electrode layer;

[0043] An upper electrode layer continuously covers the surface of the storage layer;

[0044] The conductive filling layer covers the surface of the upper electrode layer, and the top surface of the conductive filling layer is higher than the top surface of the upper electrode layer.

[0045] In some embodiments, the first lead-out structure is located directly above the first contact structure along the first direction.

[0046] The three-dimensional memory and its manufacturing method provided by the present invention, the substrate has a first contact structure penetrating the first dielectric layer, and a storage hole is formed in the first dielectric layer to expose at least the side wall of the first contact structure, and a storage structure is formed to continuously cover at least the inner wall of the storage hole, the side wall of the first contact structure and the top surface of the first contact structure, thereby forming a memory with a three-dimensional structure, which not only increases the area of ​​the storage structure and improves the performance and manufacturing yield of the memory; but also reduces the number of other dielectric layers deposited above the first dielectric layer, thereby helping to further reduce the size of the three-dimensional memory and improve the integration of the three-dimensional memory. At the same time, by forming a conductive filling layer that fills the storage hole and covers the surface of the storage structure, it is possible to avoid damage to the storage structure when the first lead-out structure is subsequently formed, thereby further improving the performance of the three-dimensional memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 is a flow chart of a method for manufacturing a three-dimensional memory in a specific embodiment of the present invention;

[0048] Figure 2 is a schematic structural diagram of a substrate in a specific embodiment of the present invention;

[0049] Figure 3 is a schematic diagram of the structure after the storage hole is formed in a specific embodiment of the present invention;

[0050] Figure 4 is a schematic diagram of the structure after forming a storage structure and a conductive filling layer in a specific embodiment of the present invention;

[0051] Figure 5 is a schematic diagram of the structure after the third dielectric layer is formed in a specific embodiment of the present invention;

[0052] Figure 6 is a schematic diagram of the structure after the conductive filling layer and the storage structure on the top surface of the first dielectric layer are removed in a specific embodiment of the present invention;

[0053] Figure 7 is a schematic diagram of the structure after the fourth dielectric layer is formed in a specific embodiment of the present invention;

[0054] Figure 8 is a schematic diagram of the structure after the first lead-out hole is formed in a specific embodiment of the present invention;

[0055] Fig. 9 is a schematic diagram of a structure after a first lead-out structure is formed in a specific embodiment of the present invention;

[0056] Fig.10 It is a schematic diagram of the structure after a metal interconnection layer located above the first lead-out structure is formed in a specific embodiment of the present invention. DETAILED DESCRIPTION

[0057] The specific implementation of the three-dimensional memory and the manufacturing method thereof provided by the present invention will be described in detail below with reference to the accompanying drawings.

[0058] This specific embodiment provides a method for manufacturing a three-dimensional memory. Figure 1 FIG. 1 is a flow chart of a method for manufacturing a three-dimensional memory in a specific embodiment of the present invention. Figure 1 As shown, the manufacturing method of the three-dimensional memory comprises the following steps:

[0059] Step S11, forming a base, the base comprising a substrate, a first dielectric layer located on the substrate, and a first contact structure penetrating the first dielectric layer along a first direction, the substrate comprising a top surface and a bottom surface that are relatively distributed, and the first direction intersects the top surface of the substrate perpendicularly;

[0060] Step S12, forming a storage hole in the first dielectric layer to expose at least a side wall of the first contact structure;

[0061] Step S13, forming a storage structure that continuously covers at least the inner wall of the storage hole, the side wall of the first contact structure and the top surface of the first contact structure, and the storage structure is in electrical contact with the first contact structure;

[0062] Step S14, forming a conductive filling layer that fills the storage holes and covers the surface of the storage structure, wherein the conductive filling layer is electrically connected to the storage structure;

[0063] Step S15, forming a first lead-out structure located above the substrate and electrically connected to the conductive filling layer.

[0064] Figure 2 Schematic diagram of the structure of the substrate in a specific embodiment of the present invention. Figure 2 As shown, the specific steps of forming the substrate include:

[0065] Providing a substrate 20, wherein the substrate 20 includes an active region;

[0066] forming a first dielectric layer 21 on the top surface of the substrate 20;

[0067] The first contact structure 25 is formed along a first direction D1 and penetrates the first dielectric layer 21 and is electrically connected to the active area in the substrate 20 .

[0068] Figure 3 : is a schematic diagram of a structure after a storage hole is formed in a specific embodiment of the present invention. In some embodiments, the active region includes a channel region and a source region and a drain region located on opposite sides of the channel region along a second direction D2, and the second direction D2 is parallel to the top surface of the substrate 20; the first contact structure 25 is electrically connected to the drain region, and the substrate further includes a second contact structure 26 that penetrates the first dielectric layer 21 and is electrically connected to the source region; the specific steps of forming a storage hole 31 in the first dielectric layer 21 to expose at least the sidewall of the first contact structure 25 include:

[0069] forming a second dielectric layer 30 covering the first dielectric layer 21, the first contact structure 25 and the second contact structure 26;

[0070] The second dielectric layer 30 and the first dielectric layer 21 are etched to form the storage hole 31 penetrating the second dielectric layer 30 and extending into the first dielectric layer 21. Figure 3 shown.

[0071] Specifically, the substrate 20 may be, but is not limited to, a silicon substrate. This specific embodiment is described by taking the substrate 20 as a silicon substrate as an example. The substrate 20 at least includes a plurality of active regions spaced apart along the second direction D2 and a shallow trench isolation region between adjacent active regions. The active region includes a channel region and a source region and a drain region located on opposite sides of the channel region along the second direction D2. The base also includes a gate structure located on the substrate 20, the gate structure including a gate dielectric layer 22 located above the channel region, a gate conductive layer 23 covering the surface of the gate dielectric layer 22, and an isolation sidewall 24 covering the sidewalls of the gate dielectric layer 22 and the sidewalls of the gate conductive layer 23, as shown in FIG. Figure 2 As shown. The first dielectric layer 21 covers the top surface of the substrate 20 and the gate structure. The material of the first dielectric layer 21 can be an oxide material, such as silicon dioxide. In one example, the first contact structure 25 penetrates the first dielectric layer 21 along the first direction D1 and is electrically connected to the drain region, and the second contact structure 26 penetrates the first dielectric layer 21 along the first direction D1 and is electrically connected to the source region. Before etching the first dielectric layer 21 to form the storage hole 31, an insulating material such as silicon oxynitride is deposited on the first dielectric layer 21 to form the second dielectric layer 30 covering the first dielectric layer 21, the first contact structure 25 and the second contact structure 26, and the second dielectric layer 30 is used as a protective layer to avoid damage to the second contact structure 26 and the gate structure during the etching of the storage hole 31.

[0072] After forming the second dielectric layer 30, the second dielectric layer 30 and the first dielectric layer 21 are etched downward from the second dielectric layer 30, so as to form the storage hole 31 penetrating the second dielectric layer 30 and extending into the first dielectric layer 21, and the storage hole 31 does not penetrate the first dielectric layer 21 along the first direction D1. Figure 3 In the process of etching the first dielectric layer 21 , the depth of the storage hole 31 along the first direction D1 can be adjusted by controlling the etching time, thereby avoiding damage to the device structures such as the gate structure in the first dielectric layer 21 and the substrate 20 .

[0073] In this specific embodiment, by forming the storage hole 31 in the first dielectric layer 21 that at least exposes the side wall of the first contact structure 25, on the one hand, the area for subsequently forming the storage structure is increased, thereby increasing the area of ​​the storage structure and improving the electrical performance of the memory; on the other hand, since the storage hole 31 is directly formed in the first dielectric layer 21, the subsequently formed storage structure is located in the first dielectric layer 21, not only a three-dimensional structured memory (i.e., the three-dimensional memory) is formed, but also the thickness of the memory is greatly reduced, which helps to further reduce the size of the memory and further improve the storage density.

[0074] In some embodiments, the specific steps of forming the storage hole 31 in the first dielectric layer 21 to expose at least the sidewall of the first contact structure 25 include:

[0075] The first dielectric layer 21 and the second dielectric layer 30 are etched to form the storage holes 31 symmetrically distributed about the first contact structure 25 .

[0076] Specifically, by making the storage holes 31 distributed around the periphery of the first contact structure 25, and the storage holes 31 symmetrically distributed about the first contact structure 25, on the one hand, the inner wall area of ​​the storage holes 31 can be further increased, thereby further increasing the area of ​​the subsequently formed storage structure, so as to further improve the storage performance of the three-dimensional storage structure; on the other hand, the contact area between the subsequently formed storage structure and the first contact structure 25 can also be increased, thereby further reducing the contact resistance between the storage structure and the first contact structure 25, thereby further improving the electrical performance of the three-dimensional memory.

[0077] Figure 4 3 is a schematic diagram of a structure after forming a storage structure and a conductive filling layer in a specific embodiment of the present invention. In some embodiments, the specific steps of forming a storage structure 40 that continuously covers at least the inner wall of the storage hole 31, the side wall of the first contact structure 25, and the top surface of the first contact structure 25 include:

[0078] forming a lower electrode layer that continuously covers the inner wall of the storage hole 31, the side wall of the first contact structure 25, the top surface of the first contact structure 25, and the top surface of the second dielectric layer 30;

[0079] forming a storage layer covering the lower electrode layer;

[0080] An upper electrode layer covering the storage layer is formed, and the lower electrode layer, the storage layer and the upper electrode layer together constitute the storage structure 40 .

[0081] For example, if Figure 4As shown, after forming the storage hole 31, TiN or other materials are deposited on the substrate to form the lower electrode layer that continuously covers the inner wall of the storage hole 31 (including the side wall and bottom surface of the storage hole 31), the side wall of the first contact structure 25, the top surface of the first contact structure 25 and the top surface of the second dielectric layer 30. Phase change material or ferroelectric material is deposited on the substrate to form a storage layer that continuously covers the lower electrode layer. TiN or other materials are deposited on the substrate again to form an upper electrode layer that continuously covers the storage layer. The lower electrode layer, the storage layer and the upper electrode layer together constitute the storage structure 40. Since the surface used to form the storage structure 40 includes not only the inner wall of the storage hole 31, but also the side wall and top surface of the first contact structure 25, the surface area of ​​the storage structure formed in the storage hole 31 is increased, thereby improving the storage performance of the three-dimensional memory and helping to further reduce the size of the three-dimensional memory. Next, a conductive material such as metal tungsten is deposited on the substrate to form the conductive filling layer 41 that fills the storage hole 31 and continuously covers the surface of the upper electrode layer. The conductive filling layer 41 can not only lead out the signal of the upper electrode layer, increase the process window when the first lead-out structure is subsequently formed, and simplify the formation process of the first lead-out structure, but also avoid damage to the storage structure 40 when the first lead-out hole is formed by an etching process, thereby ensuring the stability of the performance of the storage structure 40.

[0082] Figure 5 is a schematic diagram of the structure after the third dielectric layer is formed in a specific embodiment of the present invention, Figure 6 4 is a schematic diagram of the structure after removing the conductive filling layer and the storage structure on the top surface of the first dielectric layer in a specific embodiment of the present invention. In some embodiments, after forming the conductive filling layer 41 that fills the storage hole 31 and covers the surface of the storage structure 40, the following steps are also included:

[0083] The conductive filling layer 41 , the storage structure 40 and the second dielectric layer 30 on the top surface of the first dielectric layer 21 are removed to expose the second contact structure 26 .

[0084] In some embodiments, the specific steps of removing the conductive filling layer 41, the storage structure 40 and the second dielectric layer 30 on the top surface of the first dielectric layer 21 include:

[0085] forming a third dielectric layer 50 covering the conductive filling layer 41;

[0086] The third dielectric layer 50 , the conductive filling layer 41 , the storage structure 40 and the second dielectric layer 30 on the top surface of the first dielectric layer 21 are etched to expose the second contact structure 26 .

[0087] For example, after forming the conductive filling layer 41, a material such as silicon oxynitride is deposited on the substrate to form the third dielectric layer 50 covering the conductive filling layer 41. A patterned photoresist layer 51 is formed on the third dielectric layer 50, and the photoresist layer 51 has an etching window 52 exposing the third dielectric layer 50, such as Figure 5 The third dielectric layer 50, the conductive filling layer 41, the storage structure 40 and the second dielectric layer 30 are etched downward along the etching window 52 to disconnect the connection between the storage structures 40 in the same layer and expose the second contact structure 26. Figure 6 shown.

[0088] Figure 7 is a schematic diagram of the structure after the fourth dielectric layer is formed in a specific embodiment of the present invention, Figure 8 is a schematic diagram of the structure after the first lead-out hole is formed in a specific embodiment of the present invention, Fig. 9 4 is a schematic diagram of a structure after forming the first lead-out structure in a specific embodiment of the present invention. In some embodiments, the specific steps of forming the first lead-out structure 90 located above the substrate and electrically connected to the conductive filling layer 41 include:

[0089] forming a fourth dielectric layer covering the top surfaces of the third dielectric layer 50 and the first dielectric layer 21;

[0090] A first lead hole 80 is formed to continuously penetrate the fourth dielectric layer and the third dielectric layer 50 and expose the conductive filling layer 41, and a second lead hole 81 is formed to penetrate the fourth dielectric layer and expose the second contact structure 26. Figure 8 As shown;

[0091] A first lead-out structure 90 is formed to be filled in the first lead-out hole 80, and a second lead-out structure 91 is formed to be filled in the second lead-out hole 81. Fig. 9 shown.

[0092] Fig.10is a schematic diagram of the structure after forming a metal interconnection layer located above the first lead-out structure in a specific embodiment of the present invention. For example, a material such as silicon nitride is deposited on the substrate to form a first sub-isolation layer 70 that continuously covers the top surface of the first dielectric layer 21, the remaining sidewalls of the second dielectric layer 30, the remaining sidewalls of the storage structure 40, the remaining sidewalls of the conductive filling layer 41, and the remaining sidewalls and top surface of the third dielectric layer 50. A material such as oxide (such as silicon dioxide) is deposited on the first sub-isolation layer 70 to form a second sub-isolation layer 71, and the first sub-isolation layer 70 and the second sub-isolation layer 71 are used together as the fourth dielectric layer. Thereafter, a mask layer 72 is formed on the second sub-isolation layer 71, as shown in FIG. Figure 7 The mask layer 72, the fourth dielectric layer and the third dielectric layer 50 are etched to form a first lead-out hole 80 that continuously penetrates the fourth dielectric layer and the third dielectric layer 50 and exposes the conductive filling layer 41. At the same time, the mask layer 72 and the fourth dielectric layer are etched to form a second lead-out hole 81 that penetrates the fourth dielectric layer and exposes the second contact structure 26, as shown. Figure 8 As shown. Since the conductive filling layer 41 is used as an etching stop layer during the formation of the first lead-out hole 80, damage to the storage structure 40 during the etching process is avoided. Moreover, by forming the storage structure 40 in the first dielectric layer 21, the thickness of the dielectric layer deposited above the first dielectric layer 21 is reduced, thereby reducing the etching depth of the first lead-out hole 80 and the second lead-out hole 81, thereby simplifying the manufacturing process of the three-dimensional memory. A conductive material such as metal tungsten is filled in the first lead-out hole 80 and the second lead-out hole 81 to form the first lead-out structure 90 electrically connected to the conductive filling layer 41 and the second lead-out structure 91 electrically connected to the second contact structure 26, as shown. Fig. 9 Conductive materials such as metal are deposited on the fourth dielectric layer to form a first conductive connection pad 100 electrically connected to the first lead-out structure 90 and a second conductive connection pad 101 electrically connected to the second lead-out structure 91, so as to form a metal interconnection layer including the first conductive connection pad 100 and the second conductive connection pad 101, as shown. Fig.10 shown.

[0093] This specific embodiment also provides a three-dimensional memory. The three-dimensional memory provided in this specific embodiment can be used as follows Figure 1-Figure 10 The manufacturing method of the three-dimensional memory is formed, and the structural schematic diagram of the three-dimensional memory can be seen in Fig.10 .like Fig.10 As shown, the three-dimensional memory comprises:

[0094] A base, comprising a substrate 20, a first dielectric layer 21 located above the substrate 20, and a first contact structure 25 penetrating the first dielectric layer 21 along a first direction D1, wherein the substrate 20 comprises a top surface and a bottom surface that are relatively distributed, and the first direction D1 intersects the top surface of the substrate 20 vertically;

[0095] A storage hole 31, located in the first dielectric layer 21, wherein the storage hole 31 at least exposes a side wall of the first contact structure 25;

[0096] a storage structure 40, which continuously covers the inner wall of the storage hole 31, the side wall of the first contact structure 25 and the top surface of the first contact structure 25, and the storage structure 40 is electrically connected to the first contact structure 25;

[0097] A conductive filling layer 41, which fills the storage hole 31 and covers the surface of the storage structure 40, and the conductive filling layer 41 is electrically connected to the storage structure 40;

[0098] The first lead-out structure 90 is located above the substrate and is electrically connected to the conductive filling layer 41 .

[0099] Specifically, by forming the storage hole 31 in the first dielectric layer 21 to expose at least the sidewall of the first contact structure 25, on the one hand, the area for subsequently forming the storage structure is increased, thereby increasing the area of ​​the storage structure, and improving the electrical performance of the memory; on the other hand, since the storage hole 31 is directly formed in the first dielectric layer 21, the storage structure formed subsequently is located in the first dielectric layer 21, not only a three-dimensional memory (i.e., the three-dimensional memory) is formed, but also the thickness of the memory is greatly reduced, which is conducive to further reducing the size of the memory and further improving the storage density. At the same time, by forming the conductive filling layer 41 that fills the storage hole 31 and covers the storage structure 40, the first lead structure 90 is electrically connected to the conductive filling layer 41, thereby increasing the process window for forming the first lead structure 90, and avoiding damage to the storage structure 40 during the process of forming the first lead structure 90, further ensuring the stability of the performance of the three-dimensional memory.

[0100] In some embodiments, the storage holes 31 are symmetrically distributed about the first contact structure 25 .

[0101] Specifically, by making the storage holes 31 distributed around the periphery of the first contact structure 25, and the storage holes 31 distributed symmetrically about the first contact structure 25, on the one hand, the inner wall area of ​​the storage holes 31 can be further increased, thereby further increasing the area of ​​the storage structure 40, so as to further improve the storage performance of the three-dimensional storage structure; on the other hand, the contact area between the storage structure 40 and the first contact structure 25 can also be increased, thereby further reducing the contact resistance between the storage structure and the first contact structure 25, and further improving the electrical performance of the three-dimensional memory.

[0102] In some embodiments, the storage structure 40 includes:

[0103] A lower electrode layer continuously covers the inner wall of the storage hole 31, the side wall of the first contact structure 25, and the top surface of the first contact structure 25;

[0104] A storage layer continuously covers the surface of the lower electrode layer;

[0105] An upper electrode layer continuously covers the surface of the storage layer;

[0106] The conductive filling layer 41 covers the surface of the upper electrode layer, and the top surface of the conductive filling layer 41 is higher than the top surface of the upper electrode layer, so as to fully physically isolate the storage structure 40 from the first lead-out structure 90 through the conductive filling layer 41, and further avoid the process of forming the first lead-out structure 90 from causing damage to the storage structure 40.

[0107] In some embodiments, the first lead-out structure 90 is located directly above the first contact structure 25 along the first direction D1, so that the first lead-out structure 90 can be formed using a mask for forming the first contact structure 25, which helps to further reduce the manufacturing cost of the three-dimensional memory.

[0108] The three-dimensional memory and its manufacturing method provided in this specific embodiment, the substrate has a first contact structure that penetrates the first dielectric layer, and a storage hole that at least exposes the side wall of the first contact structure is formed in the first dielectric layer, and a storage structure that at least continuously covers the inner wall of the storage hole, the side wall of the first contact structure and the top surface of the first contact structure is formed, thereby forming a memory with a three-dimensional structure, which not only increases the area of ​​the storage structure and improves the performance and manufacturing yield of the memory; but also reduces the number of other dielectric layers deposited above the first dielectric layer, thereby helping to further reduce the size of the three-dimensional memory and improve the integration of the three-dimensional memory. At the same time, by forming a conductive filling layer that fills the storage hole and covers the surface of the storage structure, it is possible to avoid damage to the storage structure when the first lead-out structure is subsequently formed, thereby further improving the performance of the three-dimensional memory.

[0109] The above is only a preferred embodiment of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A method for manufacturing a three-dimensional memory, characterized in that: The steps include: Forming a substrate, the substrate comprising a substrate, a first dielectric layer located on the substrate, and a first contact structure penetrating the first dielectric layer along a first direction, the substrate comprising a top surface and a bottom surface that are relatively distributed, and the first direction perpendicularly intersects with the top surface of the substrate; forming a storage hole in the first dielectric layer to expose at least a side wall of the first contact structure; forming a storage structure that continuously covers at least the inner wall of the storage hole, the side wall of the first contact structure and the top surface of the first contact structure, and the storage structure is in electrical contact with the first contact structure; forming a conductive filling layer that fills the storage hole and covers the surface of the storage structure, wherein the conductive filling layer is electrically connected to the storage structure; A first lead-out structure is formed which is located above the substrate and is electrically connected to the conductive filling layer.

2. The method for manufacturing a three-dimensional memory according to claim 1, characterized in that: The specific steps of forming the substrate include: Providing a substrate, wherein the substrate includes an active region; forming a first dielectric layer on the top surface of the substrate; A first contact structure is formed that penetrates the first dielectric layer along a first direction and is electrically connected to the active area in the substrate.

3. The method for manufacturing a three-dimensional memory according to claim 2, characterized in that: The active region includes a channel region and a source region and a drain region located on opposite sides of the channel region along a second direction, wherein the second direction is parallel to the top surface of the substrate; the first contact structure is electrically connected to the drain region, and the substrate further includes a second contact structure that penetrates the first dielectric layer and is electrically connected to the source region; The specific steps of forming a storage hole in the first dielectric layer to expose at least the sidewall of the first contact structure include: forming a second dielectric layer covering the first dielectric layer, the first contact structure and the second contact structure; The second dielectric layer and the first dielectric layer are etched to form the storage hole penetrating the second dielectric layer and extending into the first dielectric layer.

4. The method for manufacturing a three-dimensional memory according to claim 3, characterized in that: The specific steps of forming a storage hole in the first dielectric layer to expose at least the sidewall of the first contact structure include: The first dielectric layer and the second dielectric layer are etched to form the storage holes symmetrically distributed about the first contact structure.

5. The method for manufacturing a three-dimensional memory according to claim 4, characterized in that: The specific steps of forming a storage structure that continuously covers at least the inner wall of the storage hole, the side wall of the first contact structure, and the top surface of the first contact structure include: forming a lower electrode layer that continuously covers the inner wall of the storage hole, the side wall of the first contact structure, the top surface of the first contact structure, and the top surface of the second dielectric layer; forming a storage layer covering the lower electrode layer; An upper electrode layer covering the storage layer is formed, and the lower electrode layer, the storage layer and the upper electrode layer together constitute the storage structure.

6. The method for manufacturing a three-dimensional memory according to claim 5, characterized in that: After forming a conductive filling layer that fills the storage holes and covers the surface of the storage structure, the following steps are also included: The conductive filling layer, the storage structure and the second dielectric layer on the top surface of the first dielectric layer are removed to expose the second contact structure.

7. The method for manufacturing a three-dimensional memory according to claim 6, characterized in that: The specific steps of removing the conductive filling layer, the storage structure and the second dielectric layer on the top surface of the first dielectric layer include: forming a third dielectric layer covering the conductive filling layer; The third dielectric layer, the conductive filling layer, the storage structure and the second dielectric layer on the top surface of the first dielectric layer are etched to expose the second contact structure.

8. The method for manufacturing a three-dimensional memory according to claim 7, characterized in that: The specific steps of forming a first lead-out structure located above the substrate and electrically connected to the conductive filling layer include: forming a fourth dielectric layer covering the top surfaces of the third dielectric layer and the first dielectric layer; forming a first lead-out hole that continuously penetrates the fourth dielectric layer and the third dielectric layer and exposes the conductive filling layer, and forming a second lead-out hole that penetrates the fourth dielectric layer and exposes the second contact structure; A first lead-out structure is formed to be filled in the first lead-out hole, and a second lead-out structure is formed to be filled in the second lead-out hole.

9. A three-dimensional memory, characterized in that: include: A base, comprising a substrate, a first dielectric layer located above the substrate, and a first contact structure penetrating the first dielectric layer along a first direction, wherein the substrate comprises a top surface and a bottom surface that are relatively distributed, and the first direction intersects the top surface of the substrate perpendicularly; A storage hole, located in the first dielectric layer, wherein the storage hole at least exposes a side wall of the first contact structure; a storage structure, continuously covering an inner wall of the storage hole, a side wall of the first contact structure and a top surface of the first contact structure, and the storage structure is electrically connected to the first contact structure; A conductive filling layer, which fills the storage hole and covers the surface of the storage structure, and the conductive filling layer is electrically connected to the storage structure; The first lead-out structure is located above the substrate and is electrically connected to the conductive filling layer.

10. The three-dimensional memory according to claim 9, characterized in that: The storage holes are symmetrically distributed about the first contact structure.

11. The three-dimensional memory according to claim 9, characterized in that: The storage structure includes: a lower electrode layer, continuously covering an inner wall of the storage hole, a side wall of the first contact structure, and a top surface of the first contact structure; A storage layer continuously covers the surface of the lower electrode layer; An upper electrode layer continuously covers the surface of the storage layer; The conductive filling layer covers the surface of the upper electrode layer, and the top surface of the conductive filling layer is higher than the top surface of the upper electrode layer.

12. The three-dimensional memory according to claim 9, characterized in that: The first lead-out structure is located directly above the first contact structure along the first direction.

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