Semiconductor device and method for manufacturing the same

Abstract

The present invention discloses a semiconductor device and a preparation method thereof, which relates to the field of semiconductor technology. The semiconductor device includes a substrate; a semiconductor epitaxial layer, located on one side of the substrate; a gate structure, including a first conductive type cap layer, a second conductive type cap layer and a gate electrode stacked in sequence; a field stop layer, located in the second conductive type cap layer and / or interspersed on the surface of the second conductive type cap layer away from the semiconductor epitaxial layer; wherein the vertical projection of the field stop layer on the substrate is smaller than the vertical projection of the second conductive type cap layer on the substrate; the conductive type of the field stop layer is the second conductive type, and the concentration of the second conductive type doped ions in the field stop layer is greater than the concentration of the second conductive type doped ions in the second conductive type cap layer. The technical solution provided by the present invention improves the gate electric field distribution, improves the reliability of the gate structure and reduces the channel resistance.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor technology, and in particular to a semiconductor device and a method for manufacturing the same. Background Art

[0002] Nitride-based semiconductor devices utilize a heterojunction interface between two materials having different band gaps to form a quantum well-type structure that accommodates a two-dimensional electron gas region, thereby meeting the needs of high power / frequency devices.

[0003] Still, there are some reliability issues that warrant attention. Figure 1 It is a schematic diagram of the structure of a semiconductor device provided in the related art, referring to Figure 1 In the related art, the semiconductor device includes a semiconductor epitaxial layer 2 and a gate structure arranged on the side of the semiconductor epitaxial layer 2 away from the substrate 1. The operation of the semiconductor device is controlled by the gate voltage applied to the gate structure, and the gate voltage controls the on and off of the channel. The voltage applied between the source and the drain can drive the 2DEG to flow. When the semiconductor device is an enhancement-mode HEMT device (i.e., an E-mode enhancement-mode HEMT), the gate structure includes a P-type doped layer 3 (e.g., a pGaN layer) and a gate electrode 4, and the holes in the P-type doped layer 3 are used to deplete the 2DEG in the channel below to achieve a normally closed state. The device with this structure has the following problems when working. When a higher positive voltage is applied to the gate electrode 4, the top area of ​​the P-type doped layer 3 has a higher electric field. As the gate voltage further increases, most of the increased voltage falls on the Schottky junction. There is a high electric field at the Schottky interface. After long-term high gate voltage stress, the Schottky will degenerate, resulting in a series of reliability problems.

[0004] In order to solve the above problems, the related art sets the gate structure as a composite structure including a P-type doping layer, an N-type doping layer and a gate electrode. Figure 1 A uniformly doped N-type doping layer (e.g., nGaN layer) is introduced between the P-type doping layer 3 and the gate electrode 4 of the HEMT device shown. At this time, the N-type doping layer and the gate electrode are in direct contact, thereby eliminating the Schottky junction. This patented technical solution will bring some new other problems, such as the concentration and thickness of the N-type doping layer need to be compromised. Figure 2 An electric field distribution diagram of a gate structure provided in the related art, the z axis represents the electric field intensity, refer to Figure 2 , a high breakdown voltage requires a low ion doping concentration in the N-type doping layer 5, but in this case a very thick cap layer (P-type doping layer 3 and N-type doping layer 5) is required to achieve the cutoff of the electric field. A thicker cap layer will increase the channel resistance and sacrifice the conduction performance of the device. Figure 3 Another electric field distribution diagram of a gate structure provided in the related art, refer to Figure 3If the ion doping concentration of the N-type doping layer 5 is directly increased, a higher electric field peak value will be caused at the interface between the P-type doping layer 3 and the N-type doping layer 5, thereby reducing the reliability of the gate structure of the device.

[0005] Therefore, how to improve the gate electric field distribution, enhance the gate structure reliability and reduce the channel resistance has become a technical problem that needs to be solved urgently. Summary of the invention

[0006] The embodiment of the present invention provides a semiconductor device and a method for manufacturing the same, so as to improve gate electric field distribution, enhance gate structure reliability and reduce channel resistance.

[0007] According to one aspect of the present invention, there is provided a semiconductor device, comprising:

[0008] substrate;

[0009] A semiconductor epitaxial layer, located on one side of the substrate; wherein the semiconductor epitaxial layer has a heterojunction of a two-dimensional electron gas;

[0010] a gate structure located on a side of the semiconductor epitaxial layer away from the substrate; the gate structure comprises a first conductive type cap layer, a second conductive type cap layer and a gate electrode stacked in sequence; and,

[0011] a field stop layer, located in the second conductive type cap layer and / or inserted in a surface of the second conductive type cap layer away from the semiconductor epitaxial layer;

[0012] Among them, the vertical projection of the field stop layer on the substrate is smaller than the vertical projection of the second conductive type cap layer on the substrate; the conductive type of the field stop layer is the second conductive type, and the concentration of the second conductive type doped ions in the field stop layer is greater than the concentration of the second conductive type doped ions in the second conductive type cap layer.

[0013] Optionally, the material of the field stop layer is the same as the material of the second conductive type cap layer;

[0014] And / or, a vertical projection of the field stop layer on the substrate includes a circle, an ellipse, a polygon or an irregular shape.

[0015] Optionally, there are multiple field stop layers, and the multiple field stop layers are arranged at intervals in the second conductive type cap layer and / or inserted on the surface of the second conductive type cap layer away from the semiconductor epitaxial layer;

[0016] Different field stop layers have different vertical projection patterns on the substrate, or at least some of the field stop layers have the same vertical projection patterns on the substrate.

[0017] Optionally, the field stop layer is integrally provided with the second conductive type cap layer, and the field stop layer is interspersed on a surface of the second conductive type cap layer away from the semiconductor epitaxial layer;

[0018] A surface of the second conductive type capping layer away from the first conductive type capping layer has a plurality of protrusions, and the protrusions are located between two adjacent field stop layers.

[0019] Optionally, in a plane parallel to the substrate, the semiconductor device comprises a plurality of strip-shaped field stop layers extending along a first direction and arranged at intervals along a second direction; a width of the strip-shaped field stop layer in the first direction is less than or equal to a width of the second conductive type cap layer in the first direction;

[0020] The first direction is intersected with the second direction; the first direction is an extension direction of the gate electrode, or the first direction is a direction perpendicular to the extension direction of the gate electrode.

[0021] Optionally, in a plane parallel to the substrate, the semiconductor device includes a plurality of block-shaped field stop layers, and the plurality of block-shaped field stop layers are arranged in an array.

[0022] Optionally, the semiconductor device further includes:

[0023] A source electrode and a drain electrode, wherein the source electrode and the drain electrode are located on a side of the semiconductor epitaxial layer away from the substrate and on two opposite sides of the gate structure;

[0024] The strain layer is located on the sidewall of the gate structure, between the gate structure and the source electrode, and between the gate structure and the drain electrode.

[0025] Optionally, the first conductive type doping ions doped in the first conductive type capping layer are P-type doping ions, and the second conductive type doping ions are N-type doping ions;

[0026] Wherein, the P-type doping ions include Mg ions; and the N-type doping ions include Si ions.

[0027] According to another aspect of the present invention, there is provided a method for preparing a semiconductor device, which is used to prepare the semiconductor device according to any embodiment of the present invention, comprising:

[0028] providing a substrate;

[0029] Forming a semiconductor epitaxial layer on one side of the substrate; wherein the semiconductor epitaxial layer has a heterojunction of a two-dimensional electron gas;

[0030] A gate structure is formed on a side of the semiconductor epitaxial layer away from the substrate, and a field stop layer is formed in the gate structure; wherein the gate structure comprises a first conductive type cap layer, a second conductive type cap layer and a gate electrode which are stacked in sequence; the field stop layer is located in the second conductive type cap layer and / or is interspersed on a surface of the second conductive type cap layer away from the semiconductor epitaxial layer; a vertical projection of the field stop layer on the substrate is smaller than a vertical projection of the second conductive type cap layer on the substrate; the conductivity type of the field stop layer is the second conductive type, and a concentration of second conductive type doped ions in the field stop layer is greater than a concentration of second conductive type doped ions in the second conductive type cap layer.

[0031] Optionally, in a case where the field stop layer is interspersed on a surface of the second conductive type cap layer away from the semiconductor epitaxial layer, forming a gate structure on a side of the semiconductor epitaxial layer away from the substrate and forming the field stop layer in the gate structure comprises:

[0032] forming a first conductivity type cap layer on a side of the semiconductor epitaxial layer away from the substrate;

[0033] forming a second conductive type doping layer on a side of the first conductive type capping layer away from the substrate; the ion doping concentration of the second conductive type doping layer is the same as the preset ion doping concentration of the second conductive type capping layer;

[0034] Based on the mask layer, doping ions of the second conductivity type are implanted into the surface of the second conductivity type doped layer away from the substrate to form the field stop layer; and a capping layer of the second conductivity type is formed in the area of ​​the second conductivity type doped layer other than the field stop layer;

[0035] A gate electrode is formed on a side of the field stop layer away from the substrate.

[0036] The technical solution provided by the embodiment of the present invention can reduce the thickness of the second conductive type cap layer by inserting a field stop layer with a higher doping concentration into the second conductive type cap layer with a lower doping concentration and / or on the surface of the second conductive type cap layer away from the semiconductor epitaxial layer, so as to reduce the channel resistance while improving the breakdown voltage of the device and ensuring the reliability of the gate structure, thereby achieving an improvement in the gate electric field distribution and taking into account the reliability of the gate structure and low channel resistance.

[0037] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0039] Figure 1 A schematic diagram of the structure of a semiconductor device provided in the related art;

[0040] Figure 2 An electric field distribution diagram of a gate structure provided in the related art;

[0041] Figure 3 An electric field distribution diagram of another gate structure provided in the related art;

[0042] Figure 4 is a schematic diagram of a three-dimensional structure of a semiconductor device provided by an embodiment of the present invention;

[0043] Figure 5 yes Figure 4 The schematic diagram of the cross-sectional structure of the structure shown along line AA1;

[0044] Figure 6 yes Figure 4 The schematic diagram of the cross-sectional structure of the structure shown along line BB1;

[0045] Figure 7 is a schematic cross-sectional structure diagram of another semiconductor device provided by an embodiment of the present invention;

[0046] Figure 8 yes Figure 4 The electric field distribution diagram of the gate structure in the structure shown;

[0047] Fig. 9 is a top view of a field stop layer and a second conductive type cap layer in another semiconductor device provided by an embodiment of the present invention;

[0048] Fig.10 is a top view of a field stop layer and a second conductive type cap layer in another semiconductor device provided by an embodiment of the present invention;

[0049] Fig.11 is a top view of a field stop layer and a second conductive type cap layer in another semiconductor device provided by an embodiment of the present invention;

[0050] Fig.12 is a top view of a field stop layer and a second conductive type cap layer in another semiconductor device provided by an embodiment of the present invention;

[0051] Fig.13is a schematic cross-sectional structure diagram of another semiconductor device provided by an embodiment of the present invention;

[0052] Fig.14 It is a flow chart of a method for preparing a semiconductor device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0053] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0054] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0055] An embodiment of the present invention provides a semiconductor device, Figure 4 is a schematic diagram of a three-dimensional structure of a semiconductor device provided by an embodiment of the present invention, Figure 5 yes Figure 4 The schematic diagram of the cross-sectional structure of the structure shown along line AA1, Figure 6 yes Figure 4 The schematic diagram of the cross-sectional structure of the structure shown along line BB1, Figure 7 is a schematic cross-sectional view of another semiconductor device provided by an embodiment of the present invention, with reference to Figure 4~Figure 7 , semiconductor devices include:

[0056] Substrate 10;

[0057] The semiconductor epitaxial layer 20 is located on one side of the substrate 10; wherein the semiconductor epitaxial layer 20 has a heterojunction of a two-dimensional electron gas;

[0058] The gate structure 30 is located on a side of the semiconductor epitaxial layer 20 away from the substrate 10; the gate structure 30 includes a first conductive type cap layer 31, a second conductive type cap layer 32 and a gate electrode 33 which are sequentially stacked along a direction Z perpendicular to the substrate;

[0059] The gate structure 30 further includes a field stop layer 34 , which is located in the second conductivity type cap layer 32 and / or interspersed on a surface of the second conductivity type cap layer 32 away from the semiconductor epitaxial layer 20 ;

[0060] Among them, the vertical projection of the field stop layer 34 on the substrate 10 is smaller than the vertical projection of the second conductive type cap layer 32 on the substrate 10; the conductive type of the field stop layer 34 is the second conductive type, and the concentration of the second conductive type doped ions in the field stop layer 34 is greater than the concentration of the second conductive type doped ions in the second conductive type cap layer 32.

[0061] Specifically, the substrate 10 may be a semiconductor substrate. The material of the substrate 10 may include but is not limited to Si, SiGe, SiC, gallium arsenide, P-doped Si, N-doped Si, sapphire, semiconductor on insulator (such as silicon on insulator (SOI)) or other suitable substrate materials. In some embodiments, the material of the substrate 10 may include, for example but not limited to, group III elements, group IV elements, group V elements or combinations thereof (e.g., III-V compounds). In other embodiments, the substrate 10 may be a <111> Oriented silicon substrate.

[0062] In some embodiments, a buffer layer may be provided between the substrate 10 and the semiconductor epitaxial layer 20, and the buffer layer may be in contact with the semiconductor epitaxial layer 20, and the buffer layer is used to reduce the lattice and thermal mismatch between the substrate 10 and the semiconductor epitaxial layer 20, thereby solving the defects attributed to the mismatch / difference. The buffer layer may include a III-V compound. The III-V compound may include, but is not limited to, aluminum, gallium, indium, nitrogen, or a combination thereof. Therefore, exemplary materials for the buffer layer may further include, for example, but not limited to, GaN, AlN, AlGaN, InAlGaN, or a combination thereof. In some embodiments, a nucleation layer may be further included between the substrate 10 and the semiconductor epitaxial layer 20. The nucleation layer may be formed below the buffer layer. The nucleation layer is used to provide a transition to accommodate the mismatch / difference between the substrate 10 and the III-nitride layer of the buffer layer. Exemplary materials for the nucleation layer may include, but are not limited to AlN.

[0063] The semiconductor epitaxial layer 20 includes a first nitride semiconductor layer 21 and a second nitride semiconductor layer 22. The first nitride semiconductor layer 21 is located on one side of the substrate 10, and the second nitride semiconductor layer 22 is located on a side of the first nitride semiconductor layer 21 away from the substrate 10, and has a band gap different from that of the first nitride semiconductor layer 21. A heterojunction of a two-dimensional electron gas may be provided between the first nitride semiconductor layer 21 and the second nitride semiconductor layer 22. The material of the first nitride semiconductor layer 21 may include, but is not limited to, nitrides or III-V compounds, such as GaN, AlN, InN, InxAlyGa(1-xy)N (where x+y≤1), AlyGa(1-y)N (where y≤1). The material of the second nitride semiconductor layer 22 may include, but is not limited to, III-V nitride semiconductor materials, such as GaN, AlGaN, InN, AlInN, InGaN, AlInGaN, or a combination thereof. The band gap (ie, forbidden band width) of the material of the first nitride semiconductor layer 21 and the band gap of the material of the second nitride semiconductor layer 22 are selected to be different so that the electron affinities of the two are different from each other and a heterojunction is formed therebetween.

[0064] The band gap of the material of the first nitride semiconductor layer 21 is set to be smaller than the band gap of the material of the second nitride semiconductor layer 22. For example, the first nitride semiconductor layer 21 can be selected as a GaN layer with a band gap of about 3.4 eV, and the second nitride semiconductor layer 22 can be selected as an AlGaN layer with a band gap of about 4.0 eV, thereby, the first nitride semiconductor layer 21 and the second nitride semiconductor layer 22 can serve as a channel layer and a barrier layer, respectively. A triangular well potential is generated at the bonding interface between the channel layer and the barrier layer, so that electrons accumulate in the triangular well, thereby generating a two-dimensional electron gas (2DEG) region adjacent to the heterojunction. Therefore, the semiconductor device is a high resistance mobility transistor (HEMT) including at least one GaN-based. It should be noted that the formation of the 2DEG region is positively correlated with the degree of polarization effect between the channel and the barrier layer.

[0065] The gate structure 30 is arranged on the side of the semiconductor epitaxial layer 20 away from the substrate 10. The operation of the semiconductor device is controlled by the gate voltage applied to the gate structure 30, and the gate voltage controls the on and off of the channel. The semiconductor device in the present invention is an enhancement-mode HEMT device (i.e., an E-mode enhancement-mode HEMT). The gate structure 30 includes a first conductive type cap layer 31, a second conductive type cap layer 32, and a gate electrode 33 stacked in sequence. The first conductive type cap layer 31 is located on the surface of the semiconductor epitaxial layer 20 away from the substrate 10, the second conductive type cap layer 32 is located on the surface of the first conductive type cap layer 31 away from the substrate 10, and the gate electrode 33 is located on the surface of the second conductive type cap layer 32 away from the substrate 10.

[0066] The gate structure 30 further includes a field stop layer 34, which is located inside the second conductive type cap layer 32 (see Figure 7 ), the surface of the field stop layer 34 close to the substrate 10 and the surface of the field stop layer 34 away from the substrate 10 are both covered by the second conductive type cap layer 32. Alternatively, the field stop layer 34 is interspersed on the surface of the second conductive type cap layer 32 away from the semiconductor epitaxial layer 20 (refer to Figure 4 and Figure 6 ), the field stop layer 34 extends from the surface of the second conductive type cap layer 32 away from the semiconductor epitaxial layer 20 to the second conductive type cap layer 32, which can be understood as replacing a part of the second conductive type cap layer 32 near the gate electrode 33 with the field stop layer 34. Alternatively, the field stop layer 34 is disposed inside the second conductive type cap layer 32, and the field stop layer 34 is disposed on the surface of the second conductive type cap layer 32 away from the semiconductor epitaxial layer 20.

[0067] The material of the field stop layer 34 and the material of the second conductive type cap layer 32 are both semiconductor materials, and the semiconductor material of the field stop layer 34 and the semiconductor material of the second conductive type cap layer 32 may be the same or different. The first conductive type cap layer 31 is doped with first conductive type doping ions; the second conductive type cap layer 32 is doped with second conductive type doping ions; the field stop layer 34 is doped with second conductive type doping ions, and the concentration of the second conductive type doping ions in the field stop layer 34 is greater than the concentration of the second conductive type doping ions in the second conductive type cap layer 32.

[0068] If the first conductivity type is P type, the second conductivity type is N type; if the first conductivity type is N type, the second conductivity type is P type. In an embodiment of the present invention, the first conductivity type is P type and the second conductivity type is N type. The first conductivity type doped ions are P type doped ions and the second conductivity type doped ions are N type doped ions; wherein the P type doped ions include but are not limited to Mg ions, C ions, Fe ions and Zn ions; the N type doped ions include but are not limited to Si ions and O ions. The first conductivity type capping layer 31 is a P type capping layer, which uses the holes in the P type capping layer to deplete the 2DEG in the channel below to achieve normally off; the second conductivity type capping layer 32 is an N type capping layer, which is used to block the contact between the P type capping layer and the gate electrode 33.

[0069] Figure 8 yes Figure 4 The electric field distribution diagram of the gate structure in the structure shown, Figure 2 , Figure 3 and Figure 8 The electric field distribution diagram shown is the electric field distribution diagram of the gate structure obtained at the same gate voltage. Figure 2 and Figure 8, the gate structure provided by the embodiment of the present invention can ensure that the interface between the first conductive type cap layer 31 and the second conductive type cap layer 32 has a lower peak voltage, while also reducing the overall thickness of the cap layer; Figure 3 and Figure 8 The gate structure provided by the embodiment of the present invention can ensure that the cap layer has a relatively low thickness, and can also reduce the peak voltage at the interface between the first conductive type cap layer 31 and the second conductive type cap layer 32 .

[0070] The semiconductor device provided by the embodiment of the present invention can achieve electric field cutoff without increasing the thickness of the second conductive type cap layer 32 by inserting a field stop layer 34 with a higher doping concentration into the second conductive type cap layer 32 with a lower doping concentration and / or on the surface of the second conductive type cap layer 32 away from the semiconductor epitaxial layer 20. This improves the problem of increased channel resistance caused by increased thickness of the second conductive type cap layer 32. It can also achieve electric field cutoff without increasing the doping concentration of the second conductive type doped ions in the second conductive type cap layer 32. This improves the problem of increased electric field peak at the interface between the second conductive type cap layer 32 and the first conductive type cap layer 31 due to increased doping concentration of the second conductive type cap layer 32, thereby ensuring the reliability of the gate structure 30.

[0071] In addition, by setting the vertical projection of the field stop layer 34 on the substrate 10 to be smaller than the vertical projection of the second conductive type cap layer 32 on the substrate 10, a field stop is achieved using a small area of ​​the field stop layer 34, which is more friendly to the roughness of the EPI surface. Since the higher the ion doping concentration in a region, the greater the surface roughness of the region, it is not conducive to the subsequent process manufacturing and affects the reliability of the device. Therefore, setting the vertical projection of the field stop layer 34 with a higher ion doping concentration on the substrate 10 to be smaller than the vertical projection of the second conductive type cap layer 32 with a lower ion doping concentration on the substrate 10 can reduce the area of ​​the region with higher roughness, improve the crystal quality of the device, and facilitate the subsequent preparation process, such as facilitating the preparation of the gate electrode 33, and further improving the reliability of the device.

[0072] It should be noted that the reference Figure 4 The field stop layer 34 closest to the first conductive type cap layer 31 has a distance t from the first conductive type cap layer 31 greater than zero.

[0073] Based on the above embodiments, optionally, the material of the field stop layer 34 is the same as that of the second conductive type cap layer 32; and / or the vertical projection of the field stop layer 34 on the substrate 10 has a circular, elliptical, polygonal or irregular shape.

[0074] Specifically, the material of the field stop layer 34 is the same as that of the second conductive type cap layer 32, for example, both are GaN doped with N-type dopant ions. Using the same material can ensure better compatibility between the two film layers and reduce interface problems caused by material differences; moreover, using the same material can simplify the manufacturing process and reduce production costs, without the need to set different processing parameters and process steps for different materials; in addition, the same material is more likely to maintain consistent stability during long-term use, reducing problems such as different aging speeds caused by material differences. The vertical projection of the field stop layer 34 on the substrate 10 includes a circle, an ellipse, a polygon or a special shape, which can be set according to actual conditions.

[0075] Based on the above embodiments, Figure 4~Figure 7 Optionally, there are multiple field stop layers 34 , and the multiple field stop layers 34 are spaced apart in the second conductive type cap layer 32 and / or inserted in the surface of the second conductive type cap layer 32 away from the semiconductor epitaxial layer 20 . Figure 4~Figure 7 illustratively shows that the number of the field stop layers 34 is two. In other embodiments, the number of the field stop layers 34 is one, or may be greater than two.

[0076] Specifically, multiple field stop layers 34 are arranged in the second conductive type cap layer 32 and / or on the surface of the second conductive type cap layer 32 away from the semiconductor epitaxial layer 20, so that the electric field cutoff can be flexibly adjusted according to the actual demand of gate withstand voltage; and the thickness of the second conductive type cap layer 32 can be further reduced. The plane where each field stop layer 34 is located is arranged parallel to the plane where the second conductive type cap layer 32 is located. Different field stop layers 34 have different vertical projection patterns on the substrate 10, or different field stop layers 34 have the same vertical projection patterns on the substrate 10, or some field stop layers 34 have the same vertical projection patterns on the substrate 10, and some field stop layers 34 have different vertical projection patterns on the substrate 10.

[0077] Based on the above embodiments, please continue to refer to Figure 4~Figure 6 Optionally, the field stop layer 34 is integrally arranged with the second conductive type cap layer 32, and the field stop layer 34 is interspersed on the surface of the second conductive type cap layer 32 away from the semiconductor epitaxial layer 20; wherein the second conductive type cap layer 32 has multiple protrusions on the surface away from the first conductive type cap layer 31, and the protrusions are located between two adjacent field stop layers 34.

[0078] Specifically, the field stop layer 34 is integrally provided with the second conductive type cap layer 32, and the field stop layer 34 is inserted into the surface of the second conductive type cap layer 32 away from the semiconductor epitaxial layer 20, which can simplify the preparation process of the field stop layer 34 and the second conductive type cap layer 32. When preparing the field stop layer 34 and the second conductive type cap layer 32, a second conductive type doping layer can be formed on the side of the first conductive type cap away from the semiconductor epitaxial layer 20, and the ion doping concentration of the second conductive type doping layer should be kept the same as the preset ion doping concentration of the second conductive type cap layer 32; after forming the second conductive type doping layer, the second conductive type doping ions can be injected into the surface of the second conductive type doping layer again based on the patterned mask layer, so as to form at least one second conductive type heavily doped region in the second conductive type doping layer, and the second conductive type heavily doped region is used as the field stop layer 34, and the area outside the second conductive type heavily doped region in the second conductive type doping layer is used as the second conductive type cap layer 32. The number and pattern of the field stop layer 34 can be determined based on the number and pattern of the openings in the mask layer. The area in the surface of the second conductive type doped layer away from the semiconductor epitaxial layer 20 where the second conductive type doped ions are not implanted again forms a protrusion on the surface of the second conductive type capping layer 32 .

[0079] Based on the above embodiments, Fig. 9 is a top view of a mid-range stop layer and a second conductive type cap layer in another semiconductor device provided by an embodiment of the present invention, with reference to Figure 5 and Fig. 9 Optionally, in a plane parallel to the substrate 10 , the semiconductor device includes a plurality of strip-shaped field stop layers 34 extending along the first direction X and arranged at intervals along the second direction Y.

[0080] The first direction X and the second direction Y are arranged to intersect each other; the first direction X and the second direction Y can be arranged perpendicularly. The first direction X is the extending direction of the gate electrode 33 (refer to Figure 5 ), or the first direction X is a direction perpendicular to the extending direction of the gate electrode 33 (reference Fig. 9 ). A plurality of strip-shaped field stop layers 34 may be uniformly arranged on the surface or inside of the second conductive type cap layer 32 to achieve uniform electric field cutoff by the field stop layer.

[0081] The width of the strip-shaped field stop layer 34 in the first direction X is less than or equal to the width of the second conductive type cap layer 32 in the first direction X. Figure 5 and Fig. 9 , exemplarily showing that the width of the strip-shaped field stop layer 34 in the first direction X is equal to the width of the second conductive type cap layer 32 in the first direction X. Fig.10is a top view of a mid-range stop layer and a second conductive type cap layer in another semiconductor device provided by an embodiment of the present invention, with reference to Fig.10 , exemplarily showing that the width of the strip-shaped field stop layer 34 in the first direction X is smaller than the width of the second conductive type cap layer 32 in the first direction X.

[0082] Based on the above embodiments, Fig.11 is a top view of a field stop layer and a second conductive type cap layer in another semiconductor device provided by an embodiment of the present invention, Fig.12 is a top view of a mid-range stop layer and a second conductive type cap layer in another semiconductor device provided by an embodiment of the present invention, with reference to Fig.11 and Fig.12 Optionally, in a plane parallel to the substrate, the semiconductor device includes a plurality of block-shaped field stop layers 34, and the plurality of block-shaped field stop layers 34 are arranged in an array. This can further achieve flexible adjustment of the electric field stop according to the actual requirements of the gate withstand voltage. The field stop layer 34 located at the edge of the second conductive type cap layer can be at a distance of zero from the boundary of the second conductive type cap layer (refer to Fig.11 ), the field stop layer 34 located at the edge of the second conductive type cap layer may be at a distance greater than zero from the boundary of the second conductive type cap layer (refer to Fig.12 ).

[0083] Based on the above embodiments, Fig.13 is a schematic cross-sectional view of another semiconductor device provided by an embodiment of the present invention, with reference to Fig.13 Optionally, the semiconductor device further includes: a source electrode S and a drain electrode D, the source electrode S and the drain electrode D are located on a side of the semiconductor epitaxial layer 20 away from the substrate 10 , and are located on opposite sides of the gate structure 30 .

[0084] Specifically, the source electrode S is located on a side of the second nitride semiconductor layer 22 away from the substrate 10, and contacts the second nitride semiconductor layer 22. The drain electrode D is located on a side of the second nitride semiconductor layer 22 away from the substrate 10, and contacts the second nitride semiconductor layer 22. The source electrode S and the drain electrode D are located on opposite sides of the gate structure 30. The source electrode S and the drain electrode D may include but are not limited to metals, alloys, doped semiconductor materials (e.g., doped crystalline silicon), compounds such as silicides and nitrides, other conductor materials, or combinations thereof. The source electrode S and the drain electrode D may be a single layer, or multiple layers having the same or different compositions. In some embodiments, the source electrode S and the drain electrode D form an ohmic contact with the second nitride semiconductor layer 22. Ohmic contact may be achieved by applying Ti, Al, or other suitable materials to the source electrode S and the drain electrode D.

[0085] Based on the above embodiments, please continue to refer to Fig.13 Optionally, the semiconductor device further includes: a strained layer 40 located on the sidewall of the gate structure 30, the surface of the semiconductor epitaxial layer 20 between the gate structure 30 and the source electrode S, and the surface of the semiconductor epitaxial layer 20 between the gate structure 30 and the drain electrode D.

[0086] Specifically, in order to increase the 2DEG concentration, a strain layer 40 (Strainlayer) can be added above the semiconductor epitaxial layer 20. The strain layer 40 modulates the stress state of the AlGaN / GaN heterojunction to reduce the on-resistance and increase the 2DEG concentration, thereby improving the saturation current density and device FOM (Factor of Merit) of the HEMT device. In addition, the strain layer 40 can also repair the damage caused to the surface of the semiconductor epitaxial layer 20 (the surface of the barrier layer) by the patterning process of the gate structure 30, thereby reducing the defect state density on the surface of the semiconductor epitaxial layer 20, reducing the dynamic on-resistance, and improving the conversion efficiency of the device.

[0087] Furthermore, the semiconductor device further includes a passivation layer, which is located on the side of the strained layer 40 away from the substrate 10 and covers the surface of the strained layer 40, the gate electrode 33, and the drain electrode D. The material of the passivation layer includes a dielectric material such as an oxide, for example, SiO2. The passivation layer is used to protect and electrically insulate the semiconductor device.

[0088] An embodiment of the present invention further provides a method for preparing a semiconductor device, which is used to prepare the semiconductor device described in any embodiment of the present invention. Fig.14 is a flow chart of a method for preparing a semiconductor device provided by an embodiment of the present invention, with reference to Fig.14 , and combined with Figure 4~Figure 7 , a method for preparing a semiconductor device comprises:

[0089] S10. Provide a substrate.

[0090] S20, forming a semiconductor epitaxial layer on one side of the substrate; wherein the semiconductor epitaxial layer has a heterojunction of a two-dimensional electron gas.

[0091] Specifically, forming the semiconductor epitaxial layer 20 on one side of the substrate 10 includes: sequentially forming a first nitride semiconductor layer 21 and a second nitride semiconductor layer 22 on one side of the substrate 10. The second nitride semiconductor layer 22 has a band gap different from that of the first nitride semiconductor layer 21, so that a heterojunction of a two-dimensional electron gas can be provided between the first nitride semiconductor layer 21 and the second nitride semiconductor layer 22. The material of the first nitride semiconductor layer 21 may include but is not limited to nitride or a III-V compound, such as GaN, AlN, InN, InxAlyGa(1-xy)N (where x+y≤1), AlyGa(1-y)N (where y≤1). The material of the second nitride semiconductor layer 22 may include but is not limited to a III-V nitride semiconductor material, such as GaN, AlGaN, InN, AlInN, InGaN, AlInGaN or a combination thereof.

[0092] Optionally, before forming the semiconductor epitaxial layer 20 on one side of the substrate 10, it also includes: forming a buffer layer on one side of the substrate 10. The buffer layer is located between the substrate 10 and the semiconductor epitaxial layer 20, and the buffer layer may be in contact with the semiconductor epitaxial layer 20. The buffer layer is used to reduce the lattice and thermal mismatch between the substrate 10 and the semiconductor epitaxial layer 20, thereby solving the defects attributed to the mismatch / difference. The buffer layer may include III-V compounds. The III-V compounds may include but are not limited to aluminum, gallium, indium, nitrogen, or a combination thereof. Therefore, exemplary materials of the buffer layer may further include, for example, but are not limited to GaN, AlN, AlGaN, InAlGaN, or a combination thereof. Further, in some embodiments, before forming the buffer layer on one side of the substrate 10, it also includes forming a nucleation layer on one side of the substrate 10. The nucleation layer is used to provide a transition to accommodate the mismatch / difference between the substrate 10 and the III-nitride layer of the buffer layer. Exemplary materials of the nucleation layer may include but are not limited to any one of AlN or its alloys.

[0093] S30. Form a gate structure on a side of the semiconductor epitaxial layer away from the substrate, and form a field stop layer in the gate structure; the gate structure includes a first conductive type cap layer, a second conductive type cap layer and a gate electrode stacked in sequence; the field stop layer is located in the second conductive type cap layer and / or is interspersed on a surface of the second conductive type cap layer away from the semiconductor epitaxial layer.

[0094] Among them, the vertical projection of the field stop layer 34 on the substrate 10 is smaller than the vertical projection of the second conductive type cap layer 32 on the substrate 10; the conductive type of the field stop layer 34 is the second conductive type, and the concentration of the second conductive type doped ions in the field stop layer 34 is greater than the concentration of the second conductive type doped ions in the second conductive type cap layer 32.

[0095] The material of the field stop layer 34 and the material of the second conductive type cap layer 32 are both semiconductor materials, and the semiconductor material of the field stop layer 34 and the semiconductor material of the second conductive type cap layer 32 may be the same or different. The first conductive type cap layer 31 is doped with first conductive type doping ions; the second conductive type cap layer 32 is doped with second conductive type doping ions; the field stop layer 34 is doped with second conductive type doping ions, and the concentration of the second conductive type doping ions in the field stop layer 34 is greater than the concentration of the second conductive type doping ions in the second conductive type cap layer 32. Exemplary materials for the first conductive type capping layer 31 may include III-V nitride semiconductor materials, such as gallium nitride, aluminum gallium nitride, indium nitride, aluminum indium nitride, indium gallium nitride, aluminum indium gallium nitride or a combination thereof; exemplary materials for the second conductive type capping layer 32 may include III-V nitride semiconductor materials, such as gallium nitride, aluminum gallium nitride, indium nitride, aluminum indium nitride, indium gallium nitride, aluminum indium gallium nitride or a combination thereof; exemplary materials for the field stop layer 34 may include III-V nitride semiconductor materials, such as gallium nitride, aluminum gallium nitride, indium nitride, aluminum indium nitride, indium gallium nitride, aluminum indium gallium nitride or a combination thereof.

[0096] If the first conductivity type is P type, the second conductivity type is N type; if the first conductivity type is N type, the second conductivity type is P type. In an embodiment of the present invention, the first conductivity type is P type and the second conductivity type is N type. The first conductivity type doping ions are P type doping ions and the second conductivity type doping ions are N type doping ions; wherein the P type doping ions include but are not limited to Mg ions, C ions, Fe ions and Zn ions; the N type doping ions include but are not limited to Si ions and O ions.

[0097] Exemplary materials of the gate electrode 33 may include metals or metal compounds. The gate electrode 33 may be formed as a single layer or multiple layers having the same or different compositions. Exemplary materials of the metal or metal compound may include, for example but not limited to, tungsten (W), gold (Au), palladium (Pd), titanium (Ti), tantalum (Ta), cobalt (Co), nickel (Ni), platinum (Pt), molybdenum (Mo), titanium nitride (TiN), tantalum nitride (TaN), metal alloys or compounds thereof, or other metal compounds.

[0098] The semiconductor device provided by the embodiment of the present invention can achieve electric field cutoff without increasing the thickness of the second conductive type cap layer 32 by inserting a field stop layer 34 with a higher doping concentration into the second conductive type cap layer 32 with a lower doping concentration and / or on the surface of the second conductive type cap layer 32 away from the semiconductor epitaxial layer 20. This improves the problem of increased channel resistance caused by increased thickness of the second conductive type cap layer 32. It can also achieve electric field cutoff without increasing the doping concentration of the second conductive type doped ions in the second conductive type cap layer 32. This improves the problem of increased electric field peak at the interface between the second conductive type cap layer 32 and the first conductive type cap layer 31 due to increased doping concentration of the second conductive type cap layer 32, thereby ensuring the reliability of the gate structure 30.

[0099] In addition, by setting the vertical projection of the field stop layer 34 on the substrate 10 to be smaller than the vertical projection of the second conductive type cap layer 32 on the substrate 10, a field stop is achieved using a small area of ​​the field stop layer 34, which is more friendly to the roughness of the EPI surface. Since the higher the ion doping concentration in a region, the greater the surface roughness of the region, it is not conducive to the subsequent process manufacturing and affects the reliability of the device. Therefore, setting the vertical projection of the field stop layer 34 with a higher ion doping concentration on the substrate 10 to be smaller than the vertical projection of the second conductive type cap layer 32 with a lower ion doping concentration on the substrate 10 can reduce the area of ​​the region with higher roughness, improve the crystal quality of the device, and facilitate the subsequent preparation process, such as using the preparation of the gate electrode 33 to improve the reliability of the device.

[0100] Optionally, in the case where the field stop layer 34 is interspersed with the surface of the second conductive type cap layer 32 away from the semiconductor epitaxial layer 20, in step S30, a gate structure is formed on a side of the semiconductor epitaxial layer away from the substrate, and a field stop layer is formed in the gate structure, including:

[0101] S310 , forming a first conductivity type cap layer on a side of the semiconductor epitaxial layer away from the substrate.

[0102] S320, forming a second conductive type doping layer on a side of the first conductive type capping layer away from the substrate, wherein the ion doping concentration of the second conductive type doping layer is the same as the preset ion doping concentration of the second conductive type capping layer.

[0103] S330, based on the mask layer, injecting second conductivity type doping ions into the surface of the second conductivity type doping layer away from the substrate to form a field stop layer; forming a second conductivity type capping layer in the area outside the field stop layer in the second conductivity type doping layer.

[0104] S340, forming a gate electrode on a side of the second conductive type doped layer away from the substrate.

[0105] Specifically, a second conductive type doped layer is formed on the side of the first conductive type cap away from the semiconductor epitaxial layer 20, and the ion doping concentration of the second conductive type doped layer should be kept the same as the preset ion doping concentration of the second conductive type cap layer 32; after the second conductive type doped layer is formed, the second conductive type doped ions can be injected again into the surface of the second conductive type doped layer based on the patterned mask layer, so as to form at least one second conductive type heavily doped region in the second conductive type doped layer, and the second conductive type heavily doped region is used as the field stop layer 34, and the area other than the second conductive type heavily doped area in the second conductive type doped layer is used as the second conductive type cap layer 32. The number and pattern of the field stop layer 34 can be determined based on the number and pattern of the openings in the mask layer. The area on the surface of the second conductive type doped layer away from the semiconductor epitaxial layer 20 where the second conductive type doped ions are not injected again forms a protrusion on the surface of the second conductive type cap layer 32.

[0106] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A semiconductor device, characterized in that: include: substrate; A semiconductor epitaxial layer, located on one side of the substrate; wherein the semiconductor epitaxial layer has a heterojunction of a two-dimensional electron gas; A gate structure is located on a side of the semiconductor epitaxial layer away from the substrate; the gate structure comprises a first conductive type cap layer, a second conductive type cap layer and a gate electrode which are stacked in sequence, and, a field stop layer, located in the second conductive type cap layer and / or inserted in a surface of the second conductive type cap layer away from the semiconductor epitaxial layer; wherein a vertical projection of the field stop layer on the substrate is smaller than a vertical projection of the second conductive type cap layer on the substrate; the conductive type of the field stop layer is the second conductive type, and a concentration of the second conductive type doped ions in the field stop layer is greater than a concentration of the second conductive type doped ions in the second conductive type cap layer; The number of the field stop layers is multiple; when the field stop layer is interspersed on the surface of the second conductive type cap layer away from the semiconductor epitaxial layer, the surface of the second conductive type cap layer away from the first conductive type cap layer includes multiple protrusions, and the protrusions are located between two adjacent field stop layers.

2. The semiconductor device according to claim 1, wherein: The material of the field stop layer is the same as the material of the second conductive type cap layer; And / or, a vertical projection of the field stop layer on the substrate includes a circle, an ellipse, a polygon or an irregular shape.

3. The semiconductor device according to claim 1, wherein: A plurality of the field stop layers are arranged at intervals in the second conductive type cap layer and / or are inserted in a surface of the second conductive type cap layer away from the semiconductor epitaxial layer; Different field stop layers have different vertical projection patterns on the substrate, or at least some of the field stop layers have the same vertical projection patterns on the substrate.

4. The semiconductor device according to claim 3, characterized in that The field stop layer and the second conductive type cap layer are integrally arranged.

5. The semiconductor device according to claim 3, characterized in that In a plane parallel to the substrate, the semiconductor device comprises a plurality of strip-shaped field stop layers extending along a first direction and arranged at intervals along a second direction; The width of the strip-shaped field stop layer in the first direction is less than or equal to the width of the second conductive type cap layer in the first direction; The first direction is intersected with the second direction; the first direction is an extension direction of the gate electrode, or the first direction is a direction perpendicular to the extension direction of the gate electrode.

6. The semiconductor device according to claim 3, characterized in that In a plane parallel to the substrate, the semiconductor device includes a plurality of block-shaped field stop layers, and the plurality of block-shaped field stop layers are arranged in an array.

7. The semiconductor device according to claim 1, wherein: Also includes: A source electrode and a drain electrode, wherein the source electrode and the drain electrode are located on a side of the semiconductor epitaxial layer away from the substrate and on two opposite sides of the gate structure; The strain layer is located on the sidewall of the gate structure, between the gate structure and the source electrode, and between the gate structure and the drain electrode.

8. The semiconductor device according to claim 1, wherein: The first conductive type doping ions doped in the first conductive type capping layer are P-type doping ions, and the second conductive type doping ions are N-type doping ions; Wherein, the P-type doping ions include Mg ions; and the N-type doping ions include Si ions.

9. A method for preparing a semiconductor device, characterized in that: Used to prepare the semiconductor device according to any one of claims 1 to 8, comprising: providing a substrate; Forming a semiconductor epitaxial layer on one side of the substrate; wherein the semiconductor epitaxial layer has a heterojunction of a two-dimensional electron gas; A gate structure is formed on a side of the semiconductor epitaxial layer away from the substrate, and a field stop layer is formed in the gate structure; wherein the gate structure comprises a first conductive type cap layer, a second conductive type cap layer and a gate electrode which are stacked in sequence; the field stop layer is located in the second conductive type cap layer and / or is interspersed on a surface of the second conductive type cap layer away from the semiconductor epitaxial layer; a vertical projection of the field stop layer on the substrate is smaller than a vertical projection of the second conductive type cap layer on the substrate; the conductivity type of the field stop layer is the second conductive type, and a concentration of second conductive type doped ions in the field stop layer is greater than a concentration of second conductive type doped ions in the second conductive type cap layer.

10. The method for preparing a semiconductor device according to claim 9, characterized in that: In a case where the field stop layer is interspersed on a surface of the second conductive type cap layer away from the semiconductor epitaxial layer, forming a gate structure on a side of the semiconductor epitaxial layer away from the substrate, and forming a field stop layer in the gate structure, comprises: forming a first conductivity type cap layer on a side of the semiconductor epitaxial layer away from the substrate; forming a second conductive type doping layer on a side of the first conductive type capping layer away from the substrate; the ion doping concentration of the second conductive type doping layer is the same as the preset ion doping concentration of the second conductive type capping layer; Based on the mask layer, doping ions of the second conductivity type are implanted into the surface of the second conductivity type doped layer away from the substrate to form the field stop layer; and a capping layer of the second conductivity type is formed in the area of ​​the second conductivity type doped layer other than the field stop layer; A gate electrode is formed on a side of the field stop layer away from the substrate.

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