Trench gate super junction metal oxide semiconductor field effect transistor, manufacturing method thereof and semiconductor device

Abstract

The invention relates to the technical field of semiconductor devices, and discloses a trench gate super junction metal oxide semiconductor field effect transistor, a manufacturing method thereof and a semiconductor device. The trench gate super junction metal oxide semiconductor field effect transistor comprises an epitaxial layer; the columnar doped regions are located in the epitaxial layer at intervals and downwards extend into the epitaxial layer from the upper surface of the epitaxial layer, and the conduction type of the columnar doped regions is different from that of the epitaxial layer; the groove layer is positioned above the epitaxial layer; the first groove is positioned in the groove layer and is positioned between two adjacent columnar doped regions; the second grooves are located in the groove layer and located between every two adjacent first grooves, and the width of the second grooves is larger than that of the first grooves; and the trench gates are respectively positioned in the first trench and the second trench and extend downwards from the openings of the trenches to the bottoms of the trenches. The compromise characteristic of the on resistance and the breakdown voltage of the trench gate super junction metal oxide semiconductor field effect transistor can be improved, and the reliability of the device is improved.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor devices, for example, to a trench gate superjunction metal oxide semi-conductor field effect transistor and a manufacturing method thereof, and a semiconductor device. Background Art

[0002] Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), also known as MOSFET for short. As an innovative MOSFET structure, superjunction MOSFET forms a charge compensation layer in the drift region by alternating P-type columns and N-type columns (or N-type columns and P-type columns), thereby effectively reducing the on-resistance of the device without sacrificing its breakdown voltage, optimizing the trade-off relationship between conductivity and breakdown voltage, and achieving smaller on-resistance and stronger current capability at the same chip size.

[0003] To further reduce the on-resistance, researchers and manufacturers have developed trench gate superjunction MOSFETs, which place the gate in the trench, increasing the channel density and further reducing the on-resistance per unit area.

[0004] However, the current trench gate super junction MOSFET has a low active area utilization rate, and when the device breaks down, due to the large spacing between adjacent trenches, electric field spikes are easily generated at the bottom of the trench, thereby reducing the breakdown voltage, affecting the compromise characteristics of the on-resistance and breakdown voltage of the trench gate super junction MOSFET, and affecting the reliability of the device.

[0005] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present application, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0006] In order to provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. The summary is not an extensive review, nor is it intended to identify key / critical components or delineate the scope of protection of these embodiments, but rather serves as a prelude to the detailed description that follows.

[0007] The embodiments of the present disclosure provide a trench gate super junction metal oxide semi-conductor field effect transistor and a manufacturing method thereof, and a semiconductor device, which can improve the trade-off characteristics of the on-resistance and breakdown voltage of the trench gate super junction metal oxide semi-conductor field effect transistor and improve the reliability of the device.

[0008] In some embodiments, a trench-gate superjunction metal-oxide-semiconductor field-effect transistor is provided, comprising: an epitaxial layer; columnar doped regions, which are spaced apart in the epitaxial layer and extend downward from the upper surface of the epitaxial layer into the epitaxial layer, and the conductivity type of the columnar doped regions is different from that of the epitaxial layer; a trench layer, which is located above the epitaxial layer; a first trench, which is located in the trench layer and between two adjacent columnar doped regions; a second trench, which is located in the trench layer and between two adjacent first trenches, and the width of the second trench is greater than the width of the first trench; and a trench gate, which is respectively located in the first trench and the second trench and extends downward from the opening of the trench to the bottom of the trench.

[0009] Optionally, the width of the first trench is smaller than the width of the columnar doping region, and the width of the second trench is larger than the width of the columnar doping region.

[0010] Optionally, the second trench is adjacent to the columnar doping region and is located above the columnar doping region.

[0011] Optionally, the trench gate located in the second trench covers a portion of the bottom adjacent to the sidewall of the second trench.

[0012] Optionally, the trench gate super junction metal oxide semi-field effect transistor further includes: a well region located in the trench layer and between the first trench and the second trench; and a source and drain region located in the trench layer and above the well region.

[0013] Optionally, the trench gate super junction metal oxide semi-field effect transistor further includes: a dielectric layer located above the trench layer and a portion of the dielectric layer is located in the second trench.

[0014] Optionally, the trench-gate superjunction metal-oxide-semiconductor field-effect transistor also includes: a metal layer, located above the dielectric layer and part of the metal layer is located in the second trench; wherein a connecting column is formed on the lower surface of the metal layer, and the connecting column extends downward from the lower surface of the metal layer through the dielectric layer and the source and drain regions to the well region in sequence.

[0015] In some embodiments, a method for manufacturing a trench-gate superjunction metal-oxide-semiconductor field-effect transistor is provided, which is used to manufacture the trench-gate superjunction metal-oxide-semiconductor field-effect transistor as described in the above embodiments, and the manufacturing method includes: etching deep trenches on an epitaxial layer and filling them with doping materials of a conductivity type different from that of the epitaxial layer to form a columnar doped region; growing a thin oxide layer as a trench layer on the epitaxial layer formed with the columnar doped region; etching a first trench and a second trench on the trench layer; wherein the first trench is located between two adjacent columnar doped regions, the second trench is located between two adjacent first trenches, and the width of the second trench is greater than the width of the first trench; after growing a gate oxide layer on the trench layer etched with the first trench and the second trench, polysilicon is deposited; etching polysilicon to form a trench gate in the first trench and the second trench; wherein the trench gate extends downward from the opening of the trench to the bottom of the trench.

[0016] Optionally, etching polysilicon to form trench gates in the first trench and the second trench includes: etching polysilicon in a direction perpendicular to the epitaxial layer to form trench gates in the first trench and the second trench, and the trench gate located in the second trench covers a portion of the bottom adjacent to the side wall of the second trench.

[0017] In some embodiments, a semiconductor device is provided, characterized in that it includes: a metal oxide semiconductor field effect transistor as described in the above embodiments.

[0018] The embodiments of the present disclosure provide a trench gate superjunction metal oxide semi-conductor field effect transistor and a manufacturing method thereof, and a semiconductor device, which can achieve the following technical effects:

[0019] The disclosed embodiment provides a trench gate super junction metal oxide semi-conductor field effect transistor, in which a second trench is added between two adjacent first trenches, and the first trench and the second trench are both formed with a trench gate extending downward from the trench opening to the bottom of the trench, forming a multi-trench structure, increasing the trench density within each active area repeating unit of the trench gate super junction metal oxide semi-conductor field effect transistor, thereby improving the effective channel density of the device and reducing the specific on-resistance. At the same time, the width of the second trench is greater than the width of the first trench. By optimizing the width and number of the trenches to reduce the electric field concentration effect at the bottom of the trench, the electric field distribution between adjacent trenches is optimized, the electric field is dispersed, and the breakdown voltage of the device is increased, thereby improving the compromise characteristics of the on-resistance and breakdown voltage of the trench gate super junction metal oxide semi-conductor field effect transistor, and improving the reliability of the device.

[0020] The above general description and the following description are exemplary and explanatory only and are not intended to limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] One or more embodiments are exemplarily described by corresponding drawings, which do not limit the embodiments. Elements with the same reference numerals in the drawings are shown as similar elements, and the drawings do not constitute a scale limitation, and wherein:

[0022] Figure 1 is a schematic structural diagram of a trench gate superjunction metal oxide semi-field effect transistor provided by an embodiment of the present disclosure;

[0023] Figure 2 is a schematic diagram of a method for manufacturing a trench gate superjunction metal oxide semi-field effect transistor provided by an embodiment of the present disclosure;

[0024] Figure 3 is a schematic diagram of a structure after etching a first groove and a second groove on a groove layer provided by an embodiment of the present disclosure;

[0025] Figure 4 is Figure 3A schematic diagram of the structure after a gate oxide layer is grown on the structure shown;

[0026] Figure 5 is Figure 4 A schematic diagram of the structure after polysilicon deposition is performed on the structure shown;

[0027] Figure 6 is Figure 5 A schematic diagram of a structure in which polysilicon is etched on the structure shown to form a trench gate;

[0028] Figure 7 is a schematic structural diagram of a trench gate superjunction metal oxide semi-field effect transistor provided by another embodiment of the present disclosure;

[0029] Figure 8 is a schematic diagram of a method for manufacturing a trench gate superjunction metal oxide semi-conductor field effect transistor provided by another embodiment of the present disclosure;

[0030] Fig. 9 It is a schematic structural diagram of a semiconductor device provided by an embodiment of the present disclosure.

[0031] Reference numerals:

[0032] 10 trench gate super junction metal oxide semi-field effect transistor; 100 epitaxial layer; 102 columnar doping region; 104 trench layer; 106 first trench; 108 second trench; 110 trench gate; 112 well region; 114 source and drain region; 116 dielectric layer; 118 metal layer; 120 connecting column; 122 substrate; 124 gate oxide layer; 126 polysilicon;

[0033] 2Semiconductor devices. DETAILED DESCRIPTION

[0034] In order to be able to understand the features and technical contents of the embodiments of the present disclosure in more detail, the implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present disclosure. In the following technical description, for the convenience of explanation, a full understanding of the disclosed embodiments is provided through multiple details. However, one or more embodiments can still be implemented without these details. In other cases, to simplify the drawings, well-known structures and devices can be simplified for display.

[0035] The terms "first", "second", etc. in the specification and claims of the embodiments of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchanged where appropriate, so that the embodiments of the embodiments of the present disclosure described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.

[0036] In the embodiments of the present disclosure, the terms "upper", "lower", "inside", "middle", "outside", "front", "back" and the like indicate directions or positional relationships based on the directions or positional relationships shown in the accompanying drawings. These terms are mainly intended to better describe the embodiments of the present disclosure and their embodiments, and are not intended to limit the indicated devices, elements or components to have a specific direction, or to be constructed and operated in a specific direction. Moreover, in addition to being used to indicate directions or positional relationships, some of the above terms may also be used to indicate other meanings. For example, the term "upper" may also be used to indicate a certain dependency or connection relationship in certain circumstances. For those of ordinary skill in the art, the specific meanings of these terms in the embodiments of the present disclosure can be understood according to specific circumstances.

[0037] In addition, the terms "disposed", "connected", and "fixed" should be understood in a broad sense. For example, "connected" can be a fixed connection, a detachable connection, or an integral structure; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be an internal connection between two devices, elements, or components. For those of ordinary skill in the art, the specific meanings of the above terms in the embodiments of the present disclosure can be understood according to specific circumstances.

[0038] Unless otherwise stated, the term "plurality" means two or more.

[0039] In the embodiment of the present disclosure, the character " / " indicates that the preceding and following objects are in an "or" relationship. For example, A / B indicates: A or B.

[0040] The term "and / or" is a description of the association relationship between objects, indicating that three relationships can exist. For example, A and / or B means: A, B, A and B.

[0041] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present disclosure may be combined with each other.

[0042] Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), also known as MOSFET. MOSFET is a field effect transistor with a MOS (Metal-Oxide-Semiconductor) structure, which uses the electric field effect of the control input loop to control the current of the output loop. MOSFET is mainly composed of three electrodes: gate (G), source (S) and drain (D). Its structural feature is that the metal gate and the semiconductor are insulated by a layer of oxide (such as silicon dioxide). According to the different types of carriers involved in conduction, MOSFET can be divided into N-channel field effect transistors and P-channel field effect transistors.

[0043] Superjunction MOSFET, also known as superjunction transistor, is an innovative MOSFET structure that forms a charge compensation layer in the drift region by alternating P-type columns and N-type columns (or N-type columns and P-type columns, depending on the type of MOSFET), thereby forming a special charge balance structure that effectively reduces the on-resistance of the device without sacrificing its breakdown voltage. Superjunction MOSFET utilizes the combined effect of lateral and longitudinal electric fields to optimize the trade-off between conductivity and breakdown voltage. Superjunction MOSFET is particularly suitable for use in full-bridge or half-bridge circuits due to its low on-resistance and fast switching speed, and is widely used in the fields of DC charging piles and high-power power supplies. Compared with traditional vertical diffused MOSFET (VDMOS), superjunction MOSFET can achieve smaller on-resistance and stronger current capability at the same chip size due to its better breakdown voltage and trade-off relationship with specific on-resistance.

[0044] In recent years, with the increase in market demand, researchers and manufacturers have continuously improved the electrical characteristics of their superjunction MOSFET products, and launched trench gate structure superjunction MOSFETs with lower on-resistance based on planar gate superjunction MOSFETs. The trench gate structure forms deep trenches inside the semiconductor material and makes the gate in the trench, so that the gate is placed in the trench, increasing the channel density, reducing the gate-to-drain capacitance and the overall output capacitance, and reducing the on-resistance per unit area, thereby significantly reducing the energy loss in the switching process, speeding up the switching speed, and improving the device's operating efficiency and frequency response.

[0045] However, the current trench gate super junction MOSFET has a low active area utilization rate, and when the device breaks down, due to the large spacing between adjacent trenches, electric field spikes are easily generated at the bottom of the trench, thereby reducing the breakdown voltage, affecting the compromise characteristics of the on-resistance and breakdown voltage of the trench gate super junction MOSFET, and affecting the reliability of the device.

[0046] Combination Figure 1 As shown, the embodiment of the present disclosure provides a trench gate superjunction metal oxide semi-field effect transistor 10, including an epitaxial layer 100, a columnar doped region 102, a trench layer 104, a first trench 106, a second trench 108 and a trench gate 110. The columnar doped region 102 is spaced apart in the epitaxial layer 100 and extends downward from the upper surface of the epitaxial layer 100 into the epitaxial layer 100, and the conductivity type of the columnar doped region 102 is different from that of the epitaxial layer 100. The trench layer 104 is located above the epitaxial layer 100. The first trench 106 is located in the trench layer 104 and between two adjacent columnar doped regions 102. The second trench 108 is located in the trench layer 104 and between two adjacent first trenches 106, and the width of the second trench 108 is greater than the width of the first trench 106. The trench gate 110 is respectively located in the first trench 106 and the second trench 108 and extends downward from the opening of the trench to the bottom of the trench.

[0047] In the disclosed embodiment, the conductivity type includes P (Positive) type and N (Negative) type, P type refers to hole conduction, and N type refers to electron conduction. The epitaxial layer 100 is used as the base layer of the device to support the entire device structure and provide the necessary electrical properties. The columnar doped region 102 refers to a P-type or N-type doped region, which is used to form a P column or an N column. The columnar doped region 102 is embedded in the epitaxial layer 100 in an interval manner and extends downward from the upper surface of the epitaxial layer 100. The conductivity type of the columnar doped region 102 is opposite to that of the epitaxial layer 100, forming alternating N-type and P-type regions (or vice versa), thereby forming a super junction structure. The super junction structure effectively reduces the on-resistance of the device through the charge balance principle while maintaining a high breakdown voltage. The trench layer 104 is located above the epitaxial layer 100 to form a trench structure. The first trench 106 is located between two adjacent columnar doped regions 102. A trench gate 110 is disposed in the first trench 106, extending downward from the opening of the trench to the bottom of the trench, forming a trench gate 110 structure. The trench gate 110 structure helps to reduce the unit size of the device and improve the current density.

[0048] In addition, the embodiment of the present disclosure provides a trench gate super junction metal oxide semi field effect transistor 10, wherein a second trench 108 is further provided between two adjacent first trenches 106, and both the first trench 106 and the second trench 108 are formed with a trench gate 110 extending downward from the trench opening to the bottom of the trench, forming a multi-trench structure, increasing the trench density within each active region repeating unit of the trench gate super junction metal oxide semi field effect transistor 10, thereby improving the effective channel density of the device and reducing the specific on-resistance. At the same time, the width of the second trench 108 is greater than the width of the first trench 106. By optimizing the width and number of the trenches to reduce the electric field concentration effect at the bottom of the trenches, optimizing the electric field distribution between adjacent trenches, dispersing the electric field, and improving the breakdown voltage of the device, the compromise characteristics of the on-resistance and breakdown voltage of the trench gate super junction metal oxide semi field effect transistor 10 are improved, and the reliability of the device is improved.

[0049] For example, Figure 1 As shown, the width of the first trench 106 is c, and the width of the second trench 108 is b, then b>c.

[0050] In some embodiments, in combination Figure 1 As shown, the columnar doped region 102 extends downward from the upper surface of the epitaxial layer 100 into the epitaxial layer 100, and extends to the lower surface of the epitaxial layer 100. In this embodiment, the columnar doped region 102 extends downward from the upper surface of the epitaxial layer 100 to the lower surface of the epitaxial layer 100, and the conductivity type of the columnar doped region 102 is opposite to that of the epitaxial layer 100, so as to form a stable super junction structure.

[0051] Optionally, combined Figure 1 As shown, the width of the first trench 106 is smaller than the width of the columnar doping region 102 , and the width of the second trench 108 is larger than the width of the columnar doping region 102 .

[0052] In this embodiment, the first trench 106 is located between two adjacent columnar doping regions 102, and the width of the first trench 106 is less than the width of the columnar doping region 102. By making the width of the first trench 106 less than the width of the columnar doping region 102, it is helpful to form a channel more effectively under gate control, reduce the capacitance from the gate to the drain, increase the switching speed, and reduce the switching loss. The second trench 108 is located between two adjacent first trenches 106, and the width of the second trench 108 is greater than the width of the columnar doping region 102. By making the width of the second trench 108 greater than the width of the columnar doping region 102 and the width of the second trench 108 greater than the width of the first trench 106, the electric field distribution is optimized, the local electric field strength is reduced, and the breakdown voltage is increased. Specifically, the wide trench design of the second trench 108 helps to form a more uniform electric field distribution inside the device, reduce the local electric field concentration, thereby optimizing the electric field distribution and reducing the failure risk of the device under high voltage. At the same time, the breakdown voltage of the device is improved without significantly increasing the on-resistance.

[0053] For example, Figure 1 As shown, the width of the first trench 106 is c, the width of the second trench 108 is b, and the width of the columnar doping region 102 is a, then a>b>c.

[0054] Optionally, combined Figure 1 As shown, the width b of the second trench 108 is in the range of 4 μm (micrometer) < b ≤ 5.3 μm. Exemplarily, the width of the columnar doping region 102 is 4 μm, and the width of the second trench 108 is 5 μm.

[0055] Optionally, combined Figure 1 As shown, the second trench 108 is adjacent to the columnar doped region 102 and is located above the columnar doped region 102 .

[0056] In this embodiment, by locating the second trench 108 above the columnar doping region 102 and adjacent to the columnar doping region 102, the second trench 108 can interact more closely with the columnar doping region 102, thereby optimizing the electric field distribution and charge balance inside the device. Since the second trench 108 is closely adjacent to the columnar doping region 102, the flow path of the current inside the device is smoother, reducing unnecessary resistance and heat generation, thereby improving the power density and efficiency of the device. At the same time, the trench gate 110 in the second trench 108 can form a closer electric field coupling with the columnar doping region 102 below. Since the trench gate 110 structure itself has a smaller gate capacitance, the switching speed of the device is faster. The adjacent layout of the second trench 108 and the columnar doping region 102 further reduces the gate-to-drain capacitance, thereby further improving the switching speed and responsiveness of the device.

[0057] Optionally, combined Figure 1 As shown, the trench gate 110 located in the second trench 108 covers a portion of the bottom adjacent to the sidewall of the second trench 108 .

[0058] In this embodiment, the trench gate 110 covers the bottom portion adjacent to the sidewall of the second trench 108, increasing the contact area between the gate and the trench, thereby increasing the gate's control capability over the channel region (which can be understood as the first trench 106 and the second trench 108 in this application). The enhanced gate control capability helps to reduce the threshold voltage, increase the switching speed of the device, improve the current handling capability of the device, and reduce the on-resistance and power consumption of the device. In high-voltage applications, increasing the contact area between the gate and the channel region helps to reduce local electric field concentration and improve the breakdown voltage and reliability of the device.

[0059] Optionally, combined Figure 1 As shown, the trench gate superjunction metal oxide semi-field effect transistor 10 further includes a well region 112 and a source and drain region 114. The well region 112 is located in the trench layer 104 and between the first trench 106 and the second trench 108. The source and drain region 114 is located in the trench layer 104 and above the well region 112.

[0060] In this embodiment, the well region 112 refers to a specific doped region formed by an ion implantation or diffusion process. The doping type (N-type or P-type) of the well region 112 depends on the type of the trench gate super junction metal oxide semi field effect transistor 10. The function of the well region 112 is to provide a region of a different conductivity type from the source and drain region 114 to form a PN junction with the source and drain region 114, thereby controlling the switching behavior of the trench gate super junction metal oxide semi field effect transistor 10. The well region 112 has the same conductivity type as the columnar doping region 102. The source and drain region 114 is a heavily doped region formed by further performing an ion implantation or diffusion process in the well region 112. The source and drain region 114 has a different conductivity type from the well region 112. The function of the source and drain region 114 is to provide a path for current flow and allow electrons or holes to flow from the source to the drain when the trench gate super junction metal oxide semi field effect transistor 10 is turned on.

[0061] In this embodiment, the presence of the well region 112 enables the trench gate super junction metal oxide semi field effect transistor 10 to more accurately control the current flow between the source and drain regions 114. The PN junction formed between the well region 112 and the source and drain regions 114 helps to increase the breakdown voltage of the trench gate super junction metal oxide semi field effect transistor 10. Under reverse bias conditions, the PN junction will deplete the charge and withstand most of the voltage drop, thereby protecting the device from high voltage damage. In addition, since the PN junction between the well region 112 and the source and drain regions 114 will form a high resistance state when reverse biased, the leakage current from the drain to the source of the trench gate super junction metal oxide semi field effect transistor 10 in the off state can be significantly reduced.

[0062] Optionally, combined Figure 1 As shown, the trench gate superjunction metal oxide semi-field effect transistor 10 further includes a dielectric layer 116. The dielectric layer 116 is located above the trench layer 104 and a portion of the dielectric layer 116 is located in the second trench 108.

[0063] In this embodiment, the dielectric layer 116 is located above the trench layer 104 to play an insulating and protective role, ensuring that the trench gate super junction metal oxide semi field effect transistor 10 can operate reliably under various working environments. The dielectric layer 116 is usually made of a material with a high dielectric constant, such as silicon dioxide (SiO2), silicon nitride (SiN), etc. The presence of the dielectric layer 116 significantly enhances the insulation performance of the trench gate super junction metal oxide semi field effect transistor 10, effectively isolates the charge exchange between the gate and the source and drain regions 114, reduces the gate leakage current, and improves the reliability and service life of the device. In this embodiment, part of the dielectric layer 116 is located in the second trench 108, so that the dielectric layer 116 can more accurately control the electric field distribution, optimize the electric field strength in the channel region, reduce the local electric field peak, and improve the breakdown voltage and reliability of the device.

[0064] Optionally, combined Figure 1 As shown, the trench gate superjunction metal oxide semi-field effect transistor 10 further includes a metal layer 118. The metal layer 118 is located above the dielectric layer 116 and a portion of the metal layer 118 is located in the second trench 108. A connecting column 120 is formed on the lower surface of the metal layer 118, and the connecting column 120 extends downward from the lower surface of the metal layer 118 through the dielectric layer 116 and the source and drain regions 114 to the well region 112 in sequence.

[0065] In this embodiment, the metal layer 118 is located above the dielectric layer 116 and is used for other metal interconnections. A connection column 120 is formed on the lower surface of the metal layer 118. The connection column 120 extends downward, passes through the dielectric layer 116 and the source and drain regions 114 in sequence, and forms an electrical connection with the well region 112, effectively reducing the parasitic resistance between the metal layer 118 and the well region 112, and realizing a direct, low-resistance path between the metal layer 118 and the well region 112, which helps to reduce energy loss during signal transmission and improve the overall performance of the circuit. Because the connection column 120 provides a low-resistance path, the trench gate superjunction metal oxide semi-field effect transistor 10 can transmit current more efficiently in the on state, thereby enhancing the current driving capability of the device.

[0066] Optionally, combined Figure 1 As shown, the trench gate superjunction metal oxide semi-field effect transistor 10 further includes a substrate 122. The substrate 122 is located below the epitaxial layer 100. The substrate 122 has the same conductivity type as the epitaxial layer 100.

[0067] In this embodiment, the substrate 122 is located below the epitaxial layer 100, and serves as a conductive substrate of the trench gate superjunction metal oxide semi-field effect transistor 10 device, providing a stable conductive channel for the device. The substrate 122 ensures the smooth flow of current in the device, thereby ensuring the normal operation of the device. Since the substrate 122 has the same conductivity type as the epitaxial layer 100, it helps to reduce the interface resistance and charge accumulation effect, thereby improving the current driving capability and switching speed of the device, while reducing the power consumption and heat generation of the device.

[0068] In a specific application, such as Figure 7 As shown, a trench gate superjunction metal oxide semi-field effect transistor 10 includes a substrate 122, an epitaxial layer 100, a columnar doped region 102, a trench layer 104, a first trench 106, a second trench 108, a trench gate 110, a well region 112, a source and drain region 114, a dielectric layer 116 and a metal layer 118. From bottom to top, the substrate 122, the epitaxial layer 100, the trench layer 104, the dielectric layer 116 and the metal layer 118 are arranged in sequence. The substrate 122 is located below the epitaxial layer 100 and has the same conductivity type as the epitaxial layer 100. The columnar doped region 102 is spaced apart in the epitaxial layer 100 and extends downward from the upper surface of the epitaxial layer 100 into the epitaxial layer 100, and extends to the lower surface of the epitaxial layer 100. The conductivity type of the columnar doped region 102 is different from that of the epitaxial layer 100. The width of the columnar doped region 102 is a. The trench layer 104 is located above the epitaxial layer 100. The first trench 106 is located in the trench layer 104 and between two adjacent columnar doped regions 102, and the width of the first trench 106 is c. The second trench 108 is located in the trench layer 104, adjacent to the columnar doped region 102 and located above the columnar doped region 102. The width of the second trench 108 is b, a>b>c. The trench gate 110 is located in the first trench 106 and the second trench 108 respectively and extends downward from the opening of the trench to the bottom of the trench, wherein the trench gate 110 located in the second trench 108 covers a portion of the bottom adjacent to the sidewall of the second trench 108. The well region 112 is located in the trench layer 104 and between the first trench 106 and the second trench 108. The source and drain region 114 is located in the trench layer 104 and above the well region 112. The dielectric layer 116 is located above the trench layer 104 and a portion of the dielectric layer 116 is located in the second trench 108. The metal layer 118 is located above the dielectric layer 116 and a portion of the metal layer 118 is located in the second trench 108. A connecting column 120 is formed on the lower surface of the metal layer 118, and the connecting column 120 extends downward from the lower surface of the metal layer 118 through the dielectric layer 116 and the source and drain regions 114 to the well region 112 in sequence.

[0069] In some embodiments, Figure 2As shown, a method for manufacturing a trench gate super junction metal oxide semi-conductor field effect transistor is provided, which is used for the trench gate super junction metal oxide semi-conductor field effect transistor described in the above embodiment.

[0070] The manufacturing method includes:

[0071] S201 , etching deep trenches on the epitaxial layer and filling them with doping materials of different conductivity type from the epitaxial layer to form columnar doping regions.

[0072] In this step, if Figure 3 As shown, a deep trench is first formed on the epitaxial layer 100 by photolithography and etching processes. Then, the deep trench is filled with a doping material of opposite conductivity type to the epitaxial layer 100 (e.g., a P-type doping material is filled on an N-type epitaxial layer 100, or vice versa) to form a columnar doping region 102 (i.e., a P-type column or an N-type column), thereby forming a super junction structure. The super junction structure can provide a low-resistance current path when the device is turned on, and can jointly withstand reverse bias in the off state, thereby improving the breakdown voltage and current handling capability of the device.

[0073] S202, growing a thin oxide layer as a trench layer on the epitaxial layer formed with the columnar doping region.

[0074] In this step, a thin oxide layer may be grown by thermal oxidation on the epitaxial layer 100 including the columnar doped regions 102. The thin oxide layer will serve as the trench layer 104 in the subsequent process. The thin oxide layer not only provides good insulation properties, but also serves as an etching barrier layer in the subsequent process so as to accurately control the size and shape of the trench.

[0075] S203, etching a first trench and a second trench on the trench layer.

[0076] The first trench is located between two adjacent columnar doping regions, the second trench is located between two adjacent first trenches, and the width of the second trench is greater than the width of the first trench.

[0077] In this step, if Figure 3 As shown, two grooves of width, namely, a first groove 106 and a second groove 108, are formed on the groove layer 104 by photolithography and etching processes to form the gate of the device. The second groove 108 is located between two adjacent first grooves 106 and has a larger width to increase the effective channel density of the device, reduce the specific on-resistance, optimize the electric field distribution of the device, and increase the breakdown voltage of the device, thereby improving the compromise characteristics of the on-resistance and breakdown voltage of the device.

[0078] S204, after growing a gate oxide layer on the trench layer etched with the first trench and the second trench, performing polysilicon deposition.

[0079] In this step, if Figure 4As shown in FIG. 1 , a gate oxide layer 124 is grown on the etched trench layer 104 to isolate the gate from the channel region. Figure 5 As shown, polysilicon 126 is deposited to fill the entire trench area in preparation for forming the gate of the device. The gate oxide layer 124 provides good insulation performance, and the polysilicon 126 gate acts as the control electrode of the device, controlling the conductivity of the channel region by changing its potential.

[0080] S205 , etching the polysilicon to form trench gates in the first trench and the second trench.

[0081] The trench gate extends downward from the opening of the trench to the bottom of the trench.

[0082] In this step, if Figure 6 As shown, the excess polysilicon 126 material is removed by etching process, and only the polysilicon 126 in the first trench 106 and the second trench 108 is retained as the trench gate 110. The trench gate 110 structure has a smaller parasitic capacitance and a higher switching speed. Since the trench gate 110 is located above the channel region, the conductivity of the channel region can be more effectively controlled to improve the performance of the device.

[0083] The manufacturing method of the trench gate super junction metal oxide semi field effect transistor provided by the embodiment of the present disclosure can be used to manufacture the trench gate super junction metal oxide semi field effect transistor described in the above embodiment. Therefore, the technical effects possessed by the trench gate super junction metal oxide semi field effect transistor described in the above embodiment are all possessed by this application and will not be repeated here. In addition, the present application can improve the effective channel density of the device and reduce the specific on-resistance without adding additional process steps, while optimizing the electric field distribution of the device, increasing the breakdown voltage of the device, and improving the compromise characteristics of the on-resistance and breakdown voltage of the device, so that the manufacturing method provided by the embodiment of the present disclosure can be compatible with the existing semiconductor manufacturing process flow and is easy to achieve large-scale production.

[0084] Optionally, etching polysilicon to form trench gates in the first trench and the second trench includes: etching polysilicon in a direction perpendicular to the epitaxial layer to form trench gates in the first trench and the second trench, and the trench gate located in the second trench covers a portion of the bottom adjacent to the side wall of the second trench.

[0085] In this embodiment, if Figure 5 and Figure 6As shown, dry etching can be used to etch in a direction perpendicular to the epitaxial layer 100, which can ensure that the shape and size of the trench gate 110 are precisely controlled. Since the deposition thickness of the polysilicon 126 is constant (e.g., the thickness of the polysilicon 126 is 0.8 μm) and isotropically deposited on the surface, and the depth of the second trench 108 (e.g., 2.5 μm) is thicker than the deposition thickness of the polysilicon 126, and the width of the second trench 108 is 5 μm, which is many times the deposition thickness of the polysilicon 126, there will be a gap in the middle area of ​​the second trench 108 when the polysilicon 126 is deposited, that is, Figure 5 When the polysilicon 126 is subsequently etched, dry etching is used to etch the polysilicon 126 only in a direction perpendicular to the epitaxial layer 100, so that the polysilicon 126 on the side wall of the second trench 108 is retained to form the final morphology, that is, the trench gate 110 in the second trench 108 covers the bottom portion adjacent to the side wall of the second trench 108, as shown in FIG. Figure 6 shown.

[0086] In this embodiment, the trench gate 110 formed in the second trench 108 covers a portion of the bottom adjacent to the sidewall to optimize the electric field distribution inside the device, disperse the electric field more effectively, and improve the voltage resistance and reliability of the device.

[0087] In some embodiments, in combination Figure 8 As shown, another method for manufacturing a trench gate super junction metal oxide semi-conductor field effect transistor is provided, comprising:

[0088] S801, growing an epitaxial layer on a substrate by using an epitaxial growth technique.

[0089] In this step, if Figure 3 As shown, an epitaxial layer 100 is grown on a substrate 122 by epitaxial growth technology. The conductivity type of the epitaxial layer 100 is the same as the conductivity type of the substrate 122. The thickness of the epitaxial layer 100 is directly related to the breakdown voltage level of the device. The higher the voltage platform level, the thicker the epitaxial layer 100. The specific thickness of the epitaxial layer 100 needs to be specifically set according to actual needs, and this application does not limit it.

[0090] S802, etching deep trenches on the epitaxial layer and filling them with doping materials of different conductivity type from the epitaxial layer to form columnar doping regions.

[0091] In this step, if Figure 3 As shown, a deep trench is etched on the epitaxial layer 100 and filled with a doping material having a conductivity type different from that of the epitaxial layer 100 to form a columnar doped region 102. The doping concentration of the doping material is related to the ion concentration of the epitaxial layer 100. The doping concentration of the doping material needs to be specifically set according to actual needs, and this application does not limit it.

[0092] S803, grow a thin oxide layer.

[0093] In this step, a thin oxide layer is grown on the epitaxial layer 100 having the columnar doped regions 102. The thickness of the thin oxide layer may be 250 nm (nanometers) to 350 nm, and the thin oxide layer is used to protect the surface and serve as a masking layer for subsequent implantation. For example, the thickness of the thin oxide layer is 300 nm.

[0094] S804, performing a first conductive ion implantation and forming a well region through a high temperature annealing process.

[0095] In this step, a first conductive ion implantation is performed after a thin oxide layer is grown, and a well region 112 is formed by a high temperature annealing process. Figure 3 Wherein, the conductivity type of the first conductive ion is the same as that of the doping material.

[0096] S805, etching a first trench and a second trench.

[0097] In this step, if Figure 3 As shown, a first trench 106 and a second trench 108 are etched on the epitaxial layer 100 having the well region 112. The first trench 106 is located between two adjacent columnar doping regions 102, and the second trench 108 is located between two adjacent first trenches 106. The width of the second trench 108 is greater than that of the first trench 106.

[0098] S806, performing sacrificial oxidation to repair damage on the surfaces of the first trench and the second trench.

[0099] S807, growing a gate oxide layer and then depositing polysilicon.

[0100] In this step, a gate oxide layer 124 is grown on the surface of the trench layer 104 where the first trench 106 and the second trench 108 are etched. Figure 4 As shown, the thickness of the gate oxide layer 124 is 100nm to 150nm. After the gate oxide layer 124 is grown, polysilicon deposition is performed to grow polysilicon 126. Figure 5 As shown, it is prepared for the subsequent formation of the gate.

[0101] S808 , performing polysilicon etching in a direction perpendicular to the epitaxial layer to form trench gates in the first trench and the second trench.

[0102] In this step, if Figure 6 As shown, the polysilicon 126 is etched in a direction perpendicular to the epitaxial layer 100 to form a trench gate 110 in the first trench 106 and the second trench 108, wherein the trench gate 110 extends downward from the opening of the trench to the bottom of the trench, and the trench gate 110 located in the second trench 108 covers a portion of the bottom adjacent to the sidewall of the second trench 108.

[0103] S809, grow a thin oxide layer.

[0104] In this step, a thin oxide layer with a thickness of 250 nm to 350 nm is grown on the surface of the trench layer 104 where the trench gate 110 is formed.

[0105] S810, performing a second conductive ion implantation and annealing to form source and drain regions.

[0106] In this step, if Figure 7 As shown, after the thin oxide layer is grown, a second conductive ion implantation is performed and annealing is performed to form the source and drain regions 114 , and the source and drain regions 114 are located above the well region 112 .

[0107] S811, growing a dielectric layer and etching to form a contact hole.

[0108] In this step, if Figure 7 As shown, after the source and drain regions 114 are formed, a dielectric layer 116 is grown. After the dielectric layer 116 is formed, it is etched to form contact holes.

[0109] S812, depositing a metal layer on the dielectric layer, and forming connecting pillars through photolithography and etching processes to complete the metallization process of the device.

[0110] In this step, if Figure 7 As shown, a metal layer 118 is deposited on the surface of the dielectric layer 114, and the thickness of the metal layer 118 can be 4-5 μm. A connecting column 120 is formed by photolithography and etching processes. The connecting column 120 extends downward from the lower surface of the metal layer 118 through the dielectric layer 116 and the source and drain regions 114 in sequence to the well region 112, and is located in the contact hole.

[0111] In a practical application, taking the manufacture of an N-type trench gate superjunction metal oxide semi-field effect transistor as an example, the specific steps include: forming an N-type epitaxial layer on an N-type substrate by epitaxial growth technology; etching a deep trench on the N-type epitaxial layer and filling it with P-type material to form a columnar doped region, i.e., a P column; growing a 300nm thin oxide layer on the surface of the epitaxial layer; performing P-type ion implantation; forming a P-type well region by a high temperature annealing process; etching a first trench and a second trench; wherein the first trench is located between two adjacent columnar doped regions, the second trench is located between two adjacent first trenches, and the width of the second trench is greater than that of the first trench. The width of the groove is determined by the following steps: performing sacrificial oxidation to repair the damage on the surface of the first groove and the second groove; growing a gate oxide layer on the surface of the groove, followed by polysilicon deposition; etching polysilicon in a direction perpendicular to the epitaxial layer to form a trench gate in the first groove and the second groove to form a gate electrode; after growing a thin oxide layer on the surface again, performing N-type ion implantation and annealing to form a source and drain region; growing an interlayer dielectric layer and etching to form a contact hole; depositing aluminum metal on the interlayer dielectric layer to form a 5μm metal layer; forming metal interconnects, i.e., connecting pillars, through photolithography and etching processes to complete the metallization process of the device.

[0112] In a practical application, taking the preparation of a P-type trench gate superjunction metal oxide semi-field effect transistor as an example, the specific steps include: forming a P-type epitaxial layer on a P-type substrate by epitaxial growth technology; etching a deep trench on the P-type epitaxial layer and filling it with N-type material to form a columnar doped region, namely, an N-column; growing a 300nm thin oxide layer on the surface of the epitaxial layer; performing N-type ion implantation; forming an N-type well region by a high temperature annealing process; etching a first trench and a second trench; wherein the first trench is located between two adjacent columnar doped regions, the second trench is located between two adjacent first trenches, and the width of the second trench is greater than that of the first trench. The width of the groove is determined by the following steps: performing sacrificial oxidation to repair the damage on the surface of the first groove and the second groove; growing a gate oxide layer on the surface of the groove, followed by polysilicon deposition; etching polysilicon in a direction perpendicular to the epitaxial layer to form a trench gate in the first groove and the second groove to form a gate electrode; after growing a thin oxide layer on the surface again, performing P-type ion implantation and annealing to form a source and drain region; growing an interlayer dielectric layer and etching to form a contact hole; depositing aluminum metal on the interlayer dielectric layer to form a 5μm metal layer; forming metal interconnects, i.e., connecting pillars, through photolithography and etching processes to complete the metallization process of the device.

[0113] In some embodiments, in combination Fig. 9 As shown, a semiconductor device 2 is provided, comprising the metal oxide semi-conductor field effect transistor as described in the above embodiment.

[0114] The semiconductor device 2 provided in the embodiment of the present disclosure includes the metal oxide semiconductor field effect transistor as described in the above embodiment. Therefore, the technical effects possessed by the trench gate super junction metal oxide semiconductor field effect transistor 10 described in the above embodiment are also possessed by this application and will not be repeated here.

[0115] The above description and the accompanying drawings sufficiently illustrate the embodiments of the present disclosure to enable those skilled in the art to practice them. Other embodiments may include structural and other changes. The embodiments represent only possible variations. Unless explicitly required, individual components and functions are optional, and the order of operations may vary. Portions and features of some embodiments may be included in or replace portions and features of other embodiments. The embodiments of the present disclosure are not limited to the structures described above and shown in the accompanying drawings, and various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A trench gate superjunction metal oxide semi-field effect transistor, characterized in that: include: Epitaxial layer; A columnar doped region is spaced apart in the epitaxial layer and extends downward from the upper surface of the epitaxial layer into the epitaxial layer, and the conductivity type of the columnar doped region is different from that of the epitaxial layer; a trench layer, located above the epitaxial layer; A first trench is located in the trench layer and between two adjacent columnar doping regions; A second groove is located in the groove layer and between two adjacent first grooves, and a width of the second groove is greater than a width of the first groove; The trench gates are respectively located in the first trench and the second trench and extend downward from the openings of the trenches to the bottoms of the trenches.

2. The metal oxide semi-field effect transistor according to claim 1, characterized in that: The width of the first trench is smaller than the width of the columnar doping region, and the width of the second trench is larger than the width of the columnar doping region.

3. The metal oxide semi-field effect transistor according to claim 1, characterized in that: The second trench is adjacent to the columnar doping region and is located above the columnar doping region.

4. The metal oxide semi-field effect transistor according to claim 1, characterized in that: The trench gate located in the second trench covers a portion of the bottom adjacent to the sidewall of the second trench.

5. The metal oxide semi-conductor field effect transistor according to any one of claims 1 to 4, characterized in that: Also includes: A well region located in the trench layer and between the first trench and the second trench; The source and drain regions are located in the trench layer and above the well region.

6. The metal oxide semi-field effect transistor according to claim 5, characterized in that: Also includes: The dielectric layer is located above the trench layer and a portion of the dielectric layer is located in the second trench.

7. The metal oxide semi-field effect transistor according to claim 6, characterized in that: Also includes: A metal layer is located above the dielectric layer and a portion of the metal layer is located in the second trench; A connection column is formed on the lower surface of the metal layer, and the connection column extends downward from the lower surface of the metal layer through the dielectric layer and the source and drain regions in sequence to the well region.

8. A method for manufacturing a trench gate super junction metal oxide semi field effect transistor, used for manufacturing the trench gate super junction metal oxide semi field effect transistor according to any one of claims 1 to 7, characterized in that: The manufacturing method includes: Etching deep trenches on the epitaxial layer and filling them with doping materials of different conductivity type from the epitaxial layer to form columnar doped regions; Growing a thin oxide layer as a trench layer on the epitaxial layer having the columnar doped regions; Etching a first trench and a second trench on the trench layer; wherein the first trench is located between two adjacent columnar doping regions, the second trench is located between two adjacent first trenches, and the width of the second trench is greater than the width of the first trench; After growing a gate oxide layer on the trench layer etched with the first trench and the second trench, polysilicon is deposited; The polysilicon is etched to form trench gates in the first trench and the second trench; wherein the trench gates extend downward from the opening of the trench to the bottom of the trench.

9. The manufacturing method according to claim 8, characterized in that: Etching polysilicon to form a trench gate in the first trench and the second trench, comprising: Polysilicon is etched in a direction perpendicular to the epitaxial layer to form trench gates in the first trench and the second trench, and the trench gate in the second trench covers a portion of the bottom adjacent to the sidewall of the second trench.

10. A semiconductor device, characterized in that: include: A metal oxide semi-field effect transistor as claimed in any one of claims 1 to 7.

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