Longitudinal conduction normally-off type diamond power transistor and preparation method thereof

Abstract

The invention discloses a longitudinal conduction normally-off type diamond power transistor and a preparation method thereof, and relates to the technical field of semiconductor power devices. The device comprises the following structures: a p-type low-resistance diamond single crystal substrate; the first p-type high-resistance diamond drift layer is located on the upper surface of the p-type low-resistance diamond single crystal substrate; the p-type low-resistance diamond insertion layer is located on the upper surface of the first p-type high-resistance diamond drift layer; the second p-type high-resistance diamond drift layer is located on the upper surface of the p-type low-resistance diamond insertion layer; and the p-type low-resistance diamond cap layer is located on the upper surface of the second p-type high-resistance diamond drift layer. The transistor provided by the invention is provided with the composite epitaxial layer with a multi-layer structure, wherein the low-resistance insertion layer can reduce the on resistance and improve the threshold voltage; and the high-resistance drift layer can bear higher voltage.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor power devices, and in particular relates to a vertically conductive normally-off diamond power transistor and a preparation method thereof. Background Art

[0002] Diamond power devices include diodes and transistors, which are mainly divided into two major technical routes: lateral and longitudinal conduction. Vertical conduction devices can improve the withstand voltage by changing the thickness of the drift layer while keeping the device size unchanged, and alleviate the premature breakdown caused by the electric field edge collection effect at the gate edge in lateral devices. The electric field peak position of the vertical device is far away from the device surface, which effectively suppresses the effect of the trap state and reduces the dynamic on-resistance. Compared with lateral devices, the current flowing out in the longitudinal direction can withstand higher power density, the electric field distribution is relatively more uniform, and the current distribution can be more extended, thus having better heat dissipation characteristics than lateral devices. Therefore, exploring new types of vertical conduction devices is expected to overcome the challenges of lateral devices in power handling capabilities, and is a very important topic in academia and industry.

[0003] In recent years, diamond field effect transistors (FETs), including metal semiconductor field effect transistors (MESFETs), metal-oxide-semiconductor field effect transistors (MOSFETs), and junction gate field effect transistors (JFETs), have been widely studied. Since there has been no breakthrough in the n-type doping of diamond materials, there are currently two main types of MOSFETs with two-dimensional hole gas on the hydrogen-terminated surface as the channel and MESFETs with p-type doped diamond as the channel. Among them, with a series of key technological breakthroughs such as the highly stable Al2O3 gate dielectric layer, MOSFETs based on two-dimensional hole gas channels on the hydrogen-terminated surface have lower gate leakage current and thermal stability, but this device is mainly aimed at the fields of high fT / fmax and high power density microwave electronics and diamond logic circuits.

[0004] Diamond MESFET and JFET are mainly used as power switching devices. The metal or heterojunction gate controls the current between the drain and source electrodes by regulating the on and off of the semiconductor channel layer below the gate through the depletion layer under the bias voltage. In 1989, Shiomi et al. first confirmed the current modulation effect of Al Schottky gate on boron-doped p-type channel layer. However, the gate electrode did not achieve complete depletion of the channel and exhibited a normally-on working mode. In 2009, Pt was used as Schottky gate at a doping concentration of 1E 15 cm -3Diamond-made MESFETs exhibit good electrical properties in the temperature range of 200°C to 500°C. However, the threshold voltage of the device is still 2.1 V, showing a normally-on working mode. However, the failure safety perspective of the power electronic circuit requires that the power switching device exhibit a normally-off working mode (the channel is in the off state when the gate voltage is zero volts). The threshold voltage regulation of MESFET devices faces great challenges. On the one hand, in order to achieve a lower forward on-resistance, a thicker channel layer and a relatively large doping concentration are required. On the other hand, the high interface state density on the oxygen-terminated boron-doped diamond surface causes the Fermi level to be pinned at the metal / semiconductor interface (about 1.2 eV), and even metals with different work functions can only obtain similar Schottky barrier height values. Therefore, the metal gate has relatively weak ability to regulate the threshold voltage of the device.

[0005] In summary, the diamond power transistor structure in the present invention is proposed. Summary of the invention

[0006] In view of the deficiencies in the prior art, the purpose of the present invention is to provide a vertical conduction normally-off diamond power transistor and a preparation method thereof, and to prepare a vertical conduction diamond normally-off transistor using a MOS structure depletion channel to avoid the challenges faced by the preparation of n-type doped diamond; at the same time, in order to reduce the on-resistance and increase the threshold voltage, a high-concentration doped low-resistance diamond layer is inserted into the high-resistance drift layer, and the high-resistance drift layer can withstand a higher voltage.

[0007] In order to achieve the above object, the present invention adopts the following technical solution:

[0008] In a first aspect, the present invention provides a vertically conductive normally-off diamond power transistor, comprising a p-type low-resistance diamond single crystal substrate;

[0009] A first p-type high-resistance diamond drift layer, located on the upper surface of the p-type low-resistance diamond single crystal substrate;

[0010] A p-type low-resistance diamond insertion layer, located on the upper surface of the p-type high-resistance diamond drift layer 1;

[0011] A second p-type high-resistance diamond drift layer, located on the upper surface of the p-type low-resistance diamond insertion layer;

[0012] A p-type low-resistance diamond cap layer, located on the upper surface of the second p-type high-resistance diamond drift layer;

[0013] An ohmic contact electrode is located on the upper surface of the p-type low-resistance diamond cap layer and the lower surface of the p-type low-resistance diamond single crystal substrate;

[0014] A gate dielectric layer is located on the upper surface of the groove structure, wherein the groove structure is formed by the p-type low-resistance diamond insertion layer, the second p-type high-resistance diamond drift layer, both sides of the p-type low-resistance diamond cap layer and the upper surface of the first p-type high-resistance diamond drift layer;

[0015] The Schottky gate electrode is located on the surface of the gate dielectric layer.

[0016] In addition, the structure of a vertically conductive normally-off diamond power transistor provided by the present invention may also include: a p-type low-resistance diamond single crystal substrate;

[0017] A first p-type high-resistance diamond drift layer, located on the upper surface of the p-type low-resistance diamond single crystal substrate;

[0018] A p-type low-resistance diamond insertion layer and a low-concentration doped p-type high-resistance drift layer 2 are arranged alternately up and down, wherein the upper surface of the p-type high-resistance diamond drift layer 1 is arranged with a p-type low-resistance diamond insertion layer, and the uppermost layer arranged alternately up and down is a p-type high-resistance diamond drift layer 2;

[0019] A p-type low-resistance diamond cap layer, located on the upper surface of the second p-type high-resistance diamond drift layer;

[0020] An ohmic contact electrode is located on the upper surface of the p-type low-resistance diamond cap layer and the lower surface of the p-type low-resistance diamond single crystal substrate;

[0021] A gate dielectric layer is located on the upper surface of the groove structure, wherein the groove structure is formed by the p-type low-resistance diamond insertion layer, the second p-type high-resistance diamond drift layer, both sides of the p-type low-resistance diamond cap layer and the upper surface of the first p-type high-resistance diamond drift layer;

[0022] The Schottky gate electrode is located on the surface of the gate dielectric layer.

[0023] In a second aspect, the present invention provides a method for preparing the vertically conductive normally-off diamond power transistor, comprising the following steps:

[0024] S1, sequentially growing a p-type high-resistance diamond drift layer 1, a p-type low-resistance diamond insertion layer, a p-type high-resistance diamond drift layer 2 and a p-type low-resistance diamond cap layer on a p-type low-resistance diamond single crystal substrate; or growing a p-type high-resistance diamond drift layer 1 on a p-type low-resistance diamond single crystal substrate, then alternately growing a p-type low-resistance diamond insertion layer 3 and a p-type high-resistance diamond drift layer 2, and finally growing a p-type low-resistance diamond cap layer on the upper surface of the p-type high-resistance diamond drift layer 2;

[0025] S2, depositing a dielectric layer on the upper surface of the p-type low-resistance diamond cap layer, and forming a pattern mask by photolithography;

[0026] S3, performing dry etching on both sides of the structure obtained in step S2 to the upper surface of the p-type high-resistance diamond drift layer 1 to form a groove structure;

[0027] S4, depositing a gate dielectric layer in the groove structure obtained in step S3, and removing the mask at the same time;

[0028] S5, depositing metal on the lower surface of the p-type low-resistance diamond single crystal substrate and the upper surface of the p-type low-resistance diamond cap layer to form an ohmic contact electrode;

[0029] S6. Depositing metal on the gate dielectric layer obtained in step S4 to form a Schottky gate electrode.

[0030] As a preferred embodiment of the technical solution of the present invention, in step S1, the p-type low-resistance diamond single crystal substrate is a single crystal diamond or polycrystalline diamond obtained by homogeneous or heterogeneous epitaxy, and the boron doping concentration is 10 19 ~10 21 cm -3 .

[0031] As a preferred embodiment of the technical solution of the present invention, in step S1, the p-type high-resistance diamond drift layer 1 and the p-type high-resistance diamond drift layer 2 are both boron-doped diamond epitaxial layers with a thickness of 10 nm to 20 μm and a boron doping concentration of 10 14 ~10 18 cm -3 .

[0032] As a preferred embodiment of the technical solution of the present invention, in step S1, the p-type low-resistance diamond insertion layer is a single-layer or multi-layer boron-doped diamond epitaxial layer with a thickness of 10 nm to 20 μm, and the boron doping concentration can be between 10 and 20 μm. 16 ~10 19 cm -3 .

[0033] As a preferred embodiment of the technical solution of the present invention, in step S1, the growth adopts one of microwave plasma chemical vapor deposition, direct current plasma jet chemical vapor deposition or pyrolysis chemical vapor deposition.

[0034] As a preferred embodiment of the technical solution of the present invention, in step S4, the gate dielectric layer is at least one of aluminum oxide, silicon oxide, and silicon nitride, and has a thickness of 1 nm to 10 μm.

[0035] As a preferred embodiment of the technical solution of the present invention, in step S5, the material of the ohmic contact electrode is one of Ti / Pt / Au alloy, Ti / Ni / Au alloy or Ti / Mo / Au alloy; the material of the Schottky gate electrode is one of Zr / Au alloy, Pt / Au alloy or W / Au alloy.

[0036] As a preferred embodiment of the technical solution of the present invention, in step S5 and step S6, the ohmic contact electrode and the Schottky gate electrode are formed by electron beam evaporation, physical vapor deposition or magnetron sputtering.

[0037] Compared with the prior art, the present invention has the following beneficial effects:

[0038] The invention provides a method for preparing a high-performance vertical conduction diamond transistor. The low-resistance insertion layer in the multi-layer composite epitaxial layer can reduce the on-resistance and increase the threshold voltage, while the high-resistance drift layer can withstand a higher voltage, thereby increasing the service life of the transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 A schematic diagram of the structure of the device for preparing step S1 provided in Example 1 of the present invention;

[0040] Figure 2 A schematic diagram of the structure of the device for preparing step S2 provided in Example 1 of the present invention;

[0041] Figure 3 A schematic diagram of the structure of the device for preparing step S3 provided in Example 1 of the present invention;

[0042] Figure 4 A schematic diagram of the structure of the device for preparing step S4 provided in Example 1 of the present invention;

[0043] Figure 5 A schematic diagram of the structure of the device for preparing step S5 provided in Example 1 of the present invention;

[0044] Figure 6 A schematic diagram of the structure of the device for preparing step S6 provided in Example 1 of the present invention;

[0045] Figure 7 This is a schematic diagram of the device structure provided in Example 2 of the present invention.

[0046] Among them, 1. p-type low-resistance diamond single crystal substrate; 2. p-type high-resistance diamond drift layer 1; 3. p-type low-resistance diamond insertion layer; 4. p-type high-resistance diamond drift layer 2; 5. p-type low-resistance diamond cap layer; 6. gate dielectric layer; 7. ohmic contact electrode; 8. Schottky gate electrode. DETAILED DESCRIPTION

[0047] The present invention is described in detail below in conjunction with specific drawings and embodiments. The examples described below are only preferred embodiments of the present invention. It should be noted that the following description is only for the purpose of explaining the present invention and does not limit the present invention in any form. Any simple modification, equivalent changes and modifications made to the embodiments according to the technical essence of the present invention are within the scope of the technical solution of the present invention.

[0048] The present invention provides a method for preparing a vertically conductive normally-off diamond power transistor, which generally comprises the following steps:

[0049] S1, providing a p-type low-resistance diamond single crystal substrate 1, and growing a composite epitaxial layer of a multilayer structure on its surface;

[0050] S2. Using photolithography technology, the area outside the ohmic contact is exposed on the mask layer;

[0051] S3, forming a groove structure by dry etching with the assistance of a mask pattern;

[0052] S4, depositing a gate dielectric layer 6;

[0053] S5, depositing metal to form an ohmic contact electrode 7;

[0054] S6 . Deposit metal to form a Schottky gate electrode 8 .

[0055] In the above technical solution, in step S2, the photoresist is a positive or negative photoresist; in step S3, the groove etching is inductively coupled plasma (ICP) or reactive ion etching (RIE), and the reaction gas is Cl2, BCl3, O2 or a mixture thereof.

[0056] More specifically, see Figure 1 to Figure 6 , the above preparation method comprises the following steps:

[0057] S1, sequentially growing a p-type high-resistance diamond drift layer 1 2, a p-type low-resistance diamond insertion layer 3, a p-type high-resistance diamond drift layer 2 4 and a p-type low-resistance diamond cap layer 5 on a p-type low-resistance diamond single crystal substrate 1; or growing a p-type high-resistance diamond drift layer 1 2 on a p-type low-resistance diamond single crystal substrate 1, then alternately growing a p-type low-resistance diamond insertion layer 3 and a p-type high-resistance diamond drift layer 2 4, and finally growing a p-type low-resistance diamond cap layer 5 on the upper surface of the p-type high-resistance diamond drift layer 2 4;

[0058] S2, depositing a dielectric layer on the upper surface of the p-type low-resistance diamond cap layer 5, and forming a pattern mask by photolithography;

[0059] S3, dry etching the two sides of the structure obtained in step S2 to the upper surface of the p-type high-resistance diamond drift layer 2 to form a groove structure;

[0060] S4, depositing a gate dielectric layer 6 in the groove structure obtained in step S3, and removing the mask at the same time;

[0061] S5, depositing metal on the lower surface of the p-type low-resistance diamond single crystal substrate 1 and the p-type low-resistance diamond cap layer 5 to form an ohmic contact electrode 7;

[0062] S6 , depositing metal on the gate dielectric layer 6 obtained in step S4 to form a Schottky gate electrode 8 .

[0063] In the above technical solution, a low-resistance diamond insertion layer is used to increase the threshold voltage of the device and reduce the on-resistance to a certain extent. Combining with a high-resistance drift layer is conducive to achieving a high voltage resistance of the device. In the above preparation method, the p-type low-resistance diamond insertion layer 3 does not need to interrupt the epitaxial growth, the spatial position is adjustable, and multiple layers can be added as needed. That is, in step S1, when the p-type low-resistance diamond insertion layer 3 and the p-type high-resistance diamond drift layer 24 are both one layer, only one corresponding growth is required; when the p-type low-resistance diamond insertion layer 3 and the p-type high-resistance diamond drift layer 24 are both multiple layers, multiple corresponding epitaxial growths are required.

[0064] Based on the above preparation method, when the p-type low-resistance diamond insertion layer 3 and the p-type high-resistance diamond drift layer 24 are both one layer, the structure of the prepared vertical conductive normally-off diamond power transistor is as follows: Figure 6 Schematically, it comprises a p-type low-resistance diamond single crystal substrate 1;

[0065] A p-type high-resistance diamond drift layer 2, located on the upper surface of the p-type low-resistance diamond single crystal substrate 1;

[0066] A p-type low-resistance diamond insertion layer 3, located on the upper surface of the p-type high-resistance diamond drift layer 2;

[0067] A p-type high-resistance diamond drift layer 2 4, located on the upper surface of the p-type low-resistance diamond insertion layer 3;

[0068] A p-type low-resistance diamond cap layer 5, located on the upper surface of the p-type high-resistance diamond drift layer 2 4;

[0069] An ohmic contact electrode 7, located on the upper surface of the p-type low-resistance diamond cap layer 5 and the lower surface of the p-type low-resistance diamond single crystal substrate 1;

[0070] The gate dielectric layer 6 is located on the upper surface of the groove structure, and the groove structure is formed by the p-type low-resistance diamond insertion layer 3, the p-type high-resistance diamond drift layer 4, both sides of the p-type low-resistance diamond cap layer 5 and the upper surface of the p-type high-resistance diamond drift layer 2;

[0071] The Schottky gate electrode 8 is located on the surface of the gate dielectric layer 6 .

[0072] Based on the above preparation method, when the p-type low-resistance diamond insertion layer 3 and the p-type high-resistance diamond drift layer 24 are both multilayers, the structure of the prepared vertical conductive normally-off diamond power transistor is as follows: Figure 7 Schematically, it comprises a p-type low-resistance diamond single crystal substrate 1;

[0073] A p-type high-resistance diamond drift layer 2, located on the upper surface of the p-type low-resistance diamond single crystal substrate 1;

[0074] A p-type low-resistance diamond insertion layer 3 and a p-type high-resistance diamond drift layer 2 4 are arranged alternately up and down, wherein the p-type low-resistance diamond insertion layer 3 is arranged on the upper surface of the p-type high-resistance diamond drift layer 1 2, and the uppermost layer arranged alternately up and down is the p-type high-resistance diamond drift layer 2 4;

[0075] A p-type low-resistance diamond cap layer 5, located on the upper surface of the p-type high-resistance diamond drift layer 2 4;

[0076] An ohmic contact electrode 7, located on the upper surface of the p-type low-resistance diamond cap layer 5 and the lower surface of the p-type low-resistance diamond single crystal substrate 1;

[0077] The gate dielectric layer 6 is located on the upper surface of the groove structure, and the groove structure is formed by the p-type low-resistance diamond insertion layer 3, the p-type high-resistance diamond drift layer 4, both sides of the p-type low-resistance diamond cap layer 5 and the upper surface of the p-type high-resistance diamond drift layer 2;

[0078] The Schottky gate electrode 8 is located on the surface of the gate dielectric layer 6 .

[0079] That is, multiple layers of p-type low-resistance diamond insertion layer 3 and p-type high-resistance diamond drift layer 2 4 are alternately arranged, wherein the bottom layer is p-type low-resistance diamond insertion layer 3 and the top layer is p-type high-resistance diamond drift layer 2 4, and the number of the two layers arranged is consistent.

[0080] In some embodiments, in step S1, the p-type low-resistance diamond single crystal substrate 1 is a single crystal diamond or polycrystalline diamond obtained by homogeneous or heterogeneous epitaxy, with a thickness of 10 nm to 50 μm and a boron doping concentration of 10 19 ~10 21 cm -3 .

[0081] In some embodiments, in step S1, the p-type high-resistance diamond drift layer 1 2 and the p-type high-resistance diamond drift layer 2 4 are both boron-doped diamond epitaxial layers with a thickness of 10 nm to 20 μm and a boron doping concentration of 10 14 ~10 18 cm -3 .

[0082] In some embodiments, in step S1, the p-type low-resistance diamond insertion layer 3 is a single-layer or multi-layer boron-doped diamond epitaxial layer with a thickness of 10 nm to 20 μm, and the boron doping concentration can be between 10 and 20 μm. 16 ~10 19 cm -3 .

[0083] In some embodiments, in step S1, the thickness of the p-type low-resistance diamond cap layer 5 is 10 nm to 10 μm, and the boron doping concentration is 10 16 ~10 19 cm -3 .

[0084] In some embodiments, the thickness of the gate dielectric layer 6 is 1 nm-10 μm.

[0085] In some embodiments, in step S1, the growth adopts one of microwave plasma chemical vapor deposition, direct current plasma jet chemical vapor deposition or pyrolysis chemical vapor deposition. Among them, microwave plasma chemical vapor deposition, English name MPCVD, is a technology that uses microwave plasma to activate the reaction gas, promotes chemical reaction on the surface of the substrate or near the surface space, and generates a solid film; direct current plasma jet chemical vapor deposition, English name DC-PCVD, is a technology that uses high-voltage direct current negative bias (-1~-5kV) to make low-pressure reaction gas glow discharge to generate plasma, and the plasma bombards the workpiece under the action of the electric field, and deposits a film on the surface of the workpiece; pyrolysis chemical vapor deposition, English name TVCD, is a method of gas phase growth using high temperature activated chemical reaction. The above methods are all prior art, and the specific process or action process is not described or limited in the present invention, which is subject to the ability of those skilled in the art to implement.

[0086] In some embodiments, in step S1 , the p-type low-resistance diamond single crystal substrate 1 may be a single crystal or polycrystalline diamond substrate synthesized by high temperature and high pressure or chemical vapor deposition.

[0087] In some embodiments, in step S4, the gate dielectric layer 6 is at least one of aluminum oxide, silicon oxide, and silicon nitride, and has a thickness of 1 nm to 10 μm.

[0088] In some embodiments, in step S5, the material of the ohmic contact electrode 7 is one of Ti / Pt / Au alloy, Ti / Ni / Au alloy or Ti / Mo / Au alloy; the material of the Schottky gate electrode 8 is one of Zr / Au alloy, Pt / Au alloy or W / Au alloy.

[0089] In some embodiments, in step S5 and step S6, the ohmic contact electrode 7 and the Schottky gate electrode 8 are formed by electron beam evaporation, physical vapor deposition or magnetron sputtering.

[0090] Example 1

[0091] See also Figure 1 to Figure 6 , a method for preparing a vertically conductive normally-off diamond power transistor, comprising the following steps:

[0092] S1, using microwave plasma chemical vapor deposition method, sequentially growing a p-type high-resistance diamond drift layer 1 2, a p-type low-resistance diamond insertion layer 3, a p-type high-resistance diamond drift layer 2 4 and a p-type low-resistance diamond cap layer 5 on a p-type low-resistance diamond single crystal substrate 1;

[0093] S2, spin coating photoresist on the upper surface of the p-type low-resistance diamond cap layer 5, and forming a pattern mask by photolithography;

[0094] S3, performing oxygen plasma dry etching on both sides of the structure obtained in step S2 to the upper surface of the p-type high-resistance diamond drift layer 2 to form a groove structure;

[0095] S4, depositing a silicon oxide gate dielectric layer 6 in the groove structure obtained in step S3, and removing the mask at the same time;

[0096] S5, using physical vapor deposition to deposit metal on the lower surface of the p-type low-resistance diamond single crystal substrate 1 and the upper surface of the p-type low-resistance diamond cap layer 5 to form an ohmic contact electrode 7 (the material is Ti / Pt / Au alloy);

[0097] S6 , using physical vapor deposition to deposit metal on the gate dielectric layer 6 obtained in step S4 to form a Schottky gate electrode 8 (the material is a W / Au alloy).

[0098] Example 2

[0099] Compared with Example 1, in this embodiment, the p-type low-resistance diamond insertion layer 3 and the p-type high-resistance diamond drift layer 2 4 are both provided with multiple layers, and the rest are the same. For the specific structure, see Figure 7 shown.

[0100] Finally, it should be noted that the above embodiments do not limit the present invention in any form. For those skilled in the art, some modifications and improvements can be made to the present invention. Therefore, any modification or improvement made without departing from the spirit of the present invention belongs to the scope of protection claimed in the present invention.

Claims

1. A vertically conductive normally-off diamond power transistor, characterized in that: The invention comprises, from bottom to top, a p-type low-resistance diamond single crystal substrate (1), a p-type high-resistance diamond drift layer 1 (2), a p-type low-resistance diamond insertion layer (3), a p-type high-resistance diamond drift layer 2 (4), a p-type low-resistance diamond cap layer (5), a gate dielectric layer (6), an ohmic contact electrode (7), and a Schottky gate electrode (8).

2. The vertically conductive normally-off diamond power transistor according to claim 1, characterized in that: The p-type low-resistance diamond insertion layer (3) is a single-layer or multi-layer structure.

3. A method for preparing the vertically conductive normally-off diamond power transistor according to claim 1 or 2, characterized in that: The steps include: S1, sequentially growing a p-type high-resistance diamond drift layer 1 (2), a p-type low-resistance diamond insertion layer (3), a low-concentration doped p-type high-resistance drift layer 2 (4) and a p-type low-resistance diamond cap layer (5) on a p-type low-resistance diamond single crystal substrate (1); or growing a p-type high-resistance diamond drift layer 1 (2) on a p-type low-resistance diamond single crystal substrate (1), then repeatedly growing a p-type low-resistance diamond insertion layer (3) and a low-concentration doped p-type high-resistance drift layer 2 (4), and finally growing a p-type low-resistance diamond cap layer (5) on the upper surface of the low-concentration doped p-type high-resistance drift layer 2 (4); S2, depositing a dielectric layer on the upper surface of the p-type low-resistance diamond cap layer (5), and forming a pattern mask by photolithography; S3, dry etching the two sides of the structure obtained in step S2 to the upper surface of the p-type high-resistance diamond drift layer 1 (2) to form a groove structure; S4, depositing a gate dielectric layer (6) in the groove structure obtained in step S3, and removing the mask at the same time; S5, depositing metal on the lower surface of the p-type low-resistance diamond single crystal substrate (1) and the upper surface of the p-type low-resistance diamond cap layer (5) to form an ohmic contact electrode (7); S6, depositing metal on the gate dielectric layer (6) obtained in step S4 to form a Schottky gate electrode (8).

4. The preparation method according to claim 3, characterized in that: In step S1, the p-type low-resistance diamond single crystal substrate (1) is a single crystal diamond or polycrystalline diamond obtained by homogeneous or heterogeneous epitaxy, and the boron doping concentration is 10 19 ~10 21 cm -3 .

5. The preparation method according to claim 3, characterized in that: In step S1, the p-type high-resistance diamond drift layer 1 (2) and the low-concentration doped p-type high-resistance drift layer 2 (4) are both boron-doped diamond epitaxial layers with a thickness of 10 nm to 20 μm and a boron doping concentration of 10 14 ~10 18 cm -3 .

6. The preparation method according to claim 3, characterized in that: In step S1, the p-type low-resistance diamond insertion layer (3) is a single-layer or multi-layer boron-doped diamond epitaxial layer with a thickness of 10 nm to 20 μm. The boron doping concentration can be between 10 16 ~10 19 cm -3 .

7. The preparation method according to claim 3, characterized in that: In step S1 , the growth is carried out by using one of microwave plasma chemical vapor deposition, direct current plasma jet chemical vapor deposition or pyrolysis chemical vapor deposition.

8. The preparation method according to claim 3, characterized in that: In step S4, the gate dielectric layer (6) is at least one of aluminum oxide, silicon oxide, and silicon nitride, and has a thickness of 1 nm to 10 μm.

9. The preparation method according to claim 3, characterized in that: In step S5, the material of the ohmic contact electrode (7) is one of a Ti / Pt / Au alloy, a Ti / Ni / Au alloy or a Ti / Mo / Au alloy; and the material of the Schottky gate electrode (8) is one of a Zr / Au alloy, a Pt / Au alloy or a W / Au alloy.

10. The preparation method according to claim 3, characterized in that: In step S5 and step S6, the ohmic contact electrode (7) and the Schottky gate electrode (8) are formed by electron beam evaporation, physical vapor deposition or magnetron sputtering.

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