Semiconductor structure and forming method thereof
By forming a two-dimensional material layer of the same layer connected in the semiconductor structure, the problem of low tunneling current in the prior art is solved, and the performance and tunneling current of the semiconductor structure are improved.
Patent Information
- Application Number
- CN202310822798.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-07-05
- Publication Date
- 2025-01-10
AI Technical Summary
The performance of existing semiconductor structures is low due to short channel effects and high energy consumption, which limits its application in high-performance devices.
A semiconductor structure is adopted, which includes forming a first, two-dimensional material layer and a third, two-dimensional material layer in the channel region, the source region and the drain region of the substrate, respectively, and making it in sequence through an epitaxial growth process. Connected and located in the same layer, heterojunctions are formed to improve carrier mobility and tunneling probability.
Improves the tunneling current and performance of semiconductor structures, enhancing its application potential in high-performance devices.
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Figure CN119300434A_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art
[0002] In the development of integrated circuits, the integration of high-density ultra-large-scale transistors brings high energy consumption and causes associated heating problems. In order to develop high-performance mobile devices and desktop computing devices, low-energy transistor devices are indispensable. Although conventional field-effect transistors (MOSFETs) have been improved and thus energy consumption has been reduced, their turn-on characteristics limit energy efficiency in principle.
[0003] The turn-on characteristic of a field effect transistor can be described by the so-called subthreshold swing (SS), that is, in order to on ) is increased tenfold (dec). The subthreshold swing describes the ease with which a transistor turns on and off, and is affected by the short channel effect and the energy distribution of carriers injected into the transistor channel. At room temperature, the theoretical subthreshold swing of a MOSFET is 60mV / dec, and increases due to other influencing factors such as the short channel effect. In planar transistors, short channel transistors in high-performance processors can expand to about 100mV / dec at a gate length of 32nm due to the short channel effect SS. The principle limitation also increases the off current (I off ) and thus increase the losses.
[0004] In order to reduce the energy consumption of transistors, the operating voltage (Vdd) and the subthreshold swing (SS) should be reduced. In order to meet these requirements, a new type of switching element, the so-called "steep slope device", is needed. Among the most promising solutions are the so-called band-to-band tunneling transistors, here called tunneling field effect transistors (TFET).
[0005] Currently, TFET technology is limited by the operating current (I on ) and more complex processes than CMOS and still need to be improved. Summary of the invention
[0006] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which is beneficial to further improve the performance of the semiconductor structure.
[0007] To solve the above problems, an embodiment of the present invention provides a semiconductor structure, including: a substrate, the substrate including a channel region, and a source region and a drain region respectively located on both sides of the channel region; a first two-dimensional material layer, located at the top of the substrate in the channel region; a second two-dimensional material layer, located at the top of the substrate in the source region; a third two-dimensional material layer, located at the top of the substrate in the drain region, the second two-dimensional material layer, the first two-dimensional material layer and the third two-dimensional material layer are sequentially connected and located in the same layer; a gate structure, located at the top of the substrate in the channel region and covering the first two-dimensional material layer.
[0008] Optionally, the semiconductor structure also includes: source-drain contact electrodes, which are located on the top of the substrate in the source region and the drain region, and are respectively located on the sides of the second two-dimensional material layer and the third two-dimensional material layer, so as to be electrically connected to the side walls of the second two-dimensional material layer and the third two-dimensional material layer, respectively.
[0009] Optionally, a material of the source-drain contact electrode in the source region is different from a material of the source-drain contact electrode in the drain region.
[0010] Optionally, the material of the source-drain contact electrode in the source region includes one or more of Al, Cu, Co, W, Pd, Pt, Ru and Au; the material of the source-drain contact electrode in the drain region includes one or more of Al, Cu, Co, W, Pd, Pt, Ru and Au.
[0011] Optionally, the second two-dimensional material layer, the first two-dimensional material layer and the third two-dimensional material layer located in the same layer constitute a two-dimensional material layer in the same layer, and the number of layers of the two-dimensional material layer in the same layer is one or more.
[0012] Optionally, the number of layers of the same two-dimensional material layer is 1 to 6 layers.
[0013] Optionally, the semiconductor structure further includes: an insulating layer located on the top of the substrate in the source region, the channel region and the drain region; the first two-dimensional material layer, the second two-dimensional material layer and the third two-dimensional material layer cover the insulating layer.
[0014] Optionally, the material of the insulating layer includes one or more of silicon oxide, silicon nitride and silicon oxynitride.
[0015] Optionally, the material of the second two-dimensional material layer includes one or more of transition metal disulfides and transition metal diselenides; the material of the third two-dimensional material layer includes one or more of transition metal disulfides and transition metal diselenides.
[0016] Optionally, the material of the second two-dimensional material layer includes MoS 2、One or more of WS2 and WSe2; the material of the third two-dimensional material layer includes MoS 2、 One or more of WS2 and WSe2.
[0017] Correspondingly, an embodiment of the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a channel region, and a source region and a drain region respectively located on both sides of the channel region; forming a first two-dimensional material layer on the top of the substrate in the channel region, forming a second two-dimensional material layer on the top of the substrate in the source region, and forming a third two-dimensional material layer on the top of the substrate in the drain region, the second two-dimensional material layer, the first two-dimensional material layer and the third two-dimensional material layer are sequentially connected and located in the same layer; and forming a gate structure covering the first two-dimensional material layer on the top of the substrate in the channel region.
[0018] Optionally, after forming the gate structure, the method for forming the semiconductor structure also includes: forming source-drain contact electrodes on the top of the substrate in the source region and the drain region on both sides of the channel region, and the source-drain contact electrodes are respectively located on the sides of the second two-dimensional material layer and the third two-dimensional material layer to be electrically connected to the side walls of the second two-dimensional material layer and the third two-dimensional material layer, respectively.
[0019] Optionally, a material of the source-drain contact electrode in the source region is different from a material of the source-drain contact electrode in the drain region.
[0020] Optionally, one or more stacked two-dimensional material layers of the same layer are formed on the substrate, and each layer of the two-dimensional material layer of the same layer includes the second two-dimensional material layer, the first two-dimensional material layer and the third two-dimensional material layer.
[0021] Optionally, the channel region, source region and drain region are respectively used to form two-dimensional material layers of corresponding materials; the steps of forming a first two-dimensional material layer on the top of the substrate in the channel region, forming a second two-dimensional material layer on the top of the substrate in the source region, and forming a third two-dimensional material layer on the top of the substrate in the drain region include: forming a preset two-dimensional material layer of the substrate covering the channel region, the source region and the drain region, the preset two-dimensional material layer having a corresponding relationship with one of the channel region, the source region and the drain region; removing the preset two-dimensional material layer in an area that does not have a corresponding relationship with the preset two-dimensional material layer to form a first opening above the substrate; forming a two-dimensional material layer of the corresponding material in the first opening; removing the preset two-dimensional material layer in another area that does not have a corresponding relationship with the preset two-dimensional material layer to form a second opening above the substrate; forming a two-dimensional material layer of the corresponding material in the second opening.
[0022] Optionally, in the step of forming a preset two-dimensional material layer of the substrate covering the channel region, the source region and the drain region, the preset two-dimensional material layer is a first two-dimensional material layer; forming a second two-dimensional material layer on the top of the substrate in the source region includes: removing the preset two-dimensional material layer in the source region on one side of the channel region, forming a first opening on the top of the substrate in the source region; forming a second two-dimensional material layer in the first opening; the step of forming a third two-dimensional material layer on the top of the substrate in the drain region includes: removing the preset two-dimensional material layer in the drain region on the other side of the channel region, forming a second opening on the top of the substrate in the drain region; forming a third two-dimensional material layer in the second opening.
[0023] Optionally, the step of forming the first opening includes: forming a first mask layer covering the preset two-dimensional material layer, the first mask layer exposing the preset two-dimensional material layer in an area that does not correspond to the preset two-dimensional material layer; using the first mask layer as a mask, patterning the preset two-dimensional material layer to form a first opening on the top of the substrate; the step of forming the second opening includes: forming a second mask layer covering the preset two-dimensional material layer, the first mask layer, and the two-dimensional material layer formed in the first opening, the second mask layer exposing the preset two-dimensional material layer in another area that does not correspond to the preset two-dimensional material layer; using the second mask layer as a mask, patterning the preset two-dimensional material layer to form a second opening on the top of the substrate; after forming the two-dimensional material layer of corresponding material in the second opening, the method for forming a semiconductor structure also includes: removing the first mask layer and the second mask layer.
[0024] Optionally, the process of forming a two-dimensional material layer of the corresponding material in the first opening includes an epitaxial growth process; and the process of forming a two-dimensional material layer of the corresponding material in the second opening includes an epitaxial growth process.
[0025] Optionally, process parameters of the epitaxial growth process include: a process temperature of 500° C. to 700° C.; and a chamber pressure of 1 mTorr to 100 mTorr.
[0026] Optionally, in the step of providing a substrate, an insulating layer is also formed on the top of the substrate in the source region, the channel region and the drain region; in the step of forming a first two-dimensional material layer on the top of the substrate in the channel region, forming a second two-dimensional material layer on the top of the substrate in the source region, and forming a third two-dimensional material layer on the top of the substrate in the drain region, the first two-dimensional material layer, the second two-dimensional material layer and the third two-dimensional material layer are formed on the insulating layer.
[0027] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:
[0028] The embodiment of the present invention provides a method for forming a semiconductor structure, wherein a first two-dimensional material layer is formed on the top of the substrate in the channel region, a second two-dimensional material layer is formed on the top of the substrate in the source region, and a third two-dimensional material layer is formed on the top of the substrate in the drain region, wherein the second two-dimensional material layer, the first two-dimensional material layer and the third two-dimensional material layer are sequentially connected and located in the same layer, and a gate structure covering the first two-dimensional material layer is formed on the top of the substrate in the channel region. Compared with the existing solution in which the second two-dimensional material layer and the third two-dimensional material layer are stacked vertically on the top of the substrate in the channel region to form a stacked structure, in the embodiment of the present invention, the second two-dimensional material layer, the first two-dimensional material layer and the third two-dimensional material layer are sequentially connected and located in the same layer, that is, the second two-dimensional material layer and the third two-dimensional material layer are arranged horizontally with the first two-dimensional material layer, and the heterojunction formed by the second two-dimensional material layer and the third two-dimensional material layer and the first two-dimensional material layer can make carriers transfer spontaneously, improve the mobility of carriers, thereby increasing the probability of tunneling, improving the tunneling current of the semiconductor structure, and thus improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS
[0029] Figure 1 It is a schematic diagram of the structure of a semiconductor structure;
[0030] Figure 2 is a schematic diagram of a structure corresponding to an embodiment of a semiconductor structure of the present invention;
[0031] Figures 3 to 14 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION
[0032] The performance of the current semiconductor structure needs to be improved. The reasons why its performance needs to be improved are analyzed in combination with a schematic diagram of a semiconductor structure.
[0033] Figure 1 It is a structural diagram of a semiconductor structure.
[0034] The semiconductor structure includes: a substrate 20, the substrate 20 including a channel region 20a, and a source region 20b and a drain region 20c respectively located on both sides of the channel region 20a; an insulating layer 21, located on the top of the substrate 20; a first two-dimensional material layer 39, located on the top of the insulating layer 21 in the channel region 20a and on the top of the insulating layer 21 in the source region 20b; a second two-dimensional material layer 26, located on the top of the insulating layer 21 in the channel region 20a and on the top of the insulating layer 21 in the drain region 20c, along the normal direction of the surface of the substrate 20, the first two-dimensional material layer 39 and the second two-dimensional material layer 26 are stacked vertically on the top of the insulating layer 21 in the channel region 20a, and the second two-dimensional material layer 26 is located on the top of the first two-dimensional material layer 39; a gate structure 22, located on the top of the substrate 20 in the channel region 20a and covering the second two-dimensional material layer 26.
[0035] Research has found that along the normal direction of the surface of the substrate 20, the first two-dimensional material layer 39 and the second two-dimensional material layer 26 are stacked vertically on the top of the insulating layer 21 in the channel region 20a, which reduces the probability of spontaneous carrier transfer, reduces the carrier mobility, and reduces the tunneling current of the semiconductor structure, thereby affecting the performance of the semiconductor structure. At the same time, the first two-dimensional material layer 39 and the second two-dimensional material layer 26 are stacked vertically on the top of the insulating layer 21 in the channel region 20a, which is not conducive to the scaling of the semiconductor structure.
[0036] In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, the substrate including a channel region, and a source region and a drain region respectively located on both sides of the channel region; forming a first two-dimensional material layer on the top of the substrate in the channel region, forming a second two-dimensional material layer on the top of the substrate in the source region, and forming a third two-dimensional material layer on the top of the substrate in the drain region, the second two-dimensional material layer, the first two-dimensional material layer and the third two-dimensional material layer are sequentially connected and located in the same layer; forming a gate structure covering the first two-dimensional material layer on the top of the substrate in the channel region.
[0037] The embodiment of the present invention provides a method for forming a semiconductor structure, wherein a first two-dimensional material layer is formed on the top of the substrate in the channel region, a second two-dimensional material layer is formed on the top of the substrate in the source region, and a third two-dimensional material layer is formed on the top of the substrate in the drain region, wherein the second two-dimensional material layer, the first two-dimensional material layer and the third two-dimensional material layer are sequentially connected and located in the same layer, and a gate structure covering the first two-dimensional material layer is formed on the top of the substrate in the channel region. Compared with the existing solution in which the second two-dimensional material layer and the third two-dimensional material layer are stacked vertically on the top of the substrate in the channel region to form a stacked structure, in the embodiment of the present invention, the second two-dimensional material layer, the first two-dimensional material layer and the third two-dimensional material layer are sequentially connected and located in the same layer, that is, the second two-dimensional material layer and the third two-dimensional material layer are arranged horizontally with the first two-dimensional material layer, and the heterojunction formed by the second two-dimensional material layer and the third two-dimensional material layer and the first two-dimensional material layer can make carriers transfer spontaneously, improve the mobility of carriers, thereby increasing the probability of tunneling, improving the tunneling current of the semiconductor structure, and thus improving the performance of the semiconductor structure.
[0038] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.
[0039] Figure 2 It is a schematic diagram of the corresponding structure in one embodiment of the semiconductor structure of the present invention.
[0040] The semiconductor structure includes: a substrate 200, the substrate 200 includes a channel region 200a, and a source region 200b and a drain region 200c respectively located on both sides of the channel region 200a; a first two-dimensional material layer 202, located at the top of the substrate 200 in the channel region 200a; a second two-dimensional material layer 206, located at the top of the substrate 200 in the source region 200b; a third two-dimensional material layer 209, located at the top of the substrate 200 in the drain region 200c, the second two-dimensional material layer 206, the first two-dimensional material layer 202 and the third two-dimensional material layer 209 are connected in sequence and located in the same layer; a gate structure 220, located at the top of the substrate 200 in the channel region 200a and covering the first two-dimensional material layer 202.
[0041] It should be noted that the second two-dimensional material layer 206, the first two-dimensional material layer 202 and the third two-dimensional material layer 209 are connected in sequence and are located in the same layer, that is, the second two-dimensional material layer 206 and the third two-dimensional material layer 209 are horizontally arranged with the first two-dimensional material layer 202, and the heterojunction formed by the second two-dimensional material layer 206 and the third two-dimensional material layer 209 and the first two-dimensional material layer 202 can enable spontaneous transfer of carriers and improve the mobility of carriers, thereby increasing the probability of tunneling, increasing the tunneling current of the semiconductor structure, and thereby improving the performance of the semiconductor structure.
[0042] The substrate 200 is used to provide a process platform for forming a tunneling field effect transistor (TFET).
[0043] In this embodiment, the substrate 200 is a silicon substrate 200. In other embodiments, the substrate material may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be other types of substrates such as a silicon on insulator substrate or a germanium on insulator substrate.
[0044] In this embodiment, the substrate 200 includes a channel region 200 a , and a source region 200 b and a drain region 200 c respectively located on two sides of the channel region 200 a .
[0045] The channel region 200a is a region where a channel layer of the transistor is formed, the source region 200b is a region where a source of the transistor is formed, and the drain region 200c is a region where a drain of the transistor is formed.
[0046] In this embodiment, the semiconductor structure further includes: an insulating layer 201 located on the top of the substrate 200 in the source region 200 b , the channel region 200 a and the drain region 200 c .
[0047] Specifically, by providing the insulating layer 201 , the risk of mutual leakage between adjacent source-drain contact electrodes through the substrate 200 at the bottom of the channel region 200 a can be reduced, thereby improving the performance of the semiconductor structure.
[0048] In this embodiment, the material of the insulating layer 201 includes one or more of silicon oxide, silicon nitride and silicon oxynitride.
[0049] It should be noted that silicon oxide, silicon nitride and silicon oxynitride are all insulating materials, which can reduce the risk of mutual leakage between adjacent source and drain contact electrodes through the substrate 200 at the bottom of the channel region 200a. At the same time, silicon oxide, silicon nitride and silicon oxynitride are all dielectric materials, which is conducive to the subsequent use of chemical vapor deposition process to grow a two-dimensional material layer on the top surface of the dielectric material, thereby improving the growth quality of the two-dimensional material layer and improving the electrical performance of the semiconductor structure.
[0050] The first two-dimensional material layer 202 is used as a channel layer of the transistor channel region 200 a .
[0051] The material of the first two-dimensional material layer 202 includes transition metal diselenide. As an example, the material of the first two-dimensional material layer 202 includes one or both of tungsten diselenide and molybdenum diselenide.
[0052] In the formation process of the second two-dimensional material layer 206, the second two-dimensional material layer 206 is formed by adopting an epitaxial growth process, which is beneficial to improving the formation quality of the second two-dimensional material layer 206. At the same time, during the epitaxial growth process, by adjusting the process parameters in the epitaxial growth process, the second two-dimensional material layer 206 can be grown in a direction parallel to the surface of the substrate 200, thereby reducing the probability of the second two-dimensional material layer 206 growing in the normal direction of the surface of the substrate 200. At the same time, by selecting the epitaxial growth process to form the second two-dimensional material layer 206, the bonding force between the chemical bonds of the second two-dimensional material layer 206 and the first two-dimensional material layer 202 can be improved, thereby improving the performance of the semiconductor structure.
[0053] In this embodiment, the material of the second two-dimensional material layer 206 includes one or more of transition metal disulfide and transition metal diselenide.
[0054] Specifically, transition metal disulfides and transition metal diselenides refer to compounds containing transition metal elements and sulfur elements or selenium elements, which have good electrical properties. At the same time, the basic structure of transition metal disulfides and transition metal diselenides is generally a layered structure, which is a two-dimensional layered material composed of multiple atoms, and has high mechanical strength, thermal stability and chemical stability. As an example, the material of the second two-dimensional material layer 206 includes one or more of MoS2, WS2 and WSe2.
[0055] In the formation process of the third two-dimensional material layer 209, the third two-dimensional material layer 209 is formed by adopting an epitaxial growth process, which is beneficial to improving the formation quality of the third two-dimensional material layer 209. At the same time, during the epitaxial growth process, by adjusting the process parameters in the epitaxial growth process, the third two-dimensional material layer 209 can be grown in a direction parallel to the surface of the substrate 200, thereby reducing the probability of the third two-dimensional material layer 209 growing in the normal direction of the surface of the substrate 200. At the same time, by selecting the epitaxial growth process to form the third two-dimensional material layer 209, the bonding force between the chemical bonds of the third two-dimensional material layer 209 and the first two-dimensional material layer 202 can be improved, thereby improving the performance of the semiconductor structure.
[0056] In this embodiment, the material of the third two-dimensional material layer 209 includes one or more of transition metal disulfide and transition metal diselenide.
[0057] Specifically, transition metal disulfides and transition metal diselenides refer to compounds containing transition metal elements and sulfur elements or selenium elements, which have good electrical properties. At the same time, the basic structure of transition metal disulfides and transition metal diselenides is generally a layered structure, which is a two-dimensional layered material composed of multiple atoms and has high mechanical strength, thermal stability and chemical stability. As an example, the material of the third two-dimensional material layer 209 includes MoS 2、 One or more of WS2 and WSe2.
[0058] As an example, the first two-dimensional material layer 202 , the second two-dimensional material layer 206 and the third two-dimensional material layer 209 cover the insulating layer 201 .
[0059] In this embodiment, the second two-dimensional material layer 206 , the first two-dimensional material layer 202 and the third two-dimensional material layer 209 located in the same layer constitute a two-dimensional material layer in the same layer, and the number of layers of the two-dimensional material layer in the same layer is one or more.
[0060] It should be noted that the properties of two-dimensional material layers with different numbers of layers are quite different. The electrical performance of the transistor can be controlled by forming one or more stacked two-dimensional material layers of the same layer on the substrate 200, that is, by controlling the number of two-dimensional material layers formed on the substrate 200.
[0061] It should also be noted that the number of layers of the same two-dimensional material layer should not be too many. If the number of layers of the same two-dimensional material layer is too many, it is easy to cause the overall height of the transistor to be too large, which is not conducive to the scaling of the transistor, thereby affecting the performance of the semiconductor structure. For this reason, in this embodiment, the number of layers of the same two-dimensional material layer is 1 to 6 layers.
[0062] The gate structure 220 is used to control the opening and closing of the conductive channel when the device is working.
[0063] As an example, the gate structure 220 is a metal gate structure 220. In other embodiments, the gate structure may also be a polysilicon gate structure.
[0064] In this embodiment, the gate structure 220 includes a gate dielectric layer (not shown) covering the first two-dimensional material layer 202 , and a gate electrode layer (not shown) covering the gate dielectric layer.
[0065] In this embodiment, the material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, La2O3 and hBN.
[0066] Specifically, the gate dielectric layer includes a gate oxide layer covering the first two-dimensional material layer 202, and a high-k gate dielectric layer covering the gate oxide layer. The material of the high-k gate dielectric layer is a high-k dielectric material, which refers to a dielectric material with a relative dielectric constant greater than that of silicon oxide.
[0067] The gate electrode layer is used for subsequent electrical connection with external structures.
[0068] In this embodiment, the material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN and TiAlC.
[0069] Specifically, the gate electrode layer may include a work function layer and an electrode layer covering the work function layer, or the gate electrode layer may include only the work function layer.
[0070] In this embodiment, the semiconductor structure also includes: a source-drain contact electrode 229, which is located on the top of the substrate 200 of the source region 200b and the drain region 200c, and is respectively located on the side of the second two-dimensional material layer 206 and the third two-dimensional material layer 209, so as to be electrically connected to the side walls of the second two-dimensional material layer 206 and the third two-dimensional material layer 209, respectively.
[0071] It should be noted that the source-drain contact electrode 229 is used to electrically connect to the side walls of the second two-dimensional material layer 206 and the third two-dimensional material layer 209 respectively, so that the second two-dimensional material layer 206 and the third two-dimensional material layer 209 can be connected to the external circuit structure through the source-drain contact electrode 229 respectively.
[0072] It should also be noted that the sidewall of the second two-dimensional material layer 206 refers to the sidewall away from the first two-dimensional material layer 202 ; the sidewall of the third two-dimensional material layer 209 refers to the sidewall away from the other side of the first two-dimensional material layer 202 .
[0073] As an example, the material of the source-drain contact electrode 229 in the source region 200 b is different from the material of the source-drain contact electrode 229 in the drain region 200 c .
[0074] Specifically, the material of the source-drain contact electrode 229 in the source region 200b is different from the material of the source-drain contact electrode 229 in the drain region 200c, which can meet the purpose of reducing the contact resistance between the source-drain contact electrode 229 in the source region 200b and the second two-dimensional material layer 206, and can meet the purpose of reducing the contact resistance between the source-drain contact electrode 229 in the drain region 200c and the third two-dimensional material layer 209, thereby improving the electrical performance of the semiconductor structure.
[0075] In other embodiments, the material of the source-drain contact electrode in the source region and the material of the source-drain contact electrode in the drain region may also be the same.
[0076] In this embodiment, the material of the source-drain contact electrode 229 in the source region 200 b includes one or more of Al, Cu, Co, W, Pd, Pt, Ru and Au.
[0077] In this embodiment, the material of the source-drain contact electrode 229 in the drain region 200 c includes one or more of Al, Cu, Co, W, Pd, Pt, Ru and Au.
[0078] Figures 3 to 14 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.
[0079] refer to Figure 3 , providing a substrate 100, wherein the substrate 100 includes a channel region 100a, and a source region 100b and a drain region 100c respectively located at two sides of the channel region 100a.
[0080] The substrate 100 is used to provide a process platform for subsequently forming a tunneling field effect transistor (TFET).
[0081] In this embodiment, the substrate 100 is a silicon substrate 100. In other embodiments, the substrate material may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be other types of substrates such as a silicon on insulator substrate or a germanium on insulator substrate.
[0082] In this embodiment, the substrate 100 includes a channel region 100 a , and a source region 100 b and a drain region 100 c respectively located at two sides of the channel region 100 a .
[0083] The channel region 100 a is a region where a channel layer of the transistor is formed, the source region 100 b is a region where a source of the transistor is formed, and the drain region 100 c is a region where a drain of the transistor is formed.
[0084] In this embodiment, in the step of providing the substrate 100 , an insulating layer 101 is further formed on the top of the substrate 100 in the source region 100 b , the channel region 100 a , and the drain region 100 c .
[0085] Specifically, by forming the insulating layer 101 , after subsequently forming the source-drain contact electrodes, the risk of mutual leakage between adjacent source-drain contact electrodes through the substrate 100 at the bottom of the channel region 100 a can be reduced, thereby improving the performance of the semiconductor structure.
[0086] In this embodiment, the material of the insulating layer 101 includes one or more of silicon oxide, silicon nitride and silicon oxynitride.
[0087] It should be noted that silicon oxide, silicon nitride and silicon oxynitride are all insulating materials. After the source-drain contact electrodes are subsequently formed, the risk of mutual leakage between adjacent source-drain contact electrodes through the substrate 100 at the bottom of the channel region 100a can be reduced. At the same time, silicon oxide, silicon nitride and silicon oxynitride are all dielectric materials, which is conducive to the subsequent use of chemical vapor deposition process to grow a two-dimensional material layer on the top surface of the dielectric material, thereby improving the growth quality of the two-dimensional material layer and improving the electrical performance of the semiconductor structure.
[0088] refer to Figures 4 to 11 A first two-dimensional material layer 102 is formed on the top of the substrate 100 in the channel region 100a, a second two-dimensional material layer 106 is formed on the top of the substrate 100 in the source region 100b, and a third two-dimensional material layer 109 is formed on the top of the substrate 100 in the drain region 100c, wherein the second two-dimensional material layer 106, the first two-dimensional material layer 102 and the third two-dimensional material layer 109 are sequentially connected and located in the same layer.
[0089] It should be noted that the second two-dimensional material layer 106, the first two-dimensional material layer 102 and the third two-dimensional material layer 109 are connected in sequence and are located in the same layer, that is, the second two-dimensional material layer 106 and the third two-dimensional material layer 109 are horizontally arranged with the first two-dimensional material layer 102. The heterojunction formed by the second two-dimensional material layer 106 and the third two-dimensional material layer 109 and the first two-dimensional material layer 102 can enable spontaneous transfer of carriers and improve the mobility of carriers, thereby increasing the probability of tunneling, increasing the tunneling current of the semiconductor structure, and thereby improving the performance of the semiconductor structure.
[0090] The channel region 100a, the source region 100b and the drain region 100c are respectively used to form two-dimensional material layers (not marked) of corresponding materials. As an example, the channel region 100a is used to form a first two-dimensional material layer 102, the source region 100b is used to form a second two-dimensional material layer 106, and the drain region 100c is used to form a third two-dimensional material layer 109.
[0091] In this embodiment, the steps of forming a first two-dimensional material layer 102 on the top of the substrate 100 in the channel region 100a, forming a second two-dimensional material layer 106 on the top of the substrate 100 in the source region 100b, and forming a third two-dimensional material layer 109 on the top of the substrate 100 in the drain region 100c include: forming a preset two-dimensional material layer (not marked) of the substrate 100 covering the channel region 100a, the source region 100b and the drain region 100c, wherein the preset two-dimensional material layer has a corresponding relationship with one of the channel region 100a, the source region 100b and the drain region 100c; removing the preset two-dimensional material layer in an area that does not have a corresponding relationship with the preset two-dimensional material layer to form a first opening located above the substrate 100; forming a two-dimensional material layer of corresponding material in the first opening; removing the preset two-dimensional material layer in another area that does not have a corresponding relationship with the preset two-dimensional material layer to form a second opening located above the substrate 100; forming a two-dimensional material layer of corresponding material in the second opening.
[0092] It should be noted that, as an example, the channel region 100a is used to form a first two-dimensional material layer 102, the source region 100b is used to form a second two-dimensional material layer 106, and the drain region 100c is used to form a third two-dimensional material layer 109, and the preset two-dimensional material layer is the first two-dimensional material layer 102.
[0093] In other embodiments, the preset two-dimensional material layer may also be a second two-dimensional material layer, or the preset two-dimensional material layer may also be a third two-dimensional material layer.
[0094] It should also be noted that when the preset two-dimensional material layer is the first two-dimensional material layer 102, by removing the first two-dimensional material layer 102 on both sides of the channel region 100a, in the process of subsequently forming the first opening and the second opening, it is beneficial to control the process window for forming the first opening and the second opening, that is, it is possible to increase the process window for forming the first opening and the second opening, thereby reducing the process difficulty of forming the first opening and the second opening, and facilitating the subsequent formation of the second two-dimensional material layer 106 in the first opening and the third two-dimensional material layer 109 in the second opening, thereby improving the performance of the semiconductor structure.
[0095] In this embodiment, in the step of forming a preset two-dimensional material layer of the substrate 100 covering the channel region 100 a , the source region 100 b and the drain region 100 c , the preset two-dimensional material layer is a first two-dimensional material layer 102 .
[0096] In this embodiment, the process of forming the covering first two-dimensional material layer 102 includes a chemical vapor deposition process.
[0097] The first two-dimensional material layer 102 is used as a channel layer of the transistor channel region 100 a .
[0098] like Figures 5 to 7 As shown, in this embodiment, forming a second two-dimensional material layer 106 on the top of the substrate 100 in the source region 100b includes: removing the preset two-dimensional material layer of the source region 100b on one side of the channel region 100a, forming a first opening 105 on the top of the substrate 100 in the source region 100b; and forming a second two-dimensional material layer 106 in the first opening 105.
[0099] The first opening 105 provides a spatial position for subsequently forming a second two-dimensional material layer 106
[0100] In this embodiment, the process of forming the first opening 105 includes an anisotropic dry etching process.
[0101] In this embodiment, the step of forming the first opening 105 includes: forming a first mask layer 103 covering the preset two-dimensional material layer, the first mask layer 103 exposing an area of the preset two-dimensional material layer that has no corresponding relationship with the preset two-dimensional material layer; using the first mask layer 103 as a mask, performing graphing on the preset two-dimensional material layer to form a first opening 105 on the top of the substrate 100.
[0102] The first mask layer 103 is used as an etching mask for forming the first opening 105 .
[0103] In this embodiment, the material of the first mask layer 103 includes photoresist. In other embodiments, the material of the first mask layer may also be silicon nitride or silicon oxide.
[0104] In this embodiment, the process of forming the two-dimensional material layer of the corresponding material in the first opening 105 includes an epitaxial growth process.
[0105] Specifically, the two-dimensional material layer of the corresponding material formed in the first opening 105 is the second two-dimensional material layer 106 .
[0106] It should be noted that by selecting an epitaxial growth process to form the second two-dimensional material layer 106 in the first opening 105, the formation quality of the second two-dimensional material layer 106 is improved. The first opening 105 exposes the first two-dimensional material layer 102. During the epitaxial growth process, by adjusting the process parameters in the epitaxial growth process, the second two-dimensional material layer 106 can be epitaxially grown in the first opening 105. The second two-dimensional material layer 106 grows in a direction parallel to the surface of the substrate 100, thereby reducing the probability of the second two-dimensional material layer 106 growing in the normal direction of the surface of the substrate 100. At the same time, by selecting an epitaxial growth process to form the second two-dimensional material layer 106, the bonding force between the chemical bonds of the second two-dimensional material layer 106 and the first two-dimensional material layer 102 can be improved, thereby improving the performance of the semiconductor structure.
[0107] Specifically, the process temperature of the epitaxial growth process should not be too high or too low. If the process temperature of the epitaxial growth process is too high or too low, it is easy to cause the growth quality of the second two-dimensional material layer 106 to be poor, affecting the electrical properties of the semiconductor structure. At the same time, it also increases the probability of the second two-dimensional material layer 106 growing in the normal direction of the surface of the substrate 100, reducing the bonding force between the chemical bonds of the second two-dimensional material layer 106 and the first two-dimensional material layer 102, thereby affecting the performance of the semiconductor structure. For this reason, in this embodiment, the process temperature of the epitaxial growth process is 500°C to 700°C.
[0108] It should be noted that the chamber pressure of the epitaxial growth process should not be too large or too small. If the chamber pressure of the epitaxial growth process is too large or too small, it is easy to cause the growth quality of the second two-dimensional material layer 106 to be poor, affecting the electrical properties of the semiconductor structure. At the same time, it also increases the probability of the second two-dimensional material layer 106 growing in the normal direction of the surface of the substrate 100, reducing the bonding force between the chemical bonds of the second two-dimensional material layer 106 and the first two-dimensional material layer 102, thereby affecting the performance of the semiconductor structure. For this reason, in this embodiment, the chamber pressure of the epitaxial growth process is 1mTorr to 100mTorr.
[0109] like Figures 8 to 10 As shown, in this embodiment, the step of forming a third two-dimensional material layer 109 on the top of the substrate 100 in the drain region 100c includes: removing the preset two-dimensional material layer of the drain region 100c on the other side of the channel region 100a, and forming a second opening 110 on the top of the substrate 100 in the drain region 100c; and forming a third two-dimensional material layer 109 in the second opening 110.
[0110] The second opening 110 provides a spatial position for subsequently forming the second two-dimensional material layer 106
[0111] In this embodiment, the process of forming the second opening 110 includes an anisotropic dry etching process.
[0112] In this embodiment, the step of forming the second opening 110 includes: forming a second mask layer 108 covering the preset two-dimensional material layer, the first mask layer 103, and the two-dimensional material layer formed in the first opening 105, the second mask layer 108 exposing the preset two-dimensional material layer in another area that does not correspond to the preset two-dimensional material layer; using the second mask layer 108 as a mask, patterning the preset two-dimensional material layer to form a second opening 110 on the top of the substrate 100.
[0113] The second mask layer 108 is used as an etching mask for forming the second opening 110 .
[0114] In this embodiment, the material of the second mask layer 108 includes photoresist. In other embodiments, the material of the second mask layer may also be silicon nitride or silicon oxide.
[0115] In this embodiment, the process of forming the two-dimensional material layer of the corresponding material in the second opening 110 includes an epitaxial growth process.
[0116] As an example, the epitaxial growth process includes a chemical vapor deposition process or a molecular beam epitaxy process.
[0117] Specifically, the two-dimensional material layer of the corresponding material formed in the second opening 110 is a third two-dimensional material layer 109 .
[0118] It should be noted that, by selecting an epitaxial growth process to form the third two-dimensional material layer 109 in the second opening 110, the formation quality of the third two-dimensional material layer 109 is improved. The second opening 110 exposes the first two-dimensional material layer 102. During the epitaxial growth process, by adjusting the process parameters in the epitaxial growth process, the third two-dimensional material layer 109 can be made to grow in a direction parallel to the surface of the substrate 100 during the epitaxial growth of the third two-dimensional material layer 109 in the second opening 110, thereby reducing the probability of the third two-dimensional material layer 109 growing in the normal direction of the surface of the substrate 100. At the same time, by selecting an epitaxial growth process to form the third two-dimensional material layer 109, the bonding force between the chemical bonds of the third two-dimensional material layer 109 and the first two-dimensional material layer 102 can be improved, thereby improving the performance of the semiconductor structure.
[0119] like Fig.11 As shown, as an example, after forming a two-dimensional material layer of a corresponding material in the second opening 110 , the method for forming a semiconductor structure further includes: removing the first mask layer 103 and the second mask layer 108 .
[0120] Specifically, after a two-dimensional material layer of corresponding material is formed in the second opening 110, the first mask layer 103 and the second mask layer 108 are removed. Compared with the scheme of removing the first mask layer 103 after forming the first opening 105 and removing the second mask layer 108 after forming the second opening 110, this embodiment removes the first mask layer 103 and the second mask layer 108 in the same step, which reduces the process cost, reduces the process steps, and improves the process efficiency of the semiconductor structure.
[0121] In this embodiment, the process of removing the first mask layer 103 and the second mask layer 108 includes an ashing process.
[0122] It should also be noted that, in the process of patterning the preset two-dimensional material layer using the second mask layer 108 as a mask and forming the second opening 110 on the top of the substrate 100, the first mask layer 103 on the top of the preset two-dimensional material layer is also patterned.
[0123] In this embodiment, the material of the second two-dimensional material layer 106 includes one or more of transition metal disulfide and transition metal diselenide.
[0124] Specifically, transition metal disulfides and transition metal diselenides refer to compounds containing transition metal elements and sulfur or selenium elements, which have good electrical properties. At the same time, the basic structure of transition metal disulfides and transition metal diselenides is generally a layered structure, which is a two-dimensional layered material composed of multiple atoms, and has high mechanical strength, thermal stability and chemical stability. As an example, the material of the second two-dimensional material layer 106 includes one or more of MoS2, WS2 and WSe2.
[0125] In this embodiment, the material of the third two-dimensional material layer 109 includes one or more of transition metal disulfide and transition metal diselenide.
[0126] Specifically, transition metal disulfides and transition metal diselenides refer to compounds containing transition metal elements and sulfur elements or selenium elements, which have good electrical properties. At the same time, the basic structure of transition metal disulfides and transition metal diselenides is generally a layered structure, which is a two-dimensional layered material composed of multiple atoms and has high mechanical strength, thermal stability and chemical stability. As an example, the material of the third two-dimensional material layer 109 includes MoS 2、 One or more of WS2 and WSe2.
[0127] In this embodiment, one or more stacked two-dimensional material layers of the same layer are formed on the substrate 100 , and each layer of the two-dimensional material layer of the same layer includes the second two-dimensional material layer 106 , the first two-dimensional material layer 102 and the third two-dimensional material layer 109 .
[0128] It should be noted that the properties of two-dimensional material layers with different numbers of layers are quite different. The electrical performance of the transistor can be controlled by forming one or more stacked two-dimensional material layers of the same layer on the substrate 100, that is, by controlling the number of two-dimensional material layers formed on the substrate 100.
[0129] It should also be noted that the number of layers of the same two-dimensional material layer should not be too many. If the number of layers of the same two-dimensional material layer is too many, it is easy to cause the overall height of the transistor to be too large, which is not conducive to the scaling of the transistor, thereby affecting the performance of the semiconductor structure. For this reason, in this embodiment, the number of layers of the same two-dimensional material layer is 1 to 6. As an example, the number of layers of the same two-dimensional material layer is 1.
[0130] In this embodiment, in the steps of forming a first two-dimensional material layer 102 on the top of the substrate 100 in the channel region 100a, forming a second two-dimensional material layer 106 on the top of the substrate 100 in the source region 100b, and forming a third two-dimensional material layer 109 on the top of the substrate 100 in the drain region 100c, the first two-dimensional material layer 102, the second two-dimensional material layer 106 and the third two-dimensional material layer 109 are formed on the insulating layer 101.
[0131] refer to Fig.12 A gate structure 120 covering the first two-dimensional material layer 102 is formed on the top of the substrate 100 in the channel region 100a.
[0132] The gate structure 120 is used to control the opening and closing of the conductive channel when the device is working.
[0133] As an example, the gate structure 120 is a metal gate structure. In other embodiments, the gate structure may also be a polysilicon gate structure.
[0134] In this embodiment, the gate structure 120 includes a gate dielectric layer (not shown) covering the first two-dimensional material layer 102 , and a gate electrode layer (not shown) covering the gate dielectric layer.
[0135] In this embodiment, the material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, La2O3 and hBN.
[0136] Specifically, the gate dielectric layer includes a gate oxide layer covering the first two-dimensional material layer 102, and a high-k gate dielectric layer covering the gate oxide layer. The material of the high-k gate dielectric layer is a high-k dielectric material, which refers to a dielectric material with a relative dielectric constant greater than that of silicon oxide.
[0137] The gate electrode layer is used for subsequent electrical connection with external structures.
[0138] In this embodiment, the material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN and TiAlC.
[0139] Specifically, the gate electrode layer may include a work function layer and an electrode layer covering the work function layer, or the gate electrode layer may include only the work function layer.
[0140] refer to Figure 13 to Figure 14 After forming the gate structure 120, the method for forming the semiconductor structure also includes: forming a source-drain contact electrode 129 on the top of the substrate 100 of the source region 100b and the drain region 100c on both sides of the channel region 100a, and the source-drain contact electrode 129 is respectively located on the side of the second two-dimensional material layer 106 and the third two-dimensional material layer 109 to be electrically connected to the side walls of the second two-dimensional material layer 106 and the third two-dimensional material layer 109, respectively.
[0141] It should be noted that the source-drain contact electrode 129 is used to electrically connect to the side walls of the second two-dimensional material layer 106 and the third two-dimensional material layer 109 respectively, so that the second two-dimensional material layer 106 and the third two-dimensional material layer 109 can be connected to the external circuit structure through the source-drain contact electrode 129 respectively.
[0142] It should also be noted that the sidewall of the second two-dimensional material layer 106 refers to the sidewall away from the first two-dimensional material layer 102 ; the sidewall of the third two-dimensional material layer 109 refers to the sidewall away from the other side of the first two-dimensional material layer 102 .
[0143] In this embodiment, the step of forming a source-drain contact electrode 129 on the top of the substrate 100 in the source region 100b and the drain region 100c includes: forming a dielectric layer 121 on the top of the substrate 100 in the source region 100b and the drain region 100c; forming a groove 126 penetrating the dielectric layer 121 in the dielectric layer 121 in the source region 100b and the drain region 100c, the groove 126 exposing the second two-dimensional material layer 106 and the third two-dimensional material layer 109; and forming a source-drain contact electrode 129 in the groove 126.
[0144] As an example, the material of the source-drain contact electrode 129 in the source region 100 b is different from the material of the source-drain contact electrode 129 in the drain region 100 c .
[0145] Specifically, the material of the source-drain contact electrode 129 in the source region 100b is different from that of the source-drain contact electrode 129 in the drain region 100c, which can meet the purpose of reducing the contact resistance between the source-drain contact electrode 129 in the source region 100b and the second two-dimensional material layer 106, and can meet the purpose of reducing the contact resistance between the source-drain contact electrode 129 in the drain region 100c and the third two-dimensional material layer 109, thereby improving the electrical performance of the semiconductor structure.
[0146] In other embodiments, the material of the source-drain contact electrode in the source region and the material of the source-drain contact electrode in the drain region may also be the same.
[0147] In this embodiment, the material of the source-drain contact electrode 129 in the source region 100 b includes one or more of Al, Cu, Co, W, Pd, Pt, Ru and Au. As an example, the material of the source-drain contact electrode 129 in the source region 100 b is Al.
[0148] In this embodiment, the material of the source-drain contact electrode 129 in the drain region 100c includes one or more of Al, Cu, Co, W, Pd, Pt, Ru and Au. As an example, the material of the source-drain contact electrode 129 in the drain region 100c is W.
[0149] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.
Claims
1. A semiconductor structure, characterized in that: include: A substrate, the substrate comprising a channel region, and a source region and a drain region respectively located on both sides of the channel region; a first two-dimensional material layer located on top of the substrate in the channel region; a second two-dimensional material layer located on top of the substrate in the source region; A third two-dimensional material layer is located on the top of the substrate in the drain region, and the second two-dimensional material layer, the first two-dimensional material layer and the third two-dimensional material layer are sequentially connected and located in the same layer; A gate structure is located on the top of the substrate in the channel region and covers the first two-dimensional material layer.
2. The semiconductor structure according to claim 1, wherein: The semiconductor structure also includes: source-drain contact electrodes, which are located on the top of the substrate in the source region and the drain region, and are respectively located on the sides of the second two-dimensional material layer and the third two-dimensional material layer, so as to be electrically connected to the side walls of the second two-dimensional material layer and the third two-dimensional material layer, respectively.
3. The semiconductor structure according to claim 2, wherein: The material of the source-drain contact electrode in the source region is different from the material of the source-drain contact electrode in the drain region.
4. The semiconductor structure according to claim 2, characterized in that The material of the source-drain contact electrode in the source region includes one or more of Al, Cu, Co, W, Pd, Pt, Ru and Au; the material of the source-drain contact electrode in the drain region includes one or more of Al, Cu, Co, W, Pd, Pt, Ru and Au.
5. The semiconductor structure according to claim 1, wherein: The second two-dimensional material layer, the first two-dimensional material layer and the third two-dimensional material layer located in the same layer constitute a two-dimensional material layer in the same layer, and the number of layers of the two-dimensional material layer in the same layer is one or more.
6. The semiconductor structure according to claim 5, characterized in that The number of layers of the same two-dimensional material layer is 1 to 6.
7. The semiconductor structure according to claim 1, wherein: The semiconductor structure further includes: an insulating layer located on top of the substrate in the source region, the channel region and the drain region; The first two-dimensional material layer, the second two-dimensional material layer and the third two-dimensional material layer cover the insulating layer.
8. The semiconductor structure according to claim 7, wherein: The material of the insulating layer includes one or more of silicon oxide, silicon nitride and silicon oxynitride.
9. The semiconductor structure according to claim 1, wherein: The material of the second two-dimensional material layer includes one or more of transition metal disulfides and transition metal diselenides; the material of the third two-dimensional material layer includes one or more of transition metal disulfides and transition metal diselenides.
10. The semiconductor structure according to claim 9, wherein: The material of the second two-dimensional material layer includes one or more of MoS2, WS2 and WSe2; the material of the third two-dimensional material layer includes one or more of MoS2, WS2 and WSe2.
11. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a channel region, and a source region and a drain region respectively located on both sides of the channel region; forming a first two-dimensional material layer on the top of the substrate in the channel region, forming a second two-dimensional material layer on the top of the substrate in the source region, and forming a third two-dimensional material layer on the top of the substrate in the drain region, wherein the second two-dimensional material layer, the first two-dimensional material layer and the third two-dimensional material layer are sequentially connected and located in the same layer; A gate structure covering the first two-dimensional material layer is formed on the top of the substrate in the channel region.
12. The method for forming a semiconductor structure according to claim 11, wherein: After forming the gate structure, the method for forming the semiconductor structure also includes: forming source-drain contact electrodes on the top of the substrate in the source region and the drain region on both sides of the channel region, and the source-drain contact electrodes are respectively located on the sides of the second two-dimensional material layer and the third two-dimensional material layer to be electrically connected to the side walls of the second two-dimensional material layer and the third two-dimensional material layer, respectively.
13. The method for forming a semiconductor structure according to claim 12, wherein: The material of the source-drain contact electrode in the source region is different from the material of the source-drain contact electrode in the drain region.
14. The method for forming a semiconductor structure according to claim 11, wherein: One or more stacked two-dimensional material layers of the same layer are formed on the substrate, and each layer of the two-dimensional material layer of the same layer includes the second two-dimensional material layer, the first two-dimensional material layer and the third two-dimensional material layer.
15. The method for forming a semiconductor structure according to claim 11, wherein: The channel region, the source region and the drain region are respectively used to form two-dimensional material layers of corresponding materials; The steps of forming a first two-dimensional material layer on the top of the substrate in the channel region, forming a second two-dimensional material layer on the top of the substrate in the source region, and forming a third two-dimensional material layer on the top of the substrate in the drain region include: forming a preset two-dimensional material layer of the substrate covering the channel region, the source region, and the drain region, wherein the preset two-dimensional material layer has a corresponding relationship with one of the channel region, the source region, and the drain region; Removing a region of the preset two-dimensional material layer that has no corresponding relationship with the preset two-dimensional material layer to form a first opening located above the substrate; and forming a two-dimensional material layer of corresponding material in the first opening; The preset two-dimensional material layer in another area which has no corresponding relationship with the preset two-dimensional material layer is removed to form a second opening located above the substrate; and a two-dimensional material layer of corresponding material is formed in the second opening.
16. The method for forming a semiconductor structure according to claim 15, wherein: In the step of forming a preset two-dimensional material layer of the substrate covering the channel region, the source region and the drain region, the preset two-dimensional material layer is a first two-dimensional material layer; Forming a second two-dimensional material layer on the top of the substrate in the source region comprises: removing the preset two-dimensional material layer in the source region on one side of the channel region, forming a first opening on the top of the substrate in the source region; forming the second two-dimensional material layer in the first opening; The step of forming a third two-dimensional material layer on the top of the substrate in the drain region includes: removing the preset two-dimensional material layer in the drain region on the other side of the channel region, forming a second opening on the top of the substrate in the drain region; and forming a third two-dimensional material layer in the second opening.
17. The method for forming a semiconductor structure according to claim 15 or 16, wherein: The step of forming the first opening includes: forming a first mask layer covering the preset two-dimensional material layer, wherein the first mask layer exposes a region of the preset two-dimensional material layer that does not correspond to the preset two-dimensional material layer; using the first mask layer as a mask, patterning the preset two-dimensional material layer to form a first opening on the top of the substrate; The step of forming the second opening includes: forming a second mask layer covering the preset two-dimensional material layer, the first mask layer, and the two-dimensional material layer formed in the first opening, wherein the second mask layer exposes the preset two-dimensional material layer in another area that does not correspond to the preset two-dimensional material layer; using the second mask layer as a mask, patterning the preset two-dimensional material layer to form a second opening on the top of the substrate; After forming a two-dimensional material layer of a corresponding material in the second opening, the method for forming a semiconductor structure further includes: removing the first mask layer and the second mask layer.
18. The method for forming a semiconductor structure according to claim 15 or 16, wherein: The process of forming a two-dimensional material layer of the corresponding material in the first opening includes an epitaxial growth process; the process of forming a two-dimensional material layer of the corresponding material in the second opening includes an epitaxial growth process.
19. The method for forming a semiconductor structure according to claim 18, wherein: The process parameters of the epitaxial growth process include: a process temperature of 500° C. to 700° C.; and a chamber pressure of 1 mTorr to 100 mTorr.
20. The method for forming a semiconductor structure according to claim 11, wherein: In the step of providing a substrate, an insulating layer is also formed on the top of the substrate in the source region, the channel region and the drain region; In the steps of forming a first two-dimensional material layer on the top of the substrate in the channel region, forming a second two-dimensional material layer on the top of the substrate in the source region, and forming a third two-dimensional material layer on the top of the substrate in the drain region, the first two-dimensional material layer, the second two-dimensional material layer and the third two-dimensional material layer are formed on the insulating layer.