SGT device with bottom thick oxide layer and manufacturing method
By forming a bottom thick silicon oxide layer at the bottom of the trench of the SGT device and forming an isolation layer on the polysilicon shielded gate, the problems of concentrated electric field and low breakdown voltage at the bottom of the trench are solved, and the stability and isolation reliability of the device are improved .
Patent Information
- Application Number
- CN202310781409.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-06-28
- Publication Date
- 2025-01-10
AI Technical Summary
SGT devices have problems such as concentrated electric field at the bottom of the trench, low breakdown voltage, and large capacitance and gate charge, which affects their stability and reliability.
The bottom thick silicon oxide layer is formed at the bottom of the trench by thermal oxidation method, and an isolation layer is formed on the polysilicon shielded gate. The second isolation layer is formed in combination with the high-density plasma chemical vapor deposition method to improve the potential distribution and isolation reliability.
It effectively improves the breakdown voltage and reverse breakdown working stability, reduces capacitance and gate charge, and enhances the isolation reliability between the polysilicon shielded gate and the control gate.
Smart Images
Figure CN119300445A_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the technical field of semiconductors and relates to a SGT device with a bottom thick oxide layer and a manufacturing method thereof. Background Art
[0002] Shielded Gate Transistor (SGT) devices have the advantages of low specific on-resistance, low Miller capacitance, low power loss, small parasitic capacitance, high switching speed, and good high-frequency characteristics, becoming the mainstay of current low- and medium-voltage applications. Due to the introduction of the shielded gate, the hot holes generated by avalanche breakdown will destroy the Si-H bonds between the shielded gate oxide layer and the silicon interface, and the separated hydrogen will diffuse to the shielded gate, which will cause the avalanche breakdown voltage of the SGT device to increase first and then decrease with the increase of stress time, that is, the SGT device has a time-related avalanche breakdown instability.
[0003] Figure 1 It shows an SGT structure with a silicon nitride barrier layer, including a first silicon oxide layer 5, a barrier layer 6a, a second silicon oxide layer 8a, a polysilicon shielding gate 9a, a gate oxide layer 12, a polysilicon control gate 13, a body region 14, a source region 15 and a source electrode 17. The barrier layer 6a is a silicon nitride layer. Since silicon nitride has a greater barrier effect on hydrogen than silicon oxide, the barrier layer 6a is introduced to inhibit the separated hydrogen from diffusing to the polysilicon shielding gate 9a, thereby improving the avalanche breakdown stability of the SGT device, thereby improving the stability and reliability of the SGT device during application. Figure 2 As shown, it is shown as Figure 1 The potential distribution diagram of the SGT device with a silicon nitride barrier layer. Due to the introduction of the silicon nitride barrier layer, the electric field at the bottom of the trench is relatively concentrated and the potential distribution is dense, which is not conducive to improving the breakdown voltage of the device; and the relative dielectric constant of silicon nitride is relatively high. Under the same trench bottom thickness, the device capacitance and gate charge are larger.
[0004] Therefore, how to provide an SGT structure with a thick bottom oxide layer and a manufacturing method to improve the potential distribution at the bottom of the trench, increase the device breakdown voltage, and reduce the capacitance and gate charge has become a technical problem that needs to be urgently solved by technical personnel in this field. Summary of the invention
[0005] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a SGT device with a thick bottom oxide layer and a manufacturing method, which is used to solve the problems of the SGT device in the prior art, such as the concentrated electric field at the bottom of the trench, low breakdown voltage, large device capacitance and gate charge.
[0006] To achieve the above object and other related objects, the present invention provides a method for manufacturing a SGT device with a bottom thick oxide layer, comprising the following steps:
[0007] Providing a silicon substrate, and forming a groove in the silicon substrate;
[0008] forming a first silicon oxide layer and a barrier layer on the sidewall and bottom of the trench;
[0009] removing the first silicon oxide layer and the barrier layer at the bottom of the trench to expose the silicon substrate at the bottom of the trench;
[0010] Forming a bottom thick silicon oxide layer in the silicon substrate exposed at the bottom of the trench by a thermal oxidation method, wherein the thickness of the bottom thick silicon oxide layer is greater than the sum of the thickness of the first silicon oxide layer and the barrier layer;
[0011] forming a second silicon oxide layer on the sidewall of the barrier layer, and forming a polysilicon shielding gate with a preset depth in the trench;
[0012] forming an isolation layer on the polysilicon shielding gate;
[0013] forming a gate oxide layer on the sidewall of the trench above the isolation layer;
[0014] A polysilicon control gate is formed in the trench above the isolation layer.
[0015] Optionally, the step of forming the isolation layer on the polysilicon shielding gate includes:
[0016] forming a first isolation layer in the polysilicon shielding gate by a thermal oxidation method;
[0017] removing the second silicon oxide layer and the barrier layer above the first isolation layer;
[0018] A second isolation layer is formed on the first isolation layer.
[0019] Optionally, a method of forming the second isolation layer includes a high density plasma chemical vapor deposition method.
[0020] Optionally, after forming the polysilicon control gate, the method further includes:
[0021] forming a body region in the silicon substrate, wherein the vertical depth of the body region does not exceed the depth of the polysilicon control gate;
[0022] A source region is formed in the body region, and a source electrode is formed above the silicon substrate, wherein the source electrode is electrically connected to the source region.
[0023] Optionally, the silicon base includes a silicon epitaxial layer formed on a semiconductor substrate.
[0024] The present invention also provides a SGT device with a bottom thick oxide layer, comprising:
[0025] A silicon substrate having a groove therein;
[0026] A first silicon oxide layer, located on the sidewalls of the trench;
[0027] A bottom thick silicon oxide layer, located at the bottom of the trench, wherein the thickness of the bottom thick silicon oxide layer is greater than the sum of the thickness of the first silicon oxide layer and the barrier layer;
[0028] a barrier layer, located inside the first silicon oxide layer;
[0029] a second silicon oxide layer, located inside the barrier layer;
[0030] A polysilicon shielding gate is located inside the second silicon oxide layer;
[0031] an isolation layer, located above the polysilicon shielding gate;
[0032] a gate oxide layer, located on a sidewall of the trench above the isolation layer;
[0033] A polysilicon control gate is located in the trench above the isolation layer.
[0034] Optionally, the isolation layer includes a first isolation layer and a second isolation layer, and the second isolation layer is located above the first isolation layer.
[0035] Optionally, the first isolation layer includes a silicon oxide layer formed by a thermal oxidation method, and the second isolation layer includes a silicon oxide layer formed by a high-density plasma vapor deposition method.
[0036] Optionally, it also includes:
[0037] A body region, located in the silicon substrate, wherein the vertical depth of the body region does not exceed the depth of the polysilicon control gate;
[0038] a source region located in the body region;
[0039] A source electrode is located above the silicon substrate, and the source electrode is electrically connected to the source region.
[0040] Optionally, the silicon base includes a silicon epitaxial layer formed on a semiconductor substrate.
[0041] As described above, in the SGT device and manufacturing method with a bottom thick oxide layer of the present invention, the barrier layer can inhibit the diffusion of separated hydrogen to the polysilicon shielding gate, thereby improving the avalanche breakdown stability of the SGT device; the bottom thick silicon oxide layer can improve the potential concentration problem of the trench oxide layer, and the potential line distribution is more uniform, which can effectively improve the breakdown voltage and reverse breakdown working stability of the device. Moreover, since the relative dielectric constant of silicon oxide is smaller than that of silicon nitride, the bottom thick silicon oxide layer is also beneficial to reducing capacitance and reducing gate charge; in addition, the superposition of the first isolation layer formed by thermal oxidation and the second isolation layer formed by HDP can effectively enhance the isolation reliability between the polysilicon shielding gate and the polysilicon control gate. BRIEF DESCRIPTION OF THE DRAWINGS
[0042] Figure 1 Shown is a schematic diagram of an SGT device with a silicon nitride barrier layer.
[0043] Figure 2 Shown is a potential profile of an SGT device with a silicon nitride barrier layer.
[0044] Figure 3 The flowchart is a method for manufacturing an SGT device with a bottom thick oxide layer according to the present invention.
[0045] Figure 4 It is a schematic diagram showing a semiconductor substrate provided in the present invention and a silicon epitaxial layer formed on the semiconductor substrate.
[0046] Figure 5 It is a schematic diagram showing the formation of trenches in a silicon epitaxial layer in the present invention.
[0047] Figure 6 It is a schematic diagram showing the formation of a first silicon oxide layer and a barrier material layer on the sidewall and bottom of the trench in the present invention.
[0048] Figure 7 It is a schematic diagram showing the removal of the first silicon oxide layer and the barrier material layer at the bottom of the trench according to the present invention.
[0049] Figure 8 It is a schematic diagram showing the formation of a bottom thick silicon oxide layer at the bottom of the trench according to the present invention.
[0050] Fig. 9 It is a schematic diagram showing forming a second oxide material layer inside the barrier material layer and forming a polysilicon material layer in the trench according to the present invention.
[0051] Fig.10 It is a schematic diagram showing the etching of the polysilicon material layer to form a polysilicon shielding gate in the present invention.
[0052] Fig.11 It is a schematic diagram showing the formation of a first isolation layer in a polysilicon shielding gate in the present invention.
[0053] Fig.12 It is a schematic diagram showing the removal of the second oxide material layer and the barrier material layer above the first isolation layer in the present invention.
[0054] Fig.13 It is a schematic diagram showing forming a second isolation material layer above the first isolation layer in the present invention.
[0055] Fig.14 It is a schematic diagram showing etching the second isolation material layer to form the second isolation layer in the present invention.
[0056] Fig.15 It is a schematic diagram showing the formation of a gate oxide layer inside the trench above the second isolation layer in the present invention.
[0057] Fig.16 It is a schematic diagram showing the formation of a polysilicon control gate in a trench above the second isolation layer in the present invention.
[0058] Fig.17 It is a schematic diagram showing the formation of a body region in a silicon epitaxial layer and the formation of a source region in the body region in the present invention.
[0059] Fig.18 It is a schematic diagram showing the formation of a source electrode on the silicon epitaxial layer in the present invention.
[0060] Fig.19 The potential distribution diagram of the SGT device with a bottom thick oxide layer of the present invention is shown.
[0061] Component number description
[0062] 1 Semiconductor substrate
[0063] 2 Silicon epitaxial layer
[0064] 3 Pad oxide layer
[0065] 4 Silicon nitride mask layer
[0066] 5. First silicon oxide layer
[0067] 6 Barrier material layer
[0068] 6a Barrier layer
[0069] 7 Thick silicon oxide layer at the bottom
[0070] 8 Second Oxide Material Layer
[0071] 8a Second silicon oxide layer
[0072] 9 Polysilicon material layer
[0073] 9a Polysilicon Shielded Gate
[0074] 10 First isolation layer
[0075] 11. Second isolation material layer
[0076] 11a Second isolation layer
[0077] 12 Gate Oxide Layer
[0078] 13 Polysilicon control gate
[0079] 14 Body Area
[0080] 15 Source area
[0081] 16 Interlayer dielectric layer
[0082] 17 Source
[0083] Steps S1 to S8 DETAILED DESCRIPTION
[0084] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.
[0085] See also Figures 1 to 19 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.
[0086] This embodiment provides a method for manufacturing a SGT device with a bottom thick oxide layer. Figure 3 , shown as a process flow chart of the method, comprising the following steps:
[0087] S1: providing a silicon substrate, and forming a groove in the silicon substrate;
[0088] S2: forming a first silicon oxide layer and a barrier layer on the sidewall and bottom of the trench;
[0089] S3: removing the first silicon oxide layer and the barrier layer at the bottom of the trench to expose the silicon substrate at the bottom of the trench;
[0090] S4: forming a bottom thick silicon oxide layer in the silicon substrate exposed at the bottom of the trench by a thermal oxidation method, wherein the thickness of the bottom thick silicon oxide layer is greater than the sum of the thickness of the first silicon oxide layer and the barrier layer;
[0091] S5: forming a second silicon oxide layer on the sidewall of the barrier layer, and forming a polysilicon shielding gate with a preset depth in the trench;
[0092] S6: forming an isolation layer on the polysilicon shielding gate;
[0093] S7: forming a gate oxide layer on the sidewall of the trench above the isolation layer;
[0094] S8: forming a polysilicon control gate in the trench above the isolation layer.
[0095] First, see Figures 4 to 5 , performing step S1: providing a silicon substrate and forming a groove in the silicon substrate.
[0096] As an example, the silicon base includes a silicon epitaxial layer 2 formed on a semiconductor substrate 1, a mask layer is formed on the upper surface of the silicon epitaxial layer 2, and the silicon epitaxial layer 2 is etched based on the mask layer to form the groove.
[0097] As an example, a pad oxide layer 3 and a silicon nitride mask layer 4 are sequentially formed on the silicon epitaxial layer 2, the silicon nitride mask layer 4 and the pad oxide layer 3 are patterned, and the silicon epitaxial layer 2 is etched based on the patterned silicon nitride mask layer 4 and the pad oxide layer 3 to form the groove in the silicon epitaxial layer 2.
[0098] Next, see Figure 6 , executing step S2: forming a first silicon oxide layer 5 and a barrier material layer 6 on the sidewall and bottom of the trench.
[0099] As an example, the inner side and bottom of the trench are oxidized by thermal oxidation to form the first silicon oxide layer 5, and the barrier material layer 6 is formed by deposition on the inner side and bottom of the first silicon oxide layer 5. In other examples, the first silicon oxide layer 5 may also be formed by deposition.
[0100] As an example, the barrier material layer 6 includes a silicon nitride layer.
[0101] Next, see Figure 7 , performing step S3: removing the first silicon oxide layer 5 and the barrier material layer 6 at the bottom of the trench to expose the silicon substrate 2 at the bottom of the trench.
[0102] As an example, the first silicon oxide layer 5 and the barrier material layer 6 at the bottom of the trench are removed by etching.
[0103] Next, see Figure 8 , perform step S4: use a thermal oxidation method to form a bottom thick silicon oxide layer 7 in the silicon epitaxial layer 2 exposed at the bottom of the trench, and the thickness of the bottom thick silicon oxide layer 7 is greater than the sum of the thicknesses of the first silicon oxide layer 5 and the barrier material layer 6.
[0104] As an example, due to the presence of the barrier material layer 6 , the sidewalls of the trench will not undergo oxidation reaction to generate silicon oxide, and only the silicon epitaxial layer 2 exposed at the bottom of the trench will be oxidized to form the relatively thick bottom silicon oxide layer 7 .
[0105] Next, see Figures 9 and 10 , executing step S5: forming a second oxide material layer 8 on the sidewall of the blocking material layer 6, and forming a polysilicon shielding gate 9a with a preset depth in the trench.
[0106] As an example, a deposition method is used to form the second oxide material layer 8 on the inner side of the barrier material layer 6, a deposition method is used to form a polysilicon material layer 9 in the groove, and the polysilicon material layer 9 is filled into the groove and formed above the silicon epitaxial layer 2. A grinding method is used to remove the polysilicon material layer 9 located above the silicon epitaxial layer 2, and an etching method is used to remove a portion of the thickness of the polysilicon material layer 9 in the groove to form a polysilicon shielding gate 9a of a preset thickness.
[0107] Next, see Figures 11 to 14 , executing step S6: forming an isolation layer on the polysilicon shielding gate 9a.
[0108] As an example, Fig.11 As shown, the top of the polysilicon shielding gate 9a is oxidized by thermal oxidation to form a first isolation layer 10.
[0109] As an example, Fig.12 As shown, the second oxide material layer 8 and the barrier material layer 6 above the first isolation layer 10 are removed to form the second silicon oxide layer 8a located between the polysilicon shielding gate 9a and the barrier layer 6a, and to form the barrier layer 6a located between the second silicon oxide layer 8a and the first silicon oxide layer 5.
[0110] As an example, Fig.13 As shown, a second isolation material layer 11 is formed by high density plasma vapor deposition (HDP) to fill the trench. During the process of filling the trench with the second isolation material layer 11, the second isolation material layer 11 is also deposited on the silicon epitaxial layer 2. The isolation material layer 11 includes a silicon oxide layer.
[0111] As an example, Fig.14As shown, the second isolation material layer 11 located above the silicon epitaxial layer 2 is removed by grinding, and a partial thickness of the second isolation material layer 11 in the groove is removed by etching to form a second isolation layer 11a of a preset thickness located above the first isolation layer 10.
[0112] As an example, after forming the second isolation layer 11 a , the method further includes removing the silicon nitride mask layer 4 and the pad oxide layer 3 .
[0113] As an example, the barrier layer 6a can inhibit the separated hydrogen from diffusing to the polysilicon shielding gate, thereby improving the avalanche breakdown stability of the SGT device, and thereby improving the stability and reliability of the SGT device during application; the first isolation layer 10 is formed by thermal oxidation, and has high density. Combined with the second isolation layer 11a formed by HDP filling, it can effectively enhance the isolation reliability between the polysilicon shielding gate 9a and the subsequent polysilicon control gate 13.
[0114] Next, see Fig.15 , executing step S7: forming a gate oxide layer 12 on the sidewall of the trench above the isolation layer.
[0115] As an example, the gate oxide layer 12 is formed by a high temperature thermal oxidation method.
[0116] Next, see Fig.16 , executing step S8: forming a polysilicon control gate 13 in the trench above the isolation layer.
[0117] As an example, Fig.17 As shown, after the polysilicon control gate 13 is formed, it also includes the steps of using ion implantation to form a body region 14 in the silicon epitaxial layer 2 on both sides of the polysilicon control gate 13, and using ion implantation to form a heavily doped source region 15 in the body region 14, wherein the vertical depth of the body region 14 does not exceed the depth of the polysilicon control gate 13.
[0118] As an example, the silicon epitaxial layer 2 is doped with the first conductivity type as the drain region, the body region 14 is doped with the second conductivity type, and the source region 15 is doped with the first conductivity type, wherein the first conductivity type is doped with N-type and the second conductivity type is doped with P-type, or the first conductivity type is doped with P-type and the second conductivity type is doped with N-type.
[0119] As an example, Fig.18As shown, after forming the source region 15, the method further includes forming a dielectric layer 16 on the silicon epitaxial layer 2, and forming a source electrode 17 on the dielectric layer 16, wherein the source electrode 17 penetrates the dielectric layer 16 and is connected to the source region 15. Moreover, the source electrode 17 extends into the body region 14, which can prevent the generation of parasitic triodes between the silicon epitaxial layer 2, the body region 14 and the source region 15, and the source and drain are equivalent to only one body diode, thereby improving the device performance.
[0120] As an example, the method further includes forming a back metal layer as a drain under the semiconductor substrate 1 .
[0121] At this point, a SGT device with a thick bottom oxide layer is manufactured. Fig.18 The SGT device with a bottom thick oxide layer includes a silicon substrate, a first silicon oxide layer 5, a bottom thick silicon oxide layer 7, a barrier layer 6a, a second silicon oxide layer 8a, a polysilicon shielding gate 9a, an isolation layer, a gate oxide layer 12 and a polysilicon control gate 13, wherein the silicon substrate has a groove; the first silicon oxide layer 5 is located on the side wall of the groove; the bottom thick silicon oxide layer 7 is located at the bottom of the groove, and the thickness of the bottom thick silicon oxide layer 7 is greater than the sum of the thicknesses of the first silicon oxide layer 5 and the barrier layer 6a; the barrier layer 6a is located on the inner side of the first silicon oxide layer 5; the second silicon oxide layer 8a is located on the inner side of the barrier layer 6a; the polysilicon shielding gate 9a is located on the inner side of the second silicon oxide layer 8a; the isolation layer is located above the polysilicon shielding gate 9a; the gate oxide layer 12 is located on the inner side of the groove above the isolation layer; the polysilicon control gate 13 is located in the groove above the isolation layer.
[0122] As an example, the silicon base includes a silicon epitaxial layer 2 formed on a semiconductor substrate 1 .
[0123] As an example, the barrier layer 6a includes a silicon nitride layer, and the barrier layer 6a can inhibit the separated hydrogen from diffusing toward the polysilicon shielding gate, thereby improving the avalanche breakdown stability of the SGT device, and further improving the stability and reliability of the SGT device during application.
[0124] As an example, the isolation layer includes a first isolation layer 10 and a second isolation layer 11a, and the second isolation layer 11a is located above the first isolation layer 10, wherein the first isolation layer 10 includes a silicon oxide layer formed by thermal oxidation, and the second isolation layer 11a includes a silicon oxide layer formed by high-density plasma vapor deposition (HDP). The first isolation layer 10 is formed by thermal oxidation and has high density. Combined with the second isolation layer 11a formed by HDP filling, it can effectively enhance the isolation reliability between the polysilicon shielding gate 9a and the subsequent polysilicon control gate 13.
[0125] As an example, it also includes a body region 14 and a source region 15, wherein the body region 14 is located in the silicon substrate 2 on both sides of the polysilicon control gate 13, and the vertical depth of the body region 14 does not exceed the depth of the polysilicon control gate 13; the source region 15 is located in the body region 14. The silicon substrate 2 is doped with a first conductivity type as a drain region, the body region 14 is doped with a second conductivity type, and the source region 15 is doped with a first conductivity type, the first conductivity type is doped with N-type doping, and the second conductivity type is doped with P-type doping, or the first conductivity type is doped with P-type doping, and the second conductivity type is doped with N-type doping.
[0126] As an example, it also includes an interlayer dielectric layer 16 and a source electrode 17, wherein the interlayer dielectric layer 16 is located above the silicon substrate 2; the source electrode 17 is located above the interlayer dielectric layer 16, and the source electrode 17 penetrates the interlayer dielectric layer 16 and is electrically connected to the source region 14, and the source electrode 17 also extends into the body region 14, which can prevent parasitic transistors from being generated between the silicon substrate 2, the body region 14 and the source region 15, and the source and drain are only equivalent to a body diode, thereby improving device performance.
[0127] As an example, see Fig.19 , which shows the potential distribution diagram of the SGT device with a bottom thick oxide layer of the present invention, compared with Figure 1 In the structure shown in the figure, in the SGT device with a bottom thick oxide layer of the present invention, a silicon nitride barrier layer is not provided at the bottom of the trench, but a bottom thick silicon oxide layer is used, which effectively improves the potential distribution at the bottom of the trench, so that the device can withstand a higher breakdown voltage; and improves the potential concentration problem of the trench oxide layer, and the potential line distribution is more uniform, which can effectively improve the breakdown voltage and reverse breakdown working stability of the device. In addition, since the relative dielectric constant of silicon oxide is smaller than that of silicon nitride, the bottom thick oxide layer is also conducive to reducing capacitance and reducing gate charge.
[0128] In summary, in the SGT device and manufacturing method with a bottom thick oxide layer of the present invention, the barrier layer can inhibit the diffusion of separated hydrogen to the polysilicon shielding gate, thereby improving the avalanche breakdown stability of the SGT device; the bottom thick silicon oxide layer can improve the potential concentration problem of the trench oxide layer, and the potential line distribution is more uniform, which can effectively improve the breakdown voltage and reverse breakdown working stability of the device. Moreover, since the relative dielectric constant of silicon oxide is smaller than that of silicon nitride, the bottom thick oxide layer is also conducive to reducing capacitance and gate charge; in addition, the first isolation layer formed by thermal oxidation and the second isolation layer formed by HDP are superimposed, which can effectively enhance the isolation reliability between the polysilicon shielding gate and the polysilicon control gate. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.
[0129] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.
Claims
1. A method for manufacturing a SGT device having a bottom thick oxide layer, characterized in that: The following steps are involved: Providing a silicon substrate, and forming a groove in the silicon substrate; forming a first silicon oxide layer and a barrier layer on the sidewall and bottom of the trench; removing the first silicon oxide layer and the barrier layer at the bottom of the trench to expose the silicon substrate at the bottom of the trench; Forming a bottom thick silicon oxide layer in the silicon substrate exposed at the bottom of the trench by a thermal oxidation method, wherein the thickness of the bottom thick silicon oxide layer is greater than the sum of the thickness of the first silicon oxide layer and the barrier layer; forming a second silicon oxide layer on the sidewall of the barrier layer, and forming a polysilicon shielding gate with a preset depth in the trench; forming an isolation layer on the polysilicon shielding gate; forming a gate oxide layer on the sidewall of the trench above the isolation layer; A polysilicon control gate is formed in the trench above the isolation layer.
2. The method for manufacturing a SGT device with a bottom thick oxide layer according to claim 1, characterized in that: The step of forming the isolation layer on the polysilicon shielding gate comprises: forming a first isolation layer in the polysilicon shielding gate by a thermal oxidation method; removing the second silicon oxide layer and the barrier layer above the first isolation layer; A second isolation layer is formed on the first isolation layer.
3. The method for manufacturing a SGT device with a bottom thick oxide layer according to claim 2, characterized in that: The method of forming the second isolation layer includes a high density plasma chemical vapor deposition method.
4. The method for manufacturing a SGT device with a bottom thick oxide layer according to claim 1, characterized in that: After forming the polysilicon control gate, the method further includes: A body region is formed in the silicon substrate, wherein the vertical depth of the body region does not exceed the depth of the polysilicon control gate; a source region is formed in the body region, and a source electrode is formed above the silicon substrate, wherein the source electrode is electrically connected to the source region.
5. The method for manufacturing a SGT device with a bottom thick oxide layer according to claim 1, characterized in that: The silicon base includes a silicon epitaxial layer formed on a semiconductor substrate.
6. A SGT device having a bottom thick oxide layer, characterized in that: include: A silicon substrate having a groove therein; A first silicon oxide layer, located on the sidewalls of the trench; A bottom thick silicon oxide layer, located at the bottom of the trench, wherein the thickness of the bottom thick oxide layer is greater than the sum of the thickness of the first silicon oxide layer and the barrier layer; a barrier layer, located inside the first silicon oxide layer; a second silicon oxide layer, located inside the barrier layer; A polysilicon shielding gate is located inside the second silicon oxide layer; an isolation layer, located above the polysilicon shielding gate; a gate oxide layer, located on a sidewall of the trench above the isolation layer; A polysilicon control gate is located in the trench above the isolation layer.
7. The SGT device with a bottom thick oxide layer according to claim 6, characterized in that: The isolation layer includes a first isolation layer and a second isolation layer, wherein the second isolation layer is located above the first isolation layer.
8. The SGT device with a bottom thick oxide layer according to claim 7, characterized in that: The first isolation layer includes a silicon oxide layer formed by a thermal oxidation method, and the second isolation layer includes a silicon oxide layer formed by a high-density plasma vapor deposition method.
9. The SGT device with a bottom thick oxide layer according to claim 6, characterized in that: Also includes: A body region, located in the silicon substrate, wherein the vertical depth of the body region does not exceed the depth of the polysilicon control gate; a source region located in the body region; A source electrode is located above the silicon substrate, and the source electrode is electrically connected to the source region.
10. The SGT device with a bottom thick oxide layer according to claim 6, characterized in that: The silicon base includes a silicon epitaxial layer formed on a semiconductor substrate.