Semiconductor structure and manufacturing method thereof

Abstract

The invention provides a semiconductor structure and a manufacturing method thereof, relates to the technical field of semiconductors, and is used for solving the technical problem of relatively high threshold voltage. The semiconductor structure comprises a semiconductor substrate with an NMOS (N-channel Metal Oxide Semiconductor) region and a PMOS (P-channel Metal Oxide Semiconductor) region, a first gate stack structure positioned on the semiconductor substrate in the NMOS region, and a second gate stack structure positioned on the semiconductor substrate in the PMOS region, and both the first gate stack structure and the second gate stack structure comprise high-K dielectric layers; the first isolation layer is located on the side wall of the first gate stack structure to cover the corresponding high-K dielectric layer, protect the oxygen vacancy and reduce the threshold voltage of the first gate stack structure; the second isolation layer is located on the side wall of the second gate stack structure, the second isolation layer at least comprises an oxide isolation layer, the oxide isolation layer at least covers at least part of the side face of the high-K dielectric layer in the second gate stack structure, the oxygen vacancy of the high-K dielectric layer in contact with the oxide isolation layer is repaired, and the threshold voltage of the second gate stack structure is reduced.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a manufacturing method thereof. Background Art

[0002] With the continuous development of science and technology, the application of semiconductor structures is becoming more and more extensive. In the fields of computers, communications, etc., semiconductor structures with different functions are needed. Semiconductor structures include transistors, such as NMOS (N Metal Oxide Semiconductor, Chinese for N-type metal-oxide-semiconductor) transistors and PMOS (P Metal Oxide Semiconductor, Chinese for P-type metal-oxide-semiconductor) transistors. In order to suppress the short channel effect of the transistor and improve the gate control ability and electrical characteristics of the transistor, the gate stack structure of the transistor contains a high-K dielectric layer. However, the high-K dielectric layer often makes the threshold voltage of the transistor higher. Summary of the invention

[0003] In view of the above problems, the embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same to reduce the threshold voltage.

[0004] According to some embodiments, a first aspect of the present disclosure provides a semiconductor structure comprising:

[0005] A semiconductor substrate, wherein the semiconductor substrate includes an NMOS region and a PMOS region;

[0006] A first gate stack structure located on the semiconductor substrate in the NMOS region, and a second gate stack structure located on the semiconductor substrate in the PMOS region, wherein both the first gate stack structure and the second gate stack structure include a high-K dielectric layer;

[0007] A first isolation layer located on a sidewall of the first gate stack structure, wherein a material of the first isolation layer comprises nitride;

[0008] A second isolation layer is located on the sidewall of the second gate stack structure, wherein the second isolation layer at least includes an oxide isolation layer, and the oxide isolation layer at least covers at least a portion of the side surface of the high-K dielectric layer in the second gate stack structure.

[0009] In some possible embodiments, the oxide isolation layer covers a sidewall of the second gate stack structure.

[0010] In some possible embodiments, the second isolation layer further includes a nitride isolation layer, the nitride isolation layer covers a portion of the sidewall of the second gate stack structure, a bottom cut is formed between the nitride isolation layer and the semiconductor substrate, and the bottom cut exposes at least a portion of the side surface of the high-K dielectric layer in the second gate stack structure;

[0011] The oxide isolation layer covers the sidewalls of the nitride isolation layer and fills the bottom cut; or, the oxide isolation layer only fills the bottom cut but does not cover the sidewalls of the nitride isolation layer located on the sidewalls of the second gate stack structure.

[0012] In some possible embodiments, a thickness of the nitride isolation layer in the second isolation layer is smaller than a thickness of the first isolation layer.

[0013] In some possible embodiments, the first gate stack structure includes a gate oxide layer, the high-K dielectric layer, a first work function adjustment structure, a gate layer and a cap layer stacked in sequence on the semiconductor substrate, wherein the first work function adjustment structure includes a first work function adjustment layer and a first diffusion barrier layer located on the first work function adjustment layer;

[0014] The second gate stack structure includes the gate oxide layer, the high-K dielectric layer, the second work function adjustment structure, the gate layer and the cap layer stacked in sequence on the semiconductor substrate, wherein the second work function adjustment structure includes a second diffusion barrier layer, a second work function adjustment layer located on the second diffusion barrier layer, and a third diffusion barrier layer located on the second work function adjustment layer.

[0015] In some possible embodiments, the material of the first work function regulating layer includes at least one of lanthanum oxide, yttrium oxide, germanium oxide, lutetium oxide and strontium oxide;

[0016] The material of the first diffusion barrier layer includes at least one of titanium nitride and tantalum nitride;

[0017] The material of the second work function regulating layer includes at least one of aluminum oxide, titanium oxide, hafnium oxide, zirconium oxide and magnesium oxide;

[0018] The materials of the second diffusion barrier layer and the third diffusion barrier layer include at least one of titanium nitride and tantalum nitride, respectively.

[0019] In some possible embodiments, the material of the gate oxide layer includes silicon oxide;

[0020] The material of the high-K dielectric layer includes at least one of hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, zirconium oxide and strontium titanate;

[0021] The material of the capping layer includes nitride.

[0022] In some possible embodiments, the semiconductor substrate includes a silicon substrate;

[0023] The semiconductor structure further comprises:

[0024] A silicon germanium layer is disposed between the silicon substrate and the second gate stack structure in the PMOS region.

[0025] In some possible embodiments, the semiconductor structure further includes:

[0026] N-type source and drain regions in the semiconductor substrate in the NMOS region, the N-type source and drain regions being located at opposite sides of the first gate stack structure;

[0027] A P-type source and drain region in the semiconductor substrate in the PMOS region, wherein the P-type source and drain regions are respectively located on two opposite sides of the second gate stack structure.

[0028] The semiconductor structure provided by the embodiments of the present disclosure has at least the following advantages:

[0029] The semiconductor structure in the embodiment of the present disclosure includes a semiconductor substrate, a first gate stack structure arranged on the NMOS region of the semiconductor substrate, a second gate stack structure arranged on the PMOS region of the semiconductor substrate, a first isolation layer located on the sidewall of the first gate stack structure, and a second isolation layer located on the sidewall of the second gate stack structure. Wherein, the first gate stack structure and the second gate stack structure both include a high-K dielectric layer, and the first isolation layer caps the high-K dielectric layer in the first gate stack structure to protect the oxygen vacancies in the high-K dielectric layer in the first gate stack structure and reduce the threshold voltage of the first gate stack structure. The second isolation layer includes at least an oxide isolation layer, and the nitride isolation layer is in contact with at least part of the side of the high-K dielectric layer in the second gate stack structure, thereby repairing the oxygen vacancies in the high-K dielectric layer in the second gate stack structure to improve the electron mobility of the second gate stack structure, thereby reducing the threshold voltage of the second gate stack structure, and reducing defect scattering, and improving the electrical characteristics of the second gate stack structure.

[0030] According to some embodiments, a second aspect of the present disclosure provides a method for manufacturing a semiconductor structure, comprising:

[0031] Providing a semiconductor substrate, wherein the semiconductor substrate includes an NMOS region and a PMOS region;

[0032] Forming a first gate stack structure on the semiconductor substrate located in the NMOS region, and forming a second gate stack structure on the semiconductor substrate located in the PMOS region, wherein both the first gate stack structure and the second gate stack structure include a high-K dielectric layer;

[0033] forming a nitride isolation layer on the sidewalls of the first gate stack structure and the sidewalls of the second gate stack structure;

[0034] Removing at least a portion of the nitride isolation layer on the sidewall of the second gate stack structure to expose at least a portion of the side surface of the high-K dielectric layer in the second gate stack structure;

[0035] An oxide isolation layer is formed to cover at least a portion of the side surface of the high-K dielectric layer in the second gate stack structure.

[0036] In some possible embodiments, removing at least a portion of the nitride isolation layer located on the sidewall of the second gate stack structure includes:

[0037] Removing all of the nitride isolation layer located on the sidewalls of the second gate stack structure by wet etching;

[0038] Forming an oxide isolation layer that at least covers the at least partial side surface of the high-K dielectric layer in the second gate stack structure includes: forming the oxide isolation layer on the sidewall of the second gate stack structure.

[0039] In some possible embodiments, removing at least a portion of the nitride isolation layer located on the sidewall of the second gate stack structure includes:

[0040] Removing a portion of the nitride isolation layer at the bottom of the sidewall of the second gate stack structure by wet etching to form a bottom cut, wherein the bottom cut exposes at least a portion of the side surface of the high-K dielectric layer in the second gate stack structure, and the thickness of the remaining nitride isolation layer on the sidewall of the second gate stack structure is less than the thickness of the nitride isolation layer on the sidewall of the first gate stack structure;

[0041] Forming an oxide isolation layer that at least covers the at least partial side surface of the high-K dielectric layer in the second gate stack structure includes: forming the oxide isolation layer that at least fills the bottom cut.

[0042] In some possible embodiments, the oxide isolation layer covers the sidewalls of the remaining nitride isolation layer on the sidewalls of the second gate stack structure and fills the bottom cut;

[0043] Alternatively, the oxide isolation layer only fills the bottom cut, but does not cover the sidewalls of the remaining nitride isolation layer on the sidewalls of the second gate stack structure.

[0044] In some possible embodiments, forming a first gate stack structure on the semiconductor substrate located in the NMOS region, and forming a second gate stack structure on the semiconductor substrate in the PMOS region, includes:

[0045] Forming a gate oxide layer, the high-K dielectric layer and a first work function adjustment structure stacked in sequence on the semiconductor substrate located in the NMOS region and the PMOS region;

[0046] removing the first work function adjustment structure relative to the PMOS region;

[0047] forming a second work function adjustment structure on the high-K dielectric layer opposite to the PMOS region;

[0048] Forming a gate layer and a cap layer stacked in sequence on the first work function adjustment structure opposite to the NMOS region and the second work function adjustment structure opposite to the PMOS region;

[0049] The gate oxide layer, the high-K dielectric layer, the first work function adjustment structure, the gate layer and the cap layer are patterned relative to the NMOS region to form the first gate stack structure, and the gate oxide layer, the high-K dielectric layer, the second work function adjustment structure, the gate layer and the cap layer are patterned relative to the PMOS region to form the second gate stack structure.

[0050] In some possible embodiments, the first work function regulating structure includes a first work function regulating layer and a first diffusion barrier layer located on the first work function regulating layer;

[0051] The second work function regulating structure includes a second diffusion barrier layer, a second work function regulating layer located on the second diffusion barrier layer, and a third diffusion barrier layer located on the second work function regulating layer.

[0052] In some possible embodiments, the semiconductor substrate includes a silicon substrate;

[0053] Before forming the gate oxide layer, the high-K dielectric layer and the first work function adjustment structure stacked in sequence on the semiconductor substrate located in the NMOS region and the PMOS region, the manufacturing method further includes:

[0054] A silicon germanium layer is formed on the silicon substrate located in the PMOS region.

[0055] The method for manufacturing a semiconductor structure provided by the embodiment of the present disclosure has at least the following advantages:

[0056] In the method for manufacturing the semiconductor structure provided by the embodiment of the present disclosure, a nitride isolation layer is formed on the sidewalls of the first gate stack structure and the sidewalls of the second gate stack structure, and at least a portion of the nitride isolation layer on the sidewalls of the second gate stack structure is removed to expose at least a portion of the side surfaces of the high-K dielectric layer in the second gate stack structure, and then an oxide isolation layer is formed on the exposed side surfaces of the high-K dielectric layer in the second gate stack structure. The oxygen introduced during the formation of the oxide isolation layer is used to repair the oxygen vacancies in the exposed high-K dielectric layer to improve the electron mobility of the second gate stack structure, thereby reducing the threshold voltage of the second gate stack structure, and reducing defect scattering, thereby improving the electrical characteristics of the second gate stack structure. In addition, the nitride isolation layer on the sidewalls of the first gate stack structure caps the high-K dielectric layer in the first gate stack structure to protect the oxygen vacancies in the high-K dielectric layer in the first gate stack structure and reduce the threshold voltage of the first gate stack structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] Figure 1 is a schematic diagram of the structure of an NMOS region in an embodiment of the present disclosure;

[0058] Figure 2 is a schematic diagram of the structure of a PMOS region in an embodiment of the present disclosure;

[0059] Figure 3 is a schematic structural diagram of a first gate stack structure in an embodiment of the present disclosure;

[0060] Figure 4 is a schematic structural diagram of a second gate stack structure in an embodiment of the present disclosure;

[0061] Figure 5 is a schematic diagram of oxygen vacancies in a first gate stack structure in an embodiment of the present disclosure;

[0062] Figure 6 is a schematic diagram of oxygen vacancies in a second gate stack structure in an embodiment of the present disclosure;

[0063] Figure 7 A schematic diagram of the structure of a second isolation layer in an embodiment of the present disclosure;

[0064] Figure 8 Another structural schematic diagram of the second isolation layer in one embodiment of the present disclosure;

[0065] Fig. 9 This is another structural schematic diagram of the second isolation layer in one embodiment of the present disclosure;

[0066] Fig.10 This is another structural schematic diagram of the second isolation layer in one embodiment of the present disclosure;

[0067] Fig.11 is a flow chart of a method for manufacturing a semiconductor structure in an embodiment of the present disclosure;

[0068] Fig.12 is a schematic diagram of a semiconductor substrate in an embodiment of the present disclosure;

[0069] Fig.13 is a schematic structural diagram after forming a first gate stack structure and a second gate stack structure in one embodiment of the present disclosure;

[0070] Fig.14 is a schematic diagram of a structure after a nitride isolation layer is formed in one embodiment of the present disclosure;

[0071] Fig.15 It is a schematic diagram of the structure after a portion of the nitride isolation layer is removed in one embodiment of the present disclosure;

[0072] Fig.16 is a schematic diagram of a structure after all nitride isolation layers on the sidewalls of the second gate stack structure are removed in one embodiment of the present disclosure;

[0073] Fig.17 It is a schematic diagram of a structure after a portion of the nitride isolation layer on the sidewall of the second gate stack structure is removed in one embodiment of the present disclosure;

[0074] Fig.18 It is a schematic diagram of the structure after forming a protective layer in one embodiment of the present disclosure;

[0075] Fig.19 A schematic diagram of the structure of an oxide isolation layer in an embodiment of the present disclosure;

[0076] Fig. 20 A schematic diagram of a structure after an oxide isolation layer is formed in one embodiment of the present disclosure;

[0077] Fig.21 is another structural schematic diagram of an oxide isolation layer in an embodiment of the present disclosure;

[0078] Fig. 22 It is a schematic diagram of the structure after removing the protective layer in one embodiment of the present disclosure;

[0079] Fig.23 is another structural schematic diagram after an oxide isolation layer is formed in one embodiment of the present disclosure;

[0080] Fig.24 is another structural schematic diagram of an oxide isolation layer in an embodiment of the present disclosure;

[0081] Fig.25 It is another structural schematic diagram of the oxide isolation layer in one embodiment of the present disclosure;

[0082] Fig.26 is a schematic diagram after forming a first work function adjustment structure in an embodiment of the present disclosure;

[0083] Fig. 27 It is a schematic diagram of removing the first work function adjustment structure of the PMOS region in one embodiment of the present disclosure;

[0084] Fig.28 is a schematic diagram after forming a second work function adjustment structure in one embodiment of the present disclosure;

[0085] Fig.29 It is a schematic diagram of an embodiment of the present disclosure after removing the second work function adjustment structure of the PMOS region;

[0086] Fig.30 It is a schematic diagram after forming a gate layer and a cap layer in one embodiment of the present disclosure;

[0087] Fig.31 FIG. 4 is a schematic diagram of a silicon germanium layer after being formed in one embodiment of the present disclosure.

[0088] Description of reference numerals:

[0089] 10-semiconductor substrate; 20-first gate stack structure;

[0090] 21-a first work function adjustment structure; 22-a first work function adjustment layer;

[0091] 23-a first diffusion barrier layer; 30-a second gate stack structure;

[0092] 31-a second work function regulating structure; 32-a second diffusion barrier layer;

[0093] 33-a second work function regulating layer; 34-a third diffusion barrier layer;

[0094] 41-gate oxide layer; 42-high K dielectric layer;

[0095] 43-gate layer; 44-cap layer;

[0096] 45-silicon germanium layer; 50-first isolation layer;

[0097] 60-a second isolation layer; 61-an oxide isolation layer;

[0098] 62-nitride isolation layer; 63-bottom cut;

[0099] 70-Protective layer. DETAILED DESCRIPTION

[0100] There is a problem of high threshold voltage of transistors in the related art. The inventors have found that the reason is that the first gate stack structure of the NMOS transistor and the second gate stack structure of the PMOS transistor both include a high-K dielectric layer, and the first gate stack structure and the second gate stack structure are both capped. The high-K dielectric layer can reduce the short channel effect of the NMOS transistor and the PMOS transistor, but oxygen vacancies will spontaneously form during the formation process. The other film layers in the first gate stack structure will form a dipole, providing a positive potential for the oxygen vacancies, thereby reducing the threshold voltage of the NMOS transistor. Capping the first gate stack structure can protect the oxygen vacancies, which is beneficial to reducing the threshold voltage of the NMOS transistor and improving the performance of the NMOS transistor. However, the presence of oxygen vacancies will reduce the mobility of the PMOS transistor, and the threshold voltage of the PMOS transistor is relatively high.

[0101] To this end, an embodiment of the present disclosure provides a semiconductor structure, which includes a semiconductor substrate, a first gate stack structure is arranged on the NMOS region of the semiconductor substrate, and a second gate stack structure is arranged on the PMOS region of the semiconductor substrate, and the first gate stack structure and the second gate stack structure both include a high-K dielectric layer. A first isolation layer is arranged on the sidewall of the first gate stack structure, and a second isolation layer is arranged on the sidewall of the second gate stack structure, and the second isolation layer includes at least an oxide isolation layer, and the oxide isolation layer is in contact with at least part of the side surface of the high-K dielectric layer in the second gate stack structure. The high-K dielectric layer in the first gate stack structure is capped with the first isolation layer to protect the oxygen vacancies in the high-K dielectric layer in the first gate stack structure and reduce the threshold voltage of the first gate stack structure. The oxygen vacancies in the high-K dielectric layer in the second gate stack structure are repaired with the oxide isolation layer to reduce the threshold voltage of the second gate stack structure.

[0102] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present disclosure more obvious and understandable, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present disclosure.

[0103] See also Figure 1 and Figure 2The present disclosure provides a semiconductor structure, which includes a semiconductor substrate 10, a first gate stack structure 20, a second gate stack structure 30, a first isolation layer 50 and a second isolation layer. The semiconductor substrate 10 provides support for the first gate stack structure 20, the second gate stack structure 30, the first isolation layer 50 and the second isolation layer.

[0104] The semiconductor substrate 10 includes an NMOS region and a PMOS region, and the NMOS region and the PMOS region may be spaced apart. Figure 1 As shown in A, it is used to form an NMOS transistor, and the PMOS region is as shown in Figure 2 As shown at B in the figure, it is used to form a PMOS transistor. The material of the semiconductor substrate 10 can be silicon, germanium, silicon germanium, arsenic germanium, silicon on insulator (SOI) or germanium on insulator (GOI).

[0105] The first gate stack structure 20 is located on the semiconductor substrate 10 in the NMOS region, and the second gate stack structure 30 is located on the semiconductor substrate 10 in the PMOS region. The first gate stack structure 20 and the second gate stack structure 30 both include multiple layers stacked, one of which is a high-K dielectric layer 42, that is, the first gate stack structure 20 and the second gate stack structure 30 both include a high-K dielectric layer 42. The high-K dielectric layer 42 is provided to suppress the short channel effect and improve the gate control capability of the first gate stack structure 20 and the second gate stack structure 30, thereby improving the electrical performance of the semiconductor structure.

[0106] See also Figure 3 The first gate stack structure 20 includes a gate oxide layer 41, a high-K dielectric layer 42, a first work function regulating structure 21, a gate layer 43 and a cap layer 44 stacked in sequence on the semiconductor substrate 10. The first work function regulating structure 21 includes a first work function regulating layer 22 and a first diffusion barrier layer 23 located on the first work function regulating layer 22.

[0107] like Figure 3 As shown, a gate oxide layer 41 of a first gate stack structure 20 is disposed on a semiconductor substrate 10 located in an NMOS region, and a high-K dielectric layer 42 of the first gate stack structure 20 is disposed on the gate oxide layer 41 of the first gate stack structure 20. A first work function adjustment layer 22 is disposed on the high-K dielectric layer 42 of the first gate stack structure 20. The first work function adjustment layer 22 is used to adjust the work function of the first gate stack structure 20 to reduce the threshold voltage of the NMOS transistor formed subsequently.

[0108] A first diffusion barrier layer 23 is disposed on the first work function regulating layer 22, and the first diffusion barrier layer 23 prevents ions in the first work function regulating layer 22 from diffusing to the gate layer 43 above the first diffusion barrier layer 23. A gate layer 43 of a first gate stack structure 20 is disposed on the first diffusion barrier layer 23, and a cap layer 44 of the first gate stack structure 20 is disposed on the gate layer 43 of the first gate stack structure 20, and the cap layer 44 of the first gate stack structure 20 isolates and protects the gate layer 43 thereunder, so as to avoid or reduce damage to the gate layer 43 of the first gate stack structure 20 and the like in subsequent processes.

[0109] The material of the first work function regulating layer 22 includes at least one of lanthanum oxide, yttrium oxide, germanium oxide, lutetium oxide and strontium oxide; the material of the first diffusion barrier layer 23 includes at least one of titanium nitride and tantalum nitride.

[0110] See also Figure 4 The second gate stack structure 30 includes a gate oxide layer 41, a high-K dielectric layer 42, a second work function regulating structure 31, a gate layer 43 and a cap layer 44 stacked in sequence on the semiconductor substrate 10, wherein the second work function regulating structure 31 includes a second diffusion barrier layer 32, a second work function regulating layer 33 located on the second diffusion barrier layer 32, and a third diffusion barrier layer 34 located on the second work function regulating layer 33.

[0111] like Figure 4 As shown, a gate oxide layer 41 of a second gate stack structure 30 is disposed on a semiconductor substrate 10 located in a PMOS region, and a high-K dielectric layer 42 of the second gate stack structure 30 is disposed on the gate oxide layer 41 of the second gate stack structure 30. A second diffusion barrier layer 32 is disposed on the high-K dielectric layer 42 of the second gate stack structure 30, a second work function regulating layer 33 is disposed on the second diffusion barrier layer 32, and a third diffusion barrier layer 34 is disposed on the second work function regulating layer 33. A gate layer 43 of the second gate stack structure 30 is disposed on the third diffusion barrier layer 34, and a cap layer 44 of the second gate stack structure 30 is disposed on the gate layer 43 of the second gate stack structure 30.

[0112] The second work function regulating layer 33 is provided with a third diffusion barrier layer 34 and a second diffusion barrier layer 32 above and below, respectively, to prevent the metal ions of the second work function regulating layer 33 from diffusing into the gate layer 43 on the third diffusion barrier layer 34, and to restrict the metal ions of the second work function regulating layer 33 from diffusing into the high-K dielectric layer 42 under the second diffusion barrier layer 32 (allowing the metal ions of the second work function regulating layer 33 to diffuse into the high-K dielectric layer 42, but preventing them from diffusing into the semiconductor substrate 10). For example, the thickness of the second diffusion barrier layer 32 is generally less than that of the third diffusion barrier layer 34.

[0113] The material of the second work function regulating layer 33 includes at least one of aluminum oxide, titanium oxide, hafnium oxide, zirconium oxide and magnesium oxide; the materials of the second diffusion barrier layer 32 and the third diffusion barrier layer 34 include at least one of titanium nitride and tantalum nitride respectively.

[0114] In some examples, the gate oxide layer 41 of the first gate stack structure 20 and the second gate stack structure 30 may be the same, so that the gate oxide layer 41 of the first gate stack structure 20 and the second gate stack structure 30 is formed simultaneously. The high-K dielectric layer 42 of the first gate stack structure 20 and the second gate stack structure 30 may be the same, so that the high-K dielectric layer 42 of the first gate stack structure 20 and the second gate stack structure 30 is formed simultaneously. The gate layer 43 of the first gate stack structure 20 and the second gate stack structure 30 may be the same, so that the gate layer 43 of the first gate stack structure 20 and the second gate stack structure 30 is formed simultaneously. The cap layer 44 of the first gate stack structure 20 and the second gate stack structure 30 may be the same, so that the cap layer 44 of the first gate stack structure 20 and the second gate stack structure 30 is formed simultaneously.

[0115] The material of the gate oxide layer 41 includes silicon oxide; the material of the high-K dielectric layer 42 includes at least one of hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, zirconium oxide and strontium titanate; the material of the cap layer 44 includes nitride, such as silicon nitride or silicon oxynitride. The material of the gate layer 43 may include polysilicon or tungsten.

[0116] Continue reading Figure 1 , Figure 3 and Figure 5 , the first isolation layer 50 is located on the sidewall of the first gate stack structure 20, that is, the first isolation layer 50 covers the sidewall of the first gate stack structure 20. The first isolation layer 50 is in contact with the cap layer 44 to cap the corresponding high-K dielectric layer 42, thereby ensuring that the high-K dielectric layer 42 in the first gate stack structure 20 is sealed, thereby protecting the oxygen vacancies in the high-K dielectric layer 42 in the first gate stack structure 20, and further reducing the threshold voltage of the first gate stack structure 20.

[0117] The top surface of the first isolation layer 50 may be flush with the top surface of the first gate stack structure 20, for example, flush with the top surface of the cap layer 44 of the first gate stack structure 20. The material of the first isolation layer 50 includes nitride, and the material of the first isolation layer 50 may be the same as the material of the cap layer 44 of the first gate stack structure 20, so that the first isolation layer 50 and the cap layer 44 of the first gate stack structure 20 are in contact with each other to form a whole, and the high-K dielectric layer 42 of the first gate stack structure 20 is located inside it to ensure the capping effect of the high-K dielectric layer 42 of the first gate stack structure 20.

[0118] Continue reading Figure 2 , Figure 4 and Figure 6 , the second isolation layer is located on the sidewall of the second gate stack structure 30, that is, the second isolation layer covers the sidewall of the second gate stack structure 30. The second isolation layer includes at least an oxide isolation layer 61, and the oxide isolation layer 61 at least covers at least a portion of the side surface of the high-K dielectric layer 42 in the second gate stack structure 30. The oxide isolation layer 61 contacts at least a portion of the side surface of the high-K dielectric layer 42 in the second gate stack structure 30, thereby repairing oxygen vacancies in the high-K dielectric layer 42 in the second gate stack structure 30, so as to improve the electron mobility of the second gate stack structure 30, thereby reducing the threshold voltage of the second gate stack structure 30, and reducing defect scattering, thereby improving the electrical characteristics of the second gate stack structure 30.

[0119] In some possible implementations, such as Figure 2 As shown, the oxide isolation layer 61 covers the sidewalls of the second gate stack structure 30. In the example where the second gate stack structure 30 includes a gate oxide layer 41, a high-K dielectric layer 42, a second work function adjustment structure 31, a gate layer 43 and a cap layer 44, the oxide isolation layer 61 covers the side surfaces of the gate oxide layer 41 located on the PMOS region, the side surfaces of the high-K dielectric layer 42, the side surfaces of the second work function adjustment structure 31, the side surfaces of the gate layer 43, and the side surfaces of the cap layer 44. The top surface of the oxide isolation layer 61 may be flush with the top surface of the second gate stack structure 30, for example, the top surface of the oxide isolation layer 61 is flush with the top surface of the cap layer 44 of the second gate stack structure 30.

[0120] For other possible implementations, see Figures 7 to 9 The second isolation layer 60 further includes a nitride isolation layer 62, and the nitride isolation layer 62 covers a portion of the sidewall of the second gate stack structure 30. A bottom cut 63 is formed between the nitride isolation layer 62 and the semiconductor substrate 10 (see Fig.17 ), the bottom cut 63 exposes at least a portion of the side surface of the high-K dielectric layer 42 in the second gate stack structure 30. For example, the thickness of the nitride isolation layer 62 in the second isolation layer 60 is less than the thickness of the first isolation layer 50.

[0121] like Figures 7 to 9 As shown, the bottom surface of the nitride isolation layer 62 is higher than the top surface of the semiconductor substrate 10 , so that a bottom cut 63 is formed between the nitride isolation layer 62 and the semiconductor substrate 10 . The bottom cut 63 exposes at least a portion of the side surface of the high-K dielectric layer 42 in the second gate stack structure 30 .

[0122] Among them, the bottom surface of the nitride isolation layer 62 is higher than the bottom surface of the high-K dielectric layer 42 in the second gate stack structure 30, and can be higher or lower than the top surface of the high-K dielectric layer 42 in the second gate stack structure 30, that is, the bottom cut 63 exposes all or part of the side surfaces of the high-K dielectric layer 42 in the second gate stack structure 30.

[0123] The top surface of the nitride isolation layer 62 can be flush with the top surface of the second gate stack structure 30, and the material of the nitride isolation layer 62 can be the same as the material of the capping layer 44 of the second gate stack structure 30, so that the nitride isolation layer 62 and the capping layer 44 of the second gate stack structure 30 form a whole to seal the film layer above the high-K dielectric layer 42 of the second gate stack structure 30.

[0124] In some examples, such as Figure 7 As shown, the bottom cut 63 is filled with an oxide isolation layer 61, and the oxide isolation layer 61 covers the sidewalls of the nitride isolation layer 62. The oxide isolation layer 61 is filled in the bottom cut 63, and is in contact with the nitride isolation layer 62 and the semiconductor substrate 10, and is in contact with the high-K dielectric layer 42 of the second gate stack structure 30, so as to repair the oxygen vacancies in the high-K dielectric layer 42 of the second gate stack structure 30.

[0125] The oxide isolation layer 61 also covers the sidewalls of the nitride isolation layer 62, for example, the top surface of the oxide isolation layer 61 is flush with the top surface of the nitride isolation layer 62. The thickness of the oxide isolation layer 61 located in the bottom cut 63 is greater than the thickness of the oxide isolation layer 61 located on the nitride isolation layer 62, so that the surface of the oxide isolation layer 61 away from the sidewall of the second gate stack structure 30 is flush and substantially parallel to the sidewall of the second gate stack structure 30.

[0126] like Figure 8 As shown, the oxide isolation layer 61 also covers the top surface of the second gate stack structure 30 , that is, the oxide isolation layer 61 encapsulates the second gate stack structure 30 and the nitride isolation layer 62 on its sidewalls to facilitate the formation of the oxide isolation layer 61 .

[0127] In other examples, such as Fig. 9 As shown, the oxide isolation layer 61 only fills the bottom cut 63, but does not cover the sidewalls of the remaining nitride isolation layer 62 on the sidewalls of the second gate stack structure 30, that is, the oxide isolation layer 61 does not cover the nitride isolation layer 62. For example, the surface of the oxide isolation layer 61 away from the sidewall of the second gate stack structure 30 is flush with the sidewall of the nitride isolation layer 62.

[0128] See also Fig.10The semiconductor substrate 10 includes a silicon substrate, and the semiconductor structure further includes a silicon germanium layer 45, which is disposed between the silicon substrate in the PMOS region and the second gate stack structure 30. By disposing the silicon germanium layer 45 between the silicon substrate in the PMOS region and the gate oxide layer 41 of the second gate stack structure 30, germanium can be used to adjust the lattice constant of silicon, thereby improving electron mobility and increasing the operating current.

[0129] In some examples, the semiconductor structure also includes an N-type source and drain region and a P-type source and drain region, the N-type source and drain region is located in the semiconductor substrate 10 in the NMOS region, and the N-type source and drain region is respectively located on opposite sides of the first gate stack structure 20; the P-type source and drain region is located in the semiconductor substrate 10 in the PMOS region, and the P-type source and drain region is respectively located on opposite sides of the second gate stack structure 30.

[0130] Among them, N-type source and drain regions are respectively arranged in the semiconductor substrate 10 on opposite sides of the first gate stack structure 20, and the N-type source and drain regions, the first gate stack structure 20, and the first isolation layer 50 form an NMOS transistor. P-type source and drain regions are respectively arranged in the semiconductor substrate 10 on opposite sides of the second gate stack structure 30, and the P-type source and drain regions, the second gate stack structure 30, and the second isolation layer 60 form a PMOS transistor.

[0131] In summary, the semiconductor structure in the embodiment of the present disclosure includes a semiconductor substrate 10, a first gate stack structure 20 disposed on an NMOS region of the semiconductor substrate 10, a second gate stack structure 30 disposed on a PMOS region of the semiconductor substrate 10, a first isolation layer 50 located on the sidewall of the first gate stack structure 20, and a second isolation layer 60 located on the sidewall of the second gate stack structure 30. Among them, the first gate stack structure 20 and the second gate stack structure 30 both include a high-K dielectric layer 42, and the first isolation layer 50 caps the high-K dielectric layer 42 in the first gate stack structure 20 to protect oxygen vacancies in the high-K dielectric layer 42 in the first gate stack structure 20 and reduce the threshold voltage of the first gate stack structure 20. The second isolation layer 60 includes at least an oxide isolation layer 61, and the oxide isolation layer 61 contacts at least part of the side surface of the high-K dielectric layer 42 in the second gate stack structure 30, thereby repairing the oxygen vacancies in the high-K dielectric layer 42 in the second gate stack structure 30 to improve the electron mobility of the second gate stack structure 30, thereby reducing the threshold voltage of the second gate stack structure 30, and reducing defect scattering, thereby improving the electrical characteristics of the second gate stack structure 30.

[0132] See also Fig.11 The present disclosure also provides a method for manufacturing a semiconductor structure, which may include the following steps:

[0133] Step S100: providing a semiconductor substrate, wherein the semiconductor substrate includes an NMOS region and a PMOS region.

[0134] See also Fig.12 The semiconductor substrate 10 includes an NMOS region and a PMOS region, and the NMOS region and the PMOS region may be spaced apart. Fig.12 As shown in A, it is used to form an NMOS transistor, and the PMOS region is as shown in Fig.12 As shown at B in the figure, it is used to form a PMOS transistor. The material of the semiconductor substrate 10 can be silicon, germanium, silicon germanium, arsenic germanium, silicon on insulator or germanium on insulator, etc.

[0135] Step S200: forming a first gate stack structure on a semiconductor substrate located in an NMOS region, and forming a second gate stack structure on a semiconductor substrate located in a PMOS region, wherein both the first gate stack structure and the second gate stack structure include a high-K dielectric layer.

[0136] See also Fig.13 A first gate stack structure 20 and a second gate stack structure 30 are formed on a semiconductor substrate 10. The first gate stack structure 20 is located on the semiconductor substrate 10 in an NMOS region, and the second gate stack structure 30 is located on the semiconductor substrate 10 in a PMOS region. The first gate stack structure 20 and the second gate stack structure 30 both include a high-K dielectric layer 42. The material of the high-K dielectric layer 42 may include at least one of hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, zirconium oxide, and strontium titanate.

[0137] Step S300: forming a nitride isolation layer on the sidewalls of the first gate stack structure and the sidewalls of the second gate stack structure.

[0138] See also Fig.14 and Fig.15 , a nitride isolation layer 62 is deposited to cover the sidewalls of the first gate stack structure 20 and the sidewalls of the second gate stack structure 30. The top surface of the nitride isolation layer 62 on the sidewall of the first gate stack structure 20 is flush with the top surface of the first gate stack structure 20, and the top surface of the nitride isolation layer 62 on the sidewall of the second gate stack structure 30 is flush with the top surface of the second gate stack structure 30.

[0139] For example, Fig.14 and Fig.15As shown, a nitride isolation layer 62 is deposited on the semiconductor substrate 10, the sidewalls and top surface of the first gate stack structure 20, and the sidewalls and top surface of the second gate stack structure 30. The nitride isolation layer 62 on the semiconductor substrate 10, the top surface of the first gate stack structure 20, and the top surface of the second gate stack structure 30 is removed by etching, and the nitride isolation layer 62 on the sidewalls of the first gate stack structure 20 and the sidewalls of the second gate stack structure 30 is retained. The nitride isolation layer 62 on the sidewalls of the first gate stack structure 20 forms a first isolation layer.

[0140] Step S400: removing at least a portion of the nitride isolation layer on the sidewall of the second gate stack structure to expose at least a portion of the side surface of the high-K dielectric layer in the second gate stack structure.

[0141] See also Fig.16 , the entire nitride isolation layer 62 on the sidewall of the second gate stack structure 30 is etched away to expose the entire sidewall of the second gate stack structure 30, that is, to expose the entire side surface of the high-K dielectric layer 42 in the second gate stack structure 30. Alternatively, refer to Fig.17 , a portion of the nitride isolation layer 62 on the sidewall of the second gate stack structure 30 close to the semiconductor substrate 10 is etched away to expose all or part of the side surfaces of the high-K dielectric layer 42 in the second gate stack structure 30 .

[0142] By removing all or part of the nitride isolation layer 62 on the side wall of the second gate stack structure 30, at least part of the side surface of the high-K dielectric layer 42 in the second gate stack structure 30 is exposed to facilitate repair of the high-K dielectric layer 42 in the second gate stack structure 30, thereby improving the electrical performance of the second gate stack structure 30.

[0143] It can be understood that the nitride isolation layer 62 on the sidewall of the first gate stack structure 20 is retained, and the nitride isolation layer 62 covers the side of the high-K dielectric layer 42 in the first gate stack structure 20. In this way, the high-K dielectric layer 42 in the first gate stack structure 20 is capped by the nitride isolation layer 62 to protect the oxygen vacancies in the high-K dielectric layer 42 in the first gate stack structure 20 and reduce the threshold voltage of the first gate stack structure 20.

[0144] In order to avoid damaging the nitride isolation layer 62 on the sidewall of the first gate stack structure 20 when removing the nitride isolation layer 62 on the sidewall of the second gate stack structure 30, refer to Fig.15 , Fig.18 and Fig.16Before removing at least a portion of the nitride isolation layer 62 located on the sidewall of the second gate stack structure 30 , the method further includes: forming a protective layer 70 , wherein the protective layer 70 covers the first gate stack structure 20 and the nitride isolation layer 62 located on the sidewall of the first gate stack structure 20 .

[0145] Step S500: forming an oxide isolation layer that at least covers at least a portion of the side surfaces of the high-K dielectric layer in the second gate stack structure.

[0146] See also Fig.19 , forming an oxide isolation layer 61, the oxide isolation layer 61 at least covers the exposed side of the high-K dielectric layer 42 in the second gate stack structure 30. Oxygen is introduced during the formation of the oxide isolation layer 61 to repair the oxygen vacancies in the exposed high-K dielectric layer 42, so as to improve the electron mobility of the second gate stack structure 30, thereby reducing the threshold voltage of the second gate stack structure 30, reducing defect scattering, and improving the electrical characteristics of the second gate stack structure 30.

[0147] In summary, in the method for manufacturing the semiconductor structure in the embodiment of the present disclosure, a nitride isolation layer 62 is formed on the sidewalls of the first gate stack structure 20 and the sidewalls of the second gate stack structure 30, and at least a portion of the nitride isolation layer 62 on the sidewalls of the second gate stack structure 30 is removed to expose at least a portion of the side surface of the high-K dielectric layer 42 in the second gate stack structure 30, and then an oxide isolation layer 61 is formed on the exposed side surface of the high-K dielectric layer 42 in the second gate stack structure 30. The oxygen introduced during the formation of the oxide isolation layer 61 is used to repair the oxygen vacancies in the exposed high-K dielectric layer 42 to improve the electron mobility of the second gate stack structure 30, thereby reducing the threshold voltage of the second gate stack structure 30, reducing defect scattering, and improving the electrical characteristics of the second gate stack structure 30. In addition, the nitride isolation layer 62 on the sidewalls of the first gate stack structure 20 caps the high-K dielectric layer 42 in the first gate stack structure 20 to protect the oxygen vacancies in the high-K dielectric layer 42 in the first gate stack structure 20 and reduce the threshold voltage of the first gate stack structure 20.

[0148] For some possible examples, see Fig.16 , Fig. 20 , Fig.21 and Fig. 22 , removing at least a portion of the nitride isolation layer 62 located on the sidewall of the second gate stack structure 30, including: using wet etching to remove all of the nitride isolation layer 62 located on the sidewall of the second gate stack structure 30. Accordingly, forming an oxide isolation layer 61 that at least covers at least a portion of the side surface of the high-K dielectric layer 42 in the second gate stack structure 30, including: forming the oxide isolation layer 61 on the sidewall of the second gate stack structure 30.

[0149] like Fig.16 As shown, the nitride isolation layer 62 on the sidewall of the second gate stack structure 30 is removed by wet etching, exposing the entire sidewall of the second gate stack structure 30, that is, exposing the side surface of the high-K dielectric layer 42 in the second gate stack structure 30, and the top surface of the second gate stack structure 30 may also be exposed. Then, an oxide isolation layer 61 is formed on the sidewall of the second gate stack structure 30. The oxide isolation layer 61 may also cover the top surface of the second gate stack structure 30.

[0150] like Fig. 20 As shown, when the oxide isolation layer 61 is formed, the oxide isolation layer 61 can be deposited on the side walls and top surface of the second gate stack structure 30, on the semiconductor substrate 10, and on the side walls and top surface of the protective layer 70, and at least the oxide isolation layer 61 on the semiconductor substrate 10 and the top surface of the protective layer 70 is etched and removed.

[0151] For example, Fig.21 As shown, the oxide isolation layer 61 on the top surface of the second gate stack structure 30, on the semiconductor substrate 10, and on the top surface of the protection layer 70 is removed by etching. Fig. 22 As shown, the protective layer 70 and the oxide isolation layer 61 on the sidewalls thereof are removed to expose the first gate stack structure 20 and the corresponding nitride isolation layer 62. The protective layer 70 is then removed. For another example, Fig.19 As shown, the oxide isolation layer 61 on the semiconductor substrate 10 and on the top surface of the protection layer 70 is removed by etching, and then the protection layer 70 and the oxide isolation layer 61 on the sidewalls thereof are removed.

[0152] For other possible examples, see Fig.15 and Fig.17 , removing at least a portion of the nitride isolation layer 62 located on the sidewall of the second gate stack structure 30, including: removing a portion of the nitride isolation layer 62 located at the bottom of the sidewall of the second gate stack structure 30 by wet etching to form a bottom cut 63, wherein the bottom cut 63 exposes at least a portion of the side surface of the high-K dielectric layer 42 in the second gate stack structure 30, and the thickness of the remaining nitride isolation layer 62 located on the sidewall of the second gate stack structure 30 is less than the thickness of the nitride isolation layer 62 located on the sidewall of the first gate stack structure 20. Accordingly, forming an oxide isolation layer 61 that at least covers at least a portion of the side surface of the high-K dielectric layer 42 in the second gate stack structure 30, including: forming an oxide isolation layer 61 that at least fills the bottom cut 63.

[0153] like Fig.17As shown, in the process of removing the nitride isolation layer 62 on the side wall of the second gate stack structure 30 by wet etching with an etching solution, since the bottom nitride isolation layer 62 on the side wall of the second gate stack structure 30 close to the semiconductor substrate 10 is exposed to a larger amount of etching solution than other parts, a portion of the nitride isolation layer 62 at the bottom of the side wall of the second gate stack structure 30 is removed, and at the same time, the nitride isolation layer 62 on other parts of the side wall of the second gate stack structure 30 is thinned.

[0154] The thickness of the remaining nitride isolation layer 62 on the sidewall of the second gate stack structure 30 is less than the thickness of the nitride isolation layer 62 on the sidewall of the first gate stack structure 20, and a bottom cut 63 is formed between the remaining nitride isolation layer 62 on the sidewall of the second gate stack structure 30 and the semiconductor substrate 10. The bottom cut 63 exposes part or all of the side surfaces of the high-K dielectric layer 42 in the second gate stack structure 30, that is, the bottom surface of the remaining nitride isolation layer 62 on the sidewall of the second gate stack structure 30 is higher than the bottom surface of the high-K dielectric layer 42 in the second gate stack structure 30.

[0155] See also Fig.17 , Fig.23 and Fig.24 , forming an oxide isolation layer 61, the oxide isolation layer 61 at least fills the bottom cut 63. For example, Fig.17 and Fig.23 As shown, an oxide isolation layer 61 is deposited on the semiconductor substrate 10, on the sidewalls and top surface of the nitride isolation layer 62 in contact with the second gate stack structure 30 in the bottom cutout 63, and on the top surface of the second gate stack structure 30. Then, the oxide isolation layer 61 deposited on the sidewalls and top surface of the nitride isolation layer 62 in contact with the second gate stack structure 30 on the semiconductor substrate 10, and on the top surface of the second gate stack structure 30 is removed, and only the oxide isolation layer 61 in the bottom cutout 63 is retained, that is, the oxide isolation layer 61 only fills the bottom cutout 63, and does not cover the sidewalls of the remaining nitride isolation layer 62 located on the sidewalls of the second gate stack structure 30.

[0156] For example, see Fig.17 , Fig.23 and Fig.25 , an oxide isolation layer 61 is deposited on the semiconductor substrate 10, in the bottom cutout 63, on the sidewalls and top surface of the nitride isolation layer 62 in contact with the second gate stack structure 30, and on the top surface of the second gate stack structure 30. The oxide isolation layer 61 on the semiconductor substrate 10 is then removed, and the remaining oxide isolation layer 61 covers the second gate stack structure 30 and the nitride isolation layer 62 thereon, that is, the oxide isolation layer 61 covers the sidewalls of the remaining nitride isolation layer 62 on the sidewalls of the second gate stack structure 30, and fills the bottom cutout 63.

[0157] Of course, before removing at least part of the nitride isolation layer 62 located on the side wall of the second gate stack structure 30, it also includes: forming a protective layer 70, the protective layer 70 covers the first gate stack structure 20 and the nitride isolation layer 62 located on the side wall of the first gate stack structure 20, so as to ensure that the nitride isolation layer 62 on the side wall of the first gate stack structure 20 is retained, thereby ensuring the sealing of the high-K dielectric layer 42 in the first gate stack structure 20.

[0158] For some possible examples, see Figures 26 to 30 , forming a first gate stack structure 20 on a semiconductor substrate 10 located in an NMOS region, and forming a second gate stack structure 30 on a semiconductor substrate 10 located in a PMOS region (step S200), comprising:

[0159] Step S201 : forming a gate oxide layer 41 , a high-K dielectric layer 42 , and a first work function adjustment structure 21 stacked in sequence on the semiconductor substrate 10 located in the NMOS region and the PMOS region.

[0160] like Fig.26 As shown, illustratively, a gate oxide layer 41 is deposited on the semiconductor substrate 10 located in the NMOS region and the semiconductor substrate 10 in the PMOS region, a high-K dielectric layer 42 is deposited on the gate oxide layer 41 , and a first work function adjustment structure 21 is deposited on the high-K dielectric layer 42 .

[0161] The gate oxide layer 41 includes silicon oxide. The first work function adjustment structure 21 includes a first work function adjustment layer 22 and a first diffusion barrier layer 23 located on the first work function adjustment layer 22. The material of the first work function adjustment layer 22 includes at least one of lanthanum oxide, yttrium oxide, germanium oxide, lutetium oxide and strontium oxide, and the material of the first diffusion barrier layer 23 includes at least one of titanium nitride and tantalum nitride.

[0162] Step S202 : removing the first work function adjustment structure 21 opposite to the PMOS region.

[0163] See also Fig.26 and Fig. 27 As shown, the first work function regulating structure 21 opposite to the PMOS region is removed by etching to expose the high-K dielectric layer 42 opposite to the PMOS region.

[0164] Step S203: forming a second work function adjustment structure 31 on the high-K dielectric layer 42 opposite to the PMOS region.

[0165] The second work function regulating structure 31 includes a second diffusion barrier layer 32, a second work function regulating layer 33 located on the second diffusion barrier layer 32, and a third diffusion barrier layer 34 located on the second work function regulating layer 33, that is, the second diffusion barrier layer 32, the second work function regulating layer 33 and the third diffusion barrier layer 34 are stacked in sequence. The material of the second work function regulating layer 33 includes at least one of aluminum oxide, titanium oxide, hafnium oxide, zirconium oxide and magnesium oxide; the materials of the second diffusion barrier layer 32 and the third diffusion barrier layer 34 include at least one of titanium nitride and tantalum nitride respectively.

[0166] For some possible implementations, see Fig.28 and Fig.29 , depositing a second work function adjustment structure 31 on the high-K dielectric layer 42 relative to the PMOS region and on the first work function adjustment structure 21 relative to the NMOS region; and etching away the second work function adjustment structure 31 relative to the NMOS region to expose the first work function adjustment structure 21 relative to the NMOS region.

[0167] Step S204 : forming a gate layer 43 and a cap layer 44 stacked in sequence on the first work function adjustment structure 21 opposite to the NMOS region and the second work function adjustment structure 31 opposite to the PMOS region.

[0168] See also Fig.30 A gate layer 43 is deposited on the first work function adjustment structure 21 opposite to the NMOS region and the second work function adjustment structure 31 opposite to the PMOS region, and a cap layer 44 is deposited on the gate layer 43. The material of the gate layer 43 includes tungsten or polysilicon, and the material of the cap layer 44 includes nitride.

[0169] Step S205: patterning the gate oxide layer 41, the high-K dielectric layer 42, the first work function adjustment structure 21, the gate layer 43 and the cap layer 44 relative to the NMOS region to form a first gate stack structure 20, and simultaneously patterning the gate oxide layer 41, the high-K dielectric layer 42, the second work function adjustment structure 31, the gate layer 43 and the cap layer 44 relative to the PMOS region to form a second gate stack structure 30.

[0170] See also Fig.30 , Figure 3 and Figure 4 The gate oxide layer 41, the high-K dielectric layer 42, the first work function adjustment structure 21, the gate layer 43 and the cap layer 44 relative to the NMOS region are patterned to form a first gate stack structure 20. The gate oxide layer 41, the high-K dielectric layer 42, the second work function adjustment structure 31, the gate layer 43 and the cap layer 44 relative to the PMOS region are patterned to form a second gate stack structure 30.

[0171] After forming the first gate stack structure 20 and the second gate stack structure 30, ion implantation and debonding are performed in the semiconductor substrate 10 on opposite sides of the first gate stack structure 20 to form N-type source and drain regions. Ion implantation and debonding are performed in the semiconductor substrate 10 on opposite sides of the second gate stack structure 30 to form P-type source and drain regions.

[0172] For some examples, see Fig.31 The semiconductor substrate 10 includes a silicon substrate; before forming a gate oxide layer 41, a high-K dielectric layer 42 and a first work function adjustment structure 21 stacked in sequence on the semiconductor substrate 10 located in the NMOS region and the PMOS region, the manufacturing method also includes: forming a silicon germanium layer 45 on the silicon substrate located in the PMOS region.

[0173] It can be understood that a silicon germanium layer 45 is formed between the silicon substrate located in the PMOS region and the gate oxide layer 41 opposite to the PMOS region. The silicon germanium layer 45 serves as an epitaxial layer of the silicon substrate and uses germanium to adjust the silicon lattice to improve electron mobility and improve the electrical performance of the PMOS region.

[0174] In this specification, each embodiment or implementation is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referenced to each other. The description of reference terms such as "one implementation", "some implementations", "illustrative implementations", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the implementation or example are included in at least one implementation or example of the present disclosure. In this specification, the schematic representation of the above terms does not necessarily refer to the same implementation or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more implementations or examples in a suitable manner.

[0175] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A semiconductor structure, characterized in that: include: A semiconductor substrate, wherein the semiconductor substrate includes an NMOS region and a PMOS region; A first gate stack structure located on the semiconductor substrate in the NMOS region, and a second gate stack structure located on the semiconductor substrate in the PMOS region, wherein both the first gate stack structure and the second gate stack structure include a high-K dielectric layer; A first isolation layer located on the sidewall of the first gate stack structure, wherein a material of the first isolation layer comprises nitride; A second isolation layer is located on the sidewall of the second gate stack structure, wherein the second isolation layer at least includes an oxide isolation layer, and the oxide isolation layer at least covers at least a portion of the side surface of the high-K dielectric layer in the second gate stack structure.

2. The semiconductor structure according to claim 1, characterized in that: The oxide isolation layer covers the sidewalls of the second gate stack structure.

3. The semiconductor structure according to claim 1, characterized in that: The second isolation layer further includes a nitride isolation layer, the nitride isolation layer covers a portion of the sidewall of the second gate stack structure, a bottom cut is formed between the nitride isolation layer and the semiconductor substrate, and the bottom cut exposes at least a portion of the side surface of the high-K dielectric layer in the second gate stack structure; The oxide isolation layer covers the sidewalls of the nitride isolation layer and fills the bottom cut; or, the oxide isolation layer only fills the bottom cut but does not cover the sidewalls of the nitride isolation layer located on the sidewalls of the second gate stack structure.

4. The semiconductor structure according to claim 3, characterized in that: The thickness of the nitride isolation layer in the second isolation layer is smaller than the thickness of the first isolation layer.

5. The semiconductor structure according to any one of claims 1 to 4, characterized in that: The first gate stack structure comprises a gate oxide layer, the high-K dielectric layer, a first work function adjustment structure, a gate layer and a cap layer stacked in sequence on the semiconductor substrate, wherein the first work function adjustment structure comprises a first work function adjustment layer and a first diffusion barrier layer located on the first work function adjustment layer; The second gate stack structure includes the gate oxide layer, the high-K dielectric layer, the second work function adjustment structure, the gate layer and the cap layer stacked in sequence on the semiconductor substrate, wherein the second work function adjustment structure includes a second diffusion barrier layer, a second work function adjustment layer located on the second diffusion barrier layer, and a third diffusion barrier layer located on the second work function adjustment layer.

6. The semiconductor structure according to claim 5, characterized in that: The material of the first work function regulating layer includes at least one of lanthanum oxide, yttrium oxide, germanium oxide, lutetium oxide and strontium oxide; The material of the first diffusion barrier layer includes at least one of titanium nitride and tantalum nitride; The material of the second work function regulating layer includes at least one of aluminum oxide, titanium oxide, hafnium oxide, zirconium oxide and magnesium oxide; The materials of the second diffusion barrier layer and the third diffusion barrier layer include at least one of titanium nitride and tantalum nitride, respectively.

7. The semiconductor structure according to claim 5, characterized in that: The material of the gate oxide layer includes silicon oxide; The material of the high-K dielectric layer includes at least one of hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, zirconium oxide and strontium titanate; The material of the capping layer includes nitride.

8. The semiconductor structure according to any one of claims 1 to 4, characterized in that: The semiconductor substrate comprises a silicon substrate; The semiconductor structure further comprises: A silicon germanium layer is disposed between the silicon substrate and the second gate stack structure in the PMOS region.

9. The semiconductor structure according to any one of claims 1 to 4, characterized in that: The semiconductor structure further comprises: N-type source and drain regions in the semiconductor substrate in the NMOS region, the N-type source and drain regions being located at opposite sides of the first gate stack structure; A P-type source and drain region in the semiconductor substrate in the PMOS region, wherein the P-type source and drain regions are respectively located on two opposite sides of the second gate stack structure.

10. A method for manufacturing a semiconductor structure, characterized in that: include: Providing a semiconductor substrate, wherein the semiconductor substrate includes an NMOS region and a PMOS region; Forming a first gate stack structure on the semiconductor substrate located in the NMOS region, and forming a second gate stack structure on the semiconductor substrate located in the PMOS region, wherein both the first gate stack structure and the second gate stack structure include a high-K dielectric layer; forming a nitride isolation layer on the sidewalls of the first gate stack structure and the sidewalls of the second gate stack structure; Removing at least a portion of the nitride isolation layer on the sidewall of the second gate stack structure to expose at least a portion of the side surface of the high-K dielectric layer in the second gate stack structure; An oxide isolation layer is formed to cover at least a portion of the side surface of the high-K dielectric layer in the second gate stack structure.

11. The manufacturing method according to claim 10, characterized in that: Removing at least a portion of the nitride isolation layer located on the sidewall of the second gate stack structure includes: Removing all of the nitride isolation layer located on the sidewalls of the second gate stack structure by wet etching; Forming an oxide isolation layer that at least covers the at least partial side surface of the high-K dielectric layer in the second gate stack structure includes: forming the oxide isolation layer on the sidewall of the second gate stack structure.

12. The manufacturing method according to claim 10, characterized in that: Removing at least a portion of the nitride isolation layer located on the sidewall of the second gate stack structure includes: Removing a portion of the nitride isolation layer at the bottom of the sidewall of the second gate stack structure by wet etching to form a bottom cut, wherein the bottom cut exposes at least a portion of the side surface of the high-K dielectric layer in the second gate stack structure, and the thickness of the remaining nitride isolation layer on the sidewall of the second gate stack structure is less than the thickness of the nitride isolation layer on the sidewall of the first gate stack structure; Forming an oxide isolation layer that at least covers the at least partial side surface of the high-K dielectric layer in the second gate stack structure includes: forming the oxide isolation layer that at least fills the bottom cut.

13. The manufacturing method according to claim 12, characterized in that: The oxide isolation layer covers the sidewalls of the remaining nitride isolation layer on the sidewalls of the second gate stack structure and fills the bottom cut; Alternatively, the oxide isolation layer only fills the bottom cut, but does not cover the sidewalls of the remaining nitride isolation layer on the sidewalls of the second gate stack structure.

14. The production method according to any one of claims 10 to 13, characterized in that: A first gate stack structure is formed on the semiconductor substrate located in the NMOS region, and a second gate stack structure is formed on the semiconductor substrate in the PMOS region, including: Forming a gate oxide layer, the high-K dielectric layer and a first work function adjustment structure stacked in sequence on the semiconductor substrate located in the NMOS region and the PMOS region; removing the first work function adjustment structure relative to the PMOS region; forming a second work function adjustment structure on the high-K dielectric layer opposite to the PMOS region; Forming a gate layer and a cap layer stacked in sequence on the first work function adjustment structure opposite to the NMOS region and the second work function adjustment structure opposite to the PMOS region; The gate oxide layer, the high-K dielectric layer, the first work function adjustment structure, the gate layer and the cap layer are patterned relative to the NMOS region to form the first gate stack structure, and the gate oxide layer, the high-K dielectric layer, the second work function adjustment structure, the gate layer and the cap layer are patterned relative to the PMOS region to form the second gate stack structure.

15. The manufacturing method according to claim 14, characterized in that: The first work function regulating structure includes a first work function regulating layer and a first diffusion barrier layer located on the first work function regulating layer; The second work function regulating structure includes a second diffusion barrier layer, a second work function regulating layer located on the second diffusion barrier layer, and a third diffusion barrier layer located on the second work function regulating layer.

16. The manufacturing method according to claim 14, characterized in that: The semiconductor substrate comprises a silicon substrate; Before forming the gate oxide layer, the high-K dielectric layer and the first work function adjustment structure stacked in sequence on the semiconductor substrate located in the NMOS region and the PMOS region, the manufacturing method further includes: A silicon germanium layer is formed on the silicon substrate located in the PMOS region.

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