Preparation method of semiconductor structure and semiconductor structure

Abstract

The embodiment of the invention provides a preparation method of a semiconductor structure and the semiconductor structure. The method comprises the following steps: providing a semiconductor substrate which comprises an NMOS (N-channel Metal Oxide Semiconductor) region and a PMOS (P-channel Forming a gate oxide layer and a high-K dielectric layer which are stacked in sequence on the NMOS region and the PMOS region; forming a first work function adjusting structure on the high-K dielectric layer in the NMOS region; forming a second work function adjusting structure on the high-K dielectric layer of the PMOS region; forming a gate layer and a first nitride layer on the first work function adjusting structure and the second work function adjusting structure; removing the first nitride layer in the PMOS region; forming an oxide layer on the first nitride layer of the NMOS region and the gate layer of the PMOS region; patterning the stack layer of the NMOS region to form a first gate stack structure, and patterning the stack layer of the PMOS region to form a second gate stack structure; and forming a second nitride layer on the side wall of the first gate stack structure and the side wall of the second gate stack structure. According to the method disclosed by the invention, the threshold voltage of the NMOS and the PMOS can be reduced.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor manufacturing technology, and in particular to a method for manufacturing a semiconductor structure and a semiconductor structure. Background Art

[0002] As the size of semiconductor process shrinks, the channel length of MOSFET (Metal Oxide Semiconductor Field Effect Transistor, Metal Oxide Semiconductor Field Effect Transistor, can be referred to as MOS) continues to decrease, making the short channel effect more serious. In order to suppress the short channel effect, a high-K dielectric layer is introduced into the gate electrode structure of NMOS (N Metal Oxide Semiconductor, N-type metal-oxide semiconductor or NMOS transistor) and PMOS (P Metal Oxide Semiconductor, P-type metal-oxide semiconductor or PMOS transistor), but the high-K dielectric layer makes the threshold voltage of NMOS and PMOS too high. Among them, during the deposition process of the high-K dielectric layer, oxygen vacancies will be formed, and the oxygen vacancies can provide a positive potential, reduce the mobility of PMOS, increase the threshold voltage of PMOS, and reduce the electrical performance of PMOS.

[0003] The above information disclosed in this background section is only for enhancement of understanding of the background of the present disclosure and therefore it may include information that does not constitute the relevant technology that is already known to one of ordinary skill in the art. Summary of the invention

[0004] The embodiments of the present disclosure provide a method for preparing a semiconductor structure and a semiconductor structure, which can reduce the threshold voltage of NMOS and PMOS and improve the electrical performance of NMOS and PMOS.

[0005] The present disclosure provides a method for preparing a semiconductor structure, comprising: providing a semiconductor substrate, the semiconductor substrate comprising an NMOS region and a PMOS region; forming a gate oxide layer and a high-K dielectric layer stacked in sequence on the NMOS region and the PMOS region; forming a first work function adjustment structure on the high-K dielectric layer in the NMOS region; forming a second work function adjustment structure on the high-K dielectric layer in the PMOS region; forming a gate layer and a first nitride layer stacked in sequence on the first work function adjustment structure in the NMOS region and the second work function adjustment structure in the PMOS region; removing the gate oxide layer and the high-K dielectric layer ... The first nitride layer; forming an oxide layer on the first nitride layer in the NMOS region and the gate layer in the PMOS region; patterning the gate oxide layer, the high-K dielectric layer, the first work function adjustment structure, the gate layer, the first nitride layer and the oxide layer in the NMOS region to form a first gate stack structure, and patterning the gate oxide layer, the high-K dielectric layer, the second work function adjustment structure, the gate layer and the oxide layer in the PMOS region to form a second gate stack structure; forming a second nitride layer on the sidewalls of the first gate stack structure and the sidewalls of the second gate stack structure.

[0006] In some embodiments of the present disclosure, a first work function adjustment structure is formed on the high-K dielectric layer in the NMOS region, including: forming a first work function adjustment layer on the high-K dielectric layer in the NMOS region; and forming a first diffusion barrier layer on the first work function adjustment layer.

[0007] In some embodiments of the present disclosure, a second work function adjustment structure is formed on the high-K dielectric layer in the PMOS region, including: forming a second diffusion barrier layer on the high-K dielectric layer in the PMOS region; forming a second work function adjustment layer on the second diffusion barrier layer; and forming a third diffusion barrier layer on the second work function adjustment layer.

[0008] In some embodiments of the present disclosure, before forming the second work function adjustment structure on the high-K dielectric layer in the PMOS region, it also includes: forming the first work function adjustment structure on the high-K dielectric layer in the PMOS region while forming the first work function adjustment structure on the high-K dielectric layer in the NMOS region; forming a mask layer on the first work function adjustment structure in the NMOS region; and removing the first work function adjustment structure on the high-K dielectric layer in the PMOS region.

[0009] In some embodiments of the present disclosure, after removing the first work function adjustment structure on the high-K dielectric layer in the PMOS region, it also includes: forming the second work function adjustment structure on the mask layer in the NMOS region and on the high-K dielectric layer in the PMOS region; removing the mask layer and the second work function adjustment structure in the NMOS region to expose the first work function adjustment structure.

[0010] In some embodiments of the present disclosure, the material of the gate oxide layer includes silicon oxide; the material of the high-K dielectric layer includes at least one of hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, zirconium oxide and strontium titanate.

[0011] In some embodiments of the present disclosure, the material of the first work function adjustment layer includes at least one of lanthanum oxide, yttrium oxide, germanium oxide, lutetium oxide and strontium oxide; the material of the first diffusion barrier layer includes at least one of titanium nitride and tantalum nitride.

[0012] In some embodiments of the present disclosure, the material of the second work function adjustment layer includes at least one of aluminum oxide, titanium oxide, hafnium oxide, zirconium oxide and magnesium oxide; the materials of the second diffusion barrier layer and the third diffusion barrier layer include at least one of titanium nitride and tantalum nitride respectively.

[0013] The presently disclosed embodiment also provides a semiconductor structure, comprising: a semiconductor substrate, comprising an NMOS region and a PMOS region; a first gate stack structure, located in the NMOS region, the first gate stack structure comprising a gate oxide layer, a high-K dielectric layer, a first work function adjustment structure, a gate layer, a first nitride layer and an oxide layer stacked in sequence on the semiconductor substrate; a second gate stack structure, located in the PMOS region, the second gate stack structure comprising the gate oxide layer, the high-K dielectric layer, the second work function adjustment structure, the gate layer and the oxide layer stacked in sequence on the semiconductor substrate; the side walls of the first gate stack structure and the second gate stack structure are respectively provided with a second nitride layer.

[0014] In some embodiments of the present disclosure, the first gate stack structure and the second gate stack structure have the same height in the vertical direction.

[0015] In some embodiments of the present disclosure, the first gate stack structure having the second nitride layer on the sidewall is a gate electrode of NMOS, and the second stack structure having the second nitride layer on the sidewall is a gate electrode of PMOS.

[0016] It can be seen from the above technical solutions that the method for preparing the semiconductor structure of the embodiment of the present disclosure has at least one of the following advantages and positive effects:

[0017] In the disclosed embodiment, a first work function adjustment structure is formed on the high-K dielectric layer in the NMOS region, which can adjust the threshold voltage of the NMOS formed subsequently, and a first nitride layer is formed on the gate layer on the first work function adjustment structure in the NMOS region, and the first nitride layer can protect the oxygen vacancies provided by the high-K dielectric layer, so that the oxygen vacancies are retained, further reducing the threshold voltage of the NMOS and improving the electrical performance of the NMOS. A second work function adjustment structure is formed on the high-K dielectric layer in the PMOS region, which can adjust the threshold voltage of the PMOS formed subsequently, and oxygen can be introduced in the process of forming an oxide layer on the gate layer of the PMOS to repair (reduce) the oxygen vacancies in the PMOS, thereby reducing the threshold voltage of the PMOS and reducing defect scattering, thereby improving the electrical performance of the PMOS. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above and other features and advantages of the present disclosure will become more apparent by describing in detail example embodiments thereof with reference to the attached drawings.

[0019] Figure 1 A flow chart of a method for preparing a semiconductor structure according to some embodiments of the present disclosure;

[0020] Figure 2 A schematic diagram of a semiconductor substrate according to some embodiments of the present disclosure;

[0021] Figure 3 A schematic diagram showing the formation of a gate oxide layer and a high-K dielectric layer in an NMOS region and a PMOS region of a semiconductor substrate according to some embodiments of the present disclosure;

[0022] Figure 4 A schematic diagram showing a first work function adjustment structure formed in an NMOS region and a PMOS region according to some embodiments of the present disclosure;

[0023] Figure 5 A schematic diagram showing forming a mask layer on the first work function adjustment structure in the NMOS region and removing the first work function adjustment structure in the PMOS region according to some embodiments of the present disclosure;

[0024] Figure 6 A schematic diagram showing a second work function adjustment structure formed on a mask layer in an NMOS region and a high-K dielectric layer in a PMOS region according to some embodiments of the present disclosure;

[0025] Figure 7 A schematic diagram of removing the mask layer of the NMOS region and the second work function adjustment structure according to some embodiments of the present disclosure;

[0026] Figure 8A schematic diagram of forming a gate layer in an NMOS region and a PMOS region according to some embodiments of the present disclosure;

[0027] Fig. 9 A schematic diagram showing forming a first nitride layer on a gate layer of an NMOS region and a PMOS region according to some embodiments of the present disclosure;

[0028] Fig.10 A schematic diagram of removing the first nitride layer in the PMOS region and forming an oxide layer on the gate layer in the PMOS region and on the first nitride layer in the NMOS region according to some embodiments of the present disclosure;

[0029] Fig.11 A schematic diagram of patterning a stacked layer of an NMOS region to form a first gate stacked structure and patterning a stacked layer of a PMOS region to form a second gate stacked structure according to some embodiments of the present disclosure;

[0030] Fig.12 Schematic diagram of forming a second nitride layer on the sidewalls of a first gate stack structure and a second gate stack structure according to some embodiments of the present disclosure.

[0031] Description of reference numerals:

[0032] 1. semiconductor substrate; 101. NMOS region; 102. PMOS region; 2. gate oxide layer; 3. high-K dielectric layer; 4. first work function adjustment structure; 41. first diffusion barrier layer; 42. first work function adjustment layer; 5. mask layer; 6. second work function adjustment structure; 61. second diffusion barrier layer; 62. second work function adjustment layer; 63. third diffusion barrier layer; 7. gate layer; 8. first nitride layer; 9. oxide layer; 10. second nitride layer; Y, vertical direction. DETAILED DESCRIPTION

[0033] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be comprehensive and complete and will fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their detailed description will be omitted.

[0034] In the following description of different exemplary embodiments of the present disclosure, reference is made to the accompanying drawings, which form a part of the present disclosure and in which different exemplary structures that can implement multiple aspects of the present disclosure are shown by way of example. It should be understood that other specific schemes of components, structures, exemplary devices, systems and steps can be used, and structural and functional modifications can be made without departing from the scope of the present disclosure. Moreover, although the terms "above", "between", "within", etc. may be used in this specification to describe different exemplary features and elements of the present disclosure, these terms are used herein only for convenience, such as according to the direction of the examples in the accompanying drawings. Nothing in this specification should be construed as requiring a specific three-dimensional direction of the structure to fall within the scope of the present disclosure. In addition, the terms "first", "second", etc. in the claims are used only as marks and are not numerical limitations on their objects.

[0035] The flowcharts shown in the accompanying drawings are only exemplary and do not necessarily include all the contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps can be decomposed, and some operations / steps can be combined or partially combined, so the actual execution order may change according to actual conditions.

[0036] In addition, in the description of the present disclosure, “plurality” means at least two, for example, two, three, etc., unless otherwise clearly and specifically defined.

[0037] like Figures 1 to 12 As shown, the embodiment of the present disclosure provides a method for preparing a semiconductor structure. Figure 1 A flow chart showing a method for preparing a semiconductor structure is shown, Figures 2 to 12 Schematic diagrams of semiconductor structures at different steps in the preparation process are shown respectively.

[0038] like Figure 1 As shown, the method for preparing the semiconductor structure of the embodiment of the present disclosure includes the following steps S110 to S190.

[0039] S110 : providing a semiconductor substrate 1 , wherein the semiconductor substrate 1 includes an NMOS region 101 and a PMOS region 102 .

[0040] S120 : forming a gate oxide layer 2 and a high-K dielectric layer 3 stacked in sequence on the NMOS region 101 and the PMOS region 102 .

[0041] S130 : forming a first work function adjustment structure 4 on the high-K dielectric layer 3 of the NMOS region 101 .

[0042] S140 : forming a second work function adjustment structure 6 on the high-K dielectric layer 3 in the PMOS region 102 .

[0043] S150 : forming a gate layer 7 and a first nitride layer 8 stacked in sequence on the first work function adjustment structure 4 of the NMOS region 101 and the second work function adjustment structure 6 of the PMOS region 102 .

[0044] S160 : removing the first nitride layer 8 in the PMOS region 102 .

[0045] S170 : forming an oxide layer 9 on the first nitride layer 8 of the NMOS region 101 and the gate layer of the PMOS region 102 .

[0046] S180: Patterning the gate oxide layer 2, high-K dielectric layer 3, first work function adjustment structure 4, gate layer 7, first nitride layer 8 and oxide layer 9 of the NMOS region 101 to form a first gate stack structure, and patterning the gate oxide layer 2, high-K dielectric layer 3, second work function adjustment structure 6, gate layer 7 and oxide layer 9 of the PMOS region 102 to form a second gate stack structure.

[0047] S190 : forming a second nitride layer 10 on the sidewalls of the first gate stack structure and the second gate stack structure.

[0048] In the disclosed embodiment, a first work function adjustment structure 4 is formed on the high-K dielectric layer 3 of the NMOS region 101, which can adjust the threshold voltage of the NMOS formed subsequently. A first nitride layer 8 is formed on the gate layer 7 on the first work function adjustment structure 4 of the NMOS region 101, which can protect the oxygen vacancies provided by the high-K dielectric layer 3, so that the oxygen vacancies are retained, further reducing the threshold voltage of the NMOS and improving the electrical performance of the NMOS. A second work function adjustment structure 6 is formed on the high-K dielectric layer 3 of the PMOS region 102, which can adjust the threshold voltage of the PMOS formed subsequently, and oxygen can be introduced in the process of forming the oxide layer 9 on the gate layer 7 of the PMOS to repair the oxygen vacancies in the PMOS, thereby reducing the threshold voltage of the PMOS and reducing defect scattering, thereby improving the electrical performance of the PMOS.

[0049] The following is a detailed description of the method for preparing the semiconductor structure according to the embodiment of the present disclosure.

[0050] S110 : providing a semiconductor substrate 1 , wherein the semiconductor substrate 1 includes an NMOS region 101 and a PMOS region 102 .

[0051] like Figure 1 and Figure 2As shown, a semiconductor substrate 1 is provided. The material of the semiconductor substrate 1 of the embodiment of the present disclosure can be silicon, silicon carbide, silicon on insulator, stacked silicon on insulator, stacked silicon germanium on insulator, silicon germanium on insulator or germanium on insulator, etc. The substrate can also be implanted with certain doping particles to change electrical parameters according to design requirements.

[0052] The semiconductor substrate 1 may include shallow trench isolation (STI), and an active region is provided between the shallow trench isolations. The semiconductor substrate 1 may also be provided with semiconductor devices, such as a word line structure, a bit line structure, etc., and the word line structure and the bit line structure are both connected to the active region. The active region also includes an NMOS region 101 and a PMOS region 102, so that in subsequent processes, an NMOS is formed in the NMOS region 101, and a PMOS is formed in the PMOS region 102.

[0053] S120 : forming a gate oxide layer 2 and a high-K dielectric layer 3 stacked in sequence on the NMOS region 101 and the PMOS region 102 .

[0054] like Figure 3 As shown, a gate oxide layer 2 can be formed in the NMOS region 101 and the PMOS region 102 simultaneously by a deposition process, and a high-K dielectric layer 3 can be formed on the gate oxide layer 2 .

[0055] The material of the gate oxide layer 2 may include silicon oxide (eg SiO 2 ), and the material of the high-K dielectric layer 3 may include at least one of hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, zirconium oxide and strontium titanate.

[0056] The gate oxide layer 2 and the high-K dielectric layer 3 can be used as dielectric layers of the gate. The high-K dielectric layer 3 can improve the short channel effect of the NMOS and PMOS formed in the subsequent process, and improve the gate control ability and electrical performance of the NMOS and PMOS. At the same time, oxygen vacancies can be formed during the deposition and formation of the high-K dielectric layer 3, and the oxygen vacancies can provide a positive potential. For NMOS, the oxygen vacancies are beneficial to reducing the threshold voltage of the NMOS and improving the electrical performance of the NMOS.

[0057] In some embodiments, the deposition process may be at least one of a chemical vapor deposition process, a physical vapor deposition process, and an atomic layer deposition process.

[0058] S130 : forming a first work function adjustment structure 4 on the high-K dielectric layer 3 of the NMOS region 101 .

[0059] like Figure 4As shown, a deposition process can be used to form a first work function adjustment structure 4 in the NMOS region 101. In some embodiments, forming the first work function adjustment structure 4 on the high-K dielectric layer 3 in the NMOS region 101 includes: forming a first work function adjustment layer 42 on the high-K dielectric layer 3 in the NMOS region 101; and forming a first diffusion barrier layer 41 on the first work function adjustment layer 42.

[0060] For example, the material of the first work function adjusting layer 42 may include at least one of lanthanum oxide, yttrium oxide, germanium oxide, lutetium oxide, and strontium oxide. The material of the first diffusion barrier layer 41 may include at least one of titanium nitride and tantalum nitride.

[0061] The first work function adjustment layer 42 can help form a dipole, reduce the effective work function of the stack including the high-K dielectric layer 3, the first work function adjustment structure 4 and the gate layer 7 formed in the subsequent process, and then adjust the threshold voltage of the NMOS to reduce the threshold voltage. The first diffusion barrier layer 41 is located on the first work function adjustment layer 42 to prevent the metal elements of the first work function adjustment layer 42 from diffusing into the gate layer 7 formed subsequently, avoid affecting the gate layer 7 of the NMOS, and ensure the stability of the electrical performance of the NMOS.

[0062] S140 : forming a second work function adjustment structure 6 on the high-K dielectric layer 3 in the PMOS region 102 .

[0063] like Figure 4 As shown, before forming the second work function adjustment structure 6 on the high-K dielectric layer 3 of the PMOS region 102, it also includes: forming the first work function adjustment structure 4 on the high-K dielectric layer 3 of the NMOS region 101 while forming the first work function adjustment structure 4 on the high-K dielectric layer 3 of the PMOS region 102; forming a mask layer 5 on the first work function adjustment structure 4 of the NMOS region 101; and removing the first work function adjustment structure 4 on the high-K dielectric layer 3 of the PMOS region 102.

[0064] Since the deposition process is performed simultaneously on different regions of the semiconductor substrate 1, the first work function adjustment structure 4 is formed on the NMOS region 101 while the first work function adjustment structure 4 is also formed on the high-K dielectric layer 3 in the PMOS region 102. Since the PMOS region 102 does not need the first work function adjustment structure 4, after the first work function adjustment structure 4 is formed in the NMOS region 101 and the PMOS region 102, the first work function adjustment structure 4 in the PMOS region 102 can be removed.

[0065] For example, Figure 5As shown, a mask layer 5 can be formed on the first work function adjustment structure 4 of the NMOS region 101 and the PMOS region 102 by a deposition process, and the material of the mask layer 5 can be photoresist. Then, the mask layer 5 located in the PMOS region 102 is removed by a photolithography process to expose the first work function adjustment structure 4 of the PMOS region 102, and the mask layer 5 of the NMOS region 101 is retained to cover the first work function adjustment structure 4 of the NMOS region 101 for shielding. The first work function adjustment structure 4 of the PMOS region 102 is removed by an etching process to expose the high-K dielectric layer 3. Among them, the material of the mask layer 5 uses photoresist to facilitate removal in subsequent processes. Of course, the material of the mask layer 5 is not limited here, as long as it can be easily removed in subsequent processes.

[0066] After the first work function adjustment structure 4 on the high-K dielectric layer 3 located in the PMOS region 102 is removed, the following contents A1-A2 are also included.

[0067] A1: forming a second work function adjustment structure 6 on the mask layer 5 of the NMOS region 101 and on the high-K dielectric layer 3 of the PMOS region 102 .

[0068] like Figure 6 As shown, a second work function adjustment structure 6 can be formed on the mask layer 5 of the NMOS region 101 and the high-K dielectric layer 3 exposed in the PMOS region 102 by a deposition process. Since the deposition process is simultaneously implemented on different regions of the semiconductor substrate 1, the second work function adjustment structure 6 is formed in both the NMOS region 101 and the PMOS region 102. Since the mask layer 5 is provided in the NMOS region 101, the second work function adjustment structure 6 is not directly formed on the first work function adjustment structure 4, and will not affect the first work function adjustment structure 4, thereby ensuring the stability of the electrical performance of the first work function adjustment structure 4.

[0069] In some embodiments, Figure 6 As shown, forming a second work function adjustment structure 6 on the high-K dielectric layer 3 of the PMOS region 102 includes: forming a second diffusion barrier layer 61 on the high-K dielectric layer 3 of the PMOS region 102; forming a second work function adjustment layer 62 on the second diffusion barrier layer 61; and forming a third diffusion barrier layer 63 on the second work function adjustment layer 62.

[0070] The material of the second work function adjustment layer 62 may include at least one of aluminum oxide, titanium oxide, hafnium oxide, zirconium oxide and magnesium oxide. The materials of the second diffusion barrier layer 61 and the third diffusion barrier layer 63 include at least one of titanium nitride and tantalum nitride, respectively.

[0071] The second work function adjustment layer 62 can increase the effective work function of the stack of the high-K dielectric layer 3, the second work function adjustment structure 6, and the gate layer 7 formed in the subsequent process in the PMOS region 102, thereby adjusting the threshold voltage of the PMOS to reduce the threshold voltage. Since the diffusion ability of the metal elements in the second work function adjustment layer 62 is higher, a third diffusion barrier layer 63 and a second diffusion barrier layer 61 are formed on the upper and lower sides of the second work function adjustment layer 62, respectively. The second diffusion barrier layer 61 is used to reduce the diffusion speed of the metal elements in the second work function adjustment layer 62 into the high-K dielectric layer 3, prevent the metal elements from diffusing into the channel, avoid affecting the reliability of the device and avoid Coulomb scattering. The third diffusion barrier layer 63 is used to block the metal elements in the second work function adjustment layer 62 from diffusing into the gate layer 7 formed in the subsequent process, avoid affecting the gate layer 7 of the PMOS, and ensure the stability of the electrical performance of the PMOS.

[0072] In some embodiments, the material of the second diffusion barrier layer 61 may be the same as or different from the material of the third diffusion barrier layer 63. The second diffusion barrier layer 61 may be a single layer or a stacked structure of multiple layers with different materials. The third diffusion barrier layer 63 may be a single layer or a stacked structure of multiple layers with different materials. The thickness of the second diffusion barrier layer 61 may be the same as the thickness of the third diffusion barrier layer 63, or the thickness of the second diffusion barrier layer 61 may be less than the thickness of the third diffusion barrier layer 63. In other words, no matter how the materials of the second diffusion barrier layer 61 and the third diffusion barrier layer 63 are selected and how the thicknesses are determined, as long as the second diffusion barrier layer 61 can reduce the diffusion speed of the metal elements of the second work function adjustment layer 62 into the high-K dielectric layer 3, and the third diffusion barrier layer 63 can prevent the metal elements of the second work function adjustment layer 62 from diffusing into the gate layer 7 formed subsequently, no special limitation is made here.

[0073] A2: removing the mask layer 5 and the second work function adjustment structure 6 of the NMOS region 101 to expose the first work function adjustment structure 4 .

[0074] like Figure 7 As shown, the second work function adjustment structure 6 located in the NMOS region 101 can be removed by an etching process, and then the mask layer 5 located on the first work function adjustment structure 4 can be removed by an ashing process to expose the first work function adjustment structure 4. Figure 7Since the second work function adjustment structure 6 has three functional layers (the second diffusion barrier layer 61, the second work function adjustment layer 62 and the third diffusion barrier layer 63), and the first work function adjustment structure 4 has two functional layers (the first diffusion barrier layer 41 and the first work function adjustment layer 42), at this time, the stacked structure formed by the gate oxide layer 2, the high-K dielectric layer 3 and the second work function adjustment structure 6 located in the PMOS region 102 has a height in the vertical direction Y greater than the stacked structure formed by the gate oxide layer 2, the high-K dielectric layer 3 and the first work function adjustment structure 4 located in the NMOS region 101.

[0075] The vertical direction Y refers to the direction perpendicular to the semiconductor substrate 1 , which can also be understood as the stacking of the above-mentioned multiple functional layers in the vertical direction Y. For example, the first diffusion barrier layer 41 and the first work function adjustment layer 42 of the first work function adjustment structure 4 are stacked in sequence in the vertical direction Y.

[0076] S150 : forming a gate layer 7 and a first nitride layer 8 stacked in sequence on the first work function adjustment structure 4 of the NMOS region 101 and the second work function adjustment structure 6 of the PMOS region 102 .

[0077] like Figure 8 As shown, a gate layer 7 can be formed on the surface of the first work function adjustment structure 4 (specifically, the first diffusion barrier layer 41) in the NMOS region 101 by a deposition process. Since a gate layer 7 is also formed on the surface of the second work function adjustment structure 6 (specifically, the third diffusion barrier layer 63) in the PMOS region 102 in the same deposition process, the gate layer 7 serves as the gate of the NMOS and PMOS respectively.

[0078] In some embodiments, the material of the gate layer 7 may include at least one of titanium nitride, polysilicon and tungsten. It may be a single layer of the above material or a stacked layer formed by multiple materials. It can be selected according to the electrical performance requirements of the gate electrode and is not specifically limited here.

[0079] like Fig. 9 As shown, after the gate layer 7 is formed, a deposition process may be continued to form a first nitride layer 8 on the gate layer 7 of the NMOS region 101 and the PMOS region 102. The material of the first nitride layer 8 may include silicon nitride.

[0080] Since multiple oxygen vacancies are generated during the deposition process of the high-K dielectric layer 3, the oxygen vacancies generate a positive potential, which is beneficial to reducing the threshold voltage of the NMOS. Therefore, for the NMOS, these oxygen vacancies need to be retained. However, in the subsequent process, oxygen will be introduced, and the oxygen will oxidize the oxygen vacancies to reduce or disappear. The first nitride layer 8 is formed on the gate layer 7 of the NMOS region 101, which can block the entry of oxygen in the subsequent process, so that the oxygen vacancies can be retained, thereby reducing the threshold voltage of the NMOS and improving the electrical performance of the NMOS.

[0081] S160 : removing the first nitride layer 8 in the PMOS region 102 .

[0082] For PMOS, oxygen vacancies in the high-K dielectric layer 3 cannot reduce the threshold voltage of PMOS, and may also cause defect scattering. Therefore, in PMOS, oxygen vacancies are not expected. In the subsequent process, oxygen can be introduced to oxidize the oxygen vacancies to reduce or eliminate them. Therefore, the first nitride layer 8 needs to be removed from the PMOS region 102 so that the oxygen generated in the subsequent process can smoothly enter the high-K dielectric layer 3 to eliminate the oxygen vacancies and the defect scattering caused by the oxygen vacancies.

[0083] In addition, as in the above embodiment, since the height of the stacked structure in the PMOS region 102 in the vertical direction Y is greater than the height of the stacked structure in the NMOS region 101 in the vertical direction Y, before removing the first nitride layer 8 in the PMOS region 102, the height of the first nitride layer 8 in the PMOS region 102 is greater than the height of the first nitride layer 8 in the NMOS region 101, so the first nitride layer 8 in the PMOS region 102 can be removed by a chemical mechanical polishing process (CMP) to expose the gate layer 7. At this time, the height of the stacked structure (gate oxide layer 2, high-K dielectric layer 3, second work function adjustment structure 6 and gate layer 7) in the PMOS region 102 and the stacked structure (gate oxide layer 2, high-K dielectric layer 3, first work function adjustment structure 4, first nitride layer 8 and gate layer 7) in the NMOS region 101 can also be made the same, which is beneficial to patterning in subsequent processes.

[0084] Of course, in some embodiments, the first nitride layer 8 may also be removed by an etching process, and those skilled in the art may select the removal process according to actual conditions, and no special limitation is made here.

[0085] S170 : forming an oxide layer 9 on the first nitride layer 8 of the NMOS region 101 and the gate layer 7 of the PMOS region 102 .

[0086] like Fig.10As shown, an oxide layer 9 can be formed on the first nitride layer 8 of the NMOS region 101 and the gate layer 7 of the PMOS region by a deposition process. In the process of forming the oxide layer 9, oxygen is introduced. Since the first nitride layer 8 is provided in the NMOS region 101, oxygen can be prevented from entering the high-K dielectric layer 3, thereby retaining oxygen vacancies. Since the first nitride layer 8 is not provided in the PMOS region 102, in the process of forming the oxide layer 9, oxygen is introduced into the high-K dielectric layer 3 to oxidize and eliminate oxygen vacancies, reduce the threshold voltage of the PMOS, and reduce defect scattering.

[0087] In some embodiments, the material of the oxide layer 9 can be at least one of silicon oxide and silicon oxynitride.

[0088] S180: Patterning the gate oxide layer 2, high-K dielectric layer 3, first work function adjustment structure 4, gate layer 7, first nitride layer 8 and oxide layer 9 of the NMOS region 101 to form a first gate stack structure, and patterning the gate oxide layer 2, high-K dielectric layer 3, second work function adjustment structure 6, gate layer 7 and oxide layer 9 of the PMOS region 102 to form a second gate stack structure.

[0089] A mask layer (not shown) having a pattern may be disposed above the NMOS region 101 and the PMOS region 102, and the pattern of the mask layer may be transferred to the stacked structure on the NMOS region 101 and the PMOS region 102 by an etching process. Fig.11 As shown, after patterning, the first gate stack structure formed in the NMOS region 101 serves as the gate electrode of the NMOS, and the second gate stack structure formed in the PMOS region 102 serves as the gate electrode of the PMOS. The patterned gate electrodes are easier to connect to other conductive elements and are easier to package.

[0090] S190 : forming a second nitride layer 10 on the sidewalls of the first gate stack structure and the second gate stack structure.

[0091] like Fig.12 As shown, a second nitride layer 10 may be formed on the sidewalls of the first gate stack structure and the second gate stack structure by a deposition process to encapsulate them.

[0092] In some embodiments, the material of the second nitride layer 10 may include silicon nitride. The material of the second nitride layer 10 may be the same as that of the first nitride layer 8 , thereby avoiding the need to replace materials and saving costs.

[0093] In summary, in the disclosed embodiment, a first work function adjustment structure 4 is formed on the high-K dielectric layer 3 of the NMOS region 101, which can adjust the threshold voltage of the NMOS formed subsequently, and a first nitride layer 8 is formed on the gate layer 7 on the first work function adjustment structure 4 of the NMOS region 101, which can protect the oxygen vacancies provided by the high-K dielectric layer 3, so that the oxygen vacancies are retained, further reducing the threshold voltage of the NMOS, and improving the electrical performance of the NMOS. A second work function adjustment structure 6 is formed on the high-K dielectric layer 3 of the PMOS region 102, which can adjust the threshold voltage of the PMOS formed subsequently, and oxygen can be introduced in the process of forming the oxide layer 9 on the gate layer 7 of the PMOS, repairing the oxygen vacancies in the PMOS, thereby reducing the threshold voltage of the PMOS and reducing defect scattering, and improving the electrical performance of the PMOS.

[0094] The present disclosure also provides a semiconductor structure, which is prepared by the preparation method in any of the above embodiments. Fig.12 As shown, the semiconductor structure includes a semiconductor substrate 1, a first gate stack structure and a second gate stack structure.

[0095] The semiconductor substrate 1 includes an NMOS region 101 and a PMOS region 102, and both the NMOS region 101 and the PMOS region 102 are located in the active region. The first gate stack structure is located in the NMOS region 101, and the first gate stack structure includes a gate oxide layer 2, a high-K dielectric layer 3, a first work function adjustment structure 4, a gate layer 7, a first nitride layer 8, and an oxide layer 9 stacked in sequence on the semiconductor substrate 1. The second gate stack structure is located in the PMOS region 102, and the second gate stack structure includes a gate oxide layer 2, a high-K dielectric layer 3, a second work function adjustment structure 6, a gate layer 7, and an oxide layer 9 stacked in sequence on the semiconductor substrate 1. The sidewalls of the first gate stack structure and the second gate stack structure are respectively provided with a second nitride layer 10.

[0096] In some embodiments, the first work function adjustment structure 4 includes a first diffusion barrier layer 41 and a first work function adjustment layer 42 sequentially stacked on the high-K dielectric layer 3 of the NMOS region 101. The second work function adjustment structure 6 includes a second diffusion barrier layer 61, a second work function adjustment layer 62, and a third diffusion barrier layer 63 sequentially stacked on the high-K dielectric layer 3 of the PMOS region 102.

[0097] In the semiconductor structure of the embodiment of the present disclosure, the first gate stack structure of the NMOS region 101 has a first work function adjustment structure 4, which can adjust the threshold voltage of the NMOS, and the first nitride layer 8 can protect the oxygen vacancies provided by the high-K dielectric layer 3, so that the oxygen vacancies are retained, the threshold voltage of the NMOS is reduced, and the electrical performance of the NMOS is improved. The second gate stack structure of the PMOS region 102 has a second work function adjustment structure 6, which can adjust the threshold voltage of the PMOS, and the oxide layer 9 can introduce oxygen to repair the oxygen vacancies in the PMOS, thereby reducing the threshold voltage of the PMOS and reducing defect scattering, and improving the electrical performance of the PMOS.

[0098] In some embodiments, the first gate stack structure and the second gate stack structure have the same height in the vertical direction Y.

[0099] The first gate stack structure of the NMOS region 101 is different from the second gate stack structure of the PMOS region 102 in that the first gate stack structure includes a first work function adjustment structure 4 and a first nitride layer 8, and the second gate stack structure includes a second work function adjustment structure 6 but does not include the first nitride layer 8. The first work function adjustment structure 4 includes two layers, namely, a first diffusion barrier layer 41 and a first work function adjustment layer 42, and the second work function adjustment structure 6 includes three layers, namely, a second diffusion barrier layer 61, a second work function adjustment layer 62, and a third diffusion barrier layer 63. Since the second work function adjustment structure 6 includes three functional layers, and the first work function adjustment structure 4 includes two functional layers, forming three functional layers with the first nitride layer 8, the first gate stack structure and the second gate stack structure have the same number of functional layers stacked in the vertical direction Y, so that the heights of the two in the vertical direction Y can be the same, which is beneficial to patterning during the preparation process, and is beneficial to the implementation of other subsequent processes, thereby improving the electrical performance of the semiconductor structure.

[0100] In some embodiments, the first gate stack structure having the second nitride layer 10 on the sidewall is a gate electrode of an NMOS, and the second stack structure having the second nitride layer 10 on the sidewall is a gate electrode of a PMOS.

[0101] In summary, the semiconductor structure of the embodiment of the present disclosure can reduce the threshold voltage of NMOS and PMOS respectively, and improve the electrical performance of NMOS and PMOS.

[0102] It should be understood that the present disclosure does not limit its application to the detailed structure and arrangement of the components proposed in this specification. The present disclosure can have other embodiments and can be implemented and executed in a variety of ways. The aforementioned variations and modifications fall within the scope of the present disclosure. It should be understood that the present disclosure disclosed and defined in this specification extends to all alternative combinations of two or more individual features mentioned or evident in the text and / or the drawings. All these different combinations constitute multiple alternative aspects of the present disclosure. The embodiments described in this specification illustrate the best mode known for implementing the present disclosure and will enable those skilled in the art to adopt the present disclosure.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: Providing a semiconductor substrate, wherein the semiconductor substrate includes an NMOS region and a PMOS region; Forming a gate oxide layer and a high-K dielectric layer stacked in sequence on the NMOS region and the PMOS region; forming a first work function adjustment structure on the high-K dielectric layer in the NMOS region; forming a second work function adjustment structure on the high-K dielectric layer in the PMOS region; forming a gate layer and a first nitride layer stacked in sequence on the first work function adjustment structure of the NMOS region and the second work function adjustment structure of the PMOS region; removing the first nitride layer in the PMOS region; forming an oxide layer on the first nitride layer of the NMOS region and the gate layer of the PMOS region; Patterning the gate oxide layer, the high-K dielectric layer, the first work function adjustment structure, the gate layer, the first nitride layer and the oxide layer in the NMOS region to form a first gate stack structure, and patterning the gate oxide layer, the high-K dielectric layer, the second work function adjustment structure, the gate layer and the oxide layer in the PMOS region to form a second gate stack structure; A second nitride layer is formed on the sidewalls of the first gate stack structure and the sidewalls of the second gate stack structure.

2. The method according to claim 1, characterized in that Forming a first work function adjustment structure on the high-K dielectric layer in the NMOS region includes: forming a first work function adjustment layer on the high-K dielectric layer in the NMOS region; A first diffusion barrier layer is formed on the first work function adjusting layer.

3. The method according to claim 1 or 2, characterized in that: Forming a second work function adjustment structure on the high-K dielectric layer in the PMOS region includes: forming a second diffusion barrier layer on the high-K dielectric layer in the PMOS region; forming a second work function adjustment layer on the second diffusion barrier layer; A third diffusion barrier layer is formed on the second work function adjusting layer.

4. The method according to claim 3, characterized in that Before forming the second work function adjustment structure on the high-K dielectric layer in the PMOS region, the method further includes: While forming the first work function adjustment structure on the high-K dielectric layer in the NMOS region, the first work function adjustment structure is formed on the high-K dielectric layer in the PMOS region; forming a mask layer on the first work function adjustment structure in the NMOS region; The first work function adjustment structure located on the high-K dielectric layer in the PMOS region is removed.

5. The method according to claim 4, characterized in that After removing the first work function adjustment structure on the high-K dielectric layer in the PMOS region, the method further includes: forming the second work function adjustment structure on the mask layer in the NMOS region and on the high-K dielectric layer in the PMOS region; The mask layer and the second work function adjustment structure in the NMOS region are removed to expose the first work function adjustment structure.

6. The method according to claim 1, characterized in that The material of the gate oxide layer includes silicon oxide; The material of the high-K dielectric layer includes at least one of hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, zirconium oxide and strontium titanate.

7. The method according to claim 2, characterized in that The material of the first work function adjustment layer includes at least one of lanthanum oxide, yttrium oxide, germanium oxide, lutetium oxide and strontium oxide; The material of the first diffusion barrier layer includes at least one of titanium nitride and tantalum nitride.

8. The method according to claim 3, characterized in that The material of the second work function adjustment layer includes at least one of aluminum oxide, titanium oxide, hafnium oxide, zirconium oxide and magnesium oxide; The materials of the second diffusion barrier layer and the third diffusion barrier layer include at least one of titanium nitride and tantalum nitride, respectively.

9. A semiconductor structure, characterized in that: include: A semiconductor substrate, including an NMOS region and a PMOS region; A first gate stack structure, located in the NMOS region, the first gate stack structure comprising a gate oxide layer, a high-K dielectric layer, a first work function adjustment structure, a gate layer, a first nitride layer and an oxide layer stacked in sequence on the semiconductor substrate; A second gate stack structure, located in the PMOS region, the second gate stack structure comprising the gate oxide layer, the high-K dielectric layer, the second work function adjustment structure, the gate layer and the oxide layer stacked in sequence on the semiconductor substrate; The sidewalls of the first gate stack structure and the second gate stack structure are respectively provided with a second nitride layer.

10. The semiconductor structure according to claim 9, characterized in that: The first gate stack structure and the second gate stack structure have the same height in a vertical direction.

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