Self-aligned backside gate contacts for backside signal line integration

Abstract

A semiconductor array structure includes: a substrate; a semiconductor device includes a substrate, a plurality of field effect transistors (FETs) arranged in a row and located on the substrate, each FET including a first source-drain region, a second source-drain region, at least one channel coupling the source-drain regions, and a gate adjacent the at least one channel. A plurality of front side signal lines on a front side of the FETs; a plurality of backside power rails on a backside of the FETs; a plurality of backside signal conductors are on the backside. A front side signal connection extends from the front side signal conductor to the first source-drain region; a power connection extends from the backside power rail to the second source-drain region; and a backside gate contact connection extends from the backside signal conductor to the gate. The backside gate contact connections each have a bottom dimension greater than the gate length.

Description

Background Art

[0001] The present invention relates generally to the electrical, electronic and computer fields, and more particularly to signal lines in integrated circuits (ICs).

[0002] In integrated circuit technology, the power delivery network of a chip provides power and reference voltages to active devices; the power delivery network is separate from the signal network. Traditionally, both the power delivery and signal networks are manufactured on the front side of the wafer by back-end-of-line (BEOL) processing. Various proposals have been made to provide power distribution on the back side of a silicon wafer, potentially allowing, for example, direct power delivery, enhanced system performance, increased chip area utilization, and reduced BEOL complexity.

[0003] Until now, providing additional networks on the backside of a chip has been limited to power rather than signals. Summary of the invention

[0004] The principles of the present invention provide a technique for self-aligned backside gate contacts for backside signal line integration. In one aspect, an exemplary semiconductor structure includes: a backside power rail; a backside signal line; a frontside signal line; a first source-drain region; a second source-drain region; at least one channel, the at least one channel coupling the first source-drain region and the second source-drain region; a gate adjacent to the at least one channel; a frontside signal connection from the frontside signal line to the first source-drain region; a power connection from the backside power rail to the second source-drain region; and a backside gate contact from the gate to the backside signal line.

[0005] In another aspect, an exemplary semiconductor array structure includes: a substrate; a plurality of field effect transistors located on the substrate, each field effect transistor including a first source-drain region, a second source-drain region, at least one channel connecting the first source-drain region and the second source-drain region, and a gate having a gate length and adjacent to the at least one channel, the plurality of field effect transistors being arranged in a row; a plurality of front side signal lines on the front side of the plurality of field effect transistors; a plurality of back side power rails on the back side of the plurality of field effect transistors; and a plurality of back side signal conductors on the back side of the plurality of field effect transistors. A plurality of front side signal connections extend from the plurality of front side signal lines to the first source-drain region; a plurality of power connections extend from the back side power rail to the second source-drain region; and a plurality of back side gate contact connections extend from the back side signal conductors to the gate. The back side gate contact connections each have a bottom dimension greater than the gate length.

[0006] In another aspect, a hardware description language (HDL) design structure is encoded on a machine-readable data storage medium, and the HDL design structure includes elements that, when processed in a computer-aided design system, generate a machine-executable representation of a device / circuit. The HDL design structure includes a semiconductor structure or a semiconductor array structure as just described.

[0007] On the other hand, an exemplary method for forming a semiconductor structure includes: defining an n-type active region and a p-type active region in a nanosheet stack on a substrate, and forming a shallow trench isolation (STI) region between the active regions; forming a back gate contact via in the shallow trench isolation (STI) region in the space between the n-type active region and the p-type active region; forming a dummy gate and a gate spacer so that a bottom portion of the back gate contact via is filled with a dummy gate material of the dummy gate; removing the dummy gate and forming a replacement high-K metal gate so that the back gate contact via is filled with the high-K metal gate material of the high-K metal gate adjacent to the bottom of the gate to obtain a resulting structure; forming a back end of a line wiring on a front side of the resulting structure opposite to the substrate; and forming a back signal line connected to the high-K metal gate material in the back gate contact via.

[0008] In yet another aspect, another exemplary method of forming a semiconductor structure includes: defining an n-type active region and a p-type active region in a nanosheet stack on a substrate, and forming a shallow trench isolation (STI) region between the active regions; forming a back gate contact via in the shallow trench isolation (STI) region in a space between the n-type active region and the p-type active region; filling the back gate contact via with a sacrificial back gate contact material and recessing the sacrificial back gate contact material; forming a dummy gate and a gate spacer so that the back gate contact via The bottom portion of the back gate contact through-hole is filled with a sacrificial back gate contact material in contact with the dummy gate material of the dummy gate; removing the dummy gate and forming a replacement high-K metal gate so that the bottom portion of the back gate contact through-hole is filled with a sacrificial back gate contact material in contact with the high-K metal gate material of the high-K metal gate to obtain a resulting structure; forming a rear end of the line wiring on the front side of the resulting structure opposite to the substrate; removing the sacrificial back gate contact material to form a gap; and forming a back side signal line connected to the high-K metal gate material through the gap.

[0009] As used herein, "facilitating" an action includes performing the action, making the action easier, helping to perform the action, or causing the action to be performed. Thus, by way of example and not limitation, instructions executed on a processor may facilitate an action performed by semiconductor manufacturing equipment by sending appropriate data or commands to cause or assist the action to be performed. In the case where an actor facilitates an action by an action other than performing the action, the action is still performed by some entity or combination of entities.

[0010] The technology disclosed herein may provide substantially beneficial technical effects. Some embodiments may not have these potential advantages, and these potential advantages are not necessarily required for all embodiments. By way of example only and not limitation, one or more embodiments may provide one or more of the following:

[0011] ■ Enhanced system performance of integrated circuits

[0012] ■Increased chip area utilization of integrated circuits

[0013] Reduced BEOL complexity of integrated circuits

[0014] These and other features and advantages will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The following drawings are presented by way of example only and not limitation, wherein like reference numerals (when used) indicate corresponding elements throughout the several views, and wherein:

[0016] Figure 1 A high-level layout (top view) of an exemplary semiconductor structure according to an aspect of the present invention is shown.

[0017] Figure 2A A top view of an exemplary completed semiconductor structure according to one aspect of the present invention is shown.

[0018] Figure 2B is along Figure 2A A cross section of the starting wafer structure taken along the cutting line Y (along the gate) in FIG.

[0019] Figure 3 After the nanosheets are patterned, Figure 2A The section line Y in Figure 2B cross section of the structure.

[0020] Figure 4 After depositing the shallow trench isolation (STI) material and removing the hard mask, Figure 2A The section line Y (along the gate) in Figure 3 cross section of the structure.

[0021] Figure 5A is similar to Figure 2A with an attached cut plane line and with details of the through-holes.

[0022] Figure 5B According to one aspect of the present invention, Figure 5AThe cross-sectional view taken along the section line Y1 in FIG. 1 after backside gate contact patterning and appropriate etching (such as reactive ion etching (RIE)) Figure 4 cross section of the structure.

[0023] Figure 5C According to one aspect of the present invention, Figure 5A The cross-sectional view taken along the section line X2 in FIG. 1 after backside gate contact patterning and appropriate etching (such as reactive ion etching (RIE)) Figure 4 Cross-section of an exemplary structure.

[0024] Fig. 6A , Figure 6B , Figure 6C and Fig.6D According to one aspect of the present invention, Figure 5A The cross-sectional lines X1, X2, Y1 and Y2 in FIG. 1 are taken after forming the dummy gate and depositing the gate hard mask material. Figure 5B and Figure 5C Cross-section of an exemplary structure.

[0025] Fig. 7A , Figure 7B , Figure 7C and Fig.7D According to one aspect of the present invention, Figure 5A The cutting plane lines X1, X2, Y1 and Y2 in Fig. 6A , Figure 6B , Figure 6C and Fig.6D 2. A cross section of an exemplary structure of FIG. 1 after photolithographic patterning of a gate hard mask material followed by a suitable etch of the dummy gate material, such as reactive ion etching (RIE).

[0026] Fig. 8A , 8B 8C and 8D are respectively along Figure 5A The cross-sectional view taken along the lines X1, X2, Y1 and Y2 in FIG. 1 after forming gate spacers, recessing the nanosheets, forming internal spacers and epitaxially growing p-type source-drain regions and n-type source-drain regions. Fig. 7A , 7B , 7C and 7D are cross-sections of exemplary structures.

[0027] Fig.9A , Fig. 9B , Fig. 9C and Fig.9D According to one aspect of the present invention, Figure 5A The cutting plane lines X1, X2, Y1 and Y2 in Fig. 8A , Figure 8B , Figure 8C and Fig.8D A cross section of an exemplary structure after interlayer dielectric (ILD) fill, chemical mechanical polishing (CMP), gate cutting, dummy gate and SiGe removal, and replacement high-K metal gate (HKMG) formation.

[0028] Fig. 10A , 10B , 10C and 10D are respectively along Figure 5A The cross-sectional view taken along the lines X1, X2, Y1 and Y2 in FIG. 1 shows a cross-sectional view of a wafer after forming middle-of-line (MOL) contacts, back-end-of-line (BEOL) interconnects and carrier wafer bonding. Fig.9A , 9B , 9C and 9D are cross-sections of exemplary structures.

[0029] Fig.11A , Fig. 11B , Fig. 11C and Fig.11D According to one aspect of the present invention, Figure 5A The section lines X1, X2, Y1 and Y2 in Fig. 10A , Fig. 10B , Fig. 10C and Fig. 10D Cross-section of an exemplary structure.

[0030] Fig. 12A , Fig. 12B , Fig. 12C and Fig.12D According to one aspect of the present invention, Figure 5A The cutting plane lines X1, X2, Y1 and Y2 in Fig.11A , Fig. 11B , Fig. 11C and Fig.11D Cross-section of an exemplary structure after removing the substrate and stopping on the etch stop layer.

[0031] Fig.13A , 13B 13C and 13D are respectively along Figure 5A The cross-sectional lines X1, X2, Y1 and Y2 in FIG. 1 are taken after removing the etching stop layer. Fig. 12A , 12B , 12C and 12D are cross-sections of exemplary structures.

[0032] Fig.14A , Fig. 14B , Fig. 14C and Fig.14D According to one aspect of the present invention, Figure 5A The cross-sectional lines X1, X2, Y1 and Y2 in FIG. 1 are taken after the silicon substrate is recessed. Fig.13A, Fig. 13B , Fig. 13C and Fig.13D Cross-section of an exemplary structure.

[0033] Fig.15A , Fig. 15B , Fig. 15C and Fig.15D According to one aspect of the present invention, Figure 5A The cross-sectional lines X1, X2, Y1 and Y2 in FIG. 1 are taken after deposition of the backside interlayer dielectric (ILD). Fig.14A , Fig. 14B , Fig. 14C and Fig.14D Cross-section of an exemplary structure.

[0034] Fig.16A , 16B 16C and 16D are respectively formed along the back side power rail and signal line after forming the back side power rail and signal line according to one aspect of the present invention. Figure 5A The cutting plane lines X1, X2, Y1 and Y2 in Fig.15A , 15B , 15C and 15D are cross-sections of exemplary structures.

[0035] Fig.17A , Fig. 17B , Fig. 17C and Fig.17D According to one aspect of the present invention, after forming the backside interconnection, Figure 5A The cutting plane lines X1, X2, Y1 and Y2 in Fig.16A , Fig. 16B , Fig. 16C and Fig.16D Cross-section of an exemplary structure.

[0036] Fig.18A and Fig.18B According to another aspect of the present invention, Figure 5A The cross-sectional view taken along the section lines Y1 and X2 in FIG. 1 after the trench is filled with sacrificial backside gate contact material and recessed. Figure 5B and Figure 5C Cross-section of an exemplary structure.

[0037] Fig.19A , 19B , 19C and 19D are respectively along Figure 5A The cross-sectional lines X1, X2, Y1 and Y2 in FIG. 1 are taken after forming a dummy gate, depositing a gate hard mask material, reactive ion etching (RIE) a dummy gate material, depositing a gate spacer, recessing a nanosheet, forming an inner spacer, and epitaxially growing a p-type source-drain region and an n-type source-drain region. Fig.18A and 18BA cross section of an exemplary inventive structure.

[0038] Fig. 20A , 20B , 20C and 20D are respectively along Figure 5A The section lines X1, X2, Y1 and Y2 in 9A to 15D The process shown in FIG. 1 (including the deposition of the backside ILD) is followed by the process Fig.19A , Fig.19B , Fig.19C and Fig.19D A cross section of an exemplary inventive structure.

[0039] Fig.21A , Fig.21B , Fig. 21C and Fig.21D are respectively along Figure 5A The cutting plane lines X1, X2, Y1 and Y2 in Fig. 20A , Fig. 20B , Fig. 20C and Fig.20D A cross section of an exemplary inventive structure after patterning and etching the backside ILD.

[0040] Fig.22A , Fig. 22B , Fig. 22C and Fig.22D are respectively along Figure 5A The cross-sectional lines X1, X2, Y1 and Y2 in FIG. 1 are taken after selectively removing the sacrificial backside gate contact material and removing the exposed HfO2 Fig.21A , Fig.21B , Fig. 21C and Fig.21D A cross section of an exemplary inventive structure.

[0041] Fig.23A , 23B , 23C and 23D are respectively along Figure 5A The cutting plane lines X1, X2, Y1 and Y2 in Fig.22A , 22B , 22C and 22D after forming the backside power rails and signal lines.

[0042] Fig.24 Exemplary signal and power connections according to aspects of the present invention are shown.

[0043] Fig.25 A schematic diagram of a backside interconnect according to aspects of the present invention is shown.

[0044] Fig.26 It shows that it is possible to implement Fig. 27 Computer system for the design process shown.

[0045] Fig. 27 A flow chart of a design process used in semiconductor design, manufacturing, and / or testing.

[0046] It should be appreciated that elements in the figures are illustrated for simplicity and clarity. Common but well-understood elements that may be useful or necessary in a commercially feasible embodiment may not be depicted in order to facilitate a less obstructed view of the illustrated embodiments. DETAILED DESCRIPTION

[0047] The principles of the invention described herein will be described in the context of illustrative embodiments. In addition, in view of the teachings herein, it will become apparent to those skilled in the art that many modifications may be made to the illustrated embodiments, which modifications are within the scope of the claims. That is, no limitation with respect to the embodiments shown and described herein is intended or should be inferred.

[0048] As noted, various proposals have been made to provide power distribution on the back side of a silicon wafer, potentially allowing, for example, direct power delivery, enhanced system performance, increased chip area utilization, and reduced BEOL complexity. Currently proposed techniques deliver power to the source / drain (S / D) region of a field effect transistor (FET), but do not provide any connection to the gate of the FET. Advantageously, one or more embodiments add a backside gate connection; for example, to provide a clock signal track. To date, power vias have been provided to connect the S / D epi to a backside power distribution network (BSPDN). One or more embodiments provide power via-to-power connections for the S / D epi and gate-to-backside signal line connections.

[0049] For example, in one or more embodiments, the semiconductor device includes at least a power via contact that connects the S / D epitaxy to the backside power rail, and a signal line contact via that connects the FET gate to the backside clock signal. In some cases, the signal line contact has a bottom dimension larger than the gate and is covered with a gate spacer. In some cases, the signal contact is a T-shaped structure at the bottom of the gate. In some cases, the power via contact and the backside power rail are located in the N2N and P2P spaces. In some cases, the signal line contact and the backside clock signal are located in the N2P space. Note that "N2N" refers to the space between adjacent n-type FETs (NFETs); "P2P" refers to the space between adjacent p-type FETs (PFETs); and "N2P" refers to the space between adjacent NFETs and PFETs. In one or more embodiments, the signal line contact is filled with a high-K metal gate (HKMG).

[0050] In one or more exemplary embodiments, an exemplary process flow includes defining an active area and forming a shallow trench isolation (STI); forming a backside gate contact via in the STI region between the N2P spaces; and forming a dummy gate and a gate spacer so that the bottom of the backside gate contact via is filled with a dummy gate material. In the end structure, the bottom of the backside gate contact via filled with the dummy gate material will eventually be filled with HKMG material, as described below, and the resulting area will be isolated from the FEOL structure by the gate spacer. In one or more exemplary embodiments, the exemplary process flow also includes: removing the dummy gate and forming a replacement high-k metal gate (HKMG) so that the backside gate contact via is also filled with HKMG attached to the bottom of the gate; flipping the wafer; and forming a backside signal line connected to the backside gate contact via.

[0051] Figure 1 A high-level layout (top view) of an exemplary semiconductor structure 101 according to one aspect of the present invention is shown. Note the backside power rails (e.g., VSS (e.g., ground voltage) 269, VDD (e.g., positive supply voltage) 271) and signal lines (e.g., clock signal 273). Also note the schematically depicted NFET region 109 and PFET region 111. As described above, the space between the NFETs 109 is referred to as the N2N space; the space between the PFETs 111 is referred to as the P2P space; and the space between the NFETs 109 and the PFETs 111 is referred to as the N2P space. Under the N2N and P2P spaces, note the respective backside power rails (VSS 269, VDD 271) connected to the S / D epi, while under the N2P space, note the backside clock signal 273 connected to the gate 201 (see discussion below). Figure 2A ).

[0052] Consider now a first exemplary process flow according to one aspect of the present invention, and now refer to Figure 2A and 2B . Figure 2B is along Figure 2A A cross section of the starting wafer structure taken along the cutting line Y (along the gate) in FIG. Figure 2A Zhongyu Figure 1 Similar elements in the drawings have the same reference numerals. Figure 2A and 5A(discussed below) is a top view of the completed structure, with the section line for reference. Note the gate 201. The starting wafer structure includes a lower silicon portion 203, an intermediate etch stop portion 205 of (e.g.) a buried oxide (BOX) or silicon germanium (SiGe), and an upper silicon portion 207. Outside the upper silicon portion is a nanosheet structure that includes alternating layers of SiGe 209, 211, 213, 215 and silicon nanosheets 217, 219, 221, 223. The SiGe regions 209, 211, 213, 215 (and 205, if made of SiGe) can include, for example, SiGe with a Ge% in the range of 15-75%. Those skilled in the art are generally familiar with the formation of nanosheet transistors.

[0053] Figure 3 After the nanosheets are patterned, Figure 2A The section line Y in Figure 2B 225 (e.g., a layer or layers of dielectric), photolithography is employed to create gaps in the hard mask, and etching is performed to create trenches 227 corresponding to the gaps in the hard mask (the area under the remaining hard mask 225 is not etched). The skilled person will generally be familiar with patterning hard masks and etching nanosheet structures via photolithography techniques.

[0054] Figure 4 After depositing shallow trench isolation (STI) material 229 (e.g., SiO or other suitable oxide, if necessary, a suitable liner can be first deposited using known techniques and materials) and removing hard mask 225 (the hard mask can be stripped using known techniques and materials), along Figure 2A The section line Y (along the gate) in Figure 3 The STI may be deposited, for example, via furnace chemical vapor deposition (FCVD) or other suitable techniques.

[0055] Reference now Figure 5A , 5B and 5C. Figure 5B It is along Figure 5A The cross section of the structure is taken along the cutting plane line Y1. The alternating layers of SiGe 209, 211, 213, 215 and silicon nanosheets 217, 219, 221, 223 are Figure 5B-17B They are not numbered to avoid confusion. Figure 5A Zhongyu Figure 1 and Figure 2A Similar elements in the drawings have the same reference numerals. Figure 5C It is along Figure 5A The cross section of the structure is taken by the cutting line X2. Figure 5B and Figure 5CDepicted is a backside gate contact after patterning and a suitable etch, such as reactive ion etching (RIE). Figure 4 structure. Note that an organic planarization layer (OPL) 231 and vias 233 are formed in the STI 229 below corresponding openings in the OPL 231. Any suitable type of OPL may be employed. Those skilled in the art will be familiar with the deposition and stripping of the OPL, patterning it using photolithography techniques, and forming corresponding vias in the STI material. Note generally that the section lines X1 and X2 intersect the gates, while the section line Y1 is along the gates, and the section line Y2 is parallel to the gate between two adjacent gates.

[0056] Reference now Fig. 6A , 6B , 6C and 6D. Fig. 6A It is along Figure 5A The cross section of the structure is taken by the cutting line X1. Figure 6B It is along Figure 5A The cross section of the structure is taken by the cutting line X2. Figure 6C It is along Figure 5A A cross section of the structure taken along the cutting line Y1. Fig.6D It is along Figure 5A The cross section of the structure taken by the cutting line Y2. Figures 6A-6D Depicted is the process after forming the dummy gate 235 and depositing the gate hard mask material 237. Figure 5B and 5C . Note that the dummy gate is shown as an integral structure to avoid confusion, but may include, for example, a thin SiO2 liner plus amorphous silicon (a-Si) in a known manner. For example, after the thin liner is deposited, an amorphous Si material is deposited and planarized; and a gate hard mask material 237 (which may be, for example, a multilayer dielectric) is deposited. Those skilled in the art are generally familiar with dummy gate processes.

[0057] Reference now Fig. 7A , 7B , 7C and 7D. Fig. 7A It is along Figure 5A The cross section of the structure is taken by the cutting line X1. Figure 7B It is along Figure 5A The cross section of the structure is taken by the cutting line X2. Figure 7C It is along Figure 5A A cross section of the structure taken along the cutting line Y1. Fig.7D It is along Figure 5A A cross section of the structure with the cutting line Y2. Figures 7A-7D The process of photolithographically patterning the gate hard mask material 237 followed by a suitable etch (such as reactive ion etching (RIE)) of the dummy gate material is depicted. Figures 6A-6DThis forms various gaps (not individually numbered) which will later include interlayer dielectrics (ILDs), epitaxially grown source-drain regions, and contacts, as will be apparent from the following description. For example, a hard mask is patterned and a-Si is etched to form a dummy gate 235. The skilled person is familiar with techniques for photolithographic patterning and etching.

[0058] Reference now Fig. 8A , 8B , 8C and 8D. Fig. 8A It is along Figure 5A The cross section of the structure is taken by the cutting line X1. Figure 8B It is along Figure 5A The cross section of the structure is taken by the cutting line X2. Figure 8C It is along Figure 5A A cross section of the structure taken along the cutting line Y1. Fig.8D It is along Figure 5A The cross section of the structure taken by the cutting line Y2. Figure 8A-8D Depicts the formation of gate spacers 241, recessing of nanosheets, formation of inner spacers 239, and epitaxial growth of p-type source-drain regions 243 and n-type source-drain regions 245. Figure 7A-7D structure. SiGe 209, 211, 213, 215 are laterally etched back (e.g., using a vapor phase HCl process for this aspect), and an inner spacer 239 is filled into the resulting region. Those skilled in the art are familiar with the techniques for the subsequent epitaxial growth of p-type and n-type source / drain regions and the deposition of gate spacers 241. Suitable materials for gate spacers 241 include dielectric materials such as silicon oxide, silicon nitride, or silicon oxynitride, which can be deposited in a known manner. A non-limiting example of a material for the inner spacer 239 is SiN, and the spacer 239 can be formed in a known manner.

[0059] Reference now Fig.9A , 9B , 9C and 9D. Fig.9A It is along Figure 5A The cross section of the structure is taken by the cutting line X1. Fig. 9B It is along Figure 5A The cross section of the structure is taken by the cutting line X2. Fig. 9C It is along Figure 5A The cross section of the structure is taken by the cutting line Y1. Fig.9D It is along Figure 5A The cross section of the structure taken by the cutting line Y2. Figures 9A-9D Depicts the interlayer dielectric (ILD) fill, chemical mechanical polishing (CMP), gate cutting, dummy gate and SiGe removal, and replacement HKMG formation after Figures 8A-8DNote the ILD 247 (e.g., FCVD SiO2; typically, exemplary materials for the ILD layer include SiOx, low-k oxides (dielectric constant <3.9), SiN, or combinations of these materials (e.g., SiN and SiO2)); HKMG material 249; and gate cutout 251. As seen at 253, the backside gate contact (part of material 249) is self-aligned to the middle gate (refer to Figures 7A-7D The dummy gate RIE shown in , the backside gate contact is connected to the bottom of the gate even if the gate is not aligned to the left or right). Figures 8A-8D The structure moves to Figures 9A-9D structure, selectively removing the sacrificial a-Si portion of the dummy gate 235 and the sacrificial nanosheets 209, 211, 213, 215; forming a conformal high-K metal gate stack; patterning and etching a cavity for the gate cut 251; and filling the cavity with a dielectric material (e.g., similar to other suitable dielectric materials discussed herein) to form the gate cut 251. In one or more embodiments, the gate stack is a high-k metal gate (HKMG) stack. HKMG includes a high-k dielectric layer combined with a metal gate feature. As just a few non-limiting examples, the high-k dielectric layer may include hafnium silicon oxide, zirconium silicon oxide, hafnium oxide, or zirconium oxide. Again, as just a few non-limiting examples, the metal gate feature may include a work function tunable material such as titanium nitride, titanium aluminum nitride, titanium silicon nitride, tantalum nitride, tantalum aluminum nitride, or tantalum silicon nitride. In one or more embodiments, the components of HKMG may be deposited by atomic layer deposition (ALD), chemical vapor deposition (CVD), or some combination of these two processes. In the context of a high-K metal gate (HKMG) stack, the term “high-K” has a well-defined meaning to those skilled in the art and is not merely a relative term.

[0060] Reference now Fig. 10A , 10B , 10C and 10D. Fig. 10A It is along Figure 5A The cross section of the structure is taken by the cutting line X1. Fig. 10B It is along Figure 5A The cross section of the structure is taken by the cutting line X2. Fig. 10C It is along Figure 5A The cross section of the structure is taken by the cutting line Y1. Fig. 10D It is along Figure 5A The cross section of the structure taken by the cutting line Y2. Figures 10A-10D Depicts the process after forming the middle of line (MOL) contacts, back end of line (BEOL) interconnects, and carrier wafer bonding. Figures 9A-9Dstructure. Note the VBPR (via for connecting to the backside power rail) 255, source / drain contacts (CA) 257, VA (via connecting the source-drain contacts to the BEOL wiring) 259, VB (via connecting the gate to the BEOL wiring) 261, BEOL wiring 263, and carrier wafer 265. Those skilled in the art will be familiar with conventional MOL and BEOL processing and wafer bonding techniques. Traditionally, BEOL refers to the interconnects, contacts, vias, and dielectric layers that wire the active devices into a specific circuit configuration. The recently introduced middle-of-line (MOL) interconnect helps reduce congestion in local wiring. The MOL is typically located below the first metal layer. In Figures 10A-10D , components 255, 257 may be considered as MOL, while components 259, 261, 263 may be considered as BEOL.

[0061] Reference now Fig.11A , Fig. 11B , Fig. 11C and Fig.11D . Fig.11A It is the reversed direction. Figure 5A The cross section of the structure is taken by the cutting line X1. Fig. 11B It is the reversed direction. Figure 5A The cross section of the structure is taken by the cutting line X2. Fig. 11C It is the reversed direction. Figure 5A The cross section of the structure is taken by the cutting line Y1. Fig.11D It is the reversed direction. Figure 5A A cross section of the structure with the cutting line Y2. Figures 11A-11D Depicts the reversal or "flip" Figures 10A-10D Those skilled in the art are familiar with fixtures and techniques for flipping semiconductor wafers during manufacturing.

[0062] Reference now Fig. 12A , Fig. 12B , Fig. 12C and Fig.12D . Fig. 12A It is the reversed direction. Figure 5A The cross section of the structure is taken by the cutting line X1. Fig. 12B It is the reversed direction. Figure 5A A cross section of the structure taken along the cutting line X2. Fig. 12C It is the reversed direction. Figure 5A The cross section of the structure is taken by the cutting line Y1. Fig.12D It is the reversed direction. Figure 5A The cross section of the structure is taken by the cutting line Y2. Figures 12A-12D Depicts the process after removing the substrate 203, stopping on the etch stop layer 205. Figures 11A-11DThose skilled in the art are familiar with suitable etchants that can etch silicon and stop on oxide or SiGe.

[0063] Reference now Fig.13A , 13B , 13C and 13D. Fig.13A It is the reversed direction. Figure 5A The cross section of the structure is taken by the cutting line X1. Fig. 13B It is the reversed direction. Figure 5A The cross section of the structure is taken by the cutting line X2. Fig. 13C It is the reversed direction. Figure 5A The cross section of the structure is taken along the cutting line Y1 shown. Fig.13D It is the reversed direction. Figure 5A The cross section of the structure is taken by the cutting line Y2. Figures 13A-13D Depicted is the etching stop layer 205 after removal (eg, using a conventional wet etching process). Figures 12A-12D structure.

[0064] Reference now Fig.14A , 14B , 14C and 14D. Fig.14A It is the reversed direction. Figure 5A The cross section of the structure is taken by the cutting line X1. Fig. 14B It is the reversed direction. Figure 5A The cross section of the structure is taken by the cutting line X2. Fig. 14C It is the reversed direction. Figure 5A The cross section of the structure is taken by the cutting line Y1. Fig.14D It is the reversed direction. Figure 5A The cross section of the structure is taken by the cutting line Y2. FIG. 14A to FIG. 14D Depicted is a diagram of a silicon substrate 207 after recessing (eg, using a conventional dry etching process). FIG. 13A to FIG. 13D structure.

[0065] Reference now Fig.15A , 15B , 15C and 15D. Fig.15A It is the reversed direction. Figure 5A The cross section of the structure is taken by the cutting line X1. Fig. 15B It is the reversed direction. Figure 5A The cross section of the structure is taken by the cutting line X2. Fig. 15C It is the reversed direction. Figure 5A The cross section of the structure is taken by the cutting line Y1. Fig.15D It is the reversed direction. Figure 5A The cross section of the structure is taken by the cutting line Y2. Figures 15A-15D Depicted is the backside ILD 267 after deposition. Figures 14A-14Dstructure (the materials and techniques applicable to ILD 247 can also be used for ILD 267).

[0066] Reference now Fig.16A , 16B , 16C and 16D. Fig.16A It is the reversed direction. Figure 5A The cross section of the structure is taken by the cutting line X1. Fig. 16B It is the reversed direction. Figure 5A The cross section of the structure is taken by the cutting line X2. Fig. 16C It is the reversed direction. Figure 5A The cross section of the structure is taken by the cutting line Y1. Fig.16D It is the reversed direction. Figure 5A The cross section of the structure is taken by the cutting line Y2. FIG. 16A to FIG. 16D Depicted after forming the backside power rails (eg, VSS 269, VDD 271) and signal lines (eg, clock signal 273) FIG. 15A to FIG. 15D The metallization process for various metal lines and vias can be completed using conventional single damascene processes. Suitable materials include copper and other conductive metals. As discussed elsewhere herein, in one or more embodiments, the backside gate contact is self-aligned with the middle gate and is connected to the bottom of the gate even if the gate is misaligned to the left or right.

[0067] Reference now Fig.17A , 17B , 17C and 17D. Fig.17A It is the reversed direction. Figure 5A The cross section of the structure is taken by the cutting line X1. Fig. 17B It is the reversed direction. Figure 5A The cross section of the structure is taken by the cutting line X2. Fig. 17C It is the reversed direction. Figure 5A The cross section of the structure is taken by the cutting line Y1. Fig.17D It is the reversed direction. Figure 5A The cross section of the structure is taken by the cutting line Y2. Figures 17A-17D Depicted is a diagram of a backside interconnect 275 after it has been formed (typically, the backside interconnect may include a power distribution network and may also include wiring for signal routing). Figures 16A-16D In view of the teachings herein, one skilled in the art will be able to adapt conventional techniques to form backside interconnects.

[0068] Now consider a second exemplary process flow according to one aspect of the present invention. Figure 2A-5C The steps discussed are the same. Now refer to Fig.18A and 18B . Fig.18A It is along Figure 5A The cross section of the structure is taken by the cutting line Y1. Fig.18B It is along Figure 5A The cross section of the structure is taken by the cutting line X2. Fig.18A and Fig.18B Depicted is the trench 233 after it has been filled and recessed with a sacrificial backside gate contact such as silicon nitride (SiN) 501. Figure 5B and Figure 5C In view of the teachings of this article, those skilled in the art can use known techniques to fill SiN or similar materials and make them recessed. In the second exemplary process flow, Figures 18A-19D Before the reversal, Figures 20A-23D After the reversal.

[0069] Reference now Fig.19A , 19B , 19C and 19D. Fig.19A It is along Figure 5A The cross section of the structure is taken by the cutting line X1. Fig.19B It is along Figure 5A The cross section of the structure is taken by the cutting line X2. Fig.19C It is along Figure 5A The cross section of the structure is taken by the cutting line Y1. Fig.19D It is along Figure 5A The cross section of the structure is taken by the cutting line Y2. Figures 19A-19D Depicted in a similar Figures 6A-8D After forming a dummy gate 235, depositing a gate hard mask material 237, reactively ion etching (RIE) a dummy gate material, a spacer 241, a recessed nanosheet, forming an inner spacer 239, and epitaxially growing a p-type source-drain region 243 and an n-type source-drain region 245, Fig.18A and Fig.18B structure. Note that the dummy gate is shown as an integral structure to avoid confusion, but may include, for example, a thin SiO2 liner plus amorphous silicon (a-Si) in a known manner. For example, a thin liner is deposited, followed by deposition of amorphous Si material and planarization; a gate hard mask material 237 (which may be, for example, a multilayer dielectric) is deposited. Those skilled in the art are generally familiar with dummy gate processes. After photolithographic patterning of the gate hard mask material 237, appropriate etching of the dummy gate material (such as reactive ion etching (RIE)) forms various gaps (not individually numbered) that will later include interlayer dielectrics (ILDs), epitaxially grown source-drain regions, and contacts, as will be apparent from the description below. For example, the hard mask is patterned and the a-Si is etched to form a dummy gate 235. Technicians are familiar with techniques for photolithographic patterning and etching. Those skilled in the art are familiar with techniques for subsequent epitaxial growth of p-type and n-type source / drain regions and deposition of the liner 241.

[0070] FIG. 19A to FIG. 19D The structure depicted in the figure can be subjected to 9A to 15D A similar process as shown in FIG. 1 is performed, including the deposition of backside ILD 267, to obtain FIG. 20A to FIG. 20D The structure shown in . Fig. 20A It is along Figure 5A A cross section of the structure taken by the cutting plane line X1; Fig. 20B It is along Figure 5A A cross section of the structure taken by the cutting plane line X2; Fig. 20C It is along Figure 5A A cross section of the structure taken along the cutting plane line Y1 in FIG. Fig.20D is along Figure 5A The cross section of the structure is taken by the cutting line Y2.

[0071] Conventional lithography and etching may be performed for the backside BPR and signal lines as part of the formation of the backside power rails and signal lines. Note cavity 511 for forming the clock signal line; cavity 513 for forming the VSS power rail, and cavity 515 for forming the VDD power rail. Fig.21A It is along Figure 5A A cross section of the structure taken by the cutting plane line X1; Fig.21B It is along Figure 5A A cross section of the structure taken by the cutting plane line X2; Fig. 21C It is along Figure 5A A cross section of the structure taken along the cutting plane line Y1 in FIG. Fig.21D is along Figure 5A Known photolithography and etching techniques can be used to make appropriate cavities in the backside ILD 267.

[0072] Fig.22A It is along Figure 5A A cross section of the structure taken by the cutting plane line X1; Fig. 22B It is along Figure 5A A cross section of the structure taken by the cutting plane line X2; Fig. 22C It is along Figure 5A A cross section of the structure taken along the cutting plane line Y1 in FIG. Fig.22D is along Figure 5A The cross section of the structure taken by the cutting line Y2. Figure 22A-22D 2 shows the structure after selectively removing the sacrificial backside gate contact (eg, SiN) 501 and removing the exposed HfO2 from the HKMG 249 adjacent to the SiN 501 (using, for example, a conventional dry or wet etching process). Figure 21A-Figure 21D structure.

[0073] Fig.23A It is along Figure 5A A cross section of the structure taken by the cutting plane line X1; Fig. 23B It is along Figure 5A A cross section of the structure taken by the cutting plane line X2; Fig.23C It is along Figure 5A A cross section of the structure of the cutting plane line Y1; Fig.23D It is along Figure 5A The cross section of the structure taken by the cutting line Y2. FIG. 23A to FIG. 23D Depicted after forming the backside power rails (eg, VSS 269, VDD 271) and signal lines (eg, clock signal 273A) FIG. 22A to FIG. 22D structure. Clock signal line 273A is similar to clock signal line 273, but extends downward into the area where SiN 501 and exposed HfO2 are removed. The metallization process for various metal lines and vias can be completed using conventional single damascene processes. Suitable materials include copper and other conductive metals. As discussed elsewhere herein, in one or more embodiments, the back gate contact is self-aligned with the middle gate and is connected to the bottom of the gate even if the gate is misaligned to the left or right.

[0074] Notice, Figures 20A-23D shows that it can be similarly performed to Figures 15A-15D The structure moves to Figures 16A-16D steps of the structure.

[0075] It is noteworthy that the various features generally have larger diameters towards the sides of the structure in which they are formed, e.g. Figure 5B and 5C shown.

[0076] Semiconductor device manufacturing includes various steps of device patterning process. For example, the manufacture of semiconductor chips can start from device patterns generated by, for example, multiple CAD (computer-aided design), and then strive to replicate these device patterns in the substrate. The replication process can involve the use of various exposure techniques and various subtractive (etching) and / or additive (deposition) material processing procedures. For example, in a photolithography process, a photoresist material layer can be first applied on the top of the substrate and then selectively exposed according to a predetermined one or more device patterns. The portion of the photoresist exposed to light or other ionizing radiation (e.g., ultraviolet rays, electron beams, X-rays, etc.) may experience some changes in its solubility to certain solutions. The photoresist can then be developed in a developer solution to remove the un-irradiated (in a negative resist) or irradiated (in a positive resist) portion of the resist layer to produce a photoresist pattern or photomask. The photoresist pattern or photomask can then be copied or transferred to the substrate below the photoresist pattern.

[0077] There are many techniques used by those skilled in the art to remove material at various stages of creating a semiconductor structure. As used herein, these processes are generally referred to as "etching." For example, etching includes techniques of wet etching, dry etching, chemical oxide removal (COR) etching, and reactive ion etching (RIE), which are all known techniques for removing selective materials when forming a semiconductor structure. Standard Clean 1 (SC1) contains a strong base (usually ammonium hydroxide) and hydrogen peroxide. SC2 includes a strong acid, such as hydrochloric acid and hydrogen peroxide. The techniques and applications of etching are well understood by those skilled in the art, and therefore, a more detailed description of these processes is not given herein.

[0078] Although the entire manufacturing method and the structure formed thereby are novel, certain individual processing steps required to implement the method can utilize conventional semiconductor manufacturing techniques and conventional semiconductor manufacturing tools. In view of the teachings herein, these techniques and tools will be familiar to those of ordinary skill in the relevant art. For example, those skilled in the art will be familiar with epitaxial growth, self-aligned contact formation, formation of high-K metal gates, etc. As noted, the term "high-K" has a clear meaning to those skilled in the art in the context of a high-K metal gate (HKMG) stack, and is not merely a relative term. In addition, one or more processing steps and tooling for manufacturing semiconductor devices are also described in many readily available publications, including, for example, James D. Plummer et al., Silicon VLSI Technology: Fundamentals, Practice, and Modeling 1st Edition, Prentice Hall, 2001; and P. Plummer et al., Silicon VLSI Technology: Fundamentals, Practice, and Modeling 1st Edition, Prentice Hall, 2001; Holloway et al., Handbook of Compound Semiconductors: Growth, Processing, Characterization, and Devices, Cambridge University Press, 2008, all of which are incorporated herein by reference. It is emphasized that although some individual processing steps are set forth herein, those steps are merely illustrative, and those skilled in the art may be familiar with several equally suitable alternatives that will apply.

[0079] It should be understood that the various layers and / or regions shown in the drawings may not be drawn to scale. In addition, for ease of explanation, one or more semiconductor layers of a type commonly used in such integrated circuit devices may not be explicitly shown in a given figure. This does not mean that the semiconductor layers not explicitly shown are omitted in the actual integrated circuit device.

[0080] Fig.25 A schematic diagram of a backside interconnect 275 according to aspects of the present invention is shown. The interconnect may include a Fig.24 The voltage supply rail VDD 2404 of the power supply 2402 and VDD 271 (at "A"); the ground rail VSS2404, which is connected to Fig.24 Ground terminal 2404 and VSS269 (at "B"); and clock signal line 2406, which is connected to Fig.24 Clock signal 2406 and clock signals 273, 273A (at "C"). Fig.25 is a schematic diagram, and components 2402, 2404, and 2406 may be in different wiring layers.

[0081] Given the discussion thus far, it should be appreciated that, in general, the exemplary semiconductor structure includes a backside power rail (e.g., power supply portion 2402 having backside interconnect 275 connected as discussed); a backside signal line (e.g., signal portion 2406 having backside interconnect 275 connected as discussed); a first source-drain region (e.g., Fig.17A or 23A, the left-hand p-epi 243 or the corresponding n-epi in the case of an NFET); and a second source-drain region (e.g., in Fig.17A or 23A, right-hand p-epi 243 or corresponding n-epi in the case of an NFET). Also included is at least one channel (e.g., at Fig.17A or 23A, a nanosheet between the first and second S / D regions); and a gate adjacent to at least one channel (e.g., in Fig.17A or 23A, around the gate of the nanosheet, which is connected to Fig. 17B 23B). Provide front side connections 257, 259 to the first source-drain region (in one or more embodiments, the source / drain region wiring 257, 259 to the BEOL wiring 263 includes signal connections rather than power connections). Provide power connections from the back side power rail to the second source-drain region (e.g., Fig.17D , Fig.23D 257, 255, 271 in the case of nFETs, or 257, 255, 269 in the case of nFETs). A backside gate contact is provided from the gate to the backside signal line (e.g., Fig. 17Belement 273 in addition to the T-shaped portion of the gate, or Fig. 23B Component 273A in.

[0082] In some cases, the gate has a length, and the backside gate contact has a bottom dimension greater than the gate length. See, for example, the discussion of dimensions X and Y below.

[0083] In some cases, such as Fig. 17B As shown, the gate is a high-K metal gate, and the backside gate contact includes a T-shaped portion of the high-K metal gate.

[0084] In some cases, the backside signal line is a backside clock signal line. In some embodiments, the backside gate contact includes a portion of the backside clock signal line extending toward the gate (e.g., from Fig. 23B The metal extending downwardly from element 273A in FIG.

[0085] In another aspect, an exemplary semiconductor array structure includes a substrate 207 and a plurality of field effect transistors located on the substrate. Each of the FETs includes a first source-drain region (e.g., Fig.17A or 23A, the left-hand p-epi 243 or the corresponding n-epi in the case of an NFET); and a second source-drain region (e.g., in Fig.17A or 23A, right-hand p-epi 243 or corresponding n-epi in the case of NFETs). Each FET also includes at least one channel (e.g., in Fig.17A or 23A, a nanosheet between the first and second S / D regions); and a gate having Fig.17A and 23A and adjacent to at least one channel (e.g., Fig.17A or 23A, around the gate of the nanosheet, which is connected to Fig. 17B or clock signals 273, 273A in 23B). As can be seen, for example, in Figure 5A In the top view of FIG. 1 , a plurality of field effect transistors are arranged in a row.

[0086] The array structure also includes a plurality of front-side signal lines on the front sides of the plurality of field effect transistors (e.g., Fig.17A and Fig.23A The portion of the BEOL wiring 263 in the BEOL wiring 263 that connects to the VA (via connecting the source-drain contacts to the BEOL wiring 259). In one or more embodiments, the source / drain region wiring 257, 259 to the BEOL wiring 263 includes signal connections rather than power connections because the power is moved to the back side / FEOL. Therefore, multiple back side power rails on the back side of multiple field effect transistors are also included (e.g., according to Fig.25The power supply portion of the backside interconnect 275 is Fig.17D and 23D Multiple backside signal conductors (e.g., connected to VSS 269 to n-epi and VDD 271 to p-epi) Fig. 17B and 23B A plurality of front side signal connections 257, 259 are provided from the plurality of front side signal lines to the first source-drain region. A plurality of power connections ( Fig.17D and 23D 257, 255, 271 in the nFET, or 257, 255, 269 in the nFET). A plurality of backside gate contact connections are provided from the backside signal conductors to the gate (e.g., Fig. 17B element 273 in addition to the T-shaped portion of the gate, or Fig. 23B Element 273A in the back side gate contact connection each having Fig. 17B and 23B The bottom dimension Y shown in is greater than the gate length X.

[0087] In some examples, gates of the plurality of field effect transistors include a high-K metal gate, and the plurality of backside gate contacts connect the T-shaped portions including the high-K metal gate, such as Fig. 17B In some cases, the backside signal conductor includes a backside clock signal conductor. In some cases, the plurality of backside gate contact connections include a portion of the backside clock signal conductor extending toward the gate (e.g., from Fig. 23B The metal extending downwardly from element 273A in FIG.

[0088] For example, refer to Figure 5A In one or more embodiments, a first adjacent pair of transistor rows is n-type 109 and a second adjacent pair of the transistor rows is p-type 111. In some cases, backside clock signal conductors 273 (and also 273A) are located between corresponding rows of n-type rows and p-type rows. In some examples, backside power connections and backside power rails are located between pairs of n-type rows (e.g., VSS 269) and between pairs of p-type rows (e.g., VDD 271).

[0089] In one or more embodiments, the channel includes a nanosheet channel region (e.g., Fig.17A or 23A, a nanosheet between the first and second S / D regions), and the gate comprises a fully surrounding gate (e.g., in Fig.17A or 23A, around the gate of the nanosheet, which is connected to Fig. 17B or clock signals 273, 273A in 23B).

[0090] refer to Fig.24 In one or more embodiments, the array structure further includes a first signal source (e.g., a clock signal 2406) coupled to the plurality of backside signal conductors; a logic signal source 2408 coupled to the plurality of frontside signal lines; and a power supply (e.g., a power supply 2402 coupled to VDD and a ground terminal 2404 coupled to VSS) coupled to the plurality of backside power rails. Element 2400 generally represents a single device or array of devices according to any of the disclosed embodiments.

[0091] On the other hand, reference Figure 2A-17D , an exemplary method of forming a semiconductor structure includes, for example, Figure 3 As shown, n-type and p-type active regions are defined in the nanosheet stack on the substrate 203, and as Figure 4 As shown, shallow trench isolation (STI) regions 229 are formed between the active regions (as shown, in one or more embodiments, the STI does not extend to the top of the nanosheet stack when located between the active regions). It should be noted that for convenience, the active regions are referred to as n-type and p-type, and it should be understood that in one or more embodiments, n-type and p-type source / drain regions are epitaxially grown at a later time. Reference FIG. 5A to FIG. 5C One or more embodiments further include forming a backside gate contact via 233 in a shallow trench isolation (STI) region 229 in a space between the n-type active region and the p-type active region.

[0092] refer to Figures 6A-7D The exemplary method further includes forming a dummy gate 235, and referring to Figures 8A-8D , further comprising forming a gate spacer 241. Figure 7B and 8B As best shown in FIG. 2 , the bottom 236 of the backside gate contact via (note the “T” shape in this example) is filled with dummy gate material of dummy gate 235. As noted elsewhere, Figure 8A-8D Depicts the formation of gate spacers 241, recessing of nanosheets, formation of inner spacers 239, and epitaxial growth of p-type source-drain regions 243 and n-type source-drain regions 245. Figure 7A-7D The structure of Figure 8B As best shown in FIG. 2 , spacer 241 is located on the thinner vertical portion of the “T” and extends laterally to a thickness equal to the protruding crossbar of the “T.” In the final structure, region 236 will be filled with HKMG material, as described below, and the resulting region 253 will be isolated from the FEOL structure by gate spacer 241 .

[0093] refer to Figure 9A-9D, the method further includes removing the dummy gate and forming a replacement high-K metal gate 249 so that the backside gate contact via is filled with high-K metal gate material 253 of the high-K metal gate adjacent to the bottom of the gate (where the high-K metal gate material replaces the dummy material at 236). As discussed elsewhere, in order to Figures 8A-8D The structure moves to Figures 9A-9D The structure of the present invention selectively removes the sacrificial a-Si portion of the dummy gate 235 and the sacrificial nanosheets 209, 211, 213, 215; forms a conformal high-K metal gate stack; patterns and etches a cavity for the gate cutout 251; and fills the cavity with a dielectric material to form the gate cutout 251. Therefore, Figures 9A-9D The resulting structure of these operations is depicted.

[0094] refer to Figures 10A to 10D The method further includes forming a rear end of the line wiring 263 on the front side of the resulting structure opposite to the substrate. Specifically, Figures 10A-10D Depicts the process after forming the middle of line (MOL) contacts, back end of line (BEOL) interconnects, and carrier wafer bonding. Figures 9A-9D Note the VBPR (via for connection to the backside power rail) 255, source / drain contacts (CA) 257, VA (via connecting the source-drain contacts to the BEOL wiring) 259, VB (via connecting the gate to the BEOL wiring) 261, BEOL wiring 263, and carrier wafer 265.

[0095] refer to Figures 11A-17D The method also includes forming a backside (substrate side) signal line (eg, clock signal 273 ) connected to the HKMG material 253 in the backside gate contact via.

[0096] In some cases, reference Figures 8A-8D The method further includes growing p-type 243 and n-type 245 source-drain regions in the p-type and n-type active regions, wherein the nanosheets of the nanosheet stack form a channel therebetween. This defines a plurality of p-type field effect transistors and a plurality of n-type field effect transistors, each p-type field effect transistor including first and second corresponding p-type source-drain regions in the p-type source-drain region, and each n-type field effect transistor including first and second corresponding n-type source-drain regions in the n-type source-drain region. FIG. 16A to FIG. 16D Another step shown includes forming a backside power rail connected to a second corresponding p-type source-drain region in the p-type source-drain region and a second corresponding n-type source-drain region in the n-type source-drain region. Note that the corresponding backside power elements (VSS 269, VDD 271) connected to the S / D epi

[0097] In some cases, reference Figures 10A to 10DAnother method step includes forming a front side signal element (eg, VA259) connected to a first corresponding p-type source drain region of the p-type source drain regions and a first corresponding n-type source drain region of the n-type source drain regions.

[0098] On the other hand, again referring to Figure 3-5C , and also refer to Figures 18A-23D Another exemplary method of forming a semiconductor structure includes, for example, Figure 3 As shown, n-type and p-type active regions are defined in the nanosheet stack on the substrate 203, and as Figure 4 As shown, shallow trench isolation (STI) regions 229 are formed between the active regions (as shown, in one or more embodiments, the STI does not extend to the top of the nanosheet stack when located between the active regions). It should be noted that for convenience, the active regions are referred to as n-type and p-type, and it should be understood that in one or more embodiments, n-type and p-type source / drain regions are epitaxially grown at a later time. Reference FIG. 5A to FIG. 5C One or more embodiments further include forming a backside gate contact via 233 in a shallow trench isolation (STI) region 229 in a space between the n-type active region and the p-type active region.

[0099] refer to Fig.18A and Fig.18B The method further includes filling the back gate contact via with a sacrificial back gate contact material (e.g., silicon nitride (SiN) 501) and recessing the sacrificial back gate contact material. For example, the sacrificial back gate contact material can be recessed to a level flush with the bottom of the nanosheet.

[0100] refer to Figures 19A-19D The method further includes forming a dummy gate 235 and a gate spacer 241 so that a bottom portion of the backside gate contact via is filled with a sacrificial backside gate contact material 501 in contact with the dummy gate material of the dummy gate 235. Figures 19A-19D In the example of , the spacer 241 also has a bottom portion adjacent to the sacrificial back side gate contact material 501 .

[0101] refer to Figures 20A-20D The method further includes removing the dummy gate and forming a replacement high-K metal gate 249 so that the bottom portion of the backside gate contact via is filled with a sacrificial backside gate contact material 501 in contact with the high-K metal gate material of the high-K metal gate 249. Figures 9A-9D The resulting intermediate structure is the intermediate structure shown.

[0102] Reference again Figures 20A to 20D The method further includes forming a rear end of the line wiring 263 on the front side of the resulting structure opposite to the substrate. Specifically, Figures 20A-20DDepicts the process after forming the middle of line (MOL) contacts, back end of line (BEOL) interconnects, and carrier wafer bonding. Figures 19A-19D Note the VBPR (via for connection to the backside power rail) 255, source / drain contacts (CA) 257, VA (via connecting the source-drain contacts to the BEOL wiring) 259, VB (via connecting the gate to the BEOL wiring) 261, BEOL wiring 263, and carrier wafer 265.

[0103] like Fig. 22B As best shown in , the method also includes removing the sacrificial backside gate contact material 501. In this example, adjacent portions of the gate spacers 241 are also removed. The resulting void is indicated as 500.

[0104] refer to Figures 21A-23D The method further includes forming a backside (substrate side) signal line (e.g., clock signal 273A) connected to the HKMG material 249 in the backside gate contact via through the region 500 where the sacrificial backside gate contact material 501 is removed, as shown in FIG. Fig. 23B Best shown.

[0105] In some cases, reference Figures 19A-19D The method further includes growing p-type 243 and n-type 245 source-drain regions in the p-type and n-type active regions, wherein the nanosheets of the nanosheet stack form a channel therebetween. This defines a plurality of p-type field effect transistors and a plurality of n-type field effect transistors, each p-type field effect transistor including first and second corresponding p-type source-drain regions in the p-type source-drain region, and each n-type field effect transistor including first and second corresponding n-type source-drain regions in the n-type source-drain region. Figure 23A-23D Another step shown includes forming backside power rails connected to second corresponding p-type source drain regions in the p-type source drain regions and second corresponding n-type source drain regions in the n-type source drain regions. Note that the corresponding backside power rails (VSS 269, VDD 271) are connected to the S / D epitaxy.

[0106] In some cases, reference Figures 20A-20D Another method step includes forming a front side signal connection (eg, VA259) connected to a first corresponding p-type source drain region of the p-type source drain regions and a first corresponding n-type source drain region of the n-type source drain regions.

[0107] One or more embodiments are implemented in the context of gate-all-around nanosheet technology, as shown in a non-limiting exemplary embodiment. Thus, in one or more embodiments, the NFET and PFET include a channel region in the form of a nanosheet channel region; and the NFET and PFET include a gate in the form of a fully-surrounding gate. However, those skilled in the art will appreciate that the technology disclosed herein may also be used with other types of transistors, for example.

[0108] Fig.26 A computer system 12 is depicted, which may be used, for example, to perform the following Fig. 27 Computer system 12 includes, for example, one or more processors or processing units 16, system memory 28, and bus 18, which couples various system components including system memory 28 to processor 16. Components 16 may be connected to the bus, for example, via a suitable bus interface unit.

[0109] Bus 18 represents any one or more of several types of bus structures, including a memory bus or memory controller, a peripheral bus, an accelerated graphics port, and a processor or local bus using any of a variety of bus architectures. By way of example and not limitation, such architectures include an Industry Standard Architecture (ISA) bus, a Micro Channel Architecture (MCA) bus, an Enhanced ISA (EISA) bus, a Video Electronics Standards Association (VESA) local bus, and a Peripheral Component Interconnect (PCI) bus.

[0110] Computer system / server 12 typically includes a variety of computer system readable media. Such media can be any available media that can be accessed by computer system / server 12, and it includes volatile and nonvolatile media, removable and non-removable media.

[0111] The system memory 28 may include computer system readable media in the form of volatile memory, such as random access memory (RAM) 30 and / or cache memory 32. The computer system / server 12 may also include other removable / non-removable, volatile / non-volatile computer system storage media. By way of example only, a storage system 34 may be provided for reading and writing from a non-removable, non-volatile magnetic medium (not shown and generally referred to as a "hard drive"). Although not shown, a disk drive for reading and writing from a removable non-volatile disk (e.g., a "floppy disk"), and an optical disk drive for reading or writing from a removable non-volatile optical disk (e.g., a CD-ROM, DVD-ROM, or other optical media) may be provided. In this case, each may be connected to the bus 18 via one or more data media interfaces. As will be further depicted and described below, the memory 28 may include at least one program product having a program configured to execute, for example, Fig. 27 A set (eg, at least one) of program modules for the design process shown.

[0112] By way of example and not limitation, a program / utility 40 having a set (at least one) of program modules 42, as well as an operating system, one or more application programs, other program modules, and program data, may be stored in memory 28. Each or some combination of the operating system, one or more application programs, other program modules, and program data may include an implementation of a networking environment. Program modules 42 typically perform software-implemented functions and / or methods.

[0113] The computer system / server 12 may also communicate with one or more external devices 14, such as a keyboard, a pointing device, a display 24, etc.; one or more devices that enable a user to interact with the computer system / server 12; and / or any device that enables the computer system / server 12 to communicate with one or more other computing devices (e.g., a network card, a modem, etc.). Such communication may occur via an input / output (I / O) interface 22. In addition, the computer system / server 12 may communicate with one or more networks, such as a local area network (LAN), a general wide area network (WAN), and / or a public network (e.g., the Internet) via a network adapter 20. As shown, the network adapter 20 communicates with other components of the computer system / server 12 via a bus 18. It should be understood that, although not shown, other hardware and / or software components may be used in conjunction with the computer system / server 12. Examples include, but are not limited to, microcode, device drivers, redundant processing units, and external disk drive arrays, RAID systems, tape drives, and data archiving storage systems, etc.

[0114] Still reference Fig.26, note the processor 16, memory 28, and input / output interface 22 to display 24 and external devices 14 (such as keyboard, pointing device, etc.). The term "processor" as used herein is intended to include any processing device, such as a processing device including a CPU (central processing unit) and / or other forms of processing circuitry. In addition, the term "processor" may refer to more than one individual processor. The term "memory" is intended to include memory associated with a processor or CPU, such as RAM (random access memory) 30, ROM (read only memory), fixed memory devices (e.g., hard disk drive 34), removable memory devices (e.g., floppy disk), flash memory, etc. In addition, the phrase "input / output interface" as used herein is intended to take into account, for example, interfaces for one or more mechanisms (e.g., mouse) for inputting data to the processing unit and one or more mechanisms (e.g., printer) for providing results associated with the processing unit. The processor 16, memory 28, and input / output interface 22 may be interconnected, for example, via bus 18 as part of the data processing unit 12. Appropriate interconnections, such as through bus 18, may also be provided to a network interface 20, such as a network card, which may be provided to interface with a computer network, and to a media interface, such as a floppy disk or CD-ROM drive, which may be provided to interface with appropriate media.

[0115] Thus, computer software including instructions or codes for performing desired tasks may be stored in one or more associated memory devices (e.g., ROM, fixed or removable memory), and when ready to be used, it is partially or completely loaded (e.g., loaded into RAM) and implemented by the CPU. Such software may include, but is not limited to, firmware, resident software, microcode, etc.

[0116] A data processing system suitable for storing and / or executing program code will include at least one processor 16 coupled directly or indirectly to memory elements 28 through a system bus 18. The memory elements may include local memory employed during actual implementation of the program code, bulk storage, and cache memory 32 which provides temporary storage of at least some program code in order to reduce the number of times code must be retrieved from bulk storage during implementation.

[0117] Input / output or I / O devices (including but not limited to keyboards, displays, pointing devices, etc.) may be coupled to the system directly or through an intermediate I / O controller.

[0118] Network adapter 20 may also be coupled to the system to enable the data processing system to become coupled to other data processing systems or remote printers or storage devices through intervening private or public networks. Modems, cable modem and Ethernet cards are just a few of the currently available types of network adapters.

[0119] As used herein (including the claims), a "server" includes a physical data processing system running a server program (eg, such as Fig.26 System 12) shown. It will be understood that such a physical server may or may not include a display and a keyboard. In addition, Fig.26 Represents a conventional general purpose computer that can be used for, for example, to implement aspects of the design process described below.

[0120] Exemplary design processes used in semiconductor design, manufacturing, and / or testing

[0121] One or more embodiments of hardware according to aspects of the invention may be implemented using techniques for simulation, testing, layout and / or manufacturing of semiconductor integrated circuit design. In this regard, Fig. 27 A block diagram of an exemplary design flow 700 used, for example, in semiconductor IC logic design, simulation, testing, layout, and manufacturing is shown. Design flow 700 includes processes, machines, and / or mechanisms for processing design structures or devices to generate logically or otherwise functionally equivalent representations of design structures and / or devices, such as those disclosed herein, etc. The design structures processed and / or generated by design flow 700 can be encoded on a machine-readable storage medium to include data and / or instructions that, when executed or otherwise processed on a data processing system, generate logically, structurally, mechanically, or otherwise functionally equivalent representations of hardware components, circuits, devices, or systems. Machines include, but are not limited to, any machine used in an IC design process, such as to design, manufacture, or simulate circuits, components, devices, or systems. For example, a machine may include: a photolithography machine, a machine and / or device for generating masks (e.g., an electron beam writer), a computer or device for simulating a design structure, any device used in a manufacturing or testing process, or any machine for programming a functionally equivalent representation of a design structure into any medium (e.g., a machine for programming a programmable gate array).

[0122] Design flow 700 may vary depending on the type of representation being designed. For example, design flow 700 for building an application specific IC (ASIC) may be different from design flow 700 for designing a standard component, or different from design flow 700 for instantiating a design into a programmable array (e.g., a Company or Design flow 700 in a programmable gate array (PGA) or field programmable gate array (FPGA)) provided by the company.

[0123] Fig. 27A plurality of such design structures are shown, including an input design structure 720 that is preferably processed by the design process 710. The design structure 720 may be a logical analog design structure generated and processed by the design process 710 to produce a logically equivalent functional representation of a hardware device. The design structure 720 may also or alternatively include data and / or program instructions that, when processed by the design process 710, generate a functional representation of the physical structure of the hardware device. Whether representing functional and / or structural design features, the design structure 720 may be generated using electronic computer-aided design (ECAD) such as implemented by a core developer / designer. When encoded on a gate array or storage medium, etc., the design structure 720 may be accessed and processed by one or more hardware and / or software modules within the design process 710 to simulate or otherwise functionally represent an electronic component, circuit, electronic or logic module, device, equipment, or system. Thus, the design structure 720 may include files or other data structures, including human and / or machine readable source code, compiled structures, and computer executable code structures that, when processed by a design or simulation data processing system, functionally simulate or otherwise represent a circuit or other level of hardware logic design. Such data structures may include hardware description language (HDL) design entities or other data structures that conform to and / or are compatible with low-level HDL design languages ​​(such as Verilog and VHDL) and / or high-level design languages ​​(such as C or C++).

[0124] The design process 710 preferably employs and combines hardware and / or software modules for synthesizing, converting or otherwise processing the design / simulation functional equivalents of components, circuits, devices or logic structures to generate a netlist 780, which may include design structures such as the design structure 720. The netlist 780 may include, for example, a compiled or otherwise processed data structure representing a list of wires, discrete components, logic gates, control circuits, I / O devices, models, etc., which describes the connection with other elements and circuits in the integrated circuit design. The netlist 780 can be synthesized using an iterative process, wherein the netlist 780 is resynthesized one or more times according to the design specifications and parameters of the device. As with other design structure types described herein, the netlist 780 can be recorded on a machine-readable data storage medium or programmed into a programmable gate array. The medium may be a non-volatile storage medium, such as a magnetic or optical drive, a programmable gate array, a compact flash or other flash memory. Additionally or alternatively, the medium may be a system or cache memory, a buffer space or other suitable memory.

[0125] The design process 710 may include hardware and software modules for processing various input data structure types including the netlist 780. Such data structure types may reside in, for example, a library element 730 and include a set of commonly used elements, circuits and devices for a given manufacturing technology (e.g., different technology nodes, 32nm, 45nm, 90nm, etc.), including models, layouts and symbolic representations. The data structure types may also include design specifications 740, feature data 750, verification data 760, design rules 770 and test data files 785, which may include input test patterns, output test results and other test information. The design process 710 may further include, for example, standard mechanical design processes such as stress analysis, thermal analysis, mechanical event simulation, process simulation for operations such as casting, molding and compression molding, etc. A person of ordinary skill in the field of mechanical design may understand the extent of possible mechanical design tools and applications used in the design process 710 without departing from the scope and spirit of the present invention. The design process 710 may also include modules for performing standard circuit design processes such as timing analysis, verification, design rule checking, layout and routing operations, etc.

[0126] Design process 710 employs and combines logical and physical design tools (such as HDL compilers and simulation model building tools) to process design structure 720 along with some or all of the supporting data structures depicted and any additional mechanical design or data (if applicable) to generate a second design structure 790. Design structure 790 resides on a storage medium or programmable gate array in a data format for data exchange of mechanical devices and structures (e.g., information stored in IGES, DXF, Parasolid XT, JT, DRG, or any other suitable format for storing or presenting such mechanical design structures). Similar to design structure 720, design structure 790 preferably includes one or more files, data structures, or other computer-encoded data or instructions residing on a data storage medium, and when processed by an ECAD system, generates a logical or other functional equivalent form of one or more IC designs, etc., as disclosed herein. In one embodiment, design structure 790 may include a compiled executable HDL simulation model that functionally simulates the device disclosed herein.

[0127] Design structure 790 may also be in a data format and / or symbol data format for exchanging layout data of integrated circuits (e.g., information stored in GDSII (GDS2), GL1, OASIS, map files, or any other suitable format for storing such design data structures). Design structure 790 may include information such as, for example, symbol data, mapping files, test data files, design content files, manufacturing data, layout parameters, wires, metal levels, vias, shapes, data for routing through a production line, and any other data required by a manufacturer or other designer / developer to produce a device or structure as described herein. Design structure 790 may then proceed to stage 795, in which, for example, design structure 790: proceeds to tape-out, is sent to manufacturing, is sent to a mask house, is sent to another design house, is sent back to a customer, etc.

[0128] Those skilled in the art will appreciate that the exemplary structures discussed above may be distributed in raw form (ie, a single wafer having multiple unpackaged chips), as a bare die, in a packaged form, or incorporated as part of an intermediate or final product.

[0129] Integrated circuits according to aspects of the present invention may be used in substantially any application and / or electronic system.Given the teachings of the present disclosure provided herein, one of ordinary skill in the art will be able to envision other implementations and applications of the embodiments disclosed herein.

[0130] The illustrations of the embodiments described herein are intended to provide a general understanding of the various embodiments, and they are not intended to serve as a complete description of all elements and features of devices and systems that may utilize the circuits and techniques described herein. In view of the teachings herein, many other embodiments will become apparent to those skilled in the art; other embodiments are utilized and derived therefrom, so that structural and logical substitutions and changes can be made without departing from the scope of the present disclosure. It should also be noted that in some alternative embodiments, some steps of the exemplary method may not occur in the order shown in the figures. For example, two steps shown in succession may actually be performed substantially simultaneously, or certain steps may sometimes be performed in the opposite order, depending on the functions involved. The drawings are also merely representative and are not drawn to scale. Therefore, the specification and drawings are considered to be illustrative rather than restrictive.

[0131] Embodiments are referred to herein individually and / or collectively by the term "embodiment", which is merely for convenience and is not intended to limit the scope of the present application to any single embodiment or inventive concept if more than one is actually shown. Therefore, although specific embodiments have been shown and described herein, it should be understood that arrangements that achieve the same purpose may replace the specific embodiments shown; that is, the present disclosure is intended to cover any and all adaptations or variations of the various embodiments. Combinations of the above embodiments, as well as other embodiments not specifically described herein, will become apparent to those skilled in the art in view of the teachings herein.

[0132] The terms used herein are only used for the purpose of describing specific embodiments and are not restrictive. As used herein, the singular forms "a", "an" and "the" are intended to also include plural forms, unless the context clearly indicates otherwise. It will be further understood that when used in this specification, the terms "include" and / or "comprise" specify the presence of the features, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, steps, operations, elements, parts and / or combinations thereof. Terms such as "bottom", "top", "up", "above", "below" and "below" are used to indicate the relative positioning of elements or structures relative to each other, rather than relative heights. If a layer of a structure is described herein as being "above" another layer, it should be understood that there may or may not be an intermediate element or layer between the two specified layers. If a layer is described as being "directly on" another layer, direct contact of the two layers is indicated. As used herein and in the appended claims, "about" means within plus or minus 10%.

[0133] The corresponding structures, materials, actions, and equivalents of any device or step plus function element in the following claims are intended to include any structure, material, or action for performing a function in conjunction with other claimed elements as specifically claimed. The descriptions of various embodiments have been presented for purposes of illustration and description, but are not intended to be exhaustive or limited to the disclosed forms. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiments are selected and described in order to best explain the principles and practical applications, and to enable those of ordinary skill in the art to understand the various embodiments with various modifications suitable for the intended specific use.

[0134] The abstract is provided to comply with 37 C.FR § 1.76 (b), which requires that the abstract will allow the reader to quickly determine the nature of the technical disclosure. It should be understood that the abstract will not be used to interpret or limit the scope or meaning of the claims. In addition, in the foregoing detailed description, it can be seen that various features are grouped together in a single embodiment for the purpose of simplifying the disclosure. This method of disclosure should not be interpreted as reflecting the intention that the claimed embodiments require more features than those explicitly recited in each claim. On the contrary, as reflected in the attached claims, the claimed subject matter may lie in less than all the features of a single embodiment. Therefore, the following claims are hereby incorporated into the detailed description, with each claim independently serving as a separately claimed subject matter.

[0135] Given the teachings provided herein, one of ordinary skill in the art will be able to envision other implementations and applications of the technology and disclosed embodiments. Although illustrative embodiments have been described herein with reference to the accompanying drawings, it should be understood that the illustrative embodiments are not limited to those precise embodiments, and that various other changes and modifications may be made therein by one skilled in the art without departing from the scope of the appended claims.

Claims

1. A semiconductor structure comprising: backside power rail; Dorsal signal line; Front signal line; a first source-drain region; a second source-drain region; at least one channel coupling the first source-drain region and the second source-drain region; a gate adjacent to the at least one channel; a front side signal connection from the front side signal line to the first source-drain region; a power connection from the backside power rail to the second source-drain region; and A backside gate contact from the gate to the backside signal line. 2 . The semiconductor device of claim 1 , wherein the gate has a length, and wherein the backside gate contact has a bottom dimension greater than the gate length. 3 . The semiconductor device of claim 2 , wherein the gate comprises a high-K metal gate, and wherein the backside gate contact comprises a T-shaped portion of the high-K metal gate. 4 . The semiconductor device according to claim 2 , wherein the backside signal line comprises a backside clock signal line, and wherein the backside gate contact comprises a portion of the backside clock signal line extending toward the gate.

5. A semiconductor array structure, comprising: substrate; a plurality of field effect transistors located on the substrate, each field effect transistor comprising a first source-drain region, a second source-drain region, at least one channel connecting the first source-drain region and the second source-drain region, and a gate having a gate length and adjacent to the at least one channel, the plurality of field effect transistors being arranged in a row; a plurality of front side signal lines on the front sides of the plurality of field effect transistors; a plurality of backside power rails on a backside of the plurality of field effect transistors; a plurality of backside signal conductors on a backside of the plurality of field effect transistors; a plurality of front side signal connections from the plurality of front side signal lines to the first source-drain region; a plurality of power connections from the backside power rail to the second source-drain region; and A plurality of backside gate contact connections are made from the backside signal conductor to the gate, the backside gate contact connections each having a bottom dimension greater than the gate length. 6 . The semiconductor array structure of claim 5 , wherein the gates of the plurality of field effect transistors comprise high-K metal gates, and wherein the plurality of backside gate contact connections comprise T-shaped portions of the high-K metal gates.

7. The semiconductor array structure of claim 5, wherein the backside signal conductor comprises a backside clock signal conductor, and wherein the plurality of backside gate contact connections comprise portions of the backside clock signal conductor extending toward the gate.

8. The semiconductor array structure of claim 7, wherein a first adjacent pair of the rows are n-type and a second adjacent pair of the rows are p-type. 9 . The semiconductor array structure according to claim 8 , wherein the backside clock signal conductor is located between corresponding ones of the n-type rows and the p-type rows.

10. The semiconductor array structure of claim 9, wherein the backside power connection and backside power rail are located between the pair of n-type rows and between the pair of p-type rows.

11. The semiconductor array structure according to claim 5, wherein: The channel includes a nanosheet channel region; and The grid includes an omnidirectional grid.

12. The semiconductor array structure according to claim 5, further comprising: a first signal source coupled to the plurality of backside signal conductors; a second signal source coupled to the plurality of front-side signal lines; and A power supply is coupled to the plurality of backside power rails.

13. A method of forming a semiconductor structure, comprising: defining an n-type active region and a p-type active region in a nanosheet stack on a substrate, and forming a shallow trench isolation (STI) region between the active regions; forming a backside gate contact via in the shallow trench isolation (STI) region in a space between the n-type active region and the p-type active region; forming a dummy gate and a gate spacer so that a bottom portion of the backside gate contact through hole is filled with a dummy gate material of the dummy gate; removing the dummy gate and forming a replacement high-K metal gate such that the backside gate contact via is filled with the high-K metal gate material of the high-K metal gate adjacent to a bottom portion of the gate to obtain a resulting structure; forming a rear end of a line routing on a front side of the resulting structure opposite the substrate; and A backside signal line connected to the high-K metal gate material in the backside gate contact via is formed.

14. The method according to claim 13, further comprising: Growing p-type source-drain regions and n-type source-drain regions in the p-type active region and the n-type active region, wherein the nanosheets of the nanosheet stack form channels therebetween, to define a plurality of p-type field effect transistors and a plurality of n-type field effect transistors, each p-type field effect transistor comprising a first corresponding p-type source-drain region and a second corresponding p-type source-drain region in the p-type source-drain region, and each n-type field effect transistor comprising a first corresponding n-type source-drain region and a second corresponding n-type source-drain region in the n-type source-drain region; and A backside power rail connected to the second corresponding p-type one of the p-type source drain regions and the second corresponding n-type one of the n-type source drain regions is formed. 15 . The method of claim 14 , further comprising forming front side signal connections connected to the first corresponding p-type ones of the p-type source drain regions and the first corresponding n-type ones of the n-type source drain regions.

16. A method of forming a semiconductor structure, comprising: defining an n-type active region and a p-type active region in a nanosheet stack on a substrate, and forming a shallow trench isolation (STI) region between the active regions; forming a backside gate contact via in the shallow trench isolation (STI) region in a space between the n-type active region and the p-type active region; filling the back side gate contact via with a sacrificial back side gate contact material and recessing the sacrificial back side gate contact material; forming a dummy gate and a gate spacer such that a bottom portion of the backside gate contact via is filled with a sacrificial backside gate contact material in contact with a dummy gate material of the dummy gate; removing the dummy gate and forming a replacement high-K metal gate such that a bottom portion of the backside gate contact via is filled with a sacrificial backside gate contact material in contact with the high-K metal gate material of the high-K metal gate to obtain a resulting structure; forming a rear end of a line routing on a front side of the resulting structure opposite the substrate; removing the sacrificial back gate contact material to form a void; and A backside signal line connected to the high-K metal gate material is formed through the gap.

17. The method according to claim 16, further comprising: Growing p-type source-drain regions and n-type source-drain regions in the p-type active region and the n-type active region, wherein the nanosheets of the nanosheet stack form channels therebetween, to define a plurality of p-type field effect transistors and a plurality of n-type field effect transistors, each p-type field effect transistor comprising a first corresponding p-type source-drain region and a second corresponding p-type source-drain region in the p-type source-drain region, and each n-type field effect transistor comprising a first corresponding n-type source-drain region and a second corresponding n-type source-drain region in the n-type source-drain region; and A backside power rail connected to the second corresponding p-type one of the p-type source drain regions and the second corresponding n-type one of the n-type source drain regions is formed. 18 . The method of claim 17 , further comprising forming front side signal connections connected to the first corresponding p-type ones of the p-type source drain regions and the first corresponding n-type ones of the n-type source drain regions.

19. A hardware description language (HDL) design structure encoded on a machine-readable data storage medium, the HDL design structure comprising elements that when processed in a computer-aided design system generate a machine-executable representation of a semiconductor array structure, wherein the HDL design structure comprises: substrate; a plurality of field effect transistors located on the substrate, each field effect transistor comprising a first source-drain region, a second source-drain region, at least one channel connecting the first source-drain region and the second source-drain region, and a gate having a gate length adjacent to the at least one channel, the plurality of field effect transistors being arranged in a row; a plurality of front side signal lines on the front sides of the plurality of field effect transistors; a plurality of backside power rails on a backside of the plurality of field effect transistors; a plurality of backside signal conductors on a backside of the plurality of field effect transistors; a plurality of front side signal connections from the plurality of front side signal lines to the first source-drain region; a plurality of power connections from the backside power rail to the second source-drain region; and A plurality of backside gate contact connections are made from the backside signal conductor to the gate, the backside gate contact connections each having a bottom dimension greater than the gate length.

20. The design structure of claim 19, wherein gates of the plurality of field effect transistors comprise high-K metal gates, and wherein the plurality of backside gate contact connections comprise T-shaped portions of the high-K metal gates.

21. The design structure of claim 19, wherein the backside signal conductor comprises a backside clock signal conductor, wherein the plurality of backside gate contact connections comprise portions of the backside clock signal conductor extending toward the gate, and wherein a first adjacent pair of the rows are n-type and a second adjacent pair of the rows are p-type.

22. The design structure of claim 21, wherein the backside clock signal conductor is located between corresponding ones of the n-type rows and the p-type rows.

23. The design structure of claim 22, wherein the backside power connection and backside power rail are located between the pair of n-type rows and between the pair of p-type rows.

24. The design structure of claim 19, wherein: The channel includes a nanosheet channel region; and The grid includes an omnidirectional grid.

25. The design structure of claim 19, further comprising: a first signal source coupled to the plurality of backside signal conductors; a second signal source coupled to the plurality of front-side signal lines; and A power supply is coupled to the plurality of backside power rails.

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