Metal integration method for manufacturing integrated device

Abstract

Fabrication of integrated devices (e.g., integrated semiconductor devices) is disclosed herein. The metal integration method can be used in the technological process for manufacturing the integrated device. The method is based on patterning different spacers and defining different metal structures using the spacers in two separate steps. Specifically, the processing steps of the metal structure of the first metal material (61) and the metal structure of the second metal material (91) are different.

Description

Technical Field

[0001] The present disclosure relates to the manufacture of integrated devices, such as integrated semiconductor devices, and provides a metal integration method that can be used in a process flow for manufacturing such integrated devices. Background Art

[0002] In the process flow for manufacturing integrated devices, advanced back end of line (BEOL) patterning can use metal pitches less than 21nm. For this advanced patterning, edge placement error (EPE) is key, and fully self-aligned vias are required to ensure robust connections between different metal layers. However, it can be observed that when using deep ultraviolet (DUV) patterning technology, there is not enough EPE margin for this advanced patterning. This is because it is impossible to reduce the EPE margin below 5nm due to inherent technological limitations.

[0003] In addition to the scaling of metal lines, one of the main bottlenecks in BEOL functions is via patterning and its alignment. Major foundries have implemented multiple self-aligned vias and fully self-aligned-via (FSAV) example schemes to alleviate the limitations of EPE. All implemented schemes use a single hard mask material. These schemes can achieve good results at the 5nm node (metal pitch of 28nm), but only if extreme ultraviolet (EUV) technology is implemented. This is because a single hard mask material is used to protect adjacent metal lines and relax the requirements for EPE. However, since EPE is difficult to achieve below 5nm, there is currently no solution for metal pitches less than 21nm. Summary of the invention

[0004] In view of the above, the present disclosure aims to provide an improved metal integration scheme that can be used in the process flow of manufacturing integrated devices. The purpose is to provide solutions for various metal spacings, for example, also for metal spacings below 21nm. Another purpose is to solve the situation of EPE margin below 5nm.

[0005] These and other objects are achieved by the disclosed solutions described in the independent claims. Advantageous implementations are further defined in the dependent claims.

[0006] The present disclosure proposes a dual material hard mask process for metal integration that enables protection of adjacent metal lines during BEOL metallization processes.

[0007] A first aspect of the present disclosure provides a metal integration method for manufacturing an integrated device, the method comprising: forming a first structure and a second structure from a common layer on a substrate, wherein the first structure and the second structure are separated from each other along a first direction and each extends to a second direction; forming a first spacer and a second spacer on the substrate, wherein the first spacer and the second spacer each extend to the second direction, the first spacer lines the first structure on both sides of the first structure, and the second spacer lines the second structure on both sides of the second structure; forming a third spacer and a fourth spacer on the substrate, wherein the third spacer and the fourth spacer each extend to the second direction , the third spacer lines the first spacer on both sides of the first spacer, and the fourth spacer lines the second spacer on both sides of the second spacer; a fifth spacer is formed between the third spacer and the fourth spacer; a plurality of first gaps are formed by selectively removing the third spacer, the fourth spacer, the first structure and the second structure; a first metal material is deposited into the first gap; a plurality of second gaps are formed by selectively removing the first spacer and the second spacer; a first dielectric material is deposited into the second gap; a plurality of grooves are formed in the first dielectric material in the second gap; a second metal material is deposited into the grooves.

[0008] The first structure and the second structure may be repeated at a given pitch. The first structure and the second structure may be parts of a unit cell of the integrated device, wherein the unit cell may be repeated once or multiple times. The first structure may be a first conductive structure, such as a first metal structure. The second structure may be a second conductive structure, such as a second metal structure. Accordingly, the first structure and the second structure may be made of the same conductive layer, such as a metal layer. The first structure and the second structure may also be nitride-based structures, such as silicon nitride structures, or may be carbon-based structures, such as amorphous carbon (aC) structures.

[0009] By forming various spaces and using these spacers to process the structures of the first metal material and the second metal material respectively, solutions can be provided for various metal pitches, and also for metal pitches below 21nm. DUV technology can be used, and EUV technology can also be used, but it is not necessary.

[0010] In an implementation of the first aspect, the method further includes: after selectively removing the third spacer, the fourth spacer, the first structure and the second structure: depositing a first filling material into the first gap; removing the first filling material to reopen the first gap; wherein the first metal material is deposited into the reopened first gap.

[0011] In an implementation of the first aspect, the method also includes: before selectively removing the first spacer and the second spacer: selectively forming one or more openings in the third spacer or the fourth spacer or the first filling material, respectively; extending the openings into the substrate; wherein depositing the first metal material into the first gap includes depositing the first metal material into the opening extending into the substrate to form one or more first vias.

[0012] Accordingly, the first via hole can be processed in a self-aligned manner.

[0013] In an implementation of the first aspect, the method further includes, before depositing the second metal material into the groove: extending one or more of the grooves through the first dielectric material and into the substrate; wherein depositing the second metal material into the groove includes depositing the second metal material into the groove extending into the substrate to form one or more second vias.

[0014] Accordingly, the second via hole can be processed in a self-aligned manner.

[0015] In an implementation of the first aspect, the one or more openings are formed in the third spacer, or in the fourth spacer, or in the first filling material by: photolithography patterning; performing a first selective etching on the third spacer, the fourth spacer, or the first filling material to form the one or more openings; performing a second selective etching on the substrate to extend the one or more openings into the substrate.

[0016] In an implementation of the first aspect, the method further includes: before selectively removing the third spacer or the fourth spacer, or before removing the first filling material: covering a portion of the third spacer or the fourth spacer or the first filling material with a protective layer to prevent the portion of the third spacer or the fourth spacer or the first filling material from being removed.

[0017] In an implementation of the first aspect, the method further includes: before selectively removing the first spacer and the second spacer: recessing the first metal material into the first gap; and depositing a first hard mask material into the first gap to cover the recessed first metal material.

[0018] In an implementation of the first aspect, the one or more grooves extend into the substrate by: depositing a second filling material into the plurality of grooves; photolithography patterning; performing a first selective etching on the second filling material in the one or more grooves; performing a second selective etching on the dielectric material to extend the one or more grooves through the dielectric material and into the substrate; and removing the second filling material.

[0019] In an implementation of the first aspect, the method further includes: after depositing the second metal material into the groove: selectively removing a portion of the second metal material; and depositing a second dielectric material to the position where the second metal material was selectively removed.

[0020] In an implementation of the first aspect, the selectively removing the portion of the second metal material includes: photolithography patterning to expose only the portion of the second metal material; and performing selective metal etching on the exposed second metal material.

[0021] In an implementation of the first aspect, the method includes: before depositing the second metal material into the trench: forming a third dielectric material in a portion of the trench to prevent the second metal material from being deposited into the portion of the trench.

[0022] In an implementation manner of the first aspect, the method further includes: recessing the exposed second metal material; and depositing a second hard mask material into the recessed second metal material.

[0023] In an implementation of the first aspect, the material of the first spacer and the second spacer is different from the material of the third spacer and the fourth spacer; and / or the first metal material and the second metal material are different materials.

[0024] In an implementation manner of the first aspect, the first metal material and / or the second metal material includes at least one of the following: ruthenium, copper, molybdenum, cobalt and tungsten.

[0025] In an implementation manner of the first aspect, the method further includes: the substrate includes at least one of the following: a middle of line (MOL) layer and a BEOL layer.

[0026] In an implementation of the first aspect, the first dielectric material includes silicon nitride and / or a dielectric for the MOL layer.

[0027] In an implementation of the first aspect, the substrate includes one or more integrated circuits; the first structure and / or the second structure is a power rail of at least one integrated circuit in the substrate.

[0028] A second aspect of the present disclosure provides an integrated device, which can be obtained by a method according to the first aspect or any implementation manner of the first aspect.

[0029] The integrated device according to the second aspect may have a metal pitch below 21 nm. However, other metal pitches, for example, metal pitches below 32 nm are also possible.

[0030] Based on the above, the scheme of the present disclosure proposes a new metal integration scheme that enables the manufacture of different metal structures (e.g., narrow metal lines) with small metal pitches below 21nm, even when using DUV technology instead of EUV technology. Specifically, this is achieved by implementing a novel spacer-defined patterning scheme (using first to fifth spacers) to define the metal structure in two separate steps. The first metal material can be etched (or trench filled) and the second metal material can be defined by a metal filling process in a different step. After metal deposition, the metal can be recessed, or area selective deposition (ASD) can be implemented to define the two separate materials of the hard mask for the FSAV process.

[0031] The solution disclosed in the present invention has at least the following advantages:

[0032] Narrow metal structures can be integrated using DUV, which can be achieved by separating the integration of the first metal material and the second metal material in two separate process sequences.

[0033] For advanced BEOL metallization (e.g., for metal pitches below 21nm), the EPE margin can be improved. This can be achieved by using a hard mask of a different material on top of the adjacent metal structures, which makes it possible to achieve true FSAV through the high etch selectivity of the hard mask material.

[0034] The capacitance of metal structures can be reduced because adjacent metal structures may not be on the same level but can be slightly staggered or have edges overlapping on the sides. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In conjunction with the accompanying drawings, the following description of the embodiments will illustrate the above aspects and their implementation methods. In the drawings:

[0036] Figures 1 to 9 A method for manufacturing an integrated device according to the present disclosure is shown;

[0037] Figures 10 to 29 A first exemplary method for manufacturing an integrated device according to the present disclosure is shown;

[0038] Figures 30 to 49 A second exemplary method for fabricating an integrated device according to the present disclosure is shown. DETAILED DESCRIPTION

[0039] Figures 1 to 9 A method for manufacturing an integrated device according to the present disclosure is shown. Specifically, the continuous processing steps of the method are shown. Each figure shows an intermediate state of the integrated device after the processing steps performed in the figure. All figures show a cross-sectional view of the integrated device, wherein the integrated device is shown along the x-axis (x-direction) and the z-axis (z-direction), as shown in the coordinate system in the lower left corner of the figure. Some of the figures also show a top view of the integrated device, wherein the integrated device is shown along the x-axis (x-direction) and the y-axis (y-direction) of the coordinate system, as shown in the upper left corner of the figure.

[0040] Figure 1 It is shown that in the first step of the method, a first structure 11 and a second structure 12 are formed by a common layer on a substrate 13. The first structure 11 and the second structure 12 can be made of metal or silicon nitride or amorphous carbon, and are separated from each other along a first direction (x direction in the coordinate system shown in the lower left corner), and each extends to a second direction (y direction). The first structure 11 and the second structure 12 can define the core of the integrated device. The substrate 13 may include an interlayer dielectric, which is disposed on a semiconductor substrate, such as a silicon-based substrate or an amorphous silicon substrate.

[0041] The minimum feature size of this method can be defined as F. Figure 1 As shown, the first structure 11 and the second structure 12 can have a width of 3F respectively (along the first direction). The spacing between the first structure 11 and the second structure 12 can be 14F, and the spacing between these metal structures is 11F. It is worth noting that more than two metal structures 11, 12 can be manufactured in this way, for example, a plurality of metal structures 11, 12 arranged at the said spacing. The method can illustrate any two metal structures 11, 12 of the plurality of metal structures 11, 12. It is worth noting that the first structure 11 and the second structure 12 can be formed by resist deposition, followed by photolithography (exposure), followed by resist development, and then pattern transfer to the underlying substrate 13.

[0042] Figure 2 It is shown that in another step of the method, a first spacer 21 and a second spacer 22 are formed on the substrate 13. The first spacer 21 and the second spacer 22 both extend to the second direction. The first spacer 21 lines the first structure 11 on both sides of the first structure 11, for example, the first spacer 21 clamps the first structure 11 in the first direction. The second spacer 22 lines the second structure 12 on both sides of the second structure 12, for example, the second spacer 22 clamps the second structure 12 in the first direction. The first spacer 21 and the second spacer 22 can be formed by depositing a spacer material and then etching the spacer material. The first spacer 21 and the second spacer 22 can have a width of 3F along the first direction on each side of the first structure 11 and the second structure 12, respectively.

[0043] Figure 3 It is shown that in another step of the method, a third spacer 31 and a fourth spacer 32 are formed on the substrate 13. The third spacer 31 and the fourth spacer 32 extend to the second direction, respectively. The third spacer 31 lines the first spacer 21 on both sides of the first spacer 21, for example, the third spacer 31 clamps the first spacer 21 and the first structure 11 in the first direction. The fourth spacer 32 lines the second spacer 22 on both sides of the second spacer 22, for example, the fourth spacer 32 clamps the second spacer 22 and the second structure 12 in the first direction. The third spacer 31 and the fourth spacer 32 can be formed by depositing a second spacer material and then etching the second spacer material. The third spacer 31 and the fourth spacer 32 can have a width of 1F along the first direction on each side of the first spacer 21 and the second spacer 22, respectively.

[0044] Figure 4 It is shown that in another step of the method, a fifth spacer 41 is formed between the third spacer 31 and the fourth spacer 32, thereby also forming the fifth spacer 41 between the first spacer 21 and the second spacer 22 and between the first structure 11 and the second structure 12, respectively. Specifically, the fifth spacer 41 can be formed by performing gap filling, for example, in which all gaps on the substrate 13 are filled with the same spacer material as used for the first spacer 21 and the second spacer 22. Then, a planarization step (e.g., chemical mechanical polishing (CMP)) can be performed to planarize the surface of the intermediate integrated device.

[0045] Figure 5 It is shown that in another step of the method, a plurality of first gaps 51 are formed by selectively removing the third spacer 31, the fourth spacer 32, the first structure 11 and the second structure 12. This step may be referred to as spacing and core pulling. Figure 5The top view and the cross-sectional view of the intermediate integrated device are shown, and the dotted line indicates the cut position of the cross-sectional view. This is the same in all other figures showing two views.

[0046] Figure 6 It is shown that in another step of the method, a first metal material 61 is deposited into the first gap 51. The first metal material 61 may be referred to as metal A, and this step may include a metal A fill and subsequent CMP.

[0047] Figure 7 It is shown that in another step of the method, a plurality of second gaps 71 are formed by selectively removing the first spacers 21 and the second spacers 22. This step may be referred to as a gap pulling step. The second gaps 71 are formed between locations where the first metal material 61 has been deposited.

[0048] Figure 8 It is shown that in another step of the method, a first dielectric material 81 is deposited in the second gap 71, and a plurality of trenches 82 are formed in the first dielectric material 81 in the second gap 71. The trenches 82 may each extend to the second direction and may be formed between locations (along the first direction) where the first material 61 has been deposited.

[0049] Fig. 9 In another step of the method, a second metallic material 91 is shown deposited into the trench 82. The second metallic material 91 may be referred to as metal B, and this step may include a metal B fill and subsequent CMP.

[0050] From the figure illustrating the method, it can be seen that Fig. 9 The spacing between all metal structures (formed by metal A and metal B, respectively) in the intermediate integrated device shown is much smaller than the initial spacing of 14F. Fig. 9 The spacing after the step can be 3F.

[0051] Figures 10 to 29 A first exemplary method for manufacturing an integrated device according to the present disclosure is shown. Specifically, Figures 1 to 4 That is, the first exemplary method includes Figures 1 to 4 The steps shown in Figures 10 to 29 The steps shown in . The repeated description of the former is omitted here.

[0052] Fig.10It is shown that in another step of the first exemplary method, photolithographic patterning is performed. Photolithographic patterning can be referred to as via patterning because the technique can be used to pattern one or more first vias. Specifically, the intermediate integrated device is covered with a resist 101 or the like, and then the resist 101 or the like is selectively developed and removed to open specific areas 102 of the underlying device for further processing. For example, as shown, portions of the first spacer 21 and the third spacer 31 are exposed. Portions of the second spacer 22 and the fourth spacer 32 may also be exposed in a similar manner (not shown).

[0053] Fig.11 It is shown that in another step of the first exemplary method, one or more openings 121 are formed in the third spacer 31 (as shown) and / or the fourth spacer 32 (not shown). For example, a first selective etching may be performed on the third spacer 31 and / or the fourth spacer 32 to form the one or more openings 121. The one or more openings 121 may each expose the substrate 13. The one or more openings 121 may be referred to as via openings because their purpose may be to form one or more first vias, as described below.

[0054] Fig.12 It is shown that in another step of the first exemplary method, the openings 121 extend into the substrate 13. For example, a second selective etch may be performed on the substrate 13 to extend one or more openings 121 into the substrate 13. The purpose may be to form one or more first vias in the substrate 13.

[0055] Fig.13 It is shown that in another step of the first exemplary method, the resist 101 is removed and then portions of the third spacer 31 and / or the fourth spacer 32 (both shown) are covered with a protective layer 131 to prevent the portions of the third spacer 31 and / or the fourth spacer 32 from being removed in a subsequent next step, respectively. The current step may be referred to as block patterning.

[0056] Fig.14 It is shown that in another step of the first exemplary method, a plurality of first gaps 51 are formed by selectively removing the third spacer 31, the fourth spacer 32, the first structure 11 and the second structure 12. This step can be referred to as spacing and core pulling. It is worth noting that the protective layer 131 prevents the third spacer 31 and / or the second spacer 32 from being partially removed.

[0057] Fig.15In another step of the first exemplary method, a first metal material 61 is shown deposited into the first gap 51. As shown, depositing the first metal material 61 into the first gap 51 includes depositing the first metal material 61 into the opening 121 extending into the substrate 13. This may form one or more first vias.

[0058] Fig.16 It is shown that in another step of the first exemplary method, the first metal material 61 (which has been deposited into the first gap 51) may be recessed (in the direction of the substrate 13). Therefore, this step may be referred to as Metal A recessing.

[0059] Fig.17 It is shown that in another step of the first exemplary method 10, a first hard mask material 171 is deposited onto the recessed first metal material 61. This step may be referred to as hard mask A formation or hard mask A selective area deposition. It is worth noting that the first hard mask material 171 may not be formed on the remaining portion of the third spacer 31 or the fourth spacer 32, or may be removed from the remaining portion of the third spacer 31 or the fourth spacer 32.

[0060] Fig.18 It is shown that in another step of the first exemplary method, a plurality of second gaps 71 are formed by selectively removing the first spacers 21 and the second spacers 22 disposed between the first metal material 61 and the hard mask material 171. This step may be referred to as a spacer pulling step. The remaining portions of the third spacers 31 and the fourth spacers 32 may also be removed in this step. The selective removal may be performed by selectively etching the corresponding materials.

[0061] Fig.19 It is shown that in another step of the first exemplary method, a first dielectric material 81 is deposited into the second gap 71. Furthermore, a plurality of trenches 82 are formed in the first dielectric material 81 (which has been deposited into the second gap 71), for example, by etching the first dielectric material 81.

[0062] Fig. 20 In another step of the first exemplary method, fill material 201 is shown deposited into a plurality of trenches 82. This step may be referred to as fill and via B patterning. Patterning may include providing mask material 202 on one or more regions, each region being located above one trench 82 (one is shown). This may be used to pattern one via or a second via, as described below.

[0063] Fig.21It is shown that in another step of the first exemplary method, photolithography patterning is performed. The photolithography patterning may include applying a resist 101 on the surface of the intermediate integrated device (which is not formed at the location where the mask material 202 is set), and removing the mask material 202 to expose the previously covered area through the mask opening, specifically, the mask opening exposes one or more grooves 82. In addition, a first selective etching of the filling material 201 can be performed in the exposed one or more grooves 82 to remove the filling material 201 from these one or more grooves 82.

[0064] Fig. 22 It is shown that in another step of the first exemplary method, a second selective etch may be performed on the exposed and etched dielectric material 81 to extend one or more trenches 82 through the dielectric material 81 and into the substrate 13. This may be referred to as a via B etch.

[0065] Fig.23 It is shown that in a further step of the first exemplary method, the resist 101 is removed and the filling material 201 is removed.

[0066] Fig.24 In another step of the first exemplary method, a second metal material 91 is deposited into the trench 82. Afterwards, a planarization step may be performed. This may be referred to as metal B filling followed by CMP. The second material 91 extending into one or more trenches 82 in the substrate 13 may form one or more second vias.

[0067] Fig.25 It is shown that in another step of the first exemplary method, photolithographic patterning is performed to expose only a portion 251 of the second metal material 91 .

[0068] Fig.26 It is shown that in another step of the first exemplary method, a portion 251 of the exposed second metal material 91 is selectively removed. This can be referred to as self-aligned cutting of metal B by direct metal etch (DME). The dielectric material 81 under the removed second metal material 91 can be freely disposed.

[0069] Fig. 27 It is shown that in another step of the first exemplary method, a second dielectric material 271 is deposited to the location where the second metal material 91 was selectively removed.

[0070] Fig.28 It is shown that in a further step of the first exemplary method, the exposed second metal material 91 may be recessed in the direction of the substrate 13. This may be referred to as metal B recessing.

[0071] Fig.29It is shown that in another step of the first exemplary method, a second hard mask material 291 is deposited into the recessed second metal material 91. This may be referred to as hard mask B formation or hard mask B selective area deposition.

[0072] Figures 30 to 49 A second exemplary method for manufacturing an integrated device according to the present disclosure is shown. Specifically, Figures 1 to 4 That is, the second exemplary method includes Figures 1 to 4 The steps shown in Figures 30 to 49 The steps shown in . The repeated description of the former is omitted here.

[0073] Fig.30 It is shown that in another step of the second exemplary method, the third and fourth spacers 31 and 32 and the first and second structures 11 and 12 are selectively removed, respectively, wherein a plurality of first gaps 51 are formed over the substrate 13 .

[0074] Fig.31 It is shown that in a further step of the second exemplary method, a filling material 311 is deposited into the first gap 51, in particular between the first spacer 21 and the second spacer 22. Subsequently, a CMP may be performed.

[0075] Fig.32 It is shown that in another step of the second exemplary method, photolithographic patterning is performed. Photolithographic patterning can be referred to as via patterning because the technique can be used to pattern one or more first vias. Specifically, the intermediate integrated device is covered with a resist 101 or the like, and then the resist 101 or the like is selectively developed and removed to open a specific area 321 of the underlying device for further processing. For example, as shown in the figure, a portion of the first spacer 21 and the filling material 311 (the position before the third spacer 31) is exposed. Another portion of the filling material 311 (the position before the fourth spacer 32) can also be exposed in a similar manner.

[0076] Fig.33 It is shown that in another step of the second exemplary method, one or more openings 121 are selectively formed in the filling material 311. For example, a first selective etching may be performed on the filling material 311 to form the one or more openings 121. These openings may be referred to as via openings, as the purpose of these openings may be to make first vias.

[0077] Fig.34 It is shown that in another step of the second exemplary method, the openings 121 extend into the substrate 13. For example, a second selective etch may be performed on the substrate 13 to extend one or more openings 121 into the substrate 13. This may be referred to as a via etch of a first via.

[0078] Fig.35 It is shown that in another step of the second exemplary method, the resist 101 is removed and a portion of the filling material 311 is covered with a protective layer 131 to prevent the removal of the portion of the filling material 311 in a subsequent step. The current step may be referred to as block patterning.

[0079] Fig.36 It is shown that in another step of the second exemplary method, the filling material 311 is removed to reopen the first gap 51. For example, the filling material 311 can be selectively etched. The protection layer 131 is then removed, and the previously covered filling material 311 remains.

[0080] Fig.37 It is shown that in another step of the second exemplary method, a first metal material 61 is deposited into the reopened first gap 51. Depositing the first metal material 61 into the reopened first gap 51 includes depositing the first metal material 61 into the opening 121 extending into the substrate 13 to form one or more first vias. Then, planarization like CMP may be performed.

[0081] Fig.38 In a further step of the second exemplary method, first metal material 61 is shown recessed in first gap 51 in the direction of substrate 13 .

[0082] Fig.39 In another step of the second exemplary method, a first hard mask material 171 is shown deposited into the recessed first metal material 61 .

[0083] Fig.40 It is shown that in another step of the second exemplary method, a plurality of second gaps 71 are formed by selectively removing the first spacers 21 and the second spacers 22. This may be referred to as spacer pulling.

[0084] Fig.41 In another step of the second exemplary method, a first dielectric material 81 is deposited into the second gap 71. In addition, a plurality of trenches 82 are formed in the first dielectric material 81 deposited into the second gap 71. For example, selective etching of the dielectric material 81 may form the one or more trenches 82.

[0085] Fig.42 It is shown that in another step of the second exemplary method, a filling material 201 is deposited into a plurality of trenches 82. Then further photolithographic patterning is performed. The photolithographic patterning may include applying a resist 101 on the surface of the intermediate integrated device, exposing one or more trenches 82 filled with the filling material 201 by forming a mask opening 42 in the resist 101.

[0086] Fig.43 It is shown that in another step of the second exemplary method, a first selective etching may be performed on the filling material 201 in the one or more exposed trenches 82 to remove the filling material 202 from these one or more trenches 82 .

[0087] Fig.44 It is shown that in another step of the second exemplary method, a second selective etch may be performed on the dielectric material 81 in the exposed one or more trenches 82 to extend the one or more trenches 82 through the dielectric material 81 and into the substrate 13. This may be referred to as a via etch of a second via.

[0088] Fig.45 It is shown that in a further step of the second exemplary method, the resist 101 is removed and a third dielectric material 451 is provided on the portion of the one or more trenches 82 filled with the filling material 201 .

[0089] Fig.46 In another step of the second exemplary method, the filling material 201 is shown to be removed. However, in the portion of the one or more trenches 82 covered with the filling material 201 of the third dielectric material 451, the filling material 201 is prevented from being removed and still remains after the third dielectric material 451 is removed.

[0090] Fig.47 It is shown that in another step of the second exemplary method, a second metal material 91 is deposited into the trench 82. The second metal material 91 is prevented from being deposited into the portion of the trench 82 where the filling material 201 remains. The second metal material 91 is deposited into the trench 82 extending into the substrate 13 to form a second via. Then, CMP may be performed.

[0091] Fig.48 It is shown that in a further step of the second exemplary method, the exposed second metal material 91 may be recessed in the direction of the substrate 13 .

[0092] Fig.49 In another step of the second exemplary method, a second hard mask material 291 is shown deposited into the recessed second metal material 91 .

[0093] All the above methods refer to Figures 1 to 9 , Figures 10 to 29 and Figures 30 to 49As described above, the materials of the first spacer 21 and the second spacer 22 are different from the materials of the third spacer 31 and the fourth spacer 33. The first spacer 21 and the second spacer 22 are made of the same material. The third spacer 31 and the fourth spacer 32 may also be made of the same material. The spacer 21, the spacer 22, the spacer 31, and the spacer 32 may be made of oxide (e.g., silicon oxide or titanium oxide) or nitride (e.g., silicon nitride) or silicon germanium or other suitable spacer materials, respectively.

[0094] All the above methods refer to Figures 1 to 9 , Figures 10 to 29 and Figures 30 to 49 The first metal material and the second metal material are different materials. For example, the first metal may include at least one of the following: ruthenium, copper, molybdenum, cobalt, and tungsten. For example, the second metal material may include at least one of the following: ruthenium, copper, molybdenum, cobalt, and tungsten.

[0095] All the above methods refer to Figures 1 to 9 , Figures 10 to 29 and Figures 30 to 49 As described, the substrate 13 includes at least one of the following: a MOL layer and a BEOL layer. In addition, the first dielectric material 81 may include silicon nitride and / or may include a dielectric for the MOL layer.

[0096] All the above methods refer to Figures 1 to 9 , Figures 10 to 29 and Figures 30 to 49 As described, the substrate 13 includes one or more integrated circuits; furthermore, the first structure 11 and / or the second structure 12 may be a power rail of at least one integrated circuit in the substrate 13 .

[0097] The invention has been described in conjunction with various embodiments as examples and in conjunction with implementations. However, from a study of the drawings, the invention and the independent claims, other variations will be understood and implemented by a person skilled in the art in implementing the claimed subject matter. In the claims and in the specification, the word "comprising" does not exclude other elements or steps, and the indefinite article "a" does not exclude a plurality. A single element or other unit may fulfil the functions of several entities or items described in the claims. The enumeration of certain measures in mutually different dependent claims does not indicate that a combination of these measures cannot be used in an advantageous implementation.

Claims

1. A metal integration method (10) for manufacturing an integrated device, characterized in that: The method (10) comprises: A first structure (11) and a second structure (12) are formed on a substrate (13) by a common layer, wherein the first structure (11) and the second metal structure (12) are separated from each other along a first direction (x) and each extends to a second direction (z); forming a first spacer (21) and a second spacer (22) on the substrate (13), wherein the first spacer (21) and the second spacer (22) each extend to the second direction (z), the first spacer (21) lines the first structure (11) on both sides of the first structure (11), and the second spacer (22) lines the second structure (12) on both sides of the second structure (12); forming a third spacer (31) and a fourth spacer (32) on the substrate (13), wherein the third spacer (31) and the fourth spacer (32) each extend to the second direction (z), the third spacer (31) lines the first spacer (21) on both sides of the first spacer (21), and the fourth spacer (32) lines the second spacer (22) on both sides of the second spacer (22); forming a fifth spacer (41) between the third spacer (31) and the fourth spacer (32); forming a plurality of first gaps (51) by selectively removing the third spacer (31), the fourth spacer (32), the first structure (11) and the second structure (12); depositing a first metal material (61) into the first gap (51); forming a plurality of second gaps (71) by selectively removing the first spacer (21) and the second spacer (22); depositing a first dielectric material (81) into the second gap (71); forming a plurality of grooves (82) in the first dielectric material (81) in the second gap (7); A second metallic material (91) is deposited into the trench (82).

2. The method (10) according to claim 1, characterized in that: After selectively removing the third spacer (31), the fourth spacer (32), the first structure (11) and the second structure (12), the method further includes: depositing a first filling material (311) into the first gap (51); removing the first filling material (311) to reopen the first gap (51); The first metal material (61) is deposited into the reopened first gap (51).

3. The method (10) according to claim 1 or 2, characterized in that: Before selectively removing the first spacer (21) and the second spacer (22), the method further includes: selectively forming one or more openings (121) in the third spacer (31), in the fourth spacer (32), or in the first filling material (311); extending the opening (121) into the substrate (13); Wherein depositing the first metal material (61) into the first gap (51) includes depositing the first metal material (61) into the opening (121) extending into the substrate (13) to form one or more first vias.

4. The method (10) according to any one of claims 1 to 3, characterized in that Before depositing the second metal material (91) into the groove (82), the method further comprises: extending one or more of the trenches (82) through the first dielectric material (81) and into the substrate (13); Depositing the second metal material (91) into the trench (82) includes depositing the second metal material (91) into the trench (82) extending into the substrate (13) to form one or more second vias.

5. The method (10) according to claim 3 or 4, characterized in that: The one or more openings (121) are formed in the third spacer (31), or in the fourth spacer (32), or in the first filling material (311) by: Photolithography patterning; Performing a first selective etching on the third spacer (31) or the fourth spacer (32) or the first filling material (311) to form the one or more openings (121); A second selective etching is performed on the substrate (13) to extend the one or more openings (121) into the substrate (13).

6. The method (10) according to any one of claims 2 to 5, characterized in that Before selectively removing the third spacer (31) or the fourth spacer (32), or before removing the first filling material (311), the method further includes: A protective layer (131) is used to cover a portion of the third spacer (31) or the fourth spacer (32) or the first filling material (311) to prevent the portion of the third spacer (31) or the fourth spacer (32) or the first filling material (311) from being removed.

7. The method (10) according to any one of claims 1 to 6, characterized in that Before selectively removing the first spacer (21) and the second spacer (22), the method further includes: recessing the first metal material (61) in the first gap (51); A first hard mask material (171) is deposited into the first gap (51) to cover the recessed first metal material (61).

8. The method (10) according to any one of claims 4 to 7, characterized in that The one or more grooves (82) extend into the substrate (13) by: depositing a second filling material (201) into the plurality of trenches (82); Photolithography patterning; performing a first selective etching on the second filling material (201) in the one or more trenches (82); performing a second selective etch on the dielectric material (81) to extend the one or more trenches (82) through the dielectric material (81) and into the substrate (13); The second filling material (201) is removed.

9. The method (10) according to any one of claims 1 to 8, characterized in that After depositing the second metal material (91) into the groove (82), the method further comprises: selectively removing a portion of the second metal material (91); A second dielectric material (271) is deposited at the location where the second metal material (91) was selectively removed.

10. The method (10) according to claim 9, characterized in that The selectively removing the portion of the second metal material (91) comprises: Photolithographic patterning to expose only the portion of the second metal material (91); Selective metal etching is performed on the exposed second metal material (91).

11. The method (10) according to any one of claims 1 to 8, characterized in that Before depositing the second metal material (91) into the groove (82), the method comprises: A third dielectric material (451) is formed in a portion of the trench (82) to prevent the second metal material (91) from being deposited into the portion of the trench (82).

12. The method (10) according to any one of claims 9 or 11, characterized in that Also includes: recessing the exposed second metal material (91); A second hard mask material (291) is deposited into the recessed second metal material (91).

13. The method (10) according to any one of claims 1 to 12, characterized in that: The material of the first spacer (21) and the second spacer (22) is different from the material of the third spacer (31) and the fourth spacer (32); and / or The first metal material (61) and the second metal material (91) are different materials.

14. The method (10) according to any one of claims 1 to 13, characterized in that: The first metal material (61) and / or the second metal material (91) includes at least one of the following: ruthenium, copper, molybdenum, cobalt and tungsten.

15. The method (10) according to any one of claims 1 to 14, characterized in that: The substrate (13) comprises at least one of the following: a middle of line (MOL) layer and a back end of line (BEOL) layer.

16. The method (10) according to any one of claims 1 to 15, characterized in that: The first dielectric material (81) includes silicon nitride and / or a dielectric for the MOL layer.

17. The method (10) according to any one of claims 1 to 16, characterized in that: The substrate (13) includes one or more integrated circuits; The first structure (11) and / or the second structure (12) is a power supply rail of at least one integrated circuit in the substrate (13).

18. An integrated device, characterized in that: It can be obtained by the method (10) according to any one of claims 1 to 17.

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