Differential current buffer circuit and direct current and alternating current source including same

Abstract

The differential current buffer circuit includes a differential input stage powered by a first positive supply voltage and a first negative supply voltage. The input stage has a first input circuit connected between first current paths of a first current mirror and a second current mirror connected between a second positive supply voltage and a second negative supply voltage. The second input circuit is connected between the first current paths of the third current mirror and the fourth current mirror, and the third current mirror and the fourth current mirror are connected between the second positive supply voltage and the second negative supply voltage. The second positive voltage is higher than the first positive supply voltage and the second negative voltage is lower than the first negative supply voltage. First and second output terminals of the differential current buffer circuit separate from between respective second current paths of the first and second current mirrors and respective second current paths of the third and fourth current mirrors, respectively.

Description

Technical Field

[0001] The present invention relates to a fully differential current source device for electrical stimulation of a patient, and more particularly to a broadband high voltage buffer circuit for DC and AC current sources for injecting current of a wide frequency range into a patient's tissue for electrical stimulation or electrical bioimpedance measurement. Background Art

[0002] Electrical bioimpedance measurements and electrical stimulation, which involve injecting or applying electrical current to patient tissue, have been used for many years to study and treat muscle and brain disorders, among other things. Using electrical current allows for precise control of the charge injected into the tissue, eliminating the effects of electrical resistance between the electrode and the tissue.

[0003] This current is applied over a wide range of frequencies, and the frequency, amplitude, and phase must be tightly controlled to obtain reproducible results under different circumstances, for example, the conductivity of a patient's skin and underlying tissues may vary from session to session or from patient to patient.

[0004] A widely used current source design for this purpose is the Howland current source, which is an operational amplifier with a specific feedback design. Figure 1a An example of a Howland current source is shown. The non-inverting input of the operational amplifier 10 is connected to the positive input of the Howland current source via a first resistor R1. The output signal of the operational amplifier 10 is fed back to the non-inverting input of the operational amplifier 10 via a second resistor R2. The non-inverting input of the operational amplifier 10 also forms the output node V of the Howland current source. X , load Z L The output signal of the operational amplifier 10 is also provided to the inverting input terminal of the operational amplifier 10 via the fourth resistor R4. The inverting input terminal of the operational amplifier 10 is also connected to the negative input terminal of the Howland current source via the third resistor R3. The feedback strength from the output terminal to the '+' and '-' input terminals is equal, that is, the ratios of R1 / R2 and R3 / R4 are equal.

[0005] If the "output" node V X (i.e. the '+' input of the op amp) is grounded, it is easy to see that the 'gain' is 1 / R1, i.e. as the input voltage changes, the output current is equal to 1 / R1. When the output is grounded, resistors R2, R3 and R4 have no effect and only the '+' input voltage is effective. When the '-' input moves up, the gain of the grounded output node is -R4 / R3 x 1 / R2. Since the ratio of the resistors is defined as R1 / R2 = R3 / R4, this gain is also equal to -1 / R1. Note that the gain at the '-' input is opposite. Therefore, it is easy to see that if Vin+ and Vin- move together, I outThere is no change, i.e. the common mode signal is rejected. When Vin+ rises, the "gain" of the output node is "1 / R1". The gain of the '-' input then follows to be "1 / R1" as well, but with a negative sign. Therefore, this current pump can accept either positive or negative inputs, i.e. it has a true differential input.

[0006] As shown below, the output impedance is high, making the gain correct for all output voltages and impedances, and for all inputs. It is easy to see that the output impedance is very high using the following analysis: If both signal inputs are grounded, and if the “output” node V X is driven high, then some source is driving resistor "R1". However, as the + input of the op amp is driven high, the - input must also go up, and the output also goes up, providing just enough current through R2 to cancel the current flowing through R1, making the output impedance very high indeed. The linear superposition principle states that no matter what Vin+ or Vin- is, no matter what Z L Whatever V out What is the current I? out Both will be (Vin+-Vin-)×1 / R1.

[0007] Detailed information on the Howland current source can be found at, for example, Texas Instruments TM The results of this study are found in Application Report AN-1515, entitled “A Comprehensive Study of the Howland Current Source,” SNOA474A-January 2008-Revised April 2013.

[0008] While the Howland current source has a limited range of applications and gain options, the enhanced or improved Howland current source provides greater gain options and higher output currents by using a differential amplifier to impose a voltage across the shunt resistor, Rs, resulting in a current source capable of driving a wide range of load resistances. Details are available at Texas Instruments TM The application report titled “Analysis of Improved Howland Current Pump Configurations” SBOA437–October 2020.

[0009] For electrical stimulation with multiple currents applied between multiple pairs of electrodes, Figure 1aA simple current source is not suitable and a fully differential design is required so that the current flows unambiguously between the desired electrode pair. Two anti-phase fed Howland current sources become a suitable solution, preferably using a quad feedback enhanced Howland current source with a fully differential op amp ( Figure 1b ).

[0010] The difficulty here is that commercially available fully differential op amps have limitations on the maximum voltage or current they can provide at the output or in the available bandwidth. In practice, this means that the available voltage swing over a wide frequency range is quite low, severely limiting the use of integrated op amps in applications where voltages below 35 volts are acceptable.

[0011] Although it is possible to construct an op amp using discrete parts with higher voltage ratings, this inevitably leads to reduced accuracy, in addition to high costs due to component discarding, especially due to the poor thermal coupling of the large number of transistors in practical designs. Summary of the invention

[0012] Therefore, it is desirable to design a differential current buffer with wide bandwidth, high accuracy, linearity, and high output impedance that can provide a high voltage output swing. It is also desirable to design a DC and AC current source that implements a differential current buffer circuit.

[0013] This object is achieved by a differential current buffer circuit according to claim 1 and a direct and alternating current source according to claim 8. Advantageous embodiments and developments are described in the dependent claims.

[0014] According to a first aspect of the present invention, a differential current buffer circuit includes a differential input stage powered by a first positive power supply voltage and a first negative power supply voltage. The differential input stage has a first input circuit, which is connected between a first current path of a first output current mirror and a first current path of a second output current mirror, the first output current mirror is connected to a second positive power supply voltage, and the second output current mirror is connected to a second negative power supply voltage. The differential input stage also has a second input circuit, which is connected between a first current path of a third output current mirror and a first current path of a fourth output current mirror, the third output current mirror is connected to a second positive power supply voltage, and the fourth output current mirror is connected to a second negative power supply voltage. With reference to a reference potential, such as a ground potential, the second positive power supply voltage is higher than the first positive power supply voltage, and the second negative power supply voltage is lower than the first negative power supply voltage. The first output terminal of the differential current buffer circuit is branched from the corresponding second current paths of the first output current mirror and the second output current mirror, and the second output terminal of the differential current buffer circuit is branched from the corresponding second current paths of the third output current mirror and the fourth output current mirror.

[0015] In one or more embodiments of the differential current buffer circuit, the first input circuit and the second input circuit each include two complementary current mirrors connected in series, and wherein the input node is located at a connection portion of the two complementary current mirrors.

[0016] In one or more embodiments of the differential current buffer circuit, the first input circuit and the second input circuit of the differential input stage are connected to a shared bias branch and form a differential translinear input unit, and the shared bias branch is connected between a first positive power supply voltage and a first negative power supply voltage. The translinear input unit may include two pairs of transistors, and the control electrodes of each pair of corresponding transistors are tied together and are also connected to an upper bias potential and a lower bias potential, respectively.

[0017] In one or more embodiments of the differential current buffer circuit, the input stage positive bias current and negative bias current are set by a single current source, which is coupled to the upstream and downstream of the first current paths of two current mirrors, the first bias current mirror is connected to the first positive power supply, and the second bias current mirror is connected to the first negative power supply voltage. The second current path of the bias current mirror provides the positive bias current and the negative bias current to the input stage. The series connection of the current mirror and the single current source facilitates setting the same bias current in the positive power supply and the negative power supply, and when a high-precision current mirror such as a Wilson current mirror is used, a very accurate bias current setting can be obtained.

[0018] In one or more embodiments of the differential current buffer circuit, the series-connected complementary current mirrors of the first input circuit and the second input circuit each include their own bias branch, i.e., each of the first input circuit and the second input circuit has a bias branch. Each bias branch is connected between a first positive power supply voltage and a first negative power supply voltage. The input node is located at the connection of the complementary current mirror in the corresponding bias branch. The output of the complementary current mirror is connected to the first current path of the associated output current mirror. The connection of the complementary current mirror in the output current path is tied to a reference potential (e.g., ground).

[0019] In one or more embodiments of the differential current buffer circuit, one or more of the first to fourth output current mirrors are cascode current mirrors, Wilson current mirrors, or modified Wilson current mirrors.

[0020] According to a second aspect of the invention, the DC and AC current sources include a differential operational amplifier connected in a Howland current source configuration, the differential outputs of which are connected to the inputs of the aforementioned differential current buffer circuit according to the first aspect of the invention. First feedback signals to the non-inverting and inverting inputs of the amplifier, respectively, are tapped from the load-side terminals of the corresponding output resistors of the differential current buffer circuit.

[0021] In one or more embodiments of the DC and AC current sources, the differential operational amplifier is connected in a quad feedback enhanced Howland current source configuration. Additional second feedback signals to the non-inverting and inverting inputs of the amplifier are tapped from the buffer side terminals of the respective opposite output resistors of the differential current buffer circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In the following, the present invention will be described with reference to the accompanying drawings, in which

[0023] Figure 1a shows a schematic circuit diagram of a known Howland current source,

[0024] Figure 1b shows a schematic circuit diagram of a known quad-feedback enhanced Howland current source,

[0025] Figure 2 shows a schematic circuit diagram of a translinear input unit,

[0026] FIG3 shows a circuit diagram of a first exemplary differential current buffer circuit according to the first aspect of the present invention,

[0027] Figure 4 1 shows a circuit diagram of a second exemplary differential current buffer circuit according to the first aspect of the present invention,

[0028] Figure 5 A circuit diagram of a DC and AC current source including the first exemplary differential current buffer circuit of FIG. 3 connected to an operational amplifier in a quad feedback enhanced Howland current source circuit configuration is shown, and

[0029] Figure 6 Shown include Figure 4 A circuit diagram of a second exemplary differential current buffer circuit of DC and AC current sources connected to operational amplifiers in a quad feedback enhanced Howland current source circuit configuration.

[0030] In the drawings, the same reference numbers may be used to refer to the same or similar elements. DETAILED DESCRIPTION

[0031] Figure 1a and Figure 1b This has been described in the background technology section and will not be repeated here.

[0032] Figure 21 shows a schematic circuit diagram of a translinear input unit 20. The bases of two pairs of transistors T1, T2 and T3, T4 are connected respectively and are also connected to corresponding bias potentials. The bias potential is provided by a bias branch of the translinear input unit. In this example, the bias branch includes two current sources, each of which provides a current I O , the two current sources are connected in series upstream and downstream of the two diodes D1 and D2 connected in the forward direction in series, respectively. Note that diode-connected transistors can also be used. The series connection is connected between a positive voltage V and a negative voltage -V. In order to provide a suitable center for the translinear input unit, the connection between the two diodes D1 and D2 is connected to a reference potential Z, such as ground.

[0033] The two pairs of transistors T1, T2 and T3, T4 are "stacked" on top of each other so that each "side" of the transistor pair is connected together, i.e. the emitters of transistors T1 and T3 are connected, and the emitters of transistors T2 and T4 are connected. A differential input signal is connected to input nodes X and Y, which are formed between the respective emitter connections. Depending on the input signal applied to the input nodes X, Y and another circuit connected thereto, output currents I1 to I4 flow through the collectors of transistors T1, T3 and T2, T4, respectively.

[0034] FIG. 3 shows a circuit diagram of a first exemplary differential current buffer circuit 100 according to the first aspect of the present invention. Figure 3a ) shows a bias power supply circuit 200, and Figure 3b ) shows the input stage 300 and the output stage of the differential current buffer circuit.

[0035] Figure 3a ) includes a first bias current mirror, whose first current path 210 is connected to a first positive power supply voltage +V1 and a first terminal of a current source 220. The bias power supply circuit 200 also includes a second bias current mirror, whose first current path 214 is connected between the second terminal of the current source 220 and the first negative power supply voltage -V1. It should be noted that throughout the specification, the first positive and negative power supply voltages and the second positive and negative power supply voltages are both referenced to a reference potential (e.g., ground) and are preferably symmetrical. The second current paths 212 and 216 of the first bias current mirror and the second bias current mirror respectively form bias current output terminals that provide power to the differential input stage 300. The bias power supply circuit 200 advantageously requires only one current source to set the bias current, and the bias current mirror only copies the set current to the positive and negative power supply lines.

[0036] Figure 3b ) shows a differential current buffer having a differential input stage 300, which is similar to the reference Figure 2 The translinear input unit 20. Figure 2 Unlike the translinear input unit of FIG. 1 , the emitters of transistors Q1, Q5 and Q3, Q4 are not directly connected, but are connected through two resistors R25, R30 and R27, R28 connected in series. Input nodes I1 and I2 are formed between two corresponding resistors. Power is provided to the differential input stage by a first positive power supply voltage +V1 and a first negative power supply voltage -V1. In the present differential input circuit, power is provided to the bias circuit by a bias power supply circuit 200. Figure 2 The diodes D1 and D2 of the bias branch of the circuit are replaced by diode-connected transistors Q2 and Q6, preferably of the same type as the transistors Q1, Q3 and Q4, Q5, respectively, and even more preferably from the same production batch. Furthermore, these diodes are not directly connected to each other, but are connected via two series resistors R26, R29, which provide emitter degeneration to supply the bias current I correspondingly set to the differential input stage in accordance with the transistor variation. O To stabilize the operating point of the input stage. The connection between the two resistors R26 and R29 is grounded as a reference potential. Transistors Q3 and Q4 together with emitter degeneration resistors R27 and R28 form a first input circuit, while transistors Q1 and Q5 together with emitter degeneration resistors R25 and R30 form a second input circuit.

[0037] The output end of the first input circuit is connected between the first current path 318 of the first output current mirror circuit and the first current path 322 of the second output current mirror circuit, the first output current mirror circuit is connected to the second positive power supply voltage +V2, and the second output current mirror circuit is connected to the second negative power supply voltage -V2.

[0038] The output end of the second input circuit is connected between the first current path 310 of the third output current mirror circuit and the first current path 314 of the fourth output current mirror circuit, the third output current mirror circuit is connected to the second positive power supply voltage +V2, and the fourth output current mirror circuit is connected to the second negative power supply voltage -V2.

[0039] The first output terminal O1 of the differential buffer circuit 100 is branched from between the corresponding second current paths 320, 324 of the first output current mirror and the second output current mirror, which are tied together and powered by the second positive power supply voltage +V2 and the second negative power supply voltage -V2 respectively.

[0040] The second output terminal O2 of the differential buffer circuit 100 is branched from the corresponding second current paths 312, 316 of the third output current mirror and the fourth output current mirror, which are tied together and powered by the second positive power supply voltage +V2 and the second negative power supply voltage -V2 respectively.

[0041] Each of the first input circuit and the second input circuit forms a series-connected complementary current mirror having a shared bias branch and whose respective output current is controlled by a current applied to a respective input node I1 or I2. The input current changes a respective current in each complementary current mirror connected to a first current path of an associated output current mirror. The current through the first current path of the output current mirror is matched in the respective second path of the output current mirror and is available at the corresponding output terminals O1 and O2, respectively.

[0042] Figure 4 FIG. 1 is a circuit diagram of a second exemplary differential current buffer circuit according to the first aspect of the present invention. The output stage of the differential current buffer circuit corresponds to the reference Figure 3b ) The input stage 300 has a different design. Here, the individual bias branches of each input circuit of the input stage 300 are directly powered by the first positive and negative power supply voltages +V1 and -V1, respectively.

[0043] The input node of the first input circuit including transistors Q2, Q3, Q4, Q6 and resistors R26, R27, R28, R29, R30, R31 is in the bias branch, more specifically, at the center point of the series connection of resistors R26 and R29 connecting diode-connected transistors Q2 and Q6. The "anode" of the diode-connected transistor Q2 is connected to the first positive power supply voltage +V1 through resistor R31, and the "cathode" of the diode-connected transistor Q6 is connected to the first negative power supply voltage -V1 through resistor R30. Resistors R26, R29, R30 and R31 will set the bias current in the bias branch of the first input circuit. The ratios of R31 / R26 and R30 / R29 will set the gain of the current buffer, and R30=R31 and R26=R27=R28=R29 are correct operations.

[0044] The output terminal of the first input circuit is connected between the first current path 318 of the first output current mirror circuit, which is connected to the second positive power supply voltage +V2, and the first current path 322 of the second output current mirror circuit, which is connected to the second negative power supply voltage -V2. The output terminals of the first input circuit are formed by the collectors of transistors Q3 and Q4, respectively, and the emitters of transistors Q3 and Q4 are connected to the reference potential (here, ground) through resistors R27 and R28, respectively.

[0045] The input node of the second input circuit including transistors Q1, Q5, Q17, Q20 and resistors R9, R10, R11, R14, R19, R25 is also in the bias branch, more specifically, at the center point of the series connection of resistors R10 and R19 connecting diode-connected transistors Q1 and Q20. The "anode" of the diode-connected transistor Q1 is connected to the first positive power supply voltage +V1 through resistor R9, and the "cathode" of the diode-connected transistor Q20 is connected to the first negative power supply voltage -V1 through resistor R25. Resistors R9, R10, R19 and R25 will set the bias current in the bias branch of the second input circuit. The ratios of R25 / R19 and R9 / R10 will set the gain of the current buffer, and R9=R25 and R10=R11=R14=R19 as correct operation.

[0046] The output terminal of the second input circuit is connected between the first current path 310 of the third output current mirror circuit, which is connected to the second positive power supply voltage +V2, and the first current path 314 of the fourth output current mirror circuit, which is connected to the second negative power supply voltage -V2. The output terminals of the second input circuit are formed by the collectors of transistors Q5 and Q17, respectively, and the emitters of transistors Q5 and Q17 are connected to the reference potential (here, ground) through resistors R11 and R14, respectively.

[0047] The first input circuit and the second input circuit each form a series-connected complementary current mirror, whose respective output current is controlled by a voltage applied to the respective input node I1 or I2. The input voltage changes the respective current through each complementary current mirror, which is connected to the first current path of the associated output current mirror. The current through the first current path of the output current mirror is replicated in the respective second path of the output current mirror and is available at the corresponding output terminals O1 and O2, respectively.

[0048] Similar to the differential buffer circuit 100 discussed with reference to FIG3 , the first output terminal O1 of the differential buffer circuit 100 is branched between the respective second current paths 320, 324 of the first output current mirror and the second output current mirror, which are tied together and powered by the second positive power supply voltage +V2 and the second negative power supply voltage −V2, respectively. The second output terminal O2 of the differential buffer circuit 100 is branched between the respective second current paths 312, 316 of the third output current mirror and the fourth output current mirror, which are tied together and powered by the second positive power supply voltage +V2 and the second negative power supply voltage −V2, respectively.

[0049] Figure 5 A circuit diagram of a DC and AC current source 400 including the first exemplary differential current buffer circuit 100 of FIG. 3 is shown, which is connected to a fully differential operational amplifier 10 in a quad feedback enhanced Howland current source circuit configuration. The differential current buffer circuit 100 includes Figure 3a ) shown in the bias power supply circuit 200 and Figure 3b ) as shown in the actual buffer circuit.

[0050] The first output terminal O1 of the differential current buffer circuit 100 is connected to a load (denoted as R3) via an output resistor R6 as a current sensing resistor. The second output terminal O2 of the differential current buffer circuit 100 is connected to the load via an output resistor R7 as a current sensing resistor.

[0051] The first negative feedback signal NF1 is divided between the load R3 and the load-side terminal of the output resistor R6. The first negative feedback signal NF1 is fed to the inverting input terminal of the operational amplifier 10 via the resistor R19. The first positive feedback signal PF1 is divided between the load R3 and the load-side terminal of the output resistor R7. The first positive feedback signal PF1 is fed to the non-inverting input terminal of the operational amplifier 10 via the resistor R14.

[0052] The second negative feedback signal NF2 is divided between the second output terminal O2 of the differential current buffer circuit 100 and the buffer side terminal of the output resistor R7. The second negative feedback signal NF2 is fed to the inverting input terminal of the operational amplifier 10 via a voltage divider including resistors R15 and R16, which is grounded. The second positive feedback signal PF2 is divided between the first output terminal O1 of the differential current buffer circuit 100 and the buffer side terminal of the output resistor R6. The second positive feedback signal PF2 is fed to the non-inverting input terminal of the operational amplifier 10 via a voltage divider including resistors R17 and R18 to the signal source SIG. The signal source SIG is referenced to the ground and, as a voltage source, represents the ground connection of the second positive feedback signal PF2.

[0053] The operational amplifier 10 may be powered from positive and negative supply voltages Vcc and Vee, respectively, which may be independent of the first supply voltages +V1 and -V1. A corresponding calibration voltage VCOM at the corresponding input of the operational amplifier 10 may be used to calibrate the common mode offset at the output.

[0054] For stability, resistors R10 and R11 may be required between the output of the operational amplifier 10 and the first input terminal I1 and the second input terminal I2 of the differential current buffer circuit 100, respectively. However, they may require a higher output swing of the operational amplifier 10 in order to generate the required input current for the input terminals I1 and I2 of the differential current buffer circuit 100. Appropriate selection of these resistors may be required for optimal step response, and minimal ringing or overshoot (i.e., resistors with low parasitic inductance) may be preferred.

[0055] Resistors R4 and R5 to ground provide a path to ground across load R3 and are effectively part of a voltage divider, allowing the output voltage to be monitored. However, resistors R4 and R5 also limit the maximum output impedance of current source 400 to the sum of the values ​​of resistors R4 and R5. The frequency response of the current source will be limited by the input capacitance of op amp 10, which is typically only a few pF.

[0056] As shown, closing the quad feedback loop around the entire circuit ensures that the output signal applied to the load has the lowest possible distortion.

[0057] Figure 6 Shown include Figure 4 1 is a circuit diagram of a second exemplary differential current buffer circuit 100 of DC and AC current sources 400 connected to operational amplifiers in a quad feedback enhanced Howland current source circuit configuration.

[0058] Similar to Figure 5 Feedback is applied to the entire circuit. R6 and R7 are current sensing resistors, and four feedback returns are made to the inputs of the fully differential op amp 10 driver stage. Again, applying feedback around the entire circuit ensures that distortion is as low as possible.

[0059] and Figure 5 Unlike the circuit shown in Figure 1, there are no resistors at the output of the op amp in this circuit because the differential buffer requires voltage drive. Any output common-mode offset voltage can be calibrated out using the VCOM input to op amp 10.

[0060] Resistors R4 and R5 are connected to ground, as Figure 5The circuit is identical to that of , providing a path to ground across load R3, which is actually part of a voltage divider, allowing the output voltage to be monitored. Likewise, resistors R4 and R5 also limit the maximum output impedance of the DC and AC current source 400 to the sum of the values ​​of resistors R4 and R5. The frequency response of the current source will be limited by the input capacitance of the op amp 10, which is typically only a few pF. The output DC offset is controlled using the VCOM input to the fully differential op amp 10.

[0061] For highest accuracy, the differential current buffer circuit 100 is preferably operated in Class A mode, which can be achieved by appropriately adjusting the corresponding bias currents.

[0062] In this circuit, the first positive and negative power supply voltages +V1 and −V1 of the differential current buffer circuit 100 are respectively the same as the power supply voltages Vcc and Vee for powering the operational amplifier 10 .

[0063] As shown in Figure 3 and Figure 4 As shown in , the output current mirror can be implemented as a cascode current mirror. A simple current mirror exhibits a dependence of the output current on the output voltage due to the finite output resistance of the transistor. A cascode current mirror can significantly reduce this dependence.

[0064] List of reference numerals (part of the specification)

[0065] 10 Operational Amplifier

[0066] 20 Translinear Input Unit

[0067] 100 Differential Current Buffer

[0068] 200 Bias power supply

[0069] 210 first current path of the first bias current mirror

[0070] 212 Second current path of the first bias current mirror

[0071] 214 First current path of the second bias current mirror

[0072] 216 second current path of the second bias current mirror

[0073] 300 differential input stage

[0074] 318 a first current path of the first output current mirror

[0075] 320 Second current path of the first output current mirror

[0076] 322 First current path of the second output current mirror

[0077] 324 A second current path of the second output current mirror

[0078] 310 A first current path of the third output current mirror

[0079] 312 A second current path of the third output current mirror

[0080] 314 The first current path of the fourth output current mirror

[0081] 316 The second current path of the fourth output current mirror

[0082] 400 AC current source

[0083] D1, D2 diodes

[0084] I1-I4 Output Current

[0085] I O Bias Current

[0086] I1 First input terminal

[0087] I2 Second input terminal

[0088] NF1 First negative feedback signal

[0089] NF2 Second negative feedback signal

[0090] O1 First output

[0091] O2 Second output

[0092] PF1 first positive feedback signal

[0093] PF2 Second positive feedback signal

[0094] Q1-Q36 Transistors

[0095] R1-R30 resistors

[0096] SIG Signal Source

[0097] T1-T4 transistor +V1 first positive power supply voltage

[0098] +V2 Second positive power supply voltage -V1 First negative power supply voltage -V2 Second negative power supply voltage Vcc Operational amplifier positive power supply voltage VCOM Common mode calibration Vee Operational amplifier negative power supply voltage V X Output nodes X, Y Input node Z Reference potential Z L load.

Claims

1. A differential current buffer circuit (100), comprising a differential input stage (300) powered by a first positive power supply voltage (+V1) and a first negative power supply voltage (-V1), wherein: The differential input stage (300) has a first input circuit and a second input circuit, wherein the output terminal of the first input circuit is connected between a first current path (318) of a first output current mirror connected to a second positive power supply voltage (+V2) and a first current path (322) of a second mirror connected to a second negative power supply voltage (-V2), and the output terminal of the second input circuit is connected between a first current path (310) of a third output current mirror connected to the second positive power supply voltage (+V2) and a first current path (314) of a fourth output current mirror connected to the second negative power supply voltage (-V2), wherein, with reference to the reference potential, the second positive power supply voltage (+V2) is higher than the first positive power supply voltage (+V1) and the second negative power supply voltage (-V2) is lower than the first negative power supply voltage (-V1), and wherein the first output terminal (O1) of the differential current buffer circuit (100) is branched from the corresponding second current paths (320, 324) of the first output current mirror and the second output current mirror, and wherein the second output terminal (O2) of the differential current buffer circuit (100) is branched from the corresponding second current paths (312, 316) of the third output current mirror and the fourth output current mirror.

2. The differential current buffer circuit (100) according to claim 1, wherein: The first input circuit and the second input circuit each include two complementary current mirrors connected in series, and wherein an input node (I1, I2) is located at a connection portion of the two complementary current mirrors.

3. The differential current buffer circuit (100) according to claim 2, wherein: The first input circuit and the second input circuit of the differential input stage (300) are connected to a shared bias branch and form a differential translinear input unit, wherein the bias branch is powered by the first positive power supply voltage (+V1) and the first negative power supply voltage (-V1).

4. The differential current buffer circuit (100) according to claim 3, wherein: A differential bias supply is connected to the first positive supply voltage (+V1) via a first bias current source and to the first negative supply voltage (-V1) via a second bias current source.

5. The differential current buffer circuit (100) according to claim 4, wherein: The first bias current source corresponds to a second current path (212) of a first bias current mirror and the second bias current source corresponds to a second current path (216) of a second bias current mirror, wherein an input stage bias (I0) is set by current sources (220) coupled upstream and downstream of the first current paths (210, 214) of the first bias current mirror and the second bias current mirror, respectively.

6. The differential current buffer circuit (100) according to claim 2, wherein: The series-connected complementary current mirrors of the first input circuit and the second input circuit each comprise their own bias branch, wherein each bias branch is connected between the first positive supply voltage (+V1) and the first negative supply voltage (-V1), wherein the input nodes (I1, I2) are located at the connection of the complementary current mirrors in the respective bias branches, wherein the outputs of the complementary current mirrors are connected to the first current paths (310, 314, 318, 322) of the associated output current mirrors, and wherein the connections of the complementary current mirrors in the output current paths are tied to a reference potential.

7. The differential current buffer circuit (100) according to any one of the preceding claims, wherein: One or more of the bias and / or output current mirrors is a cascode current mirror, a Wilson current mirror, or a modified Wilson current mirror using bipolar or field effect transistors.

8. A DC and AC current source (400) comprising a differential operational amplifier (10) connected in a differential Howland current source configuration, the differential output terminals of the differential operational amplifier being connected to corresponding input nodes (I1, I2) of a differential current buffer circuit (100) according to any one of the preceding claims, wherein First feedback signals (NF1, PF1) to the non-inverting input and inverting input of the amplifier, respectively, are separated from load-side terminals of corresponding output resistors (R6, R7) connected between the output terminals (O1, O2) of the differential current buffer circuit (100) and the load (R3), the load-side terminals representing the actual output terminals of the AC current source (400).

9. The direct and alternating current source (400) according to claim 8, wherein: The differential operational amplifier (10) is connected in a quad feedback enhanced Howland current source configuration, wherein additional second feedback signals (NF2, PF2) to the non-inverting input and inverting input of the operational amplifier (10), respectively, are tapped from buffer side terminals of corresponding relative output resistors (R6, R7).

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