Semiconductor structure for detecting metal bonding strength and testing method

Abstract

The invention provides a semiconductor structure for detecting metal bonding strength and a testing method. The semiconductor structure comprises a first substrate; the first dielectric layer is positioned on the first substrate; the two first metal bonding layers are positioned on the first dielectric layer; a second substrate; the second metal bonding layer is located on the first surface of the second substrate, and the first substrate and the second substrate are connected through the first metal bonding layer and the second metal bonding layer; a first test end and a second test end; the first metal interconnection structure and the second metal interconnection structure are located in the first dielectric layer, and the first test end and the second test end are electrically connected with the two first metal bonding layers through the first metal interconnection structure and the second metal interconnection structure respectively; a conductive layer; the conductive layer is electrically connected with the test end through the first metal interconnection structure or the second metal interconnection structure. According to the invention, the bonding degree of the first metal bonding layer and the second metal bonding layer can be monitored in real time in a rapid, accurate and lossless manner.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor structure and a testing method for detecting metal bonding strength. Background Art

[0002] Micro-Electro-Mechanical System (MEMS) is a typical system that integrates sensors, microactuators and microcircuits. It is widely used in many fields such as automobiles, aerospace, biomedicine, and military.

[0003] Metal bonding is a key step in the manufacturing process of MEMS devices. It is used to permanently encapsulate the silicon substrate and the cap layer together to form a sealed cavity structure. The degree of metal bonding directly affects the mechanical strength, airtightness and service life of MEMS devices. Therefore, establishing an efficient and accurate testing method is crucial to ensure the quality and performance of MEMS devices. Summary of the invention

[0004] A series of simplified concepts are introduced in the Summary of the Invention, which will be further described in detail in the Detailed Description of the Invention. The Summary of the Invention does not mean to attempt to define the key features and essential technical features of the claimed technical solution, nor does it mean to attempt to determine the scope of protection of the claimed technical solution.

[0005] In view of the existing problems, the present invention provides a semiconductor structure for detecting metal bonding strength, the semiconductor structure comprising:

[0006] first base;

[0007] A first dielectric layer located on the first substrate and two first metal bonding layers spaced apart from each other located on the first dielectric layer;

[0008] Second base;

[0009] a second metal bonding layer located on the first surface of the second substrate and arranged corresponding to the first metal bonding layer, wherein the first substrate and the second substrate are bonded via the first metal bonding layer and the second metal bonding layer;

[0010] a first test end and a second test end;

[0011] a first metal interconnect structure and a second metal interconnect structure located in the first dielectric layer, the first test end being electrically connected to one of the first metal bonding layers through the first metal interconnect structure, and the second test end being electrically connected to another of the first metal bonding layers through the second metal interconnect structure;

[0012] A conductive layer corresponding to the second substrate and disposed on the first dielectric layer; the conductive layer is electrically connected to the first test end or the second test end through the first metal interconnection structure or the second metal interconnection structure.

[0013] In some embodiments of the present application, a third substrate and a second dielectric layer are further included, and the second surface of the second substrate and the third substrate are bonded via the second dielectric layer.

[0014] In some embodiments of the present application, a first chamber is formed between the first substrate and the second substrate, a second chamber is formed between the third substrate and the second substrate, an opening is provided in the second substrate, and the first chamber and the second chamber are connected through the opening.

[0015] In some embodiments of the present application, the first metal bonding layer includes aluminum, and the second metal bonding layer includes germanium.

[0016] In some embodiments of the present application, the semiconductor structure is disposed in at least one exposure region of a wafer, and a MEMS device is also disposed in the exposure region.

[0017] In another aspect, the present invention further provides a method for testing metal bonding strength, the testing method comprising:

[0018] Providing a semiconductor structure for detecting metal bonding strength as described in any one of the above;

[0019] Performing a capacitance test on the semiconductor structure based on a first test terminal and a second test terminal in the semiconductor structure to obtain capacitance test data;

[0020] The bonding degree between the first metal bonding layer and the second metal bonding layer in the semiconductor structure is determined according to the capacitance test data.

[0021] In some embodiments of the present application, determining the bonding degree between the first metal bonding layer and the second metal bonding layer in the semiconductor structure according to the capacitance test data includes:

[0022] Calculating the actual bonding thickness between the first metal bonding layer and the second metal bonding layer according to the capacitance test data;

[0023] Calculating the mutual dissolution thickness of the first metal bonding layer and the second metal bonding layer according to the actual bonding thickness;

[0024] The bonding degree between the first metal bonding layer and the second metal bonding layer in the semiconductor structure is determined according to the mutual solution thickness.

[0025] In some embodiments of the present application, the actual bonding thickness is calculated based on the following formula:

[0026]

[0027] Among them, C is the capacitance test data, k is the dielectric constant of the semiconductor structure, ε0 is the dielectric constant of vacuum, A is the overlapping area between the mass block in the second substrate and the conductive layer in the first substrate in the semiconductor structure, and d0 is the actual bonding thickness.

[0028] In some embodiments of the present application, the mutual solution thickness is positively correlated with the original thickness of the second metal bonding layer.

[0029] In some embodiments of the present application, the mutual solubility thickness and the bonding degree are positively correlated.

[0030] The semiconductor structure and test method for detecting metal bonding strength of the present invention, the second substrate of the semiconductor structure and the conductive layer arranged on the first dielectric layer can constitute a capacitor structure, the semiconductor structure can be subjected to a capacitance test through the first test end and the second test end, and then the bonding degree of the first metal bonding layer and the second metal bonding layer in the semiconductor structure is determined according to the capacitance test data, the test efficiency is high, the test data is accurate, and no damage is caused to the semiconductor structure, the bonding degree of the first metal bonding layer and the second metal bonding layer is quantified, and the bonding degree of the first metal bonding layer and the second metal bonding layer can be quickly, accurately, and non-destructively monitored in real time. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The following drawings of the present invention are used to understand the present invention as part of the present invention. The embodiments of the present invention are shown in the drawings and the description thereof is used to explain the principle of the present invention.

[0032] In the attached figure:

[0033] Figure 1 A schematic cross-sectional view of a semiconductor structure showing the metal bonding strength according to a specific embodiment of the present invention.

[0034] Figure 2 A flow chart showing a method for testing metal bonding strength according to a specific embodiment of the present invention.

[0035] FIG. 3 shows a test effect diagram of a wafer according to a specific embodiment of the present invention. DETAILED DESCRIPTION

[0036] In the following description, a large number of specific details are provided to provide a more thorough understanding of the present invention. However, it is apparent to those skilled in the art that the present invention can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present invention, some technical features well known in the art are not described.

[0037] It should be understood that the present invention can be implemented in different forms and should not be construed as being limited to the embodiments presented herein. On the contrary, providing these embodiments will make the disclosure thorough and complete and fully convey the scope of the present invention to those skilled in the art. In the accompanying drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. The same reference numerals throughout represent the same elements.

[0038] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there may be no intervening elements or layers. It should be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below may be represented as a second element, component, region, layer or part.

[0039] Spatially relative terms such as "under," "below," "below," "under," "above," "above," etc., may be used herein for ease of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, then the elements or features described as "under other elements" or "under" or "under" will be oriented as "on" the other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0040] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present invention. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0041] In order to fully understand the present invention, detailed steps and structures will be presented in the following description to illustrate the technical solution proposed by the present invention. The preferred embodiments of the present invention are described in detail below, but in addition to these detailed descriptions, the present invention may also have other implementations.

[0042] Traditional metal bonding testing methods have many shortcomings, such as low test efficiency, inaccurate test data, and highly destructive test process.

[0043] Therefore, in view of the existence of the above-mentioned technical problems, the present invention proposes a semiconductor structure with metal bonding strength, the semiconductor structure comprising: a first substrate; a first dielectric layer located on the first substrate and two first metal bonding layers located on the first dielectric layer and spaced apart; a second substrate; a second metal bonding layer located on the first surface of the second substrate and corresponding to the first metal bonding layer, the first substrate and the second substrate are bonded through the first metal bonding layer and the second metal bonding layer; a first test terminal and a second test terminal; a first metal interconnection structure and a second metal interconnection structure located in the first dielectric layer, the first test terminal is electrically connected to one of the first metal bonding layers through the first metal interconnection structure, and the second test terminal is electrically connected to another of the first metal bonding layers through the second metal interconnection structure; a conductive layer corresponding to the second substrate and arranged on the first dielectric layer; the conductive layer is electrically connected to the first test terminal or the second test terminal through the first metal interconnection structure or the second metal interconnection structure.

[0044] According to the semiconductor structure with metal bonding strength of the present application, the second substrate of the semiconductor structure and the conductive layer arranged on the first dielectric layer can constitute a capacitor structure, and the capacitance test of the semiconductor structure can be performed through the first test end and the second test end, and then the bonding degree of the first metal bonding layer and the second metal bonding layer in the semiconductor structure is determined according to the capacitance test data. The test efficiency is high, the test data is accurate, and it will not cause damage to the semiconductor structure. It can realize fast, accurate, and non-destructive real-time monitoring of the bonding degree of the first metal bonding layer and the second metal bonding layer.

[0045] In order to fully understand the present invention, detailed steps and structures will be presented in the following description to illustrate the technical solution proposed by the present invention. The preferred embodiments of the present invention are described in detail below, but in addition to these detailed descriptions, the present invention may also have other implementations.

[0046] Embodiment 1

[0047] Reference below Figure 1 The semiconductor structure of metal bonding strength according to an embodiment of the present application is described. The semiconductor structure of metal bonding strength includes: a first substrate 111; a first dielectric layer 112 located on the first substrate 111 and two first metal bonding layers 113 located on the first dielectric layer 112 and spaced apart; a second substrate 121; a second metal bonding layer 122 located on a first surface of the second substrate 121 and corresponding to the first metal bonding layer 113, the first substrate 111 and the second substrate 121 being bonded via the first metal bonding layer 113 and the second metal bonding layer 122; a first test terminal 114 and a second test terminal 115; a first dielectric layer 112 located on the first dielectric layer 112 and a second metal bonding layer 122 located on the first surface of the second substrate 121 and corresponding to the first metal bonding layer 113; the first substrate 111 and the second substrate 121 are bonded via the first metal bonding layer 113 and the second metal bonding layer 122; a first test terminal 114 and a second test terminal 115; 12, the first metal interconnection structure 116 and the second metal interconnection structure 117, the first test end 114 is electrically connected to one of the first metal bonding layers 113 through the first metal interconnection structure 116, and the second test end 115 is electrically connected to the other first metal bonding layer 113 through the second metal interconnection structure 117; a conductive layer 118 corresponding to the second substrate 121 and arranged on the first dielectric layer 112, the conductive layer 118 is electrically connected to the first test end 114 or the second test end 115 through the first metal interconnection structure 116 or the second metal interconnection structure 117.

[0048] Specifically, the second substrate 121 of the semiconductor structure in this embodiment and the conductive layer 118 arranged on the first dielectric layer 112 can constitute a capacitor structure. The semiconductor structure is subjected to a capacitance test through the first test terminal 114 and the second test terminal 115, and then the bonding degree of the first metal bonding layer 113 and the second metal bonding layer 122 in the semiconductor structure can be determined according to the capacitance test data. The test efficiency is high, the test data is accurate, and no damage is caused to the semiconductor structure. The bonding degree of the first metal bonding layer 113 and the second metal bonding layer 122 is quantified, and the bonding degree of the first metal bonding layer 113 and the second metal bonding layer 122 can be quickly, accurately, and non-destructively monitored in real time.

[0049] In some embodiments, the first substrate 111 can be any suitable semiconductor substrate, such as a bulk silicon substrate, and it can also be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III / V compound semiconductors, including multilayer structures composed of these semiconductors, or silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), or it can also be double-sided polished silicon wafers (Double Side Polished Wafers, DSP), or it can be a ceramic substrate such as alumina, a quartz or glass substrate, etc.

[0050] In some embodiments, the second substrate 121 may have a first surface and a second surface opposite to each other, the first surface may be a lower surface of the second substrate 121 , and the second surface may be an upper surface of the second substrate 121 .

[0051] The second substrate 121 may include a device layer and a mass block disposed on the device layer, and the conductive layer 118 on the first dielectric layer 112 is disposed corresponding to the mass block in the device layer, so that a capacitor structure can be formed by the conductive layer 118 and the mass block disposed at intervals. Of course, in addition to arranging the mass block on the device layer, the mass block can also be replaced by other types of conductive structures to form a capacitor structure with the conductive layer 118 on the first dielectric layer 112, which is not limited thereto.

[0052] In some embodiments, the first metal bonding layer 113 may include aluminum (Al), and the second metal bonding layer 122 may include germanium (Ge). Of course, the first metal bonding layer 113 and the second metal bonding layer 122 may also include any other suitable metal, which is not limited.

[0053] In some embodiments, the first test end 114 and the second test end 115 can be located on the first dielectric layer 112 outside the first metal bonding layer 113, or can also be arranged on the second substrate 121, as long as it can be ensured that the capacitance test of the capacitance structure formed by the second substrate 121 and the conductive layer 118 can be performed through the first test end 114 and the second test end 115.

[0054] In some embodiments, the material of the first test end 114, the second test end 115, the first metal interconnect structure 116 and the second metal interconnect structure 117 can be selected from any suitable metal material, including but not limited to at least one of Ag, Au, Cu, Pd, Cr, Mo, Ti, Ta, Sn, W and Al.

[0055] In some embodiments, a contact hole is provided in the first dielectric layer 112 at a position corresponding to the first metal bonding layer 113 and the test terminal, and a metal material is filled in the contact hole to form a metal plug, and the first test terminal 114 and one of the first metal bonding layers 113 are respectively electrically connected to the first metal interconnection structure 116 through the corresponding metal plugs, and the second test terminal 115 and another first metal bonding layer 113 are respectively electrically connected to the second metal interconnection structure 117 through the corresponding metal plugs. The metal material filled in the contact hole can be any suitable metal material, including but not limited to at least one metal selected from Ag, Au, Cu, Pd, Cr, Mo, Ti, Ta, Sn, W and Al.

[0056] In some embodiments, the material of the first dielectric layer 112 may be silicon dioxide or any other suitable dielectric material, which is not limited.

[0057] In some embodiments, a third substrate 131 and a second dielectric layer 141 are further included, and the second surface of the device layer 121 and the third substrate 131 are bonded via the second dielectric layer 141 .

[0058] The third substrate may be any suitable semiconductor substrate, and reference may be made to the description of the first substrate 111 above. The material of the second dielectric layer 141 may be referenced to the description of the first dielectric layer 112 above, and is not limited thereto.

[0059] In some embodiments, Figure 1 As shown, a first cavity 123 is formed between the first substrate 111 and the second substrate 121 , a second cavity 132 is formed between the third substrate 131 and the second substrate 121 , an opening 124 is provided in the second substrate 121 , and the first cavity 123 and the second cavity 132 are connected through the opening 124 .

[0060] The chamber structure in the MEMS device can be simulated by the first chamber 123 and the second chamber 132. In the MEMS device, one chamber can be used for the sensor part, such as accommodating a structure sensitive to physical quantities such as pressure and acceleration. The other chamber can be used for the actuator part, such as providing space for actuators such as micromotors and micropumps.

[0061] In some embodiments, the semiconductor structure is disposed in at least one exposure region of the wafer, and a MEMS device is also disposed in the exposure region.

[0062] Specifically, the surface of the wafer can be divided into a grid of several rectangular areas of the same size according to the exposure area. The area in each grid is called a cell. There is an exposure area in each cell. The area of ​​the exposure area is slightly smaller than that of the cell. Each exposure is also called a "shot". There can be multiple device designs (dies) in one exposure area. Normally, the device designs set in each exposure area of ​​the wafer are MEMS devices. In this embodiment, in order to test the degree of metal bonding in the MEMS device, a semiconductor structure is set in at least one exposure area of ​​the wafer. For example, a semiconductor structure is set in one exposure area of ​​the wafer, or a semiconductor structure is set in multiple exposure areas of the wafer, or a semiconductor structure is set in each exposure area of ​​the wafer. By setting up a semiconductor structure, the actual MEMS device can be simulated using the semiconductor structure, and the capacitance test of the semiconductor structure is performed through the first test terminal 114 and the second test terminal 115. Then, according to the capacitance test data, the bonding degree of the first metal bonding layer 113 and the second metal bonding layer 122 in the semiconductor structure can be determined. The test efficiency is high, the test data is accurate, and no damage is caused to the semiconductor structure. The bonding degree of the first metal bonding layer 113 and the second metal bonding layer 122 is quantified, and the bonding degree of the first metal bonding layer 113 and the second metal bonding layer 122 can be quickly, accurately, and non-destructively monitored in real time to reflect the quality and performance of the MEMS device on the same wafer.

[0063] It should be noted that when a semiconductor structure is disposed in each exposure region of a wafer, the degree and uniformity of metal bonding in different exposure regions of the entire wafer can be detected.

[0064] like Figure 3A to Figure 3C As shown in the figure, the green circle area represents the wafer, each grid has an exposure area, and the red line represents the area where overflow occurs after the first metal bonding layer 113 and the second metal bonding layer 122 are bonded. It can be seen that Figure 3B , Figure 3A and Figure 3C The overflow area in is reduced successively, that is, Figure 3B , Figure 3A and Figure 3C The bonding degree and uniformity of the first metal bonding layer 113 and the second metal bonding layer 122 are improved.

[0065] Embodiment 2

[0066] According to yet another aspect of the present application, a method for testing metal bonding strength is provided.

[0067] For example, Figure 2 As shown, the testing method of metal bonding strength of the present invention comprises the following steps:

[0068] Step S21, providing the semiconductor structure for detecting metal bonding strength in the first embodiment;

[0069] Step S22, performing a capacitance test on the semiconductor structure based on the first test terminal 114 and the second test terminal 115 in the semiconductor structure to obtain capacitance test data;

[0070] Step S23 , determining the bonding degree between the first metal bonding layer 113 and the second metal bonding layer 122 in the semiconductor structure according to the capacitance test data.

[0071] According to the metal bonding strength testing method of the present application, a capacitance test is performed on a semiconductor structure used to detect the metal bonding strength through the first test terminal 114 and the second test terminal 115, and then the bonding degree of the first metal bonding layer 113 and the second metal bonding layer 122 in the semiconductor structure is determined according to the capacitance test data. The test efficiency is high, the test data is accurate, and no damage is caused to the semiconductor structure. The bonding degree of the first metal bonding layer 113 and the second metal bonding layer 122 is quantified, and the bonding degree of the first metal bonding layer 113 and the second metal bonding layer 122 can be quickly, accurately, and non-destructively monitored in real time.

[0072] In some embodiments, in step S22, the first test terminal 114 and the second test terminal 115 in the semiconductor structure may be connected to an electrical test instrument to test and obtain capacitance test data of the semiconductor structure. The capacitance test data includes a capacitance value C of the semiconductor structure.

[0073] In some embodiments, in step S23, determining the degree of bonding between the first metal bonding layer 113 and the second metal bonding layer 122 in the semiconductor structure according to the capacitance test data may include: calculating the actual bonding thickness of the first metal bonding layer 113 and the second metal bonding layer 122 according to the capacitance test data; calculating the mutual solubility thickness of the first metal bonding layer 113 and the second metal bonding layer 122 according to the actual bonding thickness; and determining the degree of bonding between the first metal bonding layer 113 and the second metal bonding layer 122 in the semiconductor structure according to the mutual solubility thickness.

[0074] After obtaining the capacitance test data, the actual bonding thickness between the first metal bonding layer 113 and the second metal bonding layer 122 may be calculated according to any suitable method. For example, the actual bonding thickness may be calculated based on the following capacitance formula:

[0075]

[0076] Among them, C is the capacitance test data of the semiconductor structure, k is the dielectric constant of the semiconductor structure, ε0 is the dielectric constant of vacuum, A is the overlapping area between the mass block in the second substrate 121 and the conductive layer 118 in the first substrate 111 in the semiconductor structure, and d0 is the actual bonding thickness between the first metal bonding layer 113 and the second metal bonding layer 122.

[0077] Substituting the measured capacitance test data C into the above formula, and knowing the dielectric constant k of the semiconductor structure, the dielectric constant ε0 of the vacuum, and the overlapping area A between the mass block in the second substrate 121 and the conductive layer 118 in the first substrate 111, the actual bonding thickness d0 between the first metal bonding layer 113 and the second metal bonding layer 122 can be calculated.

[0078] From a qualitative point of view, the mutual solution thickness is positively correlated with the original thickness of the second metal bonding layer 122. That is, the greater the original thickness of the second metal bonding layer 122, the greater the mutual solution thickness of the first metal bonding layer 113 and the second metal bonding layer 122.

[0079] From a qualitative perspective, after calculating the actual bonding thickness d0 between the first metal bonding layer 113 and the second metal bonding layer 122, the mutual solubility thickness between the first metal bonding layer 113 and the second metal bonding layer 122 can be calculated according to any suitable method. For example, the mutual solubility thickness can be calculated based on the following formula:

[0080] d0=d 第二金属键合层 -d 互溶 +d 台阶

[0081] Wherein, d0 is the actual bonding thickness between the first metal bonding layer 113 and the second metal bonding layer 122, d 第二金属键合层 is the original thickness of the second metal bonding layer 122 (for example, when the second metal bonding layer 122 is Ge metal, it can be the original thickness of Ge), d 互溶 is the mutual dissolution thickness of the first metal bonding layer 113 and the second metal bonding layer 122, d 台阶 It is the thickness of the standard step (ie, STD step) in the semiconductor structure.

[0082] Substitute the calculated actual bonding thickness d0 of the first metal bonding layer 113 and the second metal bonding layer 122 into the above formula, and the original thickness d of the second metal bonding layer 122 is known. 第二金属键合层 , STD step thickness d 台阶 , that is, the mutual dissolution thickness d of the first metal bonding layer 113 and the second metal bonding layer 122 can be calculated. 互溶 .

[0083] The mutual solubility thickness between the first metal bonding layer 113 and the second metal bonding layer 122 is positively correlated with the bonding degree between the first metal bonding layer 113 and the second metal bonding layer 122, that is, the greater the mutual solubility thickness between the first metal bonding layer 113 and the second metal bonding layer 122, the better the bonding degree between the first metal bonding layer 113 and the second metal bonding layer 122, and thus the better the mechanical strength, airtightness and service life of the MEMS device on the same wafer.

[0084] The present invention has been described by the above embodiments, but it should be understood that the above embodiments are only for the purpose of example and description, and are not intended to limit the present invention to the scope of the described embodiments. In addition, it can be understood by those skilled in the art that the present invention is not limited to the above embodiments, and more variations and modifications can be made according to the teachings of the present invention, and these variations and modifications all fall within the scope of the protection claimed by the present invention. The protection scope of the present invention is defined by the attached claims and their equivalents.

Claims

1. A semiconductor structure for detecting metal bonding strength, characterized in that: The semiconductor structure comprises: first base; A first dielectric layer located on the first substrate and two first metal bonding layers spaced apart from each other located on the first dielectric layer; Second base; a second metal bonding layer located on the first surface of the second substrate and arranged corresponding to the first metal bonding layer, wherein the first substrate and the second substrate are bonded via the first metal bonding layer and the second metal bonding layer; a first test end and a second test end; a first metal interconnect structure and a second metal interconnect structure located in the first dielectric layer, the first test end being electrically connected to one of the first metal bonding layers through the first metal interconnect structure, and the second test end being electrically connected to another of the first metal bonding layers through the second metal interconnect structure; A conductive layer corresponding to the second substrate and disposed on the first dielectric layer; the conductive layer is electrically connected to the first test end or the second test end through the first metal interconnection structure or the second metal interconnection structure.

2. The semiconductor structure according to claim 1, wherein: The third substrate and a second dielectric layer are also included, wherein the second surface of the second substrate and the third substrate are bonded via the second dielectric layer.

3. The semiconductor structure according to claim 2, wherein: A first cavity is formed between the first substrate and the second substrate, a second cavity is formed between the third substrate and the second substrate, an opening is provided in the second substrate, and the first cavity and the second cavity are communicated through the opening.

4. The semiconductor structure according to claim 1, wherein: The first metal bonding layer includes aluminum, and the second metal bonding layer includes germanium.

5. The semiconductor structure according to claim 1, wherein: The semiconductor structure is arranged in at least one exposure region of a wafer, and a MEMS device is also arranged in the exposure region.

6. A method for testing metal bonding strength, characterized in that: The test method includes: Providing a semiconductor structure for detecting metal bonding strength according to any one of claims 1 to 5; Performing a capacitance test on the semiconductor structure based on a first test end and a second test end in the semiconductor structure to obtain capacitance test data; The bonding degree between the first metal bonding layer and the second metal bonding layer in the semiconductor structure is determined according to the capacitance test data.

7. The testing method according to claim 6, characterized in that: Determining the bonding degree between the first metal bonding layer and the second metal bonding layer in the semiconductor structure according to the capacitance test data includes: Calculating the actual bonding thickness between the first metal bonding layer and the second metal bonding layer according to the capacitance test data; Calculating the mutual dissolution thickness of the first metal bonding layer and the second metal bonding layer according to the actual bonding thickness; The bonding degree between the first metal bonding layer and the second metal bonding layer in the semiconductor structure is determined according to the mutual solution thickness.

8. The testing method according to claim 7, characterized in that: The actual bond thickness is calculated based on the following formula: Among them, C is the capacitance test data, k is the dielectric constant of the semiconductor structure, ε0 is the dielectric constant of vacuum, A is the overlapping area between the mass block in the second substrate and the conductive layer in the first substrate in the semiconductor structure, and d0 is the actual bonding thickness.

9. The testing method according to claim 8, characterized in that: The mutual solution thickness is positively correlated with the original thickness of the second metal bonding layer.

10. The testing method according to claim 7, characterized in that: The mutual solubility thickness and the bonding degree are positively correlated.

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