Digital display interface output signal time sequence automatic detection method and test board

Abstract

The invention provides a digital display interface output signal time sequence automatic detection method and a test board. By automatically detecting establishment time and retention time of an output signal output by a digital display interface relative to a pixel clock, alignment of a horizontal synchronizing signal and a field synchronizing signal and deflection between RGB signals output in a display enabling period, detailed information of signals which do not meet requirements is printed, omission caused by manual inspection is avoided, and the accuracy of the detection result is improved. A time sequence modification strategy is provided for a back-end designer, so that the working efficiency of a verification engineer can be improved, complicated and repeated verification work is avoided, the back-end and verification period of the chip is shortened, and a digital display interface signal output by the GPU chip can be ensured to meet the VESA time sequence standard and be correctly sampled by a next-level chip.

Description

Technical Field

[0001] The present invention relates to the field of automated testing, and more specifically, to a method and a test bench for automatically detecting the timing of output signals of a digital display interface. Background Art

[0002] Chip design and verification is a time-consuming and complex process, and simulation plays a vital role in the entire design. Chip design requires pre-simulation and post-simulation. Pre-simulation is a simulation for the register transfer level, which mainly focuses on the correctness and feasibility of the logic circuit function. It does not consider circuit delays, and the signal transmission is ideal, and the simulation speed is fast. After the circuit layout design is completed, the parasitic parameters, interconnection delays and other parameters under different processes are back-labeled into the netlist. Post-simulation is a simulation of the netlist extracted at this time, which is mainly used to find timing problems caused by improper constraints. Since device delays and line delays are considered, the signal path transmission delays are uneven, and the simulation speed becomes very slow.

[0003] In the GPU chip design, the digital display interface of the display controller is output through the digital IO PAD. One digital display interface signal mainly includes pixel clock, horizontal synchronization signal (HSYNC), field synchronization signal (VSYNC), display enable signal (DE), red signal (RED[7:0]), green signal (GREEN[7:0]), blue signal (BLUE[7:0]), a total of 28 signals. When the digital display interface of the GPU chip is used by the next-level chip, the next-level chip has requirements for the setup time and hold time of the input signal. If the GPU chip does not detect the setup time and hold time of the digital display interface output signal, the setup time and hold time of the input signal of the next-level chip may not be met, resulting in failure to collect correct data. The VESA standard requires that the HSYNC signal and the VSYNC signal be aligned. If the HSYNC signal and the VSYNC signal are not aligned, some monitors on the market will appear to be offset to the left or right. At 1080P@60Hz resolution, the pixel clock is 148.5MHz, with a cycle of about 6.7ns. The pixel data may flip in each pixel clock cycle. Due to the different paths that different digital display interface signals take to the corresponding IO PAD, the device delay and line delay on different paths are also different. In addition, the time occupied by the setup time and the hold time, the transition time of the IO PAD, make a group of digital display interface signals pass through the digital IO PAD output path delay vary greatly. The pixel data remains unchanged for a short time in a single pixel clock cycle, resulting in a group of digital display interface signals cannot be correctly sampled by the lower-level chip at the same time. Therefore, it is necessary to detect the digital display interface IO timing output by the GPU chip in the post-chip simulation stage. If the test is performed after the chip is returned, additional test circuits and environments are required. If the timing is not met, equal length windings are required on the board-level circuit, which not only increases the complexity of the board-level circuit design, but also leads to a decrease in signal quality due to a large number of windings, and the production cost will also increase. Therefore, it is a better method to perform detection during chip post-simulation.

[0004] It takes 16.7ms to run one frame of a 1080P@60Hz image, and post-simulation takes a month. The iteration time is too long. Using data that can flip each display interface, it is also necessary to run several lines, but even a few lines have nearly 10,000 pixel data. Manual inspection of such a large amount of data is not only prone to errors, but also time-consuming and inefficient. In addition, the post-simulation iterations are frequent and the post-simulation waveforms are large, making the verification workload of verification engineers quite cumbersome. Summary of the invention

[0005] The present invention aims at the technical problems existing in the prior art and provides a method and a test bench for automatically detecting the timing of output signals of a digital display interface.

[0006] According to a first aspect of the present invention, there is provided a method for automatically detecting the timing of output signals of a digital display interface, comprising:

[0007] Step S1, before the display controller of the GPU chip is reset, setting a setup time threshold, a hold time threshold and a signal skew threshold;

[0008] Step S2, before the display controller is reset, the polarity of the horizontal synchronization signal and the field synchronization signal of the digital display interface is configured to enable automatic detection of the timing of the output signal of the digital display interface;

[0009] Step S3, the display controller is reset, and the automatic detection model starts to automatically detect each output signal of the digital display interface, and based on the setup time threshold and the hold time threshold, the setup time and the hold time of each output signal relative to the pixel clock are detected; based on the signal skew threshold, the alignment of the horizontal synchronization signal and the field synchronization signal of the digital display interface is detected, and during the display enable period, the skew between the RGB signals output by the digital display interface is detected;

[0010] Step S4, determining whether each output signal of the digital display interface meets the requirements according to the detection result of each output signal, and printing the information of the output signal that does not meet the requirements.

[0011] According to a second aspect of the present invention, a test bench for automatic detection of the timing of a digital display interface output signal of the present invention is provided, which is applied to the post-simulation stage of a GPU chip, and is characterized in that the test bench includes a plurality of automatic detection models, each of which is used to detect the timing of a corresponding digital display interface output signal in a GPU chip;

[0012] Each of the automatic detection models is used to detect the timing of the output signal of the corresponding digital display interface in the GPU chip, including:

[0013] Before the display controller is reset, the setup time threshold, hold time threshold, and signal skew threshold are set;

[0014] Before the display controller is reset, the polarity of the horizontal synchronization signal and the field synchronization signal is configured to enable automatic detection of the timing of the output signal of the digital display interface;

[0015] The display controller is reset, and the automatic detection model starts to automatically detect each output signal output by the digital display interface, and detects the setup time and the hold time of each output signal relative to the pixel clock based on the setup time threshold and the hold time threshold; detects the alignment of the horizontal synchronization signal and the field synchronization signal of the digital display interface based on the signal skew threshold, and detects the skew between the RGB signals output by the digital display interface during the display enable period;

[0016] Determine whether each output signal of the digital display interface meets the requirements according to the detection result of each output signal, and print the information of the output signal that does not meet the requirements.

[0017] The present invention provides a digital display interface output signal timing automatic detection method and test bench, which automatically detect the output signal timing of the digital display interface of a chip, print detailed timing information of signals that do not meet the requirements, and find out the maximum and minimum delay values. This method can not only avoid omissions in manual inspection, but also provide timing modification strategies for back-end designers, while improving test efficiency and reliability, reducing the number of iterations, shortening the verification cycle, and is simple to implement. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 A flow chart of a method for automatically detecting the timing of output signals of a digital display interface provided by the present invention;

[0019] Figure 2 This is a flow chart of automatically detecting the output signal of the digital display interface in the present invention;

[0020] Figure 3 A schematic diagram of the structure of a test bench for automatic detection of timing of output signals of a digital display interface provided by the present invention. DETAILED DESCRIPTION

[0021] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention. In addition, the technical features in the various embodiments or single embodiments provided by the present invention can be arbitrarily combined with each other to form a feasible technical solution. This combination is not subject to the constraints of the sequence of steps and / or the structural composition mode, but must be based on the ability of ordinary technicians in this field to achieve. When the combination of technical solutions is contradictory or cannot be achieved, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0022] Figure 1 A flow chart of a method for automatically detecting the timing of output signals of a digital display interface provided by the present invention is shown in FIG. Figure 1 As shown, the method includes:

[0023] Step S1, before the display controller is reset, setting a setup time threshold, a hold time threshold and a signal skew threshold.

[0024] It is understandable that the present invention mainly performs automatic detection of the timing of the output signal of each digital display interface in the GPU chip in the post-simulation stage, wherein the GPU chip includes multiple digital display interfaces, and uses an automatic detection model to automatically detect the timing of the output signal of one digital display interface.

[0025] Before the display controller of the GPU chip is reset, the setup time threshold (SETUP_LIMIT) and hold time threshold (HOLD_LIMIT) are configured and set according to the requirements of the next-level chip manual. The signal skew threshold (SKEW_LIMIT) requires the chip design engineer to set the corresponding threshold according to the design requirements.

[0026] Step S2, before resetting the display controller, configure the polarity of the horizontal synchronization signal and the field synchronization signal of the digital display interface to enable automatic detection of the timing of the output signal of the digital display interface.

[0027] Before the display controller is reset, the polarity of the line synchronization signal and the field synchronization signal of the digital display interface is configured according to the polarity of the line synchronization signal and the field synchronization signal of the display controller, and the polarity includes positive polarity and negative polarity. In the post-simulation stage, only the simulation related to the digital display interface needs to automatically detect the timing of the output signal, so the automatic detection model of the output signal timing of the digital display interface needs to be enabled separately.

[0028] Step S3, the display controller is reset, and the automatic detection model starts to automatically detect each output signal output by the digital display interface. Based on the setup time threshold and the hold time threshold, the setup time and the hold time of each output signal relative to the pixel clock are detected; based on the signal skew threshold, the alignment of the horizontal synchronization signal and the field synchronization signal of the digital display interface is detected, and during the display enable period, the skew between the RGB signals output by the digital display interface is detected.

[0029] Exemplarily, in step S3, based on the setup time threshold and the hold time threshold, detecting the setup time and the hold time of each output signal relative to the pixel clock includes:

[0030] The automatic detection model can obtain the setup time and hold time of each output signal of the digital display interface relative to the pixel clock;

[0031] The holding time of each output signal relative to the pixel clock is compared with the holding time threshold. If it is greater than the holding time threshold, the holding time of the output signal relative to the pixel clock does not meet the requirement; otherwise, it meets the requirement.

[0032] It can be understood that the output signals of each digital display interface include pixel clock, line synchronization signal (HSYNC), field synchronization signal (VSYNC), display enable signal (DE), red signal (RED[7:0]), green signal (GREEN[7:0]), blue signal (BLUE[7:0]), a total of 28 signals.

[0033] With the pixel clock as a reference, the setup time and hold time of the other 27 output signals relative to the pixel clock are detected. Specifically, if the setup time of any output signal relative to the pixel clock is less than or equal to the setup time threshold, the setup time of the output signal meets the requirement, otherwise, the setup time of the output signal does not meet the requirement. Similarly, if the hold time of any output signal relative to the pixel clock is less than or equal to the hold time threshold, the hold time of the output signal meets the requirement, otherwise, the hold time of the output signal does not meet the requirement.

[0034] Exemplarily, in step S3, detecting the alignment of a horizontal synchronization signal and a vertical synchronization signal of a digital display interface based on a signal skew threshold value includes:

[0035] If the polarity of the horizontal synchronization signal and the field synchronization signal of the digital display interface is positive, when the automatic detection model first detects the rising edge of the horizontal synchronization signal, flag_hv is set to 1, and when the rising edge of the field synchronization signal is detected, flag_hv is set to 0; when the automatic detection model first detects the rising edge of the field synchronization signal, flag_hv is set to 1, and when the rising edge of the horizontal synchronization signal is detected, flag_hv is set to 0, and the time when flag_hv is 1 is the delay phase difference time of the horizontal synchronization signal and the field synchronization signal;

[0036] When the delay phase difference between the horizontal synchronization signal and the vertical synchronization signal is greater than the signal skew threshold, the horizontal synchronization signal and the vertical synchronization signal are not aligned, otherwise, the horizontal synchronization signal and the vertical synchronization signal are aligned.

[0037] Similarly, if the polarity of the horizontal synchronization signal and the field synchronization signal of the digital display interface is negative, when the automatic detection model first detects the falling edge of the horizontal synchronization signal, flag_hv is set to 1, and when the falling edge of the field synchronization signal is detected, flag_hv is set to 0; when the automatic detection model first detects the falling edge of the field synchronization signal, flag_hv is set to 1, and when the falling edge of the horizontal synchronization signal is detected, flag_hv is set to 0, and the time when flag_hv is 1 is the delay phase difference time of the horizontal synchronization signal and the field synchronization signal;

[0038] When the delay phase difference between the horizontal synchronization signal and the vertical synchronization signal is greater than the signal skew threshold, the horizontal synchronization signal and the vertical synchronization signal are not aligned, otherwise, the horizontal synchronization signal and the vertical synchronization signal are aligned.

[0039] The maximum and minimum values ​​of the delay phase difference between the horizontal synchronization signal and the vertical synchronization signal within the detection period are recorded.

[0040] It is understandable that the line synchronization signal (HSYNC signal) and field synchronization signal (VSYNC signal) output by each digital display interface need to be aligned. Specifically, the influence of the polarity of the line field signal (the abbreviation of the line synchronization signal and the field synchronization signal) needs to be considered. When the polarity of the line field signal is positive, if the automatic detection model first detects the rising edge of the HSYNC signal, flag_hv is set to 1, and when the rising edge of the VSYNC signal is detected, flag_hv is set to 0. If the automatic detection model first detects the rising edge of the VSYNC signal, flag_hv is set to 1, and when the rising edge of the HSYNC signal is detected, flag_hv is set to 0. The time when flag_hv is 1 is the delay difference time between the HSYNC signal and the VSNC signal. When this delay difference time is greater than the signal skew threshold SKEW_LIMIT, a violation information is reported.

[0041] It can automatically detect the delay difference between the HSYNC signal and the VSNC signal within a period of time, find out the maximum and minimum values ​​of the delay difference, and provide it to the back-end designer for timing modification.

[0042] When the polarity of the line field signal is negative, the detection process is the same as when the polarity of the line field signal is positive, except that the falling edges of the HSYNC signal and the VSYNC signal are detected instead.

[0043] Figure 2 The flowchart of skew detection of the RGB signal of each pixel output by each digital display interface is as follows:

[0044] In the step S3, during the display enabling period, the skew between the RGB signals output by the digital display interface is detected based on the signal skew threshold, including:

[0045] Compare the RGB signal output by the current pixel with the pre-stored RGB pixel data, obtain the skew value between the RGB signals of the current pixel according to the comparison result, and determine whether the RGB signal of the current pixel meets the requirements according to the magnitude relationship between the skew value between the RGB signals of the current pixel and the signal skew threshold. If the requirements are met, wait for the RGB signal output by the next pixel to be detected;

[0046] If the current pixel RGB signal does not meet the requirements, the red pixel data, green pixel data and blue pixel data in the RGB signal output by the current pixel are compared with the pre-stored red pixel data, green pixel data and blue pixel data respectively, and the skew values ​​between the red pixel data, the skew values ​​between the green pixel data and the skew values ​​between the blue pixel data are obtained respectively according to the comparison results, and according to the size relationship between the skew values ​​between the red pixel data, the skew values ​​between the green pixel data and the skew values ​​between the blue pixel data and the corresponding signal skew threshold values, it is determined whether the red pixel data, the green pixel data and the blue pixel data meet the requirements respectively;

[0047] If the red pixel data, green pixel data or blue pixel data meets the requirements, then wait until the RGB signal output by the next pixel is detected; if the red pixel data, green pixel data or blue pixel data does not meet the requirements, then detect multiple red signals, multiple green signals or multiple blue signals of the red pixel data, green pixel data or blue pixel data that does not meet the requirements.

[0048] Before detecting the RGB signal, an array rgb_group is defined in the automatic detection model. The size of the array is determined by the maximum value of the number of pixels to be checked, and the initialized pre-stored pixel data is stored in the array rgb_group.

[0049] It should be noted that each digital display interface outputs RGB signals of multiple pixels, and each RGB signal includes three-color signals, namely red (R), green (G) and blue (B). The three-color signals in the RGB signal are hereinafter referred to as red pixel data, green pixel data and blue pixel data.

[0050] First, the skew value of the RGB signal output by the digital display interface is detected. Specifically, the RGB signal output by the current pixel is compared with the pre-stored RGB pixel data. If the RGB signal output by the current pixel is different from the pre-stored RGB pixel data, flag_rgb is set to 1. If the RGB signal output by the current pixel is the same as the pre-stored RGB pixel data, flag_rgb is set to 0. The time when flag_rgb is 1 is the skew value between the RGB signals of the current pixel.

[0051] If the skew value is less than or equal to the signal skew threshold, it is determined that the current pixel RGB signal meets the requirements. If the skew value is greater than the signal skew threshold, it is determined that the current pixel RGB signal does not meet the requirements, and the RGB signal that does not meet the requirements and the current skew value are printed.

[0052] If the skew value detection of the current pixel RGB signal as a whole meets the requirements, it means that the skew values ​​of the red pixel data, green pixel data and blue pixel data in the RGB signal all meet the requirements, and the RGB signal output by the next pixel is waiting to be detected. If the skew value of the RGB signal output by the current pixel does not meet the requirements, it means that the skew of the red pixel data, green pixel data and / or blue pixel data in the RGB signal may not meet the requirements. At this time, the red pixel data, green pixel data and blue pixel data in the RGB signal need to be detected separately.

[0053] The red pixel data, the green pixel data, and the blue pixel data in the RGB signal are detected, including:

[0054] If the red pixel data, green pixel data, or blue pixel data in the current pixel RGB signal is different from the pre-stored red pixel data, pre-stored green pixel data, or pre-stored blue pixel data, then flag_r, flag_g, or flag_b is set to 1; if the red pixel data, green pixel data, or blue pixel data in the current pixel RGB signal is the same as the pre-stored red pixel data, pre-stored green pixel data, or pre-stored blue pixel data, then flag_r, flag_g, or flag_b is set to 0, and the time when flag_r, flag_g, or flag_b is 1 is the skew value of the red pixel data, the skew value of the green pixel data, or the skew value of the blue pixel data, respectively;

[0055] If the skew value of the red pixel data, the skew value of the green pixel data or the skew value of the blue pixel data is less than or equal to the corresponding signal skew threshold, the red pixel data, the green pixel data or the blue pixel data meets the requirement and waits for the RGB signal output by the next pixel to be detected;

[0056] If the skew value of the red pixel data, the skew value of the green pixel data or the skew value of the blue pixel data is greater than the corresponding signal skew threshold, the red pixel data, the green pixel data or the blue pixel data does not meet the requirements, and the pixel data that does not meet the requirements and the current skew value are printed.

[0057] It is understandable that if the skew value of the RGB signal does not meet the requirements, the red pixel data, green pixel data and blue pixel data in the RGB signal are detected respectively. Taking the red pixel data as an example, for example, if it is detected that the skew value of the red pixel data meets the requirements, the detection of the RGB signal output by the next pixel is waited. If it is detected that the skew value of the red pixel data does not meet the requirements, since the red pixel data includes 8 red signals, at this time, it is necessary to continue to detect the 8 red signals in the red pixel data until a red signal that does not meet the requirements is found.

[0058] The process of detecting the skew values ​​of the green pixel data and the blue pixel data in the RGB signal is the same as the process of detecting the skew value of the red pixel data, and will not be repeated here.

[0059] Exemplarily, the red signal, the green signal or the blue signal all have 8, and the skew value of a red signal, a green signal or a blue signal is detected, including:

[0060] If a red signal, a green signal or a blue signal of the red pixel data, the green pixel data or the blue pixel data is different from the pre-stored red signal, the pre-stored green signal or the pre-stored blue signal, then flag_rm or flag_gm or flag_bm is set to 1, where m is the index of the red signal, the green signal or the blue signal; if the red signal, the green signal or the blue signal of the red pixel data, the green pixel data or the blue pixel data is the same as the pre-stored red signal, the pre-stored green signal or the pre-stored blue signal, then flag_rm or flag_gm or flag_bm is set to 0, and the time when flag_rm or flag_gm or flag_bm is 1 is the skew value of the red signal, the green signal or the blue signal;

[0061] If the skew value of any red signal, any green signal or any blue signal is less than or equal to the corresponding signal skew threshold, the red signal, the green signal or the blue signal meets the requirement and waits for detection of the RGB signal output by the next pixel;

[0062] If the skew value of any red signal, any green signal or any blue signal is greater than the corresponding signal skew threshold, the red signal, the green signal or the blue signal does not meet the requirements, and the signal that does not meet the requirements and the current skew value are printed.

[0063] Step S4, determining whether each output signal of the digital display interface meets the requirements according to the detection result of each output signal, and printing the information of the output signal that does not meet the requirements.

[0064] The above step S3 introduces the detection of the setup time and hold time of each output signal of the digital display interface relative to the pixel clock, the alignment of the line synchronization signal and the field synchronization signal, and the skew value of the RGB signal. When it is detected that one or more output signals output by the digital display interface do not meet the requirements, the output signal that does not meet the requirements is located, and the output signal that does not meet the requirements and the items that do not meet the requirements are output, such as the setup time and hold time of the output signal do not meet the requirements, or the line synchronization signal and the field synchronization signal are not aligned, or the skew value of the RGB signal does not meet the requirements, including whether the red pixel data, the green pixel data, or the blue pixel data does not meet the requirements, and which red signal, green signal, or blue signal does not meet the requirements.

[0065] At this point, the detection of the output signal timing of a digital display interface in the GPU chip has been completed.

[0066] See also Figure 3 , a test bench for automatic detection of the timing of digital display interface output signals is provided, the test bench comprising a plurality of automatic detection models, each of which is used to detect the timing of the corresponding digital display interface output signal in the GPU chip in the post-simulation stage;

[0067] Each of the automatic detection models is used to detect the timing of the output signal of the corresponding digital display interface in the GPU chip, including:

[0068] Before the display controller is reset, the setup time threshold, hold time threshold, and signal skew threshold are set;

[0069] Before the display controller is reset, the polarity of the horizontal synchronization signal and the field synchronization signal is configured to enable automatic timing check of the output signal of the digital display interface;

[0070] The display controller is reset, and the automatic detection model starts to automatically detect each output signal of the digital display interface, and detects the setup time and hold time of each output signal relative to the pixel clock based on the setup time threshold and the hold time threshold; detects the alignment of the horizontal synchronization signal and the field synchronization signal of the digital display interface based on the signal skew threshold, and detects the skew between the RGB signals output by the digital display interface during the display enable period;

[0071] Determine whether each output signal of the digital display interface meets the requirements according to the detection result of each output signal, and print the information of the output signal that does not meet the requirements.

[0072] Understandably, see Figure 3The GPU chip includes a display controller, which controls the display of n digital display interfaces. One digital display interface corresponds to an automatic detection model of the test bench, and one automatic detection model detects the output signal timing of one digital display interface. The specific detection method can refer to the technical features of the above-mentioned digital display interface output signal timing automatic detection method, which will not be repeated here.

[0073] The present invention provides a method and a test bench for automatically detecting the timing of a digital display interface output signal. In a post-simulation stage, the method automatically detects the setup time and hold time of the output signal output by the digital display interface relative to the pixel clock, the alignment of the line synchronization signal and the field synchronization signal, and the skew of the RGB signal output during the display enable period, prints detailed information of the signal that does not meet the requirements, and finds the maximum and minimum delay values. This can avoid making equal lengths in the chip back-end design, and avoiding the situation where the timing is not met after the film is returned due to insufficient post-simulation verification. The automatic detection model reduces a large amount of repetitive work, greatly improves the work efficiency of verification engineers, ensures the correctness and reliability of the design, and ensures that the digital display interface signal output by the GPU chip meets the VESA standard and can be correctly sampled by the next-level chip.

[0074] It should be noted that in the above embodiments, the description of each embodiment has its own emphasis, and for parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0075] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0076] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded computer, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0077] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0078] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0079] Although the preferred embodiments of the present invention have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0080] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A method for automatically detecting the timing of output signals of a digital display interface, applied to the post-simulation stage of a GPU chip, characterized in that: include: Step S1, before the display controller of the GPU chip is reset, setting a setup time threshold, a hold time threshold and a signal skew threshold; Step S2, before the display controller is reset, the polarity of the horizontal synchronization signal and the field synchronization signal of the digital display interface is configured to enable automatic detection of the timing of the output signal of the digital display interface; Step S3, the display controller is reset, and the automatic detection model starts to automatically detect each output signal of the digital display interface, and based on the setup time threshold and the hold time threshold, the setup time and the hold time of each output signal relative to the pixel clock are detected; based on the signal skew threshold, the alignment of the horizontal synchronization signal and the field synchronization signal of the digital display interface is detected, and during the display enable period, the skew between the RGB signals output by the digital display interface is detected; Step S4, determining whether each output signal of the digital display interface meets the requirements according to the detection result of each output signal, and printing the information of the output signal that does not meet the requirements.

2. The method for automatically detecting the timing of output signals of a digital display interface according to claim 1, characterized in that: The step S2, before resetting the display controller, configures the polarity of the horizontal synchronization signal and the vertical synchronization signal of the digital display interface, including: The polarities of the horizontal synchronization signal and the field synchronization signal of the digital display interface are configured according to the polarities of the horizontal synchronization signal and the field synchronization signal of the display controller, wherein the polarities include positive polarity and negative polarity.

3. The method for automatically detecting the timing of output signals of a digital display interface according to claim 1, characterized in that: In the step S3, based on the setup time threshold and the hold time threshold, the setup time and the hold time of each output signal relative to the pixel clock are detected, including: The automatic detection model obtains the setup time and hold time of each output signal of the digital display interface relative to the pixel clock; The holding time of each output signal relative to the pixel clock is compared with the holding time threshold. If it is greater than the holding time threshold, the holding time of the output signal relative to the pixel clock does not meet the requirement; otherwise, it meets the requirement.

4. The method for automatically detecting the timing of output signals of a digital display interface according to claim 2, characterized in that: In the step S3, based on the signal skew threshold, the alignment of the horizontal synchronization signal and the field synchronization signal of the digital display interface is detected, including: If the polarity of the horizontal synchronization signal and the field synchronization signal of the digital display interface is positive, when the automatic detection model first detects the rising edge of the horizontal synchronization signal, flag_hv is set to 1, and when the rising edge of the field synchronization signal is detected, flag_hv is set to 0; when the automatic detection model first detects the rising edge of the field synchronization signal, flag_hv is set to 1, and when the rising edge of the horizontal synchronization signal is detected, flag_hv is set to 0, and the time when flag_hv is 1 is the delay phase difference time of the horizontal synchronization signal and the field synchronization signal; When the delay phase difference between the horizontal synchronization signal and the vertical synchronization signal is greater than the signal skew threshold, the horizontal synchronization signal and the vertical synchronization signal are not aligned, otherwise, the horizontal synchronization signal and the vertical synchronization signal are aligned; Record the maximum and minimum values ​​of the delay phase difference between the horizontal synchronization signal and the vertical synchronization signal within the detection period; or, If the polarity of the horizontal synchronization signal and the field synchronization signal of the digital display interface is negative, when the automatic detection model first detects the falling edge of the horizontal synchronization signal, flag_hv is set to 1, and when the falling edge of the field synchronization signal is detected, flag_hv is set to 0; when the automatic detection model first detects the falling edge of the field synchronization signal, flag_hv is set to 1, and when the falling edge of the horizontal synchronization signal is detected, flag_hv is set to 0, and the time when flag_hv is 1 is the delay phase difference time of the horizontal synchronization signal and the field synchronization signal; When the delay phase difference between the horizontal synchronization signal and the vertical synchronization signal is greater than the signal skew threshold, the horizontal synchronization signal and the vertical synchronization signal are not aligned, otherwise, the horizontal synchronization signal and the vertical synchronization signal are aligned; The maximum and minimum values ​​of the delay phase difference between the horizontal synchronization signal and the vertical synchronization signal within the detection period are recorded.

5. The method for automatically detecting the timing of output signals of a digital display interface according to claim 1, characterized in that: In the step S3, during the display enabling period, the skew between the RGB signals output by the digital display interface is detected based on the signal skew threshold, including: Compare the RGB signal output by the current pixel with the pre-stored RGB pixel data, obtain the skew value between the RGB signals of the current pixel according to the comparison result, and determine whether the RGB signal of the current pixel meets the requirements according to the magnitude relationship between the skew value between the RGB signals of the current pixel and the signal skew threshold. If the requirements are met, wait for the RGB signal output by the next pixel to be detected; If the current pixel RGB signal does not meet the requirements, the red pixel data, green pixel data and blue pixel data in the RGB signal output by the current pixel are compared with the pre-stored red pixel data, green pixel data and blue pixel data respectively, and the skew value between the red pixel data, the skew value between the green pixel data and the skew value between the blue pixel data are obtained according to the comparison results, and according to the size relationship between the skew value between the red pixel data, the skew value between the green pixel data and the skew value between the blue pixel data and the signal skew threshold, it is determined whether the red pixel data, the green pixel data and the blue pixel data meet the requirements respectively; If the red pixel data, green pixel data or blue pixel data meets the requirements, wait for the RGB signal output by the next pixel to be detected; if the red pixel data, green pixel data or blue pixel data does not meet the requirements, detect multiple red signals, multiple green signals or multiple blue signals of the red pixel data, green pixel data or blue pixel data that does not meet the requirements.

6. The method for automatically detecting the timing of output signals of a digital display interface according to claim 5, characterized in that: Before the step S3 detects the skew between the RGB signals output by the digital display interface, the step S3 includes: An array rgb_group is defined in the automatic detection model. The size of the array is determined by the maximum number of pixels to be checked, and the initialized pre-stored pixel data is saved in the array rgb_group.

7. The method for automatically detecting the timing of output signals of a digital display interface according to claim 5, characterized in that: The RGB signal output by the current pixel is compared with the pre-stored RGB pixel data, a skew value between the RGB signals of the current pixel is obtained according to the comparison result, and whether the RGB signal of the current pixel meets the requirement is determined according to the magnitude relationship between the skew value between the RGB signals of the current pixel and the signal skew threshold, including: Compare the RGB signal output by the current pixel with the pre-stored RGB pixel data. If the RGB signal output by the current pixel is different from the pre-stored RGB pixel data, set flag_rgb to 1. If the RGB signal output by the current pixel is the same as the pre-stored RGB pixel data, set flag_rgb to 0. The time when flag_rgb is 1 is the skew value between the RGB signals of the current pixel. If the skew value is less than or equal to the signal skew threshold, it is determined that the current pixel RGB signal meets the requirements. If the skew value is greater than the signal skew threshold, it is determined that the current pixel RGB signal does not meet the requirements, and the RGB signal that does not meet the requirements and the current skew value are printed.

8. The method for automatically detecting the timing of output signals of a digital display interface according to claim 5, characterized in that: The determining whether the red pixel data, the green pixel data, and the blue pixel data meet the requirements includes: If the red pixel data, green pixel data, or blue pixel data in the current pixel RGB signal is different from the pre-stored red pixel data, pre-stored green pixel data, or pre-stored blue pixel data, then flag_r, flag_g, or flag_b is set to 1; if the red pixel data, green pixel data, or blue pixel data in the current pixel RGB signal is the same as the pre-stored red pixel data, pre-stored green pixel data, or pre-stored blue pixel data, then flag_r, flag_g, or flag_b is set to 0, and the time when flag_r, flag_g, or flag_b is 1 is the skew value of the red pixel data, the skew value of the green pixel data, or the skew value of the blue pixel data, respectively; If the skew value of the red pixel data, the skew value of the green pixel data or the skew value of the blue pixel data is less than the signal skew threshold, the red pixel data, the green pixel data or the blue pixel data meets the requirement, and the RGB signal output by the next pixel is waited for detection; If the skew value of the red pixel data, the skew value of the green pixel data or the skew value of the blue pixel data is greater than the signal skew threshold, the red pixel data, the green pixel data or the blue pixel data does not meet the requirements, and the pixel data that does not meet the requirements and the current skew value are printed.

9. The method for automatically detecting the timing of output signals of a digital display interface according to claim 5, characterized in that: The detecting of multiple red signals, multiple green signals or multiple blue signals of red pixel data, green pixel data or blue pixel data that do not meet the requirements includes: If any red signal, any green signal or any blue signal of the red pixel data, green pixel data or blue pixel data is different from the pre-stored red signal, pre-stored green signal or pre-stored blue signal, flag_rm or flag_gm or flag_bm is set to 1, where m represents the index of the red signal, green signal or blue signal; if any red signal, any green signal or any blue signal of the red pixel data, green pixel data or blue pixel data is the same as the pre-stored red signal, pre-stored green signal or pre-stored blue signal, flag_rm or flag_gm or flag_bm is set to 0, and the time when flag_rm or flag_gm or flag_bm is 1 is the skew value of any red signal, any green signal or any blue signal; If the skew value of any one of the red signals, any one of the green signals or any one of the blue signals is less than or equal to the corresponding signal skew threshold, then any one of the red signals, any one of the green signals or any one of the blue signals meets the requirement, and the detection of the RGB signal output by the next pixel is waited; If the skew value of any of the red signals, any of the green signals or any of the blue signals is greater than the corresponding signal skew threshold, then any of the red signals, any of the green signals or any of the blue signals do not meet the requirements, and the signal that does not meet the requirements and the current skew value are printed.

10. A test bench for automatic detection of the timing of output signals of a digital display interface, applied to the post-simulation stage of a GPU chip, characterized in that: The test bench includes a plurality of automatic detection models, each of which is used to detect the timing of the output signal of the corresponding digital display interface in the GPU chip; Each of the automatic detection models is used to detect the timing of the output signal of the corresponding digital display interface in the GPU chip, including: Before the display controller is reset, the setup time threshold, hold time threshold, and signal skew threshold are set; Before the display controller is reset, the polarity of the horizontal synchronization signal and the field synchronization signal is configured to enable automatic detection of the timing of the output signal of the digital display interface; The display controller is reset, and the automatic detection model starts to automatically detect each output signal output by the digital display interface, and detects the setup time and the hold time of each output signal relative to the pixel clock based on the setup time threshold and the hold time threshold; detects the alignment of the horizontal synchronization signal and the field synchronization signal of the digital display interface based on the signal skew threshold, and detects the skew between the RGB signals output by the digital display interface during the display enable period; Determine whether each output signal of the digital display interface meets the requirements according to the detection result of each output signal, and print the information of the output signal that does not meet the requirements.

Images