VCSEL chip testing method and system

Abstract

The invention provides a VCSEL (Vertical Cavity Surface Emitting Laser) chip testing method and a VCSEL chip testing system. The VCSEL chip test method is applied to the multi-channel VCSEL chip test device, the multi-channel VCSEL chip test device comprises a driving test board, a motion module and a plurality of test devices used for executing different test items, the driving test board comprises a plurality of test hole sites, each test hole site is used for being connected with a corresponding VCSEL chip, and the motion module is used for executing the test items. The motion module is connected with the VCSEL chip so as to provide a driving signal to the connected VCSEL chip, and the motion module is respectively connected with the plurality of test devices and is used for driving the connected test devices to move to a target position to execute a test; the VCSEL chip test method comprises the following steps: determining target test equipment according to target test items corresponding to each VCSEL chip; according to the hole site number of the target test hole site corresponding to each VCSEL chip, planning a test route of each target test device; the target test hole site is a test hole site connected with a VCSEL chip; and controlling the motion module to sequentially drive each target test device to test the VCSEL chip along the test route.

Description

Technical Field

[0001] The present application relates to the technical field of VCSEL chip testing, and in particular to a VCSEL chip testing method and system thereof. Background Art

[0002] LiDAR is a technology that measures the distance, speed and shape of a target by emitting laser pulses and receiving reflected signals. It is widely used in autonomous driving, industrial automation, surveying and mapping and other fields. VCSEL chips (vertical cavity surface emitting lasers) are a key light source technology in LiDAR. With the development of LiDAR technology, people's requirements for VCSEL chips are gradually increasing. Correspondingly, there are more and more test items for VCSEL chips, and the test methods in related technologies can no longer meet the increasingly complex evaluation requirements of VCSEL chips. Summary of the invention

[0003] Based on this, it is necessary to provide a VCSEL chip testing method and system that can realize automated testing in response to the above technical problems.

[0004] In a first aspect, the present application provides a VCSEL chip testing method, which is applied to a multi-channel VCSEL chip testing device, wherein the multi-channel VCSEL chip testing device comprises a driving test board, a motion module, and a plurality of testing devices for performing different test items, wherein the driving test board comprises a plurality of testing holes, each of which is respectively used to connect a corresponding VCSEL chip to provide a driving signal to the connected VCSEL chip, and the motion module is respectively connected to the plurality of testing devices to drive the connected testing devices to move to a target position to perform a test; the VCSEL chip testing method comprises:

[0005] Determine the target test equipment according to the target test items corresponding to each VCSEL chip;

[0006] Planning the test route of each target test device according to the hole number of the target test hole corresponding to each VCSEL chip; the target test hole is a test hole connected to the VCSEL chip;

[0007] The motion module is controlled to drive each of the target test devices in turn to test the VCSEL chip along the test route.

[0008] In one embodiment, the method further comprises:

[0009] Generate a test map according to the test results; the test map includes a plurality of grid units having the same number as the test wells, and the grid units are used to display the test results of the corresponding test wells;

[0010] The test result of the target test hole connected to the VCSEL chip includes any one of to be tested, qualified and unqualified, and the test result of the remaining test holes includes not tested.

[0011] In one embodiment, the method further comprises:

[0012] An in-situ test is performed on each of the test holes to determine at least one target test hole among the multiple test holes.

[0013] In one embodiment, each of the VCSEL chips is provided with a plurality of pins for connecting to the target test hole positions, and the in-situ testing of each of the test hole positions includes:

[0014] Providing an in-position detection signal through one of the pins at the test hole position, and obtaining an in-position feedback signal according to another pin at the test hole position; the in-position feedback signal is generated by the VCSEL chip according to the in-position detection signal;

[0015] A target test hole position among the plurality of test hole positions is determined according to the in-situ feedback signal.

[0016] In one embodiment, the performing in-situ testing on each of the test holes to determine at least one target test hole among the multiple test holes comprises:

[0017] Performing in-situ testing on each of the test hole positions to determine the test hole position connected to the VCSEL chip;

[0018] The numbers of the test holes connected to the VCSEL chips are displayed on the interactive interface;

[0019] The target test hole position is determined in response to a user operation on the interactive interface.

[0020] In one of the embodiments, before determining the target test equipment according to the target test items corresponding to each VCSEL chip, the method further includes:

[0021] Obtain the model of the VCSEL chip connected to the target test hole;

[0022] The test items corresponding to the target test holes are determined according to the models of the VCSEL chips.

[0023] In one embodiment, the method further comprises:

[0024] Determining the evaluation strategy of the corresponding target test hole position according to the model of each VCSEL chip;

[0025] According to the test data collected by each target test device and the evaluation strategy, the test results of each target test hole position are obtained respectively.

[0026] In one embodiment, the step of sequentially controlling each of the target test devices to test the VCSEL chip along the test route includes:

[0027] Determine the priority of each of the target test items according to the evaluation strategy;

[0028] In the case where the multiple target test items corresponding to the VCSEL chip include test items of multiple priorities, the control motion module sequentially drives the target test devices corresponding to the target test items of the multiple priorities to test the VCSEL chip according to the priority order;

[0029] The step of obtaining the test results of each target test hole position according to the test data collected by each target test device and the evaluation strategy includes:

[0030] When the test data of the test items of all priorities meet the corresponding evaluation requirements, the test result of the target test hole position is determined to be qualified.

[0031] In one embodiment, the plurality of target test items include test items of two priorities, the first priority item includes at least one of spectral test and LIV test, and the second priority item includes at least one of near field test and far field test.

[0032] In one embodiment, obtaining the test results of each target test hole position according to the test data collected by each target test device and the evaluation strategy includes:

[0033] Determine the weight of each target test item according to the evaluation strategy;

[0034] Obtaining a test score of the VCSEL chip connected to the target test hole position according to the test data of each target test item and the weight;

[0035] When the test score meets the corresponding evaluation requirements, the test result of the target test hole position is determined to be qualified.

[0036] In one embodiment, the method further comprises: at least one of the following:

[0037] The hole number of each target test hole and the model of the connected VCSEL chip are displayed on the interactive interface respectively;

[0038] The hole number of each target test hole and the corresponding test parameters of the target test item are displayed on the interactive interface respectively; the test parameters include at least one of spectral test conditions, LIV test conditions, near-field test conditions and far-field test conditions;

[0039] The hole number of each target test hole and the corresponding test data collected by each target test device are displayed on the interactive interface respectively;

[0040] The hole number of each target test hole and the corresponding evaluation strategy are displayed on the interactive interface.

[0041] In one of the embodiments, before determining the target test equipment according to the target test items corresponding to each VCSEL chip, the method further includes:

[0042] Acquire manufacturing information and aging identification of the VCSEL chip; the manufacturing information includes at least one of a batch number, a manufacturing order number, and a wafer ID, and the aging identification includes unaged and aged;

[0043] When the aging mark of the VCSEL chip indicates that the chip has been aged, the test items when the VCSEL chip with the same manufacturing information has not been aged are used as the target test items for the current test.

[0044] In one embodiment, the method further comprises:

[0045] After completing the test on the VCSEL chip with the aging mark as aged, the test data of the VCSEL chip with the same manufacturing information before and after aging are compared.

[0046] In one embodiment, the method further comprises:

[0047] generating a data graph according to the test data collected by the target test device;

[0048] Displaying the data graph on an interactive interface;

[0049] Wherein, generating a data graph according to the test data collected by the target test device includes at least one of the following:

[0050] In the case where the test items include spectrum testing, generating an OSA curve according to the spectrum testing data;

[0051] In the case where the test items include LIV test, generating a light-current-voltage curve according to LIV test data;

[0052] In the case where the test items include near-field testing, generating a near-field light intensity distribution diagram according to the near-field testing data;

[0053] In the case where the test items include far-field testing, a far-field light intensity distribution diagram is generated according to the far-field testing data.

[0054] In a second aspect, the present application provides a VCSEL chip testing system, comprising:

[0055] A multi-channel VCSEL chip testing device, comprising a driving test board, a motion module and a plurality of testing devices for performing different test items, wherein the driving test board comprises a plurality of testing holes, each of which is respectively used to electrically connect a corresponding VCSEL chip to provide a driving signal to the connected VCSEL chip, and the motion module is respectively connected to the plurality of testing devices to drive the connected testing devices to move to a target position to perform a test;

[0056] A host computer is connected to the multi-channel VCSEL chip testing device and is used to execute the VCSEL chip testing method as described above.

[0057] The above-mentioned VCSEL chip testing method and system, by configuring a plurality of test holes for the driving test board, can perform the test together after connecting a plurality of VCSEL chips to be tested to the corresponding target test holes, without the need to frequently replace the VCSEL chips connected to the driving test board. By setting a plurality of test devices, all target test items for a VCSEL chip can be completed in a multi-channel VCSEL chip testing device without the need to frequently replace the test machine. Moreover, in the case where some target test items can be executed in parallel, the total time required for the test can be further shortened. In addition, compared with manual operation by the user, the route planning is unified by the host computer, and the motion module and the test equipment are controlled to execute the test process according to the planned test route, which can make the test process more efficient. Therefore, the present embodiment provides a VCSEL chip testing method with high test efficiency and relatively simple user operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0059] Figure 1 This is one of the flow charts of a VCSEL chip testing method according to an embodiment;

[0060] Figure 2 This is a second flowchart of a VCSEL chip testing method according to an embodiment;

[0061] Figure 3 This is a third flow chart of a VCSEL chip testing method according to an embodiment;

[0062] Figure 4 This is a fourth flow chart of a VCSEL chip testing method according to an embodiment;

[0063] Figure 5 Flow chart 5 of a VCSEL chip testing method according to an embodiment;

[0064] Figure 6 FIG. 4 is a schematic diagram of a VCSEL chip testing device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0065] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0066] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0067] It should be noted that when an element is considered to be "connected" to another element, it can be directly connected to the other element, or connected to the other element through an intermediate element. In addition, the "connection" in the following embodiments should be understood as "electrical connection", "communication connection", etc. if there is transmission of electrical signals or data between the connected objects.

[0068] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" etc. specify the presence of stated features, wholes, steps, operations, components, parts or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts or combinations thereof.

[0069] The present application provides a VCSEL chip testing method, which is applied to a multi-channel VCSEL chip testing device. A multi-channel VCSEL chip testing device refers to a device that can simultaneously detect the performance parameters of multiple VCSEL chips. Compared with a single-channel testing device in the related art, a multi-channel VCSEL chip testing device can improve the testing efficiency and reduce the number of technicians required. The multi-channel VCSEL chip testing device includes a drive test board, a motion module, and multiple test devices for performing different test items.

[0070] The drive test board includes a plurality of test holes. For example, the drive test board includes 10, 16, 20 and other test holes. Taking 16 test holes as an example, the 16 test holes can be arranged in 2 rows and 8 columns, or in 4 rows and 4 columns, which is not limited in this embodiment. Each test hole is used to connect the corresponding VCSEL chip to provide a drive signal to the connected VCSEL chip. Specifically, the VCSEL chip can be connected to the test hole by any of the connection methods such as welding and plugging. The drive test board can receive instructions from the host computer and adjust the current value, power-on timing, etc. of the drive signal according to the received instructions. Specifically, the drive test board may include a test board and a driver board. The test board is used to connect the VCSEL chip, and the test board is provided with a peripheral test circuit for performing electrical testing on the VCSEL chip. The driver board is used to power the test board to drive the VCSEL chip on the test board.

[0071] The motion module is connected to a plurality of test devices, respectively, and is used to drive the connected test devices to move to the target position to perform the test. The motion module includes an XYZ motion track and a stepper motor. The XYZ motion track can also be called a three-axis motion track, and each axis is independently controlled by a corresponding stepper motor. Specifically, the host computer can control the stepper motor to rotate so that the corresponding axis moves, thereby driving the test device connected to the axis to move to the target position to perform the test. It is understandable that different test devices can be configured with different target positions to support different test functions. Furthermore, the motion module can also be connected to the drive test board, and drive the drive test board to move to adjust the position of each VCSEL chip connected to the drive test board.

[0072] Figure 1 This is one of the flow charts of a VCSEL chip testing method according to an embodiment, referring to Figure 1 The VCSEL chip testing method includes steps 102 to 106.

[0073] Step 102: determining a target test device according to target test items corresponding to each VCSEL chip.

[0074] Among them, the test items supported by the VCSEL chip testing method include but are not limited to at least one of LIV test, spectrum test, peak power test, polarization test, near-field test, and far-field test.

[0075] The LIV test is used to obtain the optical power, current, voltage and other parameters of the VCSEL chip. Specifically, corresponding test equipment can be configured for each test hole. The test equipment corresponding to the LIV test includes but is not limited to an optical power test device and a multimeter. The optical power test device is used to test the optical power of the VCSEL chip, and the multimeter is used to collect relevant electrical parameter data such as the voltage and current of the VCSEL chip.

[0076] Spectral testing is used to obtain the wavelength distribution, peak wavelength, side mode suppression ratio and other spectral characteristics of VCSEL chips. The corresponding test equipment for spectral testing includes but is not limited to integrating spheres, spectrometers and necessary coupling mechanisms (such as movable optical fibers with light-collecting lenses).

[0077] Peak power testing is used to obtain the highest power value that a VCSEL chip can reach in a short period of time. The corresponding test equipment for peak power testing includes but is not limited to integrating spheres, spectrometers, high-speed detectors, and necessary coupling mechanisms (such as movable optical fibers with light-collecting lenses).

[0078] Polarization testing is used to obtain the polarization state of the laser beam emitted by the VCSEL chip. The test equipment corresponding to the polarization test includes but is not limited to polarization detectors and some optical components. Polarization detectors are used to measure the polarization state of the light beam, usually including polarization analyzers or polarimeter. Optical components include wave plates, polarizers, etc., which are used to adjust and analyze the polarization characteristics of the light beam.

[0079] Near-field testing refers to testing performed at a position close to the light-emitting surface of the VCSEL chip, which is mainly used to observe and analyze the near-field spot characteristics of the VCSEL chip. Near-field testing can provide information about the luminous intensity distribution and luminous diameter of the VCSEL chip. The test equipment corresponding to the near-field test includes but is not limited to imaging equipment.

[0080] Far-field testing refers to testing performed at a distance from the light-emitting surface of the VCSEL chip, and is mainly used to observe and analyze the far-field light spot characteristics of the VCSEL chip. Far-field testing is used to provide information about the divergence angle and beam shape of the VCSEL chip light beam. The test equipment corresponding to the far-field test includes but is not limited to imaging equipment.

[0081] It is understandable that in some test items, a corresponding test device can be configured for each test hole position, and in other test items, one test device can be configured for multiple test holes. In addition, in a test cycle, multiple VCSEL chips connected to the driver test board can use the same or different target test items, and one VCSEL chip can correspond to multiple target test items, which can be flexibly set according to user needs and is not limited here.

[0082] Step 104 , planning a test route for each target test device according to the hole number of the target test hole corresponding to each VCSEL chip.

[0083] Among them, the target test hole position is a test hole position connected to a VCSEL chip. Specifically, before planning the test route, the route planning strategy can be automatically selected or manually selected by the user. Route planning strategies include but are not limited to hole position order priority and test item priority. Hole position order priority means that after completing all target test items corresponding to a target test hole position, the next target test hole position is tested. Test item priority means that after completing the test of all target test holes corresponding to a target test item, the next target test item is tested. In some examples, a mixed method of hole position order priority and test item priority can also be adopted, for example, after completing the test of all target test holes corresponding to some target test items, each target test hole position is tested one by one to complete the remaining target test items.

[0084] Step 106 , controlling the motion module to sequentially drive each target test device to test the VCSEL chip along the test route.

[0085] In the embodiment of the application, by configuring a plurality of test holes for the drive test board, the test can be performed together after connecting a plurality of VCSEL chips to be tested to the corresponding target test holes, without the need to frequently replace the VCSEL chips connected to the drive test board. By setting a plurality of test devices, all target test items for a VCSEL chip can be completed in a multi-channel VCSEL chip test device without the need to frequently replace the test machine. Moreover, in the case where some target test items can be executed in parallel, the total time required for the test can be further shortened. In addition, compared with manual operation by the user, the route planning is unified by the host computer, and the motion module and the test equipment are controlled to execute the test process according to the planned test route, which can make the test process more efficient. Therefore, the present embodiment provides a VCSEL chip testing method with high test efficiency and simple user operation.

[0086] In one of the embodiments, before executing the aforementioned VCSEL chip testing method, the multi-channel VCSEL chip testing device can also be configured and initialized. Specifically, the user can log in to the account on the interactive interface to distinguish the user as an operator or a developer, thereby providing different permissions for the user. After the user logs in, he can select the save path of the test data. After the test is completed, the test data is saved according to the path selected by the user, and can be further uploaded to the database for the user to retrieve the data. After accessing the test equipment, it can be determined whether the interface address of each test equipment is correct and whether a communication connection can be established to ensure that the test data can be correctly saved and uploaded. After completing the initialization work of the above-mentioned multi-channel VCSEL chip testing device, the aforementioned VCSEL chip testing method can be executed.

[0087] In one embodiment, after the test equipment and the motion module are connected, the motion module can also be positioned and calibrated so that each test equipment can be moved to a desired position during the test. The positions where positioning and calibration can be performed include but are not limited to the integrating sphere light receiving position, the collimator light receiving position, the near-field test position, and the far-field test position.

[0088] In one embodiment, the multi-channel VCSEL chip testing device further includes a visual module. The visual module is used to collect original images of multiple VCSEL chips after the VCSEL chips are connected to the target test holes. The mapping relationship between the image pixels of the original image and the real-world coordinates is obtained through a distortion correction algorithm, and based on the mapping relationship, information such as the size of the VCSEL chip, the total number of VCSEL chips, and the position coordinates of each VCSEL chip is obtained, so as to control the motion module to move the test equipment according to the above information to test each target test hole.

[0089] In one of the embodiments, the VCSEL chip testing method further includes: generating a test map according to the test results.

[0090] The test map diagram can also be called a test mapping diagram or a test strategy diagram. The test map diagram is a data visualization method. The test map diagram can be displayed on an interactive interface or in a saved file. The test map diagram includes a plurality of grid units equal to the number of test wells. The grid units are used to display the test results of the corresponding test wells.

[0091] In an exemplary manner, a test map diagram can be generated at one time after completing the test of all VCSEL chips. In the case of generating the test map diagram at one time, the test results of the target test holes connected to the VCSEL chips include any one of qualified and unqualified, and the test results of the remaining test holes include not tested. In another exemplary manner, the test map diagram can also be updated in real time during the test process. In the case of updating the test map diagram in real time, the test results can further include "to be tested" to reflect the progress of the test. That is, the test results of the target test holes include any one of to be tested, qualified and unqualified, and the test results of the remaining test holes include not tested.

[0092] Different test results can be displayed in different colors. For example, to be tested is displayed in gray, qualified is displayed in green, unqualified is displayed in red, and untested is displayed in black. In the case where the VCSEL chip connected to the test hole needs to perform multiple target test items, a grid unit can be further divided into multiple sub-grids to display the test progress and test results of different target test items respectively. Furthermore, the host computer can also respond to a click operation or touch operation on the grid unit or sub-grid of the interactive interface to display the test data of the test hole corresponding to the grid unit or sub-grid.

[0093] In the embodiment of the application, by generating a test map, visualization of information such as test progress and test results can be achieved, so that users can intuitively monitor the VCSEL chip test process.

[0094] Figure 2 This is a second flow chart of a VCSEL chip testing method according to an embodiment, referring to Figure 2 In one embodiment, the VCSEL chip testing method includes steps 202 to 208. Steps 204 to 208 may refer to the above embodiments and will not be described in detail here.

[0095] Step 202 : Perform in-situ testing on each test hole position to determine at least one target test hole position among the multiple test hole positions.

[0096] In an exemplary embodiment, the original image can be captured by the visual module, and the original image can cover each test hole position. The original image is image recognized according to the preset VCSEL chip features or hole position features, and the hole position with the VCSEL chip features recognized is used as the target test hole position, or the hole position without the hole position features recognized is used as the target test hole position.

[0097] In another exemplary embodiment, each test hole position may be controlled to provide a driving signal in sequence, and when a change in an optical parameter such as optical power is detected when providing the driving signal, the test hole position is determined to be a target test hole position.

[0098] As another example, each VCSEL chip may be provided with a plurality of pins for connecting to a target test hole position, an in-situ detection signal is provided through a pin of the test hole position, and an in-situ feedback signal is obtained according to another pin of the test hole position, and a target test hole position among multiple test holes positions is determined according to the in-situ feedback signal. The in-situ feedback signal is generated by the VCSEL chip according to the in-situ detection signal. The in-situ detection signal may be either a voltage signal or a current signal, and the in-situ feedback signal may be either a voltage signal or a current signal. For example, when a VCSEL chip is not connected to the test hole position, the corresponding in-situ feedback signal is 0V. When a VCSEL chip is connected to the test hole position, the corresponding in-situ feedback signal is 3V.

[0099] Step 204 , determining a target test device according to the target test items corresponding to each VCSEL chip.

[0100] Step 206 , planning a test route for each target test device according to the hole number of the target test hole corresponding to each VCSEL chip.

[0101] Step 208 : Control the motion module to drive each target test device in turn to test the VCSEL chip along the test route.

[0102] In the embodiments of the application, the target test hole positions can be automatically and quickly screened out through in-situ testing, without the need for the user to manually select the target test hole positions, thereby reducing the user's workload and improving the efficiency of VCSEL chip testing.

[0103] In one of the embodiments, each test hole position is tested in situ to determine at least one target test hole position among multiple test hole positions, including: performing an in situ test on each test hole position to determine the test hole position connected to the VCSEL chip; displaying the number of the test hole position connected to the VCSEL chip on an interactive interface; and determining the target test hole position in response to user operations on the interactive interface.

[0104] Specifically, the user's operation on the interactive interface may be a check operation. For example, the interactive interface presents the number of the test hole position connected to the VCSEL chip, and each test hole position is not the target test hole position by default. The user can click the number position or the corresponding check box position to use the test hole position as the target test hole position. The user's operation on the interactive interface may also be a cancel check operation. For example, the interactive interface presents the number of the test hole position connected to the VCSEL chip, and each test hole position is the target test hole position by default. The user can click the number position or the corresponding check box position to not use the test hole position as the target test hole position.

[0105] Compared with the previous embodiment, in this embodiment, after the test holes connected with the VCSEL chip are determined through in-situ testing, the user can manually select some of them as target test holes according to actual testing requirements. In other words, some test holes automatically identified as connected with the VCSEL chip are not used as target test holes, so that the target test holes can be selected more flexibly, thereby improving the flexibility of the VCSEL chip testing method.

[0106] Figure 3 This is a flowchart of a VCSEL chip testing method according to an embodiment of the present invention. Figure 3 In one embodiment, the VCSEL chip testing method includes steps 302 to 310. That is, before determining the target test equipment according to the target test items corresponding to each VCSEL chip, this embodiment also includes steps 302 to 304. Among them, steps 306 to 310 can refer to the above embodiments and will not be repeated here.

[0107] Step 302: Obtain the model of the VCSEL chip connected to the target test hole.

[0108] In an exemplary manner, the model of the VCSEL chip can be automatically matched according to the information obtained in step 202. For example, the model of the VCSEL chip can be matched based on the identified VCSEL chip features according to the original image obtained in step 202. The model of the VCSEL chip can also be matched according to the changes in optical parameters such as the drive signal and the corresponding optical power. The model of the corresponding VCSEL chip can also be matched according to the amplitude of the in-situ feedback signal. It can be understood that in some embodiments, the above-mentioned multiple model matching methods can be combined to achieve automatic model matching.

[0109] In another exemplary embodiment, the user may be prompted to input the model of the VCSEL chip connected to the target test hole position in the interactive interface according to the result of the in-situ test. The input method includes but is not limited to inputting the VCSEL chip model in the interactive interface, importing a table including the target test hole position and the VCSEL chip model, etc.

[0110] Step 304 : determining the test items corresponding to each target test hole position according to the model of each VCSEL chip.

[0111] Specifically, different models of VCSEL chips can be configured with different test items, and the above configuration information can be pre-stored in the memory of the host computer. Based on the VCSEL chip model obtained in step 302, the stored configuration information can be directly retrieved, and the VCSEL chip can be tested based on the retrieved configuration information. Furthermore, after retrieving the stored configuration information, the above information can be displayed on the interactive interface, so that the user can change the test items according to actual test requirements. Further, after the user makes the change, the user can also be asked through the interactive interface whether to save the changed configuration information for use in subsequent tests. In some embodiments, the model of the VCSEL chip can also be used to generate and save test-related files, etc., which is not limited here.

[0112] Step 306 , determining a target test device according to the target test items corresponding to each VCSEL chip.

[0113] Step 308 : planning a test route for each target test device according to the hole number of the target test hole corresponding to each VCSEL chip.

[0114] Step 310 : Control the motion module to drive each target test device in turn to test the VCSEL chip along the test route.

[0115] In the embodiment of the application, by pre-configuring the VCSEL chip model and the corresponding test items, the user does not need to perform cumbersome test item selection when performing VCSEL chip testing. The VCSEL chip testing method of this embodiment can, on the one hand, reduce the workload of the user, thereby improving the efficiency of the VCSEL chip testing method. On the other hand, it can also reduce the input errors that are prone to occur during the input of the test items, thereby improving the reliability of the VCSEL chip testing method.

[0116] In one of the embodiments, the VCSEL chip testing method further includes: determining an evaluation strategy for a corresponding target test hole position according to the model of each VCSEL chip; and obtaining a test result for each target test hole position according to test data and an evaluation strategy collected by each target test device.

[0117] It is understandable that different types of VCSEL chips may have different usage scenarios and have different requirements for the performance parameters of VCSEL chips. For example, in the LiDAR scenario, VCSEL chips with wavelengths of about 905nm, 942nm or 950nm are required, while in the data communication scenario, VCSEL chips with wavelengths of about 850nm are required. For another example, in the scenario of vehicle-mounted LiDAR, VCSEL chips with high peak power are required, while in the data communication scenario, the peak power requirement is relatively low. Therefore, using different evaluation strategies for different types of VCSEL chips can make the evaluation strategy more compatible with the actual application scenarios of the VCSEL chips, and put forward higher requirements for key test items, thereby improving the reliability of the test results.

[0118] Figure 4 This is a fourth flow chart of a VCSEL chip testing method according to an embodiment, referring to Figure 4 In one embodiment, the VCSEL chip testing method includes steps 402 to 414. That is, the aforementioned steps sequentially control each target test device to test the VCSEL chip along the test route, including steps 410 to 412 of this embodiment. Among them, steps 402 to 408 can refer to the aforementioned embodiment and will not be repeated here.

[0119] Step 402: Obtain the model of the VCSEL chip connected to the target test hole.

[0120] Step 404 : determining the evaluation strategy of the corresponding target test hole position according to the model of each VCSEL chip.

[0121] Step 406 , determining a target test device according to the target test items corresponding to each VCSEL chip.

[0122] Step 408 : planning a test route for each target test device according to the hole number of the target test hole corresponding to each VCSEL chip.

[0123] Step 410: Determine the priority of each target test item according to the evaluation strategy.

[0124] Step 412: When the multiple target test items corresponding to the VCSEL chip include test items of multiple priorities, the motion control module drives the target test devices corresponding to the target test items of multiple priorities to test the VCSEL chip in sequence according to the priority order.

[0125] Specifically, according to the order of priority means testing the VCSEL chip from high to low priority. Among them, the test items that have a greater impact on the performance of the VCSEL chip can be set with a higher priority, otherwise a lower priority can be set. In other words, it can be understood that if the VCSEL chip cannot meet the evaluation requirements of the test items with higher priority, it is also difficult to meet the evaluation requirements of the test items with lower priority, and thus it cannot be put into use. Therefore, by dividing the test items into multiple priorities, the test items with lower priority can be adaptively adjusted according to the test data of the test items with higher priority. For example, some test items with lower priority can be canceled, or the evaluation requirements of some test items with lower priority can be lowered, or the test parameters of some test items with lower priority can be changed.

[0126] The evaluation requirements for spectrum testing include but are not limited to the wavelength of the laser beam being within a preset range, and the evaluation requirements for LIV testing include but are not limited to the threshold current, operating current, and operating voltage being within a preset range, as well as the light output power and photoelectric conversion efficiency being within a preset range. The evaluation requirements for near-field testing include but are not limited to the luminous intensity distribution and luminous diameter being within a preset range. The evaluation requirements for far-field testing include but are not limited to the divergence angle, beam shape, and uniformity of the far-field light spot being within a preset range.

[0127] Step 414: When the test data of the test items of all priorities meet the corresponding evaluation requirements, the test results of the target test holes are determined to be qualified.

[0128] In the embodiment of the application, by configuring different priorities for multiple target test items and performing tests from high to low priority, the test data of the previous test item can be used as a reference for the subsequent test item, thereby improving the test efficiency of the VCSEL chip testing method.

[0129] In one embodiment, a corresponding route planning strategy can be determined according to the evaluation strategy determined in step 404, so that the test process matches the evaluation strategy. For example, when the evaluation strategy is to use different priorities for different test items, the test items with higher priorities can be tested first through the planned test route, and when the test data of the test items with higher priorities meet the evaluation requirements, the test items with lower priorities can be tested, until all the test items with all priorities are completed, and a comprehensive test result is given.

[0130] Specifically, multiple test items can be divided into n priorities, n≥2. In order of priority from high to low, the test items are named first priority item, second priority item...n-1 priority item, n priority item. During the test process, for the VCSEL chip connected to the same target test hole, the kth priority item can be tested if the test data of the k-1th priority item meets the corresponding evaluation requirements. Among them, 1<k≤n. Taking the test items including two priorities as an example, if the test data of the first priority item of the VCSEL chip meets the evaluation requirements, the target test equipment corresponding to the second priority item can be controlled to test the VCSEL chip. When the test data of the test items of all priorities meet the corresponding evaluation requirements, the test results of the target test hole are judged to be qualified. In addition, if the test data of the test items of any priority cannot meet the evaluation requirements, the remaining test items with lower priorities may not be tested, thereby shortening the test cycle.

[0131] In one embodiment, the multiple target test items include test items of two priorities, the first priority item includes at least one of the spectrum test and the LIV test, and the second priority item includes at least one of the near field test and the far field test. For example, when the test data of the spectrum test and the LIV test of the VCSEL chip connected to a test hole position meet the evaluation requirements, the near field test and the far field test can be performed on the VCSEL chip connected to the test hole position, otherwise the near field test and the far field test are not performed. It can be understood that the spectrum test and the LIV test can provide comprehensive information about the optoelectronic characteristics of the VCSEL chip, including but not limited to key parameters such as wavelength, optical power, and conversion efficiency, which are crucial for evaluating the overall performance of the VCSEL chip. Although the near field test and the far field test can also provide some useful information, they focus more on the characteristics such as the spatial distribution and divergence angle of the light beam. Although these characteristics are important, they are not as directly related to the core performance indicators of the VCSEL chip as the spectrum test and the LIV test. Therefore, the priority division method of the test items in this embodiment can achieve efficient and high-quality testing of the VCSEL chip.

[0132] Figure 5 This is a flowchart of a VCSEL chip testing method according to an embodiment of the present invention. Figure 5 In one embodiment, the VCSEL chip testing method includes steps 502 to 514. That is, the aforementioned steps include steps 512 to 516 of this embodiment to obtain the test results of each target test hole position according to the test data and evaluation strategy collected by each target test device. Among them, steps 502 to 510 can refer to the aforementioned embodiment and will not be repeated here.

[0133] Step 502: Obtain the model of the VCSEL chip connected to the target test hole.

[0134] Step 504 : determining the evaluation strategy of the corresponding target test hole position according to the model of each VCSEL chip.

[0135] Step 506 , determining a target test device according to the target test items corresponding to each VCSEL chip.

[0136] Step 508 : planning a test route for each target test device according to the hole number of the target test hole corresponding to each VCSEL chip.

[0137] Step 510 : Control the motion module to sequentially drive each target test device to test the VCSEL chip along the test route.

[0138] Step 512, determining the weight of each target test item according to the evaluation strategy.

[0139] Specifically, a larger weight can be set for the test items that have a greater impact on the performance of the VCSEL chip, otherwise a smaller weight can be set. For example, the weight of the spectral test can be set to 35%, the weight of the LIV test can be set to 35%, the weight of the near-field test can be set to 15%, and the weight of the far-field test can be set to 15%. It should be noted that the values ​​of the above weights are only used for exemplary descriptions and are not used to limit the scope of protection of this embodiment. Furthermore, in the case where the VCSEL chip does not need to be tested for all test items, the weights can be normalized according to the selected target test items. For example, if the target test items include spectral testing, LIV testing, and near-field testing, the weight of the spectral test can be adjusted to 41%, the weight of the LIV test can be adjusted to 41%, and the weight of the near-field test can be adjusted to 18% through normalization.

[0140] Step 514 , obtaining a test score of the VCSEL chip connected to the target test hole position according to the test data and weight of each target test item.

[0141] Specifically, the individual scores of the VCSEL chip under each target test item can be determined based on the test data of each target test item and the corresponding evaluation requirements. Then, the test score of the VCSEL chip connected to the target test hole position can be obtained by weighted average according to the individual scores and weights of each target test item.

[0142] Step 516: When the test score meets the corresponding evaluation requirements, the test result of the target test hole position is determined to be qualified.

[0143] In the embodiment of the application, the evaluation strategy is determined according to the model of the VCSEL chip, and the weight is determined according to the evaluation strategy. Therefore, the weight matched according to the evaluation strategy can also be adapted to the model of the VCSEL chip, so that the test score finally obtained can better characterize the characteristics of the corresponding model of the VCSEL chip. Moreover, by configuring corresponding weights for multiple target test items respectively, calculating according to the weights and the test data of the multiple target test items to obtain a comprehensive test score, and obtaining the test results based on the test scores, the test data of multiple target test items can be effectively integrated, thereby improving the reliability of the test results.

[0144] In one embodiment, the VCSEL chip testing method further includes: displaying the hole number of each target test hole and the model of the connected VCSEL chip on the interactive interface. The above method of displaying the hole number and the VCSEL chip model on the interactive interface can facilitate the user to verify the information of the VCSEL chip to be tested corresponding to each target test hole.

[0145] In one of the embodiments, the VCSEL chip testing method further includes: displaying the hole position number of each target test hole position and the test parameters of the corresponding target test items on the interactive interface. Among them, the test parameters include at least one of spectral test conditions, LIV test conditions, near-field test conditions and far-field test conditions. Specifically, spectral test conditions and LIV test conditions can be collectively referred to as electro-optical test conditions, and include VCSEL chip scanning conditions, spectrometer operating parameters, test logic function parameters, collimator coupling conditions, oscilloscope operating parameters, short wavelength type spectral parameters, optical pulse width test, oscilloscope differential probe parameters, differential probe waveform test, multimeter operating parameters, oscilloscope OE photocurrent parameters. At least one of the following. The above-mentioned method of displaying the hole position number and test parameters on the interactive interface can facilitate users to verify the test parameters corresponding to each target hole position to be tested, and adjust the test parameters according to actual test requirements.

[0146] In one embodiment, the VCSEL chip testing method further includes: displaying the hole number of each target test hole and the test data collected by each corresponding target test device on the interactive interface. The above method of displaying the hole number and test data on the interactive interface can facilitate users to check the original test data corresponding to each target test hole.

[0147] In one embodiment, the VCSEL chip testing method further includes: displaying the hole number and the corresponding evaluation strategy of each target test hole on the interactive interface. The above method of displaying the hole number and test data on the interactive interface can facilitate the user to learn the evaluation strategy corresponding to each target test hole.

[0148] In one embodiment, the VCSEL chip testing method further includes: displaying the test efficiency and / or test progress on the interactive interface. The test efficiency is, for example, testing one VCSEL chip per minute. The test progress is, for example, that the test of the VCSEL chips corresponding to 5 target test holes has been completed, or that the test of the VCSEL chips corresponding to 50% of the target test holes has been completed.

[0149] In one of the embodiments, the VCSEL chip testing method further includes: displaying at least one of a start button, a reset button, a pause button, and a stop button on an interactive interface.

[0150] In one of the embodiments, before determining the target test equipment according to the target test items corresponding to each VCSEL chip, the VCSEL chip testing method further includes: acquiring manufacturing information and an aging mark of the VCSEL chip; when the aging mark of the VCSEL chip indicates that it is aged, using the test items of the VCSEL chip with the same manufacturing information when it is not aged as the target test items for the current test.

[0151] Among them, the manufacturing information includes at least one of the batch number, the manufacturing order number and the wafer ID. Therefore, the manufacturing information is related to the production process information of the VCSEL chip. The aging mark includes unaged and aged. The aging test refers to a long-term continuous working test of the VCSEL chip by simulating the actual use conditions. VCSEL chips usually need to be tested before and after the aging test, and observe whether their performance parameters such as output power, wavelength, threshold current, etc. will degrade over time. The aging test can ensure the reliability and stability of the VCSEL chip in practical applications and meet the needs of long-term use. Therefore, in the embodiment of the application, by obtaining the aging mark, the VCSEL chip that has been subjected to the aging test can be subjected to the same test items as before the aging test, which is convenient for data comparison and analysis to understand the stability of the VCSEL chip and evaluate whether there are abnormalities in the production process. Moreover, automatically matching the target test items based on the manufacturing information and the aging mark can save the user the configuration process of the test items, thereby improving the efficiency of the VCSEL chip test.

[0152] Furthermore, when the aging mark is aged, at least one of the aging board number, aging time and aging temperature can also be obtained. The aging board number is used to reflect the order number voucher for completing the aging test, and is an important import information in the aging equipment. The aging time is used to generate test data for different aging stages, and the aging temperature is used to generate test data for different aging environments. The aging time and aging temperature help to comprehensively evaluate the reliability of the VCSEL chip. It helps to comprehensively evaluate the reliability of the VCSEL chip.

[0153] In one of the embodiments, the VCSEL chip testing method further includes: after completing the test of the VCSEL chip with the aging mark as aged, comparing the test data of the VCSEL chip with the same manufacturing information before and after aging. In the embodiment of the application, after completing the test of the VCSEL chip with the aging mark as aged, the test data before and after aging are automatically compared, so that the user can timely learn about the stability of the VCSEL chip and evaluate whether there are abnormalities in the production process. Moreover, automatically performing the comparison and outputting the comparison results can greatly save the user's comparison operations, thereby improving the efficiency of VCSEL chip testing.

[0154] In one embodiment, the VCSEL chip testing method further includes: generating a data graph based on the test data collected by the target test device; and displaying the data graph on an interactive interface. The generated data graph includes at least one of an OSA curve, a light-current-voltage curve, a near-field light intensity distribution graph, and a far-field light intensity distribution graph.

[0155] Specifically, when the test items include spectrum testing, an OSA curve is generated according to the spectrum testing data. The optical spectrum analysis (OSA) curve is used to display the output power of the VCSEL chip at different wavelengths and can reflect the spectrum characteristics of the VCSEL chip. When the test items include LIV testing, a light-current-voltage curve is generated according to the LIV test data. The light-current-voltage curve can reflect the power, current, voltage, pulse width, amplitude, rise time and other characteristics of the VCSEL chip. When the test items include near-field testing, a near-field light intensity distribution diagram is generated according to the near-field test data. The near-field light intensity distribution diagram is used to display the light intensity distribution of the output light beam of the VCSEL chip at a close distance, so that the quality of the light beam can be evaluated. For example, if the near-field light intensity distribution is uniform and symmetrical, it means that the light beam quality is good. When the test items include far-field testing, a far-field light intensity distribution diagram is generated according to the far-field test data. The far-field light intensity distribution diagram is used to display the divergence of the output light beam of the VCSEL chip at a long distance, so that the divergence angle of the light beam can be measured.

[0156] It should be understood that, although the steps in each flowchart are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear description in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least a part of the steps in each flowchart may include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0157] The present application also provides a VCSEL chip testing device. Figure 6 FIG. 1 is a schematic diagram of a VCSEL chip testing device according to an embodiment of the present invention. Figure 6 The VCSEL chip testing device includes a device determination module, a route planning module and a test module. The device determination module is used to determine the target test device according to the target test items corresponding to each VCSEL chip. The route planning module is used to plan the test route of each target test device according to the hole number of the target test hole corresponding to each VCSEL chip; the target test hole is the test hole connected to the VCSEL chip. The test module is used to control the motion module to drive each target test device to test the VCSEL chip along the test route in turn.

[0158] In one embodiment, the VCSEL chip testing device further includes: a map generating module. The map generating module is used to generate a test map according to the test results; the test map includes a plurality of grid units equal to the number of the test holes, and the grid units are used to display the test results of the corresponding test holes; wherein the test results of the target test holes connected with the VCSEL chip include any one of to be tested, qualified and unqualified, and the test results of the remaining test holes include not tested.

[0159] In one embodiment, the VCSEL chip testing device further includes: an in-situ testing module. The in-situ testing module is used to perform in-situ testing on each test hole position respectively to determine at least one target test hole position among the multiple test hole positions.

[0160] In one of the embodiments, the in-situ test module is used to provide an in-situ detection signal through a pin of the test hole position, and obtain an in-situ feedback signal according to another pin of the test hole position; the in-situ feedback signal is generated by the VCSEL chip according to the in-situ detection signal; and the target test hole position among multiple test hole positions is determined according to the in-situ feedback signal.

[0161] In one embodiment, the in-situ testing module is used to perform in-situ testing on each test hole position to determine the test hole position connected to the VCSEL chip; display the number of the test hole position connected to the VCSEL chip on the interactive interface; and determine the target test hole position in response to the user's operation on the interactive interface.

[0162] In one embodiment, the VCSEL chip testing device further includes: a model acquisition module and a first item determination module. The model acquisition module is used to acquire the model of the VCSEL chip connected to the target test hole. The first item determination module is used to determine the test item corresponding to each target test hole according to the model of each VCSEL chip.

[0163] In one embodiment, the VCSEL chip testing device further includes: a strategy determination module and a result acquisition module. The strategy determination module is used to determine the evaluation strategy of the corresponding target test hole position according to the model of each VCSEL chip. The result acquisition module is used to obtain the test results of each target test hole position according to the test data and evaluation strategy collected by each target test device.

[0164] In one embodiment, the test module is used to determine the priority of each target test item according to the evaluation strategy; when the multiple target test items corresponding to the VCSEL chip include test items of multiple priorities, the control motion module drives the target test equipment corresponding to the target test items of multiple priorities to test the VCSEL chip in order of priority. The result acquisition module is used to determine that the test result of the target test hole is qualified when the test data of the test items of all priorities meet the corresponding evaluation requirements.

[0165] In one embodiment, the plurality of target test items include test items of two priorities, the first priority item includes at least one of spectral test and LIV test, and the second priority item includes at least one of near field test and far field test.

[0166] In one of the embodiments, the result acquisition module is used to determine the weight of each target test item according to the evaluation strategy; obtain the test score of the VCSEL chip connected to the target test hole according to the test data and weight of each target test item; when the test score meets the corresponding evaluation requirements, the test result of the target test hole is determined to be qualified.

[0167] In one embodiment, the VCSEL chip testing device further includes: a first visualization module. The first visualization module is used to display the hole number of each target test hole and the model of the connected VCSEL chip on the interactive interface; display the hole number of each target test hole and the test parameters of the corresponding target test item on the interactive interface; the test parameters include at least one of spectral test conditions, LIV test conditions, near-field test conditions and far-field test conditions; display the hole number of each target test hole and the corresponding test data collected by each target test device on the interactive interface; display the hole number of each target test hole and the corresponding evaluation strategy on the interactive interface.

[0168] In one embodiment, the VCSEL chip testing device further includes: an aging identification acquisition module and a second item determination module. The aging identification acquisition module is used to acquire the manufacturing information and aging identification of the VCSEL chip; the manufacturing information includes at least one of the batch number, the manufacturing order number and the wafer ID, and the aging identification includes not aged and aged. The second item determination module is used to, when the aging identification of the VCSEL chip is aged, use the test items of the VCSEL chip with the same manufacturing information when it is not aged as the target test items of the current test.

[0169] In one embodiment, the VCSEL chip testing device further includes: an aging comparison module. The aging comparison module is used to compare the test data of the VCSEL chip with the same manufacturing information before and after aging after completing the test of the VCSEL chip with the aging mark as aged.

[0170] In one embodiment, the VCSEL chip testing device further includes: a second visualization module. The second visualization module is used to generate a data graph according to the test data collected by the target test device; and display the data graph on an interactive interface; wherein, generating the data graph according to the test data collected by the target test device includes at least one of the following: generating an OSA curve according to the spectrum test data when the test item includes a spectrum test; generating a light-current-voltage curve according to the LIV test data when the test item includes a LIV test; generating a near-field light intensity distribution graph according to the near-field test data when the test item includes a near-field test; and generating a far-field light intensity distribution graph according to the far-field test data when the test item includes a far-field test.

[0171] For the specific definition of the VCSEL chip testing device, please refer to the definition of the VCSEL chip testing method above, which will not be repeated here. Each module in the above-mentioned VCSEL chip testing device can be implemented in whole or in part by software, hardware and a combination thereof. The above-mentioned modules can be embedded in or independent of the processor in the computer device in the form of hardware, or can be stored in the memory in the computer device in the form of software, so that the processor can call and execute the operations corresponding to the above modules. It should be noted that the division of modules in the embodiment of the present application is schematic and is only a logical function division. There may be other division methods in actual implementation.

[0172] The embodiment of the present application also provides a VCSEL chip testing system, including a multi-channel VCSEL chip testing device and a host computer. Among them, the multi-channel VCSEL chip testing device includes a drive test board, a motion module and a plurality of test devices for performing different test items. The drive test board includes a plurality of test holes, each of which is used to electrically connect the corresponding VCSEL chip to provide a drive signal to the connected VCSEL chip. The motion module is connected to a plurality of test devices respectively, and is used to drive the connected test devices to move to the target position to perform the test. The host computer is connected to the multi-channel VCSEL chip testing device, and is used to perform the VCSEL chip testing method as described above.

[0173] In one embodiment, an electronic device is provided, including a memory and a processor, wherein a computer program is stored in the memory, and the processor implements the steps in the above method embodiments when executing the computer program.

[0174] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps in the above method embodiments are implemented.

[0175] In one embodiment, a computer program product is provided, including a computer program, which implements the steps in the above method embodiments when executed by a processor.

[0176] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, etc., but are not limited to this.

[0177] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0178] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0179] The above embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. A VCSEL chip testing method, characterized in that: The invention is applied to a multi-channel VCSEL chip testing device, which comprises a driving test board, a motion module and a plurality of testing devices for executing different test items. The driving test board comprises a plurality of testing holes, each of which is respectively used to connect a corresponding VCSEL chip to provide a driving signal to the connected VCSEL chip. The motion module is respectively connected to the plurality of testing devices to drive the connected testing devices to move to a target position to execute a test. The VCSEL chip testing method comprises: Determine the target test equipment according to the target test items corresponding to each VCSEL chip; Planning the test route of each target test device according to the hole number of the target test hole corresponding to each VCSEL chip; the target test hole is a test hole connected to the VCSEL chip; The motion module is controlled to drive each of the target test devices in turn to test the VCSEL chip along the test route.

2. The VCSEL chip testing method according to claim 1, characterized in that: The method further comprises: Generate a test map according to the test results; the test map includes a plurality of grid units having the same number as the test wells, and the grid units are used to display the test results of the corresponding test wells; The test result of the target test hole connected to the VCSEL chip includes any one of to be tested, qualified and unqualified, and the test result of the remaining test holes includes not tested.

3. The VCSEL chip testing method according to claim 1, characterized in that: The method further comprises: An in-situ test is performed on each of the test holes to determine at least one target test hole among the multiple test holes.

4. The VCSEL chip testing method according to claim 3, characterized in that: Each of the VCSEL chips is respectively provided with a plurality of pins for connecting to the target test hole positions, and the in-situ testing of each of the test hole positions is respectively performed, including: Providing an in-position detection signal through one of the pins at the test hole position, and obtaining an in-position feedback signal according to another pin at the test hole position; the in-position feedback signal is generated by the VCSEL chip according to the in-position detection signal; A target test hole position among the plurality of test hole positions is determined according to the in-situ feedback signal.

5. The VCSEL chip testing method according to claim 3, characterized in that: The performing in-situ testing on each of the test holes to determine at least one target test hole among the multiple test holes comprises: Performing in-situ testing on each of the test hole positions to determine the test hole position connected to the VCSEL chip; The numbers of the test holes connected to the VCSEL chips are displayed on the interactive interface; The target test hole position is determined in response to a user operation on the interactive interface.

6. The VCSEL chip testing method according to claim 1, characterized in that: Before determining the target test equipment according to the target test items corresponding to each VCSEL chip, the method further includes: Obtain the model of the VCSEL chip connected to the target test hole; The test items corresponding to the target test holes are determined according to the models of the VCSEL chips.

7. The VCSEL chip testing method according to claim 6, characterized in that: The method further comprises: Determining the evaluation strategy of the corresponding target test hole position according to the model of each VCSEL chip; According to the test data collected by each target test device and the evaluation strategy, the test results of each target test hole position are obtained respectively.

8. The VCSEL chip testing method according to claim 7, characterized in that: The step of sequentially controlling each of the target test devices to test the VCSEL chip along the test route includes: Determine the priority of each of the target test items according to the evaluation strategy; In the case where the multiple target test items corresponding to the VCSEL chip include test items of multiple priorities, the control motion module sequentially drives the target test devices corresponding to the target test items of the multiple priorities to test the VCSEL chip according to the priority order; The step of obtaining the test results of each target test hole position according to the test data collected by each target test device and the evaluation strategy includes: When the test data of the test items of all priorities meet the corresponding evaluation requirements, the test result of the target test hole position is determined to be qualified.

9. The VCSEL chip testing method according to claim 8, characterized in that: The multiple target test items include test items of two priorities, the first priority items include at least one of spectrum test and LIV test, and the second priority items include at least one of near field test and far field test.

10. The VCSEL chip testing method according to claim 7, characterized in that: The step of obtaining the test results of each target test hole position according to the test data collected by each target test device and the evaluation strategy includes: Determine the weight of each target test item according to the evaluation strategy; Obtaining a test score of the VCSEL chip connected to the target test hole position according to the test data of each target test item and the weight; When the test score meets the corresponding evaluation requirements, the test result of the target test hole position is determined to be qualified.

11. The VCSEL chip testing method according to any one of claims 7 to 10, characterized in that: The method further comprises at least one of the following: The hole number of each target test hole and the model of the connected VCSEL chip are displayed on the interactive interface respectively; The hole number of each target test hole and the corresponding test parameters of the target test item are displayed on the interactive interface respectively; the test parameters include at least one of spectral test conditions, LIV test conditions, near-field test conditions and far-field test conditions; The hole number of each target test hole and the corresponding test data collected by each target test device are displayed on the interactive interface respectively; The hole number of each target test hole and the corresponding evaluation strategy are displayed on the interactive interface.

12. The VCSEL chip testing method according to claim 1, characterized in that: Before determining the target test equipment according to the target test items corresponding to each VCSEL chip, the method further includes: Acquire manufacturing information and aging identification of the VCSEL chip; the manufacturing information includes at least one of a batch number, a manufacturing order number, and a wafer ID, and the aging identification includes unaged and aged; When the aging mark of the VCSEL chip indicates that the chip has been aged, the test items when the VCSEL chip with the same manufacturing information has not been aged are used as the target test items for the current test.

13. The VCSEL chip testing method according to claim 12, characterized in that: The method further comprises: After completing the test on the VCSEL chip with the aging mark as aged, the test data of the VCSEL chip with the same manufacturing information before and after aging are compared.

14. The VCSEL chip testing method according to claim 1, characterized in that: The method further comprises: generating a data graph according to the test data collected by the target test device; Displaying the data graph on an interactive interface; Wherein, generating a data graph according to the test data collected by the target test device includes at least one of the following: In the case where the test items include spectrum testing, generating an OSA curve according to the spectrum testing data; In the case where the test items include LIV test, generating a light-current-voltage curve according to LIV test data; In the case where the test items include near-field testing, generating a near-field light intensity distribution diagram according to the near-field test data; In the case where the test items include far-field testing, a far-field light intensity distribution diagram is generated according to the far-field testing data.

15. A VCSEL chip testing system, characterized in that: include: A multi-channel VCSEL chip testing device, comprising a driving test board, a motion module and a plurality of testing devices for performing different test items, wherein the driving test board comprises a plurality of testing holes, each of which is respectively used to electrically connect a corresponding VCSEL chip to provide a driving signal to the connected VCSEL chip, and the motion module is respectively connected to the plurality of testing devices to drive the connected testing devices to move to a target position to perform a test; A host computer is connected to the multi-channel VCSEL chip testing device and is used to execute the VCSEL chip testing method according to any one of claims 1 to 14.

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