Circuit for voltage offset compensation

Abstract

The embodiment of the invention relates to a circuit for voltage offset compensation. A circuit includes a current source, a differential pair of transistors coupled with the current source, an active load, and a current injection circuit. The transistors of the differential pair have a first offset voltage and an input transconductance. The current injection circuit is configured to supply the first current and the second current, thereby generating a second offset voltage across the transistors of the differential pair, the second offset voltage being opposite the first offset voltage. The first current and the second current have the same thermal dependency as the input transconductance of the transistors of the differential pair.

Description

Technical Field

[0001] The present invention relates generally to electronic circuits, and in particular to circuits for voltage offset compensation. Background Art

[0002] Analog comparators and operational amplifiers are important components in CMOS analog circuit design. However, the accuracy of the analog function may be affected by the input voltage V IN+ With V IN- The input-dependent offset voltage V OS This offset voltage appears in analog comparator and op amp circuits due to device mismatch. For example, random offset voltages are generated by device mismatch caused by process variations in devices that are assumed to be identical pairs, such as transistors in a differential pair (also called a long-tailed pair) or current mirrors in an active load. Conventional source-coupled differential pairs used in such devices can typically achieve an input offset voltage V in the range of ±5mV. OS To achieve the desired circuit performance, offset compensation (also called voltage offset trimming or just trimming) can be used to reduce the offset voltage V OS .

[0003] Device mismatch produces offset voltage V OS The main contributors to are the parameters associated with the first-order MOS transistor saturated drain current equation (1):

[0004]

[0005] That is, the threshold voltage V TH And the gain factor β = μ n,p C ox (W / L). The gain factor β depends on the electron / hole mobility μ n,p , gate oxide capacitance per unit area C ox And the channel aspect ratio W / L. In the saturation state, the gate-source voltage V GS The threshold voltage V can be expressed by equation (1) TH and overload voltage V OV The sum of:

[0006]

[0007] Small changes in ΔV GS Resulting in a corresponding change ΔI D , corresponding to the change ΔI D The transconductance g can be obtained by evaluating the derivative of equation (1) m to be sure.

[0008]

[0009] In addition to the layout quality, the matching error may roughly follow the Pelgrom model, which will contribute σ(ΔV T ) and σ(Δβ / β) are related to the transistor active area W·L:

[0010]

[0011] In this model, A VT and A β is a parameter of mismatch. Improving the matching by increasing the differential pair area may result in a serious increase in parasitic capacitance and silicon area. In contrast, reducing the offset by circuit design allows maintaining reasonable area efficiency as well as the frequency characteristics of the operational amplifier or comparator. Summary of the invention

[0012] According to an embodiment, a circuit includes: a current source; a differential pair of transistors, the transistors of the differential pair are coupled to the current source, the transistors of the differential pair have a first offset voltage and an input transconductance; an active load, the active load is coupled to the corresponding drains of the transistors of the differential pair opposite to the current source; and a current injection circuit, the current injection circuit is coupled to the corresponding drains of the transistors of the differential pair, the current injection circuit is configured to supply a first current and a second current to the corresponding drains, the first current and the second current generate a second offset voltage across the transistors of the differential pair, the second offset voltage is opposite to the first offset voltage, and the first current and the second current have the same thermal dependence as the input transconductance of the transistors of the differential pair.

[0013] According to another embodiment, a circuit includes: a current source, the current source is coupled to a supply voltage node; a differential pair of transistors, the transistors of the differential pair are coupled to the current source opposite to the supply voltage node, the transistors of the differential pair have a first offset voltage and an input transconductance, and the input transconductance has a thermal dependency; an active load, the active load is coupled to the transistors of the differential pair opposite to the current source, the active load includes a first current mirror, each transistor of the first current mirror is coupled to the supply voltage node across a corresponding source resistance, each transistor of the first current mirror is also coupled to a corresponding unipolar current source, wherein the corresponding unipolar current source is configured to generate a first current and a second current; and a current injection circuit, the current injection circuit is coupled to a corresponding node between the drains of the transistors of the differential pair and the active load, the current injection circuit is configured to supply the first current and the second current to the corresponding node between the drains of the transistors of the differential pair and the active load, the first current and the second current generate a second offset voltage across the transistors of the differential pair, the second offset voltage is opposite to the first offset voltage, and the first current and the second current have the same thermal dependency as the input transconductance of the transistors of the differential pair.

[0014] According to yet another embodiment, a circuit includes: a differential pair, the differential pair including a first transistor and a second transistor, the first transistor and the second transistor being coupled through a first resistor; a first programmable current source, the first programmable current source being coupled to a first node, the first node being between the first transistor and the first resistor; a second programmable current source, the second programmable current source being coupled to a second node, the second node being between the second transistor and the first resistor; and a first bias current source, the first bias current source being coupled to the differential pair.

[0015] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure, as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] For a more complete understanding of the present invention and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which:

[0017] Figure 1 illustrates a schematic diagram of an example operational transconductance amplifier;

[0018] Figure 2 illustrates a schematic diagram of another example operational transconductance amplifier;

[0019] Figure 3 illustrates a schematic diagram of yet another example operational transconductance amplifier;

[0020] Figure 4 and Figure 5 illustrates a schematic diagram of a circuit including temperature compensated programmable current injection according to some embodiments;

[0021] Figure 6 and Figure 7 illustrates a schematic diagram of a circuit including a current mirror circuit with current injection according to some embodiments;

[0022] Figure 8 , Fig. 9 , Fig.10 and Fig.11 illustrates a schematic diagram of a circuit including tail offset voltage trimming according to some embodiments;

[0023] Fig.12 A schematic diagram illustrating a circuit for an offset voltage according to some embodiments; and

[0024] Fig.13 A schematic diagram of an operational transconductance amplifier configured for trimming with temperature compensated current injection is illustrated in accordance with some embodiments.

[0025] Unless otherwise indicated, corresponding reference numerals in different figures generally refer to corresponding parts. The figures are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale. The edges of features drawn in the figures do not necessarily indicate the end of the scope of the features. DETAILED DESCRIPTION

[0026] The making and use of various embodiments will be discussed in detail below. However, it should be understood that the various embodiments described herein are applicable to a wide range of specific contexts. The specific embodiments discussed only illustrate specific methods for making and using various embodiments and should not be interpreted in a limited sense. The specific embodiments only illustrate specific configurations and do not limit the scope of the claimed embodiments. Unless otherwise stated, features from different embodiments may be combined to form other embodiments.

[0027] The variations or modifications described in one embodiment may also be applicable to other embodiments. In addition, various changes, substitutions and modifications may be made without departing from the spirit and scope of the present disclosure defined by the appended claims.

[0028] According to one or more embodiments of the present disclosure, the present application relates to circuits and operating methods that provide voltage offset compensation while also reducing the temperature dependence of the compensated offset voltage. Embodiments of the disclosed circuits and methods may help significantly reduce temperature drift while reducing voltage offset. Temperature compensated current injection for offset voltage trimming can be performed between a differential pair and an active load. An active load current mirror can be used to apply a temperature compensated voltage offset. A tail voltage generation circuit can provide offset voltage trimming with temperature stability. The offset voltage can also be provided after the gate of the differential pair transistor. By selectively applying temperature transconductance damping to a PMOS or NMOS transistor using a selected resistor, the temperature stability of the transconductance ratio between the current mirror and the differential pair can be improved. This can improve the residual temperature stability of the trimmed and untrimmed offset voltages.

[0029] Figure 1-Figure 3 A schematic diagram of an example operational transconductance amplifier (OTA) having a PMOS differential pair is illustrated. Figure 1 FIG. 4 shows a schematic diagram of a Miller OTA with two gain stages. Figure 2 shows the schematic diagram of a single gain stage symmetrical OTA, and Figure 3 A folded cascode OTA with a single gain stage is illustrated. Embodiments of the disclosed system and method for voltage offset compensation may be applied to Figure 1-Figure 3 Any of the OTAs shown, and any other suitable OTA or other circuits. Figure 1-Figure 3Some of the widely used operational transconductance amplifiers (OTAs) shown here form the basis of most operational amplifiers and comparators. OS Mainly caused by mismatches in the transistors of the differential pair receiving the input voltage or in the active load comprising one or more current mirrors.

[0030] Figure 1 A schematic diagram of an example of a PMOS differential pair Miller operational transconductance amplifier (OTA) 100 with two gain stages is illustrated. The Miller OTA 100 accepts two input voltages with the aid of differential pair transistors and outputs a signal that is the difference of the input voltages boosted by the gains of the two gain stages.

[0031] The bias current source 102 is coupled to provide a supply voltage V DD , and is coupled to node 103. In some examples, bias current source 102 is a transistor (e.g., a PMOS or NMOS device) coupled to a bias voltage at its gate. However, any suitable current source may be used for bias current source 102. Bias current source 102 may be coupled at its source terminal to a supply voltage V DD 103. The bias current source 102 may also be coupled to the supply voltage node at its drain terminal and to the node 103 at its source terminal. The source terminal and the drain terminal of a CMOS transistor may also be interchangeably referred to as source / drain terminals or terminals.

[0032] Transistors 104 and 106 form a differential pair (also referred to as a long-tail pair). Transistors 104 and 106 are also referred to as input transistors. The terminals of transistors 104 and 106 are coupled to node 103, which receives bias current I0 from bias current source 102 and is at tail voltage V TAIL . is provided with a corresponding input voltage V IN+ and V IN- The terminals of are coupled to the gate of transistor 104 and the gate of transistor 106, respectively. In some examples, transistors 104 and 106 of the differential pair are PMOS devices. However, any suitable transistors, such as NMOS devices, etc., can be used to form the differential pair.

[0033] The active load is formed by transistors 114 and 116. In some examples, transistors 114 and 116 are NMOS devices. However, any suitable transistor, such as a PMOS device, etc., can be used to form the active load. The terminal of transistor 114 is coupled to the terminal of transistor 104 opposite to node 103 through node 120, and the terminal of transistor 116 is coupled to the terminal of transistor 106 opposite to node 103 through node 122. Current I1 flows from transistor 104 to node 120, and current I2 flows from transistor 106 to node 122. The corresponding terminals of transistors 114 and 116 opposite to the differential pair are coupled to the ground node. The corresponding gates of transistors 114 and 116 are coupled to each other and to node 122.

[0034] Current source 192 is coupled between the supply voltage node and the terminal of output transistor 118 through node 124. Current source 192 can provide a current k·I0, where k is a suitable constant, such as 0.5. In some examples, output transistor 118 is an NMOS device. However, any suitable transistor can be used. Current source 192 provides current k·I0 to node 124. The opposite terminal of output transistor 118 is coupled to a ground node, and the gate of output transistor 118 is coupled to node 122. Provided with an output voltage V OUT The output voltage node of is coupled to node 124 .

[0035] Figure 2 Illustrated is a schematic diagram of an example single gain stage symmetrical OTA 200. The single gain stage symmetrical OTA 200 accepts two input voltages by means of a differential pair of transistors and outputs a voltage that is the difference of the input voltages amplified by the gain of the OTA. A current mirror is used to establish symmetrical operation.

[0036] The bias current source 102 is coupled to provide a supply voltage V DD The supply voltage node and node 103. The respective terminals of the differential pair of transistors 104 and 106 are coupled to node 103, which receives the bias current I0 from the bias current source 102 and is at the tail voltage V TAIL The corresponding input voltage V IN+ and V IN- The terminals at are coupled to the gates of transistors 104 and 106, respectively.

[0037] The active load is formed by transistors 214, 216, 218, 224, 226, and 228. In some examples, transistors 214, 216, 218, and 224 are NMOS devices and transistors 226 and 228 are PMOS devices. However, any suitable transistors, such as PMOS devices, etc., may be used. The terminal of transistor 214 is coupled to the terminal of transistor 104 opposite to node 103 through node 220, and the terminal of transistor 216 is coupled to the terminal of transistor 106 opposite to node 103 through node 222. Current I1 flows from transistor 104 to node 220, and current I2 flows from transistor 106 to node 222. Respective terminals of transistors 214 and 216 opposite to the differential pair are coupled to the ground node. The gate of transistor 214 is coupled to the gate of transistor 224 and node 220. The gate of transistor 216 is coupled to the gate of transistor 218 and node 222.

[0038] The terminals of transistor 226 are coupled to a supply voltage node and a node 238, and the terminals of transistor 224 are coupled to a ground node and a node 238. The gate of transistor 228 is coupled to node 238 and the gate of transistor 228. Transistors 228 and 232 are coupled in series between the supply voltage node and node 236. Transistors 232 and 234 form a common source and common gate (also referred to as a common source and common gate transistor). In some examples, transistors 232 and 234 are PMOS devices. However, any suitable transistors, such as NMOS devices, etc., may be used. Transistors 234 and 218 are coupled between node 236 and a ground node. The respective gates of common source and common gate transistors 232 and 234 are coupled to provide a bias voltage V b One or more bias voltage nodes. Provided with an output voltage V OUT The output voltage node of is coupled to node 236.

[0039] Figure 3 A schematic diagram of an example folded cascode OTA 300 is illustrated, which is also referred to as a folded cascode OTA with a single gain stage. The folded cascode OTA 300 accepts two input voltages with the aid of a differential pair of transistors and outputs a signal that is the difference of the input voltages amplified by the gain of the OTA. The folded cascode can improve the gain and linearity of the OTA.

[0040] The bias current source 102 is coupled to provide a supply voltage V DD The supply voltage node and node 103. The respective terminals of the differential pair of transistors 104 and 106 are coupled to node 103, which receives the bias current I0 from the bias current source 102 and is at the tail voltage V TAIL The corresponding input voltage VIN+ and V IN- The terminals at are coupled to the gates of transistors 104 and 106, respectively.

[0041] The active load is formed by transistors 314, 316, 322, and 324. Transistors 314 and 316 form a first current mirror and transistors 322 and 324 form a second current mirror. In some embodiments, transistors 314 and 316 are NMOS devices and transistors 322 and 324 are PMOS devices. However, any suitable transistors may be used to form the active load. The terminal of transistor 314 is coupled to the terminal of transistor 104 opposite to node 103 through node 320, and the terminal of transistor 316 is coupled to the terminal of transistor 106 opposite to node 103 through node 340. Current I1 flows from transistor 104 to node 320, and current I2 flows from transistor 106 to node 340. Respective terminals of transistors 314 and 316 opposite to the differential pair are coupled to a ground node. Respective gates of transistors 314 and 316 are coupled to a voltage providing a bias voltage V b1 The current I3 flows from the transistor 314 to the ground node, and the current I4 flows from the transistor 316 to the ground node.

[0042] The folded cascode includes transistors 332 and 334 (also referred to as cascode transistors). In some examples, transistors 332 and 334 are NMOS devices. However, any suitable transistors may be used to form the folded cascode.

[0043] Transistors 322 and 326 are coupled in series through their terminals between the supply voltage node and node 338, and transistors 324 and 328 are coupled in series through their terminals between the supply voltage node and node 336. The gates of transistors 322 and 324 are coupled to node 338, and the gates of transistors 326 and 328 are coupled to a bias voltage V b3 The bias voltage node.

[0044] Transistor 332 is coupled through its terminals between nodes 320 and 338, and transistor 334 is coupled through its terminals between nodes 340 and 336. Current I5 flows from node 338 into transistor 332, and current I6 flows from node 336 into transistor 334. The gates of transistors 332 and 334 are coupled to a bias voltage V b2 The bias voltage node is provided with an output voltage V OUT The output voltage node of is coupled to node 336.

[0045] Embodiments of the present disclosure are described in the context of the accompanying drawings. Embodiments of a circuit including a temperature compensated programmable current injection will use Figure 4 and Figure 5 The embodiment of the current mirror circuit with current injection will use Figure 6 and Figure 7 The embodiment of the tail voltage generating circuit will use Figure 8 , Fig. 9 , Fig.10 and Fig.11 An embodiment of the circuit for gate input offset voltage will use Fig.12 The operational transconductance amplifier embodiment will use Fig.13 In the present invention, an operational transconductance amplifier is configured for trimming by means of temperature compensation current injection and allows adjustment of the transconductance temperature characteristic.

[0046] The first gain stage of a typical comparator or operational amplifier (e.g., one using CMOS devices) comprises a source-coupled differential pair and one or more current mirrors operating as active loads (see above, Figure 1-Figure 3 ). Ideally, when ΔV IN = 0, the currents at the output branches are balanced. In other words, if the terminals of the OTA are short-circuited, the input differential voltage should ideally be zero and the output current should also be zero. However, there is usually an offset voltage V due to device mismatch in the differential pair or current mirror of the active load. OS This device mismatch may occur due to process variations in the devices of the assumed identical pair. Under this condition, the output voltage V OUT Equal to the supply voltage V DD About half of.

[0047] Derived from the threshold voltage difference ΔV TH(IN) and the gain factor difference Δ(β / β) between the input transistors (eg, transistors 104 and 106) IN The input-dependent offset voltage V OS It can be expressed as equation (5):

[0048]

[0049] Large aspect ratio (W / L) in the structure of the input transistor IN resulting in a relatively low overload voltage V OV In this case, the principal component of equation (5) is ΔV TH(IN) . In large (W / L) IN and low differential pair bias current, the differential pair can operate in the subthreshold region. In this case, equation (5) may no longer apply. However, while subthreshold operation can provide advantages such as improved transconductance, it can also result in an offset voltage V OS The temperature drift decreased slightly.

[0050] Active load current mirror (e.g., transistors 314 and 316; see above, Figure 3 ) in the mismatch ΔV TH(CM) and Δ(β / β) CM An offset is created between currents I1 and I2 (see above, Figure 3 ). The offset ΔI in the OTA current mirror CM / I D(0) can be written as:

[0051]

[0052] Among them I D(0) is the drain current, e.g. in the example OTA example, I D(0) =0.5·I0. Compared with the differential pair, the current mirror can operate at a high overload (in other words, low W / L), which helps to reduce the current mirror offset ΔI CM Advantageously, the folded cascode OTA 300 (see above, Figure 3 ) reduces the I of the second current mirror including transistors 322 and 324. D(0) .

[0053] Current mirror offset ΔI CM Reference input V OS , as shown in equation (7):

[0054]

[0055] where g m(IN) represents the transconductance of the differential pair, and ΔI CM(n) represents the contribution of the corresponding current mirror in the OTA.

[0056] Equations (5), (6), and (7) can be rewritten to emphasize their dependence on the main bias current I0. The offset voltage V in equation (5) is derived from the differential pair in saturation. OS(IN) can be rewritten as equation (8):

[0057]

[0058] And the current offset due to current mirror mismatch in equation (6) can be rewritten as equation (9):

[0059]

[0060] The previous equations can be combined using equation (7) to convert the total offset voltage V OS Expressed as design variables gain factor β, bias current I0, and matching error Δ(β / β) IN,CMn and ΔVTH(IN,CMn) This leads to the general offset formula for an OTA with a transistor operating in saturation, as shown in equation (10):

[0061]

[0062] For some OTAs with an integer number of current mirrors, the factor Δ(β CMn / β CMn ) and ΔV TH(CMn) should be included in equation (10) according to the appropriate drain current I D(0) Scaling. ΔV TH , Δβ / β, and I0 can be considered first order and independent of temperature and bias. However, the differential pair gain factor β IN and the current mirror gain factor β CM The embodiment of the present disclosure includes a method for reducing the gain factor β of the differential pair. IN and the current mirror gain factor β CM The thermal drift caused by the offset voltage V OS circuit and method of operation.

[0063] Typically, for low overload differential pairs or differential pairs operating in the subthreshold region, ΔV TH(IN) is the offset voltage V OS The main factor that contributes to V is the threshold voltage V between the differential pair transistors (e.g., between transistors 104 and 106). TH Its value may depend on the input transistor active area (W·L) IN Therefore, ΔV TH(IN) may exhibit very good temperature stability, resulting in an uncompensated V OS Low thermal drift dV OS / dT.

[0064] Mismatch factor Δβ IN / β IN and Δβ CMn / β CMn It may be due to the lithography accuracy and the spatial gradient of carrier mobility. Both are determined by the term √(I 0,D(0) / (4β IN )) are weighted. They have an effect on the offset voltage V OS The contribution depends on the bias current I0, the drain current I D(0) , temperature, gain factor β IN =μ n,p C ox (W / L) INand the corresponding areas of the input differential pair transistors and the current mirror transistors. In the case of low overload differential pairs and high overload current mirrors, the overall contribution is typically low and can be considered negligible.

[0065] ΔV TH(CMn) Contribution to ΔV TH(IN) Equivalent and according to the transconductance ratio g m(CMn) / g m(IN) This ratio represents the voltage gain between the gate and input terminals of the current mirror n. Therefore, all ΔV TH(CMn) The overall contribution may be lower than ΔV TH(IN) When the channel doping polarity of the differential pair is the same as that of the current mirror n, g m(CM) right Dependencies can be reduced or eliminated In this case, ΔV TH(CMn) V OS The contribution has a very low temperature drift, similar to ΔV TH(IN) Very low thermal drift contribution.

[0066] The programmable current I AUX Injecting the corresponding terminals (e.g., drain terminals) of the differential pair (e.g., transistors 104 and 106) allows the offset voltage V OS The cancellation of IN = 0), reaching equilibrium (where the output voltage is at the supply voltage V DD The adjustable current source is implemented as a current-steering digital-to-analog converter (DAC) with discrete steps. The value of the discrete steps is determined by the offset trim step size and can be very small, such as in the nA range. The programmable current source can be implemented as a bipolar current source (in other words, a single source that delivers either positive or negative current), as two unipolar current sources, such as a left (L) source and a right (R) source. In the two unipolar current source configuration, each source can compensate for the offset voltage V OS In other words, a current source compensates for the positive offset voltage V OS And another current source compensates for the negative offset voltage V OS .

[0067] The programmable current I AUX The generated offset voltage V OS(IAUX) Appears at the input voltage terminal V IN+ With V IN- As shown in equation (11):

[0068]

[0069] where gm(IN) is the differential pair transconductance:

[0070]

[0071] Offset voltage compensation for V OS(IAUX) =–V OS is achieved. Although the offset voltage may be mainly determined by the thermally stable ΔV TH(IN) OK, but the differential pair transconductance g m(IN) Including carrier mobility μ n,p (T) is the temperature dependent term. Therefore, the compensated offset voltage V in equation (11) is OS(IAUX) may have high temperature drift. Therefore, with the initial uncompensated offset voltage V OS In contrast, with the thermally unstable transconductance g m(IN) To compensate for the relatively thermally stable offset voltage ΔV TH(IN) Can result in significantly higher thermal drift dV OS / d T.

[0072] Provides a programmable current I with appropriate thermal function AUX(L,R) (T) can reduce or eliminate the temperature drift of the compensation described above in relation to equation (12). From equation (11), it can be concluded that the programmable current I AUX(L,R) The preferred temperature characteristic of (T) can be compared with the input differential pair transconductance g m(IN) Same as (see above, equation (12)). This compensates the programmable current I AUX(L,R) (T) thus generating a temperature-stable input offset V OS(AUX) , input offset V OS(AUX) The temperature-stable or weakly temperature-dependent terms in equation (10) (e.g., those caused by high g m(CM) / g m(IN) ratio decay term).

[0073] Figure 4 and Figure 5 A schematic diagram of a circuit is shown, the circuit comprising temperature compensated programmable current generator(s) provided by complementary current mirrors. Figure 4 FIG. 4 is a schematic diagram of a current source 400 according to some embodiments, the current source 400 provides a current with a desired compensated thermal dependency to match the thermal dependency of an OTA input differential pair. The current source 400 includes a reference transistor 402, source transistors 404 and 406, a reference current source I REF and auxiliary offset voltage sources 412 and 414. In some embodiments, reference transistor 402 and source transistors 404 and 406 are PMOS devices. However, any suitable transistors may be used. The polarity of the temperature compensated current generator transistor is preferably the same as the channel polarity of the differential pair.

[0074] The reference current source 410 provides a reference current I REF , reference current I REF The reference current source 410 is coupled between the ground node and the node 416. The reference transistor 402 is coupled to provide a supply voltage V DD 416. The source transistors 404 and 406 are coupled to the supply voltage node through respective terminals. The auxiliary offset voltage source 412 is coupled to the gate of the reference transistor 402 through a node 418 and to the gate of the source transistor 404. The auxiliary offset voltage source 414 is coupled to the gate of the reference transistor 402 through a node 420 and a node 418, to the reference current source 410 through nodes 420 and 416, and to the gate of the source transistor 406. The node 420 is coupled to nodes 416 and 418. The temperature-dependent current I s(L) and I s(R) Flows out of the terminals of source transistors 404 and 406 opposite the supply voltage node.

[0075] In some embodiments, reference transistor 402 forms a supplementary current mirror with source transistors 404 and 406, which includes an auxiliary offset voltage V OS(CM) , auxiliary offset voltage V OS(CM) is applied between the respective gates of reference transistor 402 and the respective gates of source transistors 404 and 406. In other embodiments, the described complementary current mirror is implemented in a cascode variant. The drain current I s(L) and the drain current I of the source transistor 406 s(R) (Equivalent to Figure 5 The source transistors 504 and 506 in the circuit will be relative to the reference current I REF Drift occurs, which is expressed as the auxiliary current I AUX(L) (T) = I REF –I S(L) (T) and I AUX(R) (T) = I REF –I S(R) (T). The offset current I generated by the current source 400 and used to provide temperature stable compensation of the OTA OS is the auxiliary current difference I OS =I AUX(L) (T)-I AUX(R) (T).

[0076] I for a given temperature OS The drift of I can be determined using the drain current formula (see above, equation (1)). REF can be written as:

[0077]

[0078] Where W / L refers to the aspect ratio of transistors 402, 404, and 406. For a given reference current I REF , the gate-source voltage V of the reference transistor 402 GS(R) can be isolated from equation (13), as in equation (16):

[0079]

[0080] The drain current I of each source transistor 404 and 406 is S By V GS(R) +V OS(CM) It turns out that:

[0081]

[0082] Combining equation (14) and equation (15) and from the reference current I REF Subtract the result from the current difference I OS =I REF –I S :

[0083]

[0084] The term in equation (16) can be ignored. The remaining first term in equation (16) is related to the input differential transconductance g m(IN) = (see above, equation (12)). By substituting the offset current I OS Injection differential pair (e.g., transistors 104 and 106; see above, Figure 1-Figure 3 ) of the drain terminal, at the input voltage terminal V IN+ With V IN The input offset voltage V OS(AUX) The offset voltage is determined by I OS / g m(IN) It is generated and can be expressed by equation (12) and equation (16) as:

[0085]

[0086] In this equation, W / L, C OX ,I REF and I0 are constant terms with no temperature contribution. When considering the same channel polarity of the differential pair and the current source 400, the numerator and denominator terms μ n,p cancel each other out. In this case, equation (17) can be simplified to:

[0087]

[0088] Where α represents the constant term in equation (18). Figure 5 The Folded Cascode OTA 500 provides a threshold voltage difference ΔV for the input differential pair. TH(IN) In addition to compensation, I OS It is also ΔV in equation (10) TH(CM5,6) This is because the current mirror transistors 322 and 324 have the same temperature stability as the input differential pair transistors 104 and 106 and the reference transistor 402 and the source transistors 404 and 406 (or Figure 5 The source transistors 504 and 506 have the same channel polarity.

[0089] Figure 5 A schematic diagram of a folded cascode OTA 500 with current injection from a temperature compensated current source is illustrated in accordance with some embodiments. The folded cascode OTA 500 includes a current source (also referred to as a current injection circuit) that provides a current with a compensated thermal dependency to match the thermal dependency of the OTA input differential pair transconductance (e.g., a current source similar to current source 400; see above, Figure 4 ). This uses the example folded cascode OTA 300 (see above, Figure 3 ) is implemented, and the details are not repeated herein. However, embodiments of providing a current source with a current that compensates for thermal dependence may be implemented in any suitable OTA or comparator circuit, including but not limited to Figure 1 and Figure 2 examples, and all such combinations are within the scope of the disclosed embodiments.

[0090] In the folded cascode OTA 500, the terminals of the reference transistor 402 are coupled to the supply voltage node across the source resistor 522, and the terminals of the source transistors 504 and 506 are coupled to the supply voltage node across the corresponding source resistors 524 and 526, respectively. The source transistors 504 and 506 are equivalent to the source transistors 404 and 406 of the current source 400, respectively (see above, Figure 4 ). Source transistors 504 and 506 may also be cascoded. Reference current source 410 is coupled to a terminal of reference transistor 402 opposite source resistor 522 and to a respective gate of reference transistor 402 and respective gates of source transistors 504 and 506. Programmable current source 512 is coupled to node 528 between source resistor 524 and source transistor 504, and programmable current source 514 is coupled to node 530 between source resistor 526 and source transistor 506. In some embodiments, programmable current sources 512 and 514 are unipolar current sources.

[0091] In some embodiments, the respective bases (also referred to as bulk terminals) of source transistors 504 and 506 are coupled to nodes 528 and 530, respectively, and the base of reference transistor 402 is coupled to node 540 between source resistor 522 and reference transistor 402. Electrically coupling the transistor base or bulk to a terminal (e.g., source of the respective transistor) may be advantageous by reducing or eliminating substrate effects of the transistor, thereby maintaining desired temperature characteristics. Bulk-source coupling may be included for any transistor of the disclosed embodiments.

[0092] Terminals of source transistors 504 and 506 opposite source resistors 524 and 526 are coupled to nodes 532 and 534, respectively, to provide offset current injection between the differential pair and the active load.

[0093] Auxiliary offset voltage sources 412 and 414 (see above, Figure 4 ) between the corresponding gates of the complementary current mirror gates can be implemented using a large number of additional bias circuits. Figure 4 Another way of thinking about the concept, Figure 5 The folded cascode OTA 500 introduces a supplementary current mirror, which includes a reference transistor 402 and source transistors 504 and 506, with an additional source resistor R OS (across corresponding source resistors 522, 524, and 526) and programmable current sources 512 and 514. In some embodiments, programmable current sources 512 and 514 are unipolar current steering DACs. These current sources adjust the currents by the product R OS I REF The voltage V across source resistors 524 and 526 given by programmable current sources 512 and 514 (eg, DACs) is AUX(L,R) For a unipolar current source, the offset voltage V OS The initial polarity, voltage V AUX(L,R) Can be on left or right R OS In this configuration, the offset current I OS The value of the difference I AUX(L) –I AUX(R) To provide efficient temperature compensation of the offset voltage, V generated by the quiescent current and programmable current sources 512 and 514 (eg, DACs) is AUX(L,R) The voltage on should be temperature stable.

[0094] Figure 6 and Figure 7 The schematic diagram of the circuit includes the adjustment by means of an active load current mirror. OSThe offset voltage of / d T can be compensated by adjusting the offset voltage V between the gates of the current mirror. OS(CM) To provide, for example, a current mirror having the same channel doping polarity as the differential pair transistors 104 and 106 .

[0095] Figure 6 A schematic diagram of a current mirror circuit 600 for adjusting an offset voltage using current injection is shown, the current mirror circuit 600 including transistors 322 and 324. The current mirror circuit 600 (also referred to as a current injection circuit) can be part of a larger circuit such as an OTA or a comparator. In some embodiments, the current mirror circuit is similar to the example folded cascode OTA 300 (see above, Figure 3 ) is part of a folded cascode OTA of FIG. In current mirror circuit 600, transistors 322 and 324 are coupled to a supply voltage node across respective source resistors 624 and 626. Node 338 is coupled to respective gates of transistors 322 and 324, and a terminal of transistor 322 opposite source resistor 624.

[0096] Programmable current source 512 is coupled to node 632 between source resistor 624 and transistor 322, and programmable current source 514 is coupled to node 634 between source resistor 626 and transistor 324. Programmable current sources 512 and 514 provide respective injection currents I AUX(L) and I AUX(L) In some embodiments, programmable current sources 512 and 514 are unipolar current sources. In some embodiments, the respective bases (also referred to as body terminals) of transistors 322 and 324 are coupled to nodes 632 and 634, respectively. Electrically coupling the transistor base or body to a terminal (e.g., the source of the transistor) may be advantageous by reducing or eliminating substrate effects of the transistor.

[0097] The offset voltage V across the first current mirror including transistors 322 and 324 OS(CM) The voltage drop V across the left source resistor 624 and the right source resistor 626 is AUX(L) With V AUX(R) The difference between: V OS(CM) =V AUX(L) –V AUX(R) For the injected current I DAC(L,R) = 0, the voltage drop V AUX(L,R) is determined by the DC bias current of the first current mirror comprising transistors 322 and 324, and therefore V AUX(L) and V AUX(R) Equal. Current I L and I RThe current flows out from the terminals of transistors 322 and 324 opposite to source resistors 624 and 626 (eg, drain terminals of transistors 322 and 324). OS =I L -I R The mathematical formula and resulting temperature characteristics are equivalent to the above Figure 4-Figure 5 Therefore, the current mirror circuit 600 provides a current compensation circuit with low temperature drift dV by means of an active load current mirror including transistors 322 and 324. OS / dT compensation offset voltage.

[0098] Figure 7 A schematic diagram of a folded cascode OTA 700 with current injection for adjusting the offset voltage of active load current mirror(s) from a temperature compensated current source is illustrated in accordance with some embodiments. The folded cascode OTA 700 includes a current mirror circuit that provides an offset voltage with a compensated thermal dependency to match the thermal dependency of an OTA differential pair similar to that described using the example folded cascode OTA 300 (see above, Figure 3 ) implements an example current mirror circuit 600 (see above, Figure 6 ), and the details are not repeated herein. However, embodiments of a current mirror circuit providing an offset voltage with a compensated thermal dependency may be implemented in any suitable OTA or comparator circuit, including but not limited to Figure 1 and Figure 2 , and all such combinations are within the scope of the disclosed embodiments. Compensation for thermal dependency is achieved by applying trimming (in other words, programmable current) to a current mirror including transistors 322 and 324, which have the same polarity as the input differential pair (e.g., transistors 104 and 106). In order to provide efficient temperature compensation of the offset voltage, the voltage across the source resistors 524 and 526 generated by the quiescent current and programmable current sources 512 and 514 (e.g., DACs) is desirably temperature stable.

[0099] Figure 8 , Fig. 9 , Fig.10 and Fig.11 Schematic diagram of a circuit including tail offset voltage trimming is shown. Tail offset voltage trimming can be implemented using a circuit including a single source resistor or two source resistors between terminals (e.g., source terminals) of a differential pair of transistors (e.g., transistors 104 and 106). Figure 8 In the embodiment shown, the bias current I0 is divided into two current sources, each of which provides 1 / 2 I0, and the two programmable currents I AUX(L,R)is added to the terminals of the input differential pair transistors. Fig. 9 In the embodiment shown, two programmable currents I AUX(L,R) is coupled to the terminals of the differential pair of transistors (e.g., transistors 104 and 106), but only a single bias current I0 is present. Figure 8-Figure 11 The tail offset voltage trimming shown provides a constant transconductance g for the entire offset trim range. m(IN) The difference between the current I AUX(L) -I AUX(R) A voltage drop is created between the sources of the differential pair. This voltage drop induces an offset between the input terminals that compensates for the initial offset voltage. To provide efficient temperature compensation of the offset voltage, the quiescent current and the programmable current I AUX(L,R) The voltage generated (eg, by a DAC) across the source resistance(s) Ros of the differential pair transistors is ideally temperature stable.

[0100] Figure 8 FIG. 8 is a schematic diagram of a circuit 800 with tail offset voltage trimming and two bias current sources according to some embodiments. According to some embodiments, the circuit 800 includes a differential pair including transistors 104 and 106. The differential pair may be a OTA or a comparator (e.g., Figure 1 , Figure 2 or Figure 3 OTA) shown in FIG. However, the differential pair can be part of any suitable circuit. The differential pair can be implemented by NMOS devices and / or PMOS devices. The corresponding terminal of transistor 106 is coupled to bias current source 802 through node 842, and the corresponding terminal of transistor 104 is coupled to bias current source 802 through node 844. Bias current sources 802 each provide 1 / 2I0 of bias current I0 for the differential pair. Nodes 842 and 844 are coupled to each other through source resistor 810. In some embodiments, capacitor 812 is coupled in parallel with source resistor 810 between nodes 842 and 844. This may be beneficial to improve the differential pair input transconductance g m(IN) .

[0101] Programmable current source 512 is coupled to node 844 and programmable current source 514 is coupled to node 842. In some embodiments, programmable current sources 512 and 514 are bipolar current sources for supplying current to one or both nodes 842 and 844 (or Fig. 9 In some embodiments, the programmable current sources 512 and 514 are unipolar and provide a unipolar compensation current to one of the terminals of the transistors 104 and 106.

[0102] Fig. 9FIG. 1 is a schematic diagram of a circuit 900 that uses a bias current source for tail offset voltage trimming according to some embodiments. According to some embodiments, the circuit 900 includes a differential pair, and the differential pair includes transistors 104 and 106. The differential pair can be, for example, an OTA or a comparator (e.g., Figure 1 , Figure 2 or Figure 3 OTA) shown in FIG. However, the differential pair may be part of any suitable circuit. The respective terminals of transistor 106 are coupled to bias current source 102 via node 942, source resistor 920, and node 903, and the respective terminals of transistor 104 are coupled to bias current source 102 via node 944, source resistor 920, and node 903. Bias current sources 802 each provide 1 / 2I0 of bias current I0 for the differential pair. In some embodiments, capacitor 922 is coupled in parallel with source resistor 920 between nodes 942 and 944 (coupled in series via node 903). This may be advantageous in improving the differential pair input transconductance g. m(IN) Programmable current source 512 is coupled to node 944 , and programmable current source 514 is coupled to node 942 .

[0103] In some embodiments, the respective bases (also referred to as body terminals) of transistors 104 and 106 are coupled to nodes 944 and 942, respectively. Electrically coupling the transistor bases or bodies to the terminals (e.g., sources of transistors 104 and 106) may be advantageous by reducing or eliminating substrate effects of the transistors and thereby improving thermal stability of offset compensation.

[0104] Figure 8 The circuit 800 shown and Fig. 9 Both circuits 900 shown allow for temperature-stable compensation of the offset voltage to be provided. This is achieved when the voltage drop across source resistor 810 and / or source resistor 920 is temperature-stable. This can be achieved, for example, by using temperature-stable resistors and temperature-stable current sources. Since the voltage across these resistors is referenced to the input, the stable voltage across source resistors 810 and 920 compensates for the threshold voltage difference ΔV (e.g., of input differential transistors 104 and 106) that is primarily derived from TH The temperature stable offset voltage

[0105] Fig.10 FIG. 1 is a schematic diagram of a folded cascode OTA 1000 with tail offset voltage trimming according to some embodiments. The folded cascode OTA 1000 includes a folded cascode OTA 300 (see above) using an example Figure 3 ) of the circuit 800 (see above, Figure 8), and the details are not repeated here. However, the tail voltage trimming embodiment similar to circuit 800 can be implemented in any suitable OTA or comparator circuit, including but not limited to Figure 1 and Figure 2 Examples and Figure 5 , Figure 7 and Fig.13 The embodiments shown, and all such combinations are within the scope of the disclosed embodiments.

[0106] Fig.11 FIG. 1 is a schematic diagram of a folded cascode OTA 1100 with tail offset voltage trimming according to some embodiments. The folded cascode OTA 1000 includes a folded cascode OTA 300 (see above) using an example Figure 3 ) of the circuit 900 (see above, Fig. 9 ), and the details are not repeated here. However, the tail voltage trimming embodiment similar to circuit 900 can be implemented in any suitable OTA or comparator circuit, including but not limited to Figure 1 and Figure 2 Examples and Figure 5 , Figure 7 and Fig.13 The embodiments shown, and all such combinations are within the scope of the disclosed embodiments.

[0107] Fig.12 FIG. 1 is a schematic diagram of a circuit 1200 for providing a gate input offset voltage behind the gates of a differential pair of transistors according to some embodiments. In the case where the output resistance of the voltage source is relatively small, the offset voltage V AUX It may be generated directly between one or both gates of the input differential pair (eg, transistors 104 and 106 ) and the input voltage terminal.

[0108] The bias current source 1202 is coupled to provide a supply voltage V DD The bias current source 1202 is coupled to the bias voltage V at its gate. b However, any suitable current source may be used for biasing current source 102. Bias current source 1202 may be coupled at its source terminal to a supply voltage V DD The bias current source 102 may also be coupled to the supply voltage node at its drain terminal and to the node 103 at its source terminal.

[0109] Transistors 104 and 106 form a differential pair (also referred to as a long-tailed pair). The terminals of transistors 104 and 106 are coupled to node 103, which receives bias current I0 from bias current source 1202 and is at tail voltage V TAIL is provided with a corresponding input voltage V IN+ and V IN- The terminals of are coupled to the gates of transistors 104 and 106, respectively. In some examples, transistors 104 and 106 of the differential pair are CMOS devices. However, any suitable transistors, such as NMOS devices, etc., can be used to form the differential pair.

[0110] One or more programmable current sources 1212 inject current across the shunt resistor 1220. This generates a voltage drop V between the gate of transistor 104 and the voltage source. AUX . Using a temperature-stable shunt resistor, this trimming method provides reliable compensation for the temperature constant term in equation (10) above. The programmable current source 1212 can be used with the above Figure 5 The described programmable current sources 512 and 514 are similar and the details are not repeated here.

[0111] Embodiments of the circuit 1200 for providing an offset voltage behind the gates of a differential pair of transistors may be implemented in any suitable OTA or comparator circuit, including but not limited to Figure 1-Figure 3 Examples and Figure 5 , Figure 7 , Fig.10 , Fig.11 and Fig.13 The embodiments shown, and all such combinations are within the scope of the disclosed embodiments.

[0112] Fig.13 FIG. 1 shows a schematic diagram of a Miller OTA 1300 configured for trimming with temperature compensation current injection according to some embodiments. Figure 1) and the details are not repeated here. The corresponding resistor 1310 is coupled between the node 103 and the transistors 104 and 106. The corresponding resistor 1320 is coupled between the corresponding transistors 114, 116 and the output transistor 118 and the ground node. In some embodiments, the corresponding bases (also referred to as body terminals) of the transistors 104, 106, 114, 116 and 118 are coupled to the corresponding terminals (e.g., sources) of the transistors 104, 106, 114, 116 and 118. It may be advantageous to electrically couple the transistor base or body with the terminal (e.g., the source of the corresponding transistor) by reducing or eliminating the substrate effect of the transistor, thereby maintaining the desired temperature characteristics. For Figure 4-Figure 13 For any transistor of the disclosed embodiments, body-source coupling may be included.

[0113] Temperature compensation offset current injection is similar to the above Figure 5 The configuration described is performed similarly. The left programmable current I AUX(L) is injected at node 1342 between transistors 104 and 114, and the right programmable current I AUX(L) is injected at node 1344 between transistors 106 and 116. Reference current I REF is injected at node 1344 between current source 192 and output transistor 118. Figure 5 In the initial configuration, in order to compare the temperature characteristics of the offset current Ios(T) with the input transconductance g of the differential pair, m (IN) temperature characteristics, it may be desirable to have a source resistance R os This may result in inconvenient or undesirably high trim currents. To reduce the trim current (e.g., the left programmable current I AUX(L) , right programmable current I AUX(L) and reference current I REF ), a high source resistor R in the range of 1 to 10 kΩ can be used OS For example, 5 kΩ resistors may be used to be equivalent to source resistors 522, 524, and 526 (see above, Figure 5 ). However, this may change the offset current I OS The temperature characteristics of the Ios(T) and the temperature matching compensation based on the temperature characteristics of the differential pair are degraded. This degradation may be due to the offset current I OS (T) no longer depends only on g m , but in addition to g m In addition, it also depends on the source resistance R OS . With a corresponding resistance of 1 / 2R P The resistor 1310 and the resistor R NThe resistor 1320 may be employed to convert the offset current I OS The modified characteristics of (T) align with the temperature characteristics of the differential pair and further improve the temperature matching of active loads implemented with transistors of different channel polarity than the differential pair (e.g., a PMOS differential pair and an NMOS active load or vice versa). In some embodiments, the resistor R P In the range of 100Ω to 10kΩ, and the resistance R N In the range of 100Ω to 10kΩ.

[0114] The above equation (10) solves the problem of TH(CM) and ΔV IN The temperature-dependent term is related to the gain between , which is related to the ratio of electron to hole mobilities. Although electron and hole mobilities arise from different scattering mechanisms, their temperature dependencies may be similar but not exactly equal for a given process. In some cases, the mutual ratio of the transconductances can exhibit significant temperature drift. This may occur, for example, when different types of devices are used within an OTA, when the differential pair operates in the subthreshold region where the transconductance differs from that of equation (3), or when the resulting transconductance is subject to high channel length modulation effects. In such scenarios, the last term in equation (10) may introduce significant (residual) temperature instabilities, resulting in a compensated or uncompensated offset voltage V OS of higher voltage drift.

[0115] In some embodiments, by selectively applying temperature transconductance damping to the PMOS or NMOS transistors in the OTA, the transconductance ratio g m(CMn) / g m(IN) The temperature stability is improved. The temperature damping is achieved by using a total resistance R P The resistor 1310 and the corresponding resistor R N The resistor 1320 (see above, Fig.13 ) to achieve this. These resistors modify the temperature behavior of the current mirror or the temperature behavior of the differential pair transconductance. The effectiveness of the improvement depends on the process parameters and the OTA DC operating point. The incorporation of temperature damping can improve the resulting trimming performance and effectively reduce the temperature drift exhibited by an uncompensated OTA. This may be advantageous for systems where the offset of the signal processing chain is trimmed externally (such as by a reference voltage source). It can also improve the offset current I degraded by large source resistance Ros. os (T) matching. These resistors R N and R P It is used to adjust the temperature characteristics of the differential pair and current mirror transistors, rather than being used to improve the linearity or matching of the circuit, for example by acting as a degeneration resistor.

[0116] Temperature transconductance damping can be performed using adjustments implemented by an additional element having different temperature characteristics than the MOS transistor. For example, the element can be a temperature-stable resistor coupled to the source of the MOS transistor. Thus, the resulting transconductance depends proportionally on the temperature characteristics of both the MOS transistor and the additional element. For example, a temperature-stable resistor. For example, a differential pair (e.g., transistors 104 and 106, see above, Figure 8-Figure 11 and Fig.13 ) with modification g m(IN) (T) Temperature slope of source resistance R OS . Due to R OS The modified (in other words, degenerated) transconductance of the differential pair resulting from the presence of can be described by the following equation:

[0117]

[0118] where g m1,2 Reference transistors 104 and 106. Similarly, the active load current mirror g m(CM) The temperature behavior of (T) can also be adjusted by additional series source resistance.

[0119] Example embodiments of the present disclosure are summarized here. Other embodiments may also be understood from the entire specification and claims submitted herein.

[0120] Example 1. A circuit comprising: a current source; a differential pair of transistors, the transistors of the differential pair being coupled to the current source, the transistors of the differential pair having a first offset voltage and an input transconductance; an active load, the active load being coupled to the corresponding drains of the transistors of the differential pair opposite to the current source; and a current injection circuit, the current injection circuit being coupled to the corresponding drains of the transistors of the differential pair, the current injection circuit being configured to supply a first current and a second current to the corresponding drains, the first current and the second current generating a second offset voltage across the transistors of the differential pair, the second offset voltage being opposite to the first offset voltage, the first current and the second current having the same thermal dependence as the input transconductance of the transistors of the differential pair.

[0121] Example 2. The circuit of Example 1, wherein the transistors of the differential pair are PMOS devices.

[0122] Example 3. The circuit of one of Examples 1 or 2, wherein the active load comprises a first current mirror, the first current mirror comprising an NMOS device.

[0123] Example 4. The circuit of one of Examples 1 to 3, wherein the current injection circuit comprises a complementary current mirror.

[0124] Example 5. The circuit of one of Examples 1 to 4, wherein the body of the transistor that complements the current mirror is coupled to the source of the transistor that complements the current mirror.

[0125] Example 6. The circuit of one of Examples 1 to 5, wherein the current injection circuit further comprises a programmable current source.

[0126] Example 7. The circuit of Example 6, wherein the programmable current source is a current-steering digital-to-analog converter.

[0127] Example 8. A circuit comprising: a current source, the current source being coupled to a supply voltage node; a differential pair of transistors, the transistors of the differential pair being coupled to the current source relative to the supply voltage node, the transistors of the differential pair having a first offset voltage and an input transconductance, the input transconductance having a thermal dependency; an active load, the active load being coupled to the transistors of the differential pair relative to the current source, the active load comprising a first current mirror, each transistor of the first current mirror being coupled to the supply voltage node across a corresponding source resistance, each transistor of the first current mirror being further coupled to a corresponding unipolar current source, wherein the corresponding unipolar current source is configured to generate a first current and a second current; and a current injection circuit, the current injection circuit being coupled to a corresponding node between the drains of the transistors of the differential pair and the active load, the current injection circuit being configured to supply the first current and the second current to the corresponding node between the drains of the transistors of the differential pair and the active load, the first current and the second current generating a second offset voltage across the transistors of the differential pair, the second offset voltage being opposite to the first offset voltage, and the first current and the second current having the same thermal dependency as the input transconductance of the transistors of the differential pair.

[0128] Example 9. The circuit of Example 8, wherein the transistors of the differential pair have a first polarity and the first current mirror has a second polarity, the second polarity being the same as the first polarity.

[0129] Example 10. The circuit of one of Examples 8 or 9, wherein a respective body of each transistor of the first current mirror is coupled to a respective source of each transistor of the first current mirror.

[0130] Example 11. The circuit of one of Examples 8 to 10, further comprising a programmable current source coupled to a first node between a gate of a first transistor of the differential pair of transistors and the input voltage node.

[0131] Example 12. The circuit of Example 11, further comprising a resistor and a capacitor coupled in parallel between the first node and the input voltage node.

[0132] Example 13. The circuit of one of Examples 8 to 12, wherein the circuit comprises a folded cascode.

[0133] Example 14. A circuit comprising: a differential pair, the differential pair comprising a first transistor and a second transistor, the first transistor and the second transistor being coupled through a first resistor; a first programmable current source, the first programmable current source being coupled to a first node, the first node being between the first transistor and the first resistor; a second programmable current source, the second programmable current source being coupled to a second node, the second node being between the second transistor and the first resistor; and a first bias current source, the first bias current source being coupled to the differential pair.

[0134] Example 15. The circuit of Example 14, further comprising a second bias current source coupled to the second node.

[0135] Example 16. The circuit of Example 15, wherein a first bias current source is coupled to the first node.

[0136] Example 17. The circuit of Example 14 further includes a second resistor, the second resistor is coupled in series with the first resistor between the first transistor and the second transistor, and the third node is between the first resistor and the second resistor.

[0137] Example 18. The circuit of Example 17, wherein the first bias current source is coupled to the third node.

[0138] Example 19. The circuit of one of Examples 14 to 18, further comprising a capacitor coupled between the first transistor and the second transistor, the capacitor being connected in parallel with the first resistor.

[0139] Example 20. The circuit of one of Examples 14 to 19, wherein the body of the first transistor is coupled to the source of the first transistor.

[0140] Although the present invention has been described with reference to exemplary embodiments, the description is not intended to be interpreted in a limiting sense. Various modifications and combinations of the exemplary embodiments and other embodiments of the present invention will be apparent to those skilled in the art upon reference to the description. Therefore, the appended claims are intended to cover any such modifications or embodiments.

Claims

1. A circuit comprising: Current source; a differential pair of transistors coupled to the current source, the transistors of the differential pair having a first offset voltage and an input transconductance; an active load coupled to respective drains of transistors of the differential pair opposite the current source; as well as a current injection circuit coupled to the respective drains of the transistors of the differential pair, the current injection circuit being configured to supply a first current and a second current to the respective drains, the first current and the second current generating a second offset voltage across the transistors of the differential pair, the second offset voltage being opposite to the first offset voltage, the first current and the second current having the same thermal dependency as the input transconductance of the transistors of the differential pair.

2. The circuit of claim 1, wherein the transistors of the differential pair are PMOS devices. 3 . The circuit of claim 1 , wherein the active load comprises a first current mirror comprising an NMOS device.

4. The circuit of claim 1, wherein the current injection circuit comprises a complementary current mirror.

5. The circuit of claim 4, wherein the body of the transistor of the supplementary current mirror is coupled to the source of the transistor of the supplementary current mirror. The circuit of claim 4 , wherein the current injection circuit further comprises a programmable current source.

7. The circuit of claim 6, wherein the programmable current source is a current-steering digital-to-analog converter.

8. A circuit comprising: a current source coupled to a supply voltage node; a differential pair of transistors coupled to the current source opposite the supply voltage node, the transistors of the differential pair having a first offset voltage and an input transconductance, the input transconductance having a thermal dependency; an active load coupled to the transistors of the differential pair opposite the current source, the active load comprising a first current mirror, each transistor of the first current mirror being coupled to the supply voltage node across a respective source resistance, each transistor of the first current mirror being further coupled to a respective unipolar current source, wherein the respective unipolar current source is configured to generate a first current and a second current; as well as a current injection circuit coupled to respective nodes between drains of transistors of the differential pair and the active load, the current injection circuit being configured to supply a first current and a second current to respective nodes between the drains of transistors of the differential pair and the active load, the first current and the second current generating a second offset voltage across the transistors of the differential pair, the second offset voltage being opposite to the first offset voltage, the first current and the second current having the same thermal dependency as the input transconductance of the transistors of the differential pair.

9. The circuit of claim 8, wherein the transistors of the differential pair have a first polarity and the first current mirror has a second polarity, the second polarity being the same as the first polarity.

10. The circuit of claim 8, wherein a respective body of each transistor of the first current mirror is coupled to a respective source of each transistor of the first current mirror.

11. The circuit of claim 8, further comprising a programmable current source coupled to a first node between a gate of a first transistor of the differential pair of transistors and an input voltage node.

12. The circuit of claim 11, further comprising a resistor and a capacitor coupled in parallel between the first node and the input voltage node.

13. The circuit of claim 8, wherein the circuit comprises a folded cascode.

14. A circuit comprising: a differential pair, the differential pair comprising a first transistor and a second transistor, the first transistor and the second transistor being coupled via a first resistor; a first programmable current source coupled to a first node between the first transistor and the first resistor; a second programmable current source coupled to a second node between the second transistor and the first resistor; as well as A first bias current source is coupled to the differential pair.

15. The circuit of claim 14, further comprising a second bias current source coupled to the second node.

16. The circuit of claim 15, wherein the first bias current source is coupled to the first node.

17. The circuit of claim 14, further comprising a second resistor coupled in series with the first resistor between the first transistor and the second transistor, a third node being between the first resistor and the second resistor.

18. The circuit of claim 17, wherein the first bias current source is coupled to the third node.

19. The circuit of claim 14, further comprising a capacitor coupled between the first transistor and the second transistor, the capacitor being connected in parallel with the first resistor.

20. The circuit of claim 14, wherein a body of the first transistor is coupled to a source of the first transistor.

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