Coach aircraft avionics system bus architecture based on aviation Ethernet

Abstract

The invention belongs to the technical field of aircraft design, and particularly relates to a coach aircraft avionics system bus architecture based on aviation Ethernet, which comprises a core processor and equipment / subsystems, and each equipment / subsystem comprises a video processor, a display end, a data loading recorder and an electromechanical management computing system; the video processor, the display end, the data loading recorder and the electromechanical management computing system are all connected with the core processor; the core processor comprises a first core processor and a second core processor, the first core processor and the second core processor are hot backups for each other, and the first core processor and the second core processor are in cross connection with each device / subsystem through a bus; when any core processor has an error, the core processor in a normal state can work, the normal task short range of each device / subsystem cannot be influenced, the error cannot be spread to the whole combat flight software, and the normal operation of the waypoint system is ensured.

Description

Technical Field

[0001] The present application belongs to the field of aircraft design technology, and in particular relates to an avionics system bus architecture for a trainer aircraft based on aviation Ethernet. Background Art

[0002] Currently, the active training aircraft generally adopts the joint avionics system configuration, which connects most avionics equipment / subsystems through the MIL-STD-1553B bus, and the bus controller (BC) realizes the unified dispatch of information. The signal processing and data processing tasks of each subsystem are completed by the dedicated computer of each subsystem, using real-time operating systems such as VxWorks. However, with the improvement of aircraft mission capability requirements and higher safety requirements, the software function points of each device / subsystem of the avionics system have skyrocketed, and the amount of bus data has also increased exponentially, which has put forward higher requirements for the data transmission rate and data reliability of the avionics system bus network. The traditional MIL-STD-1553B bandwidth (1Mbps) can no longer meet the use requirements of the avionics system, and the current real-time operating system does not have a fault isolation function. Once a mission process fails, it will spread to the entire combat flight software, thereby seriously affecting the realization of the avionics system function.

[0003] Therefore, how to achieve large-capacity information transmission needs is a problem that needs to be solved. Summary of the invention

[0004] The purpose of this application is to provide a trainer aircraft avionics system bus architecture based on aviation Ethernet to solve the problem that the traditional MIL-STD-1553B bandwidth (1Mbps) can no longer meet the requirements of the avionics system after the existing bus data volume has increased significantly.

[0005] The technical solution of the present application is: a trainer aircraft avionics system bus architecture based on aviation Ethernet, including a core processor and various devices / subsystems, each device / subsystem including a video processor, a display terminal, a data loading recorder and an electromechanical management computing system; the video processor, the display terminal, the data loading recorder and the electromechanical management computing system are all connected to the core processor;

[0006] The core processor includes a first core processor and a second core processor, the first core processor and the second core processor are hot backup for each other, and the first core processor and the second core processor are interconnected with each device / subsystem through a bus;

[0007] The first core processor is the main processor, and the second core processor is the sub-processor. The first core processor and the second core processor both obtain data of each device / subsystem at the same time. At the same time, the first core processor obtains its own working data and data of each device / subsystem in the second core processor, and the second core processor obtains its own working data and data of each device / subsystem in the first core processor. The first core processor determines whether the operation of the second core processor is abnormal through the data of the second core processor and the data of each device / subsystem. If abnormal, an alarm is issued; the second core processor determines whether the operation of the first core processor is abnormal through the data of the first core processor and the data of each device / subsystem. If abnormal, the first core processor is switched, and the second core processor is converted to the main processor.

[0008] Preferably, the specific method for the first core processor and the second core processor to perform abnormality judgment is: the first core processor stores the operating standard data of the second core processor under different working conditions, and obtains the second core processor's own working data in real time, and compares it with the operating standard data. If they are different, the second core processor is judged to be abnormal; the second core processor stores the operating standard data of the first core processor under different working conditions, and obtains the first core processor's own working data in real time, and compares it with the operating standard data. If they are different, the first core processor is judged to be abnormal.

[0009] Preferably, the first core processor and the second core processor are also provided with a switching unit. When any core processor sends an abnormal information to the switching unit, the corresponding core processor is turned off and the other core processor is turned on; if the two core processors send abnormal information at the same time, the first core processor and the second core processor are cut off at the same time, and an alarm is issued.

[0010] Preferably, the video processor stores digital map information, and transmits it to the core processor after processing. The core processor determines the data type and transmits it to the display terminal for display.

[0011] Preferably, the display end includes a first display end and a second display end, the first display end adopts a touch-type large-screen LCD display, which is used to undertake the comprehensive control management and comprehensive display functions of the system; the display end is interconnected with the core processor through the AFDX bus, and receives various system states, system parameters, status information, and control information collected by the core processor; the display end is provided with a classification display processing module, after receiving the data sent by the core processor, it judges the data type and then determines its display position on the touch-type large-screen LCD display; the second display end receives various system parameters and generates a character display screen.

[0012] Preferably, the data loading recorder is connected to the core processor via the AFDX bus and is capable of loading and recording data; the core processor receives data sent by each device / subsystem, including AFDX bus data, 1553B bus data, all switch signals in the cockpit, alarm data, and maintenance data; and sends them to the data loading recorder for data processing. The data loading recorder sends the ground mission planning data to the core processor, and then loads it to each subsystem / device in the form of a data card, including but not limited to navigation data, radio data, and data link data.

[0013] Preferably, the electromechanical management computing system collects various signals from non-avionics systems such as fuel, hydraulics, landing gear, and engines, and accesses the core processor of the avionics system through the 1553B bus for display; at the same time, the electromechanical management computing system collects the onboard flight control computer, inertial navigation, atmospheric data, engine, power supply, and hydraulic / fuel system parameters, and sends them to the core processor. After determining the data type, the core processor sends it to the data loading recorder and the protection recorder for recording.

[0014] Preferably, the equipment / subsystem also includes an atmospheric data system, a communication, navigation and identification system, an inertial navigation system and an airborne data link; the atmospheric data system collects total temperature signals, calculates standard pressure altitude, relative pressure altitude, true airspeed, indicated airspeed, vertical speed and field pressure, and sends them to the core processor; after receiving the data collected by the atmospheric data system, the core processor classifies the data and sends the data to the avionics system through the electromechanical system for its use.

[0015] Preferably, the communication, navigation and identification system is capable of airborne ultra-short wave communication, whole-aircraft audio management, VOR, TCN, DME, radio altimetry, instrument landing, beacon, air traffic control / friend-or-foe identification response, ADS-B and data link clear / confidential communication; the communication, navigation and identification system is connected to the core processor via the AFDX bus, and sends internal data to the core processor, the core processor sends the data to the display terminal after determining the data type, and interacts with the air and ground crew through the display terminal.

[0016] Preferably, the inertial navigation system can obtain the aircraft position information, attitude information and time information. The inertial navigation system transmits the position, attitude information and time information to the core processor through the AFDX bus. The core processor sends different data to different locations of the avionics system after determining the data type; the airborne data link sends the data summarized by the avionics system to the core processor after receiving it. The core processor sends the data to the ground node or the air node for data sharing after determining the data type.

[0017] The avionics system bus architecture of the trainer aircraft based on aviation Ethernet of the present application can make the core processor in normal state work when any core processor has an error, which will not affect the normal mission of each device / subsystem, nor will it spread to the entire combat flight software, thus ensuring the normal operation of the waypoint system. And through the aviation Ethernet bus network, the functions of the avionics system such as comprehensive display, mission management, navigation, radio communication / navigation, air traffic control and identification of friend or foe, aircraft status monitoring and the corresponding equipment / subsystems are integrated into an organic whole, so as to achieve a high degree of sharing of system resources, so as to realize high utilization of aircraft data and high efficiency and cost-effectiveness of equipment use. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solution provided by the present application, the following is a brief introduction to the accompanying drawings. Obviously, the accompanying drawings described below are only some embodiments of the present application.

[0019] Figure 1 This is a schematic diagram of the overall configuration of the avionics system of this application. DETAILED DESCRIPTION

[0020] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0021] A trainer aircraft avionics system bus architecture based on aviation Ethernet, such as Figure 1 As shown, the bus architecture mode adopts aviation Ethernet bus network bus as the main network, ARINC 818, MIL-STD-1553B, RS-422A, ARINC 429, etc. as auxiliary buses, and two core processors with hot backup to each other are used as the core of the whole system, which are interconnected with various devices / subsystems to realize information transmission and control management of avionics system.

[0022] Figure 1 In the figure, MC is the core processor; VPU is the video processor; DISPLAY_1 is the first display terminal; DISPLAY_2 is the second display terminal; EMMS is the electromechanical management computing system; ADS is the atmospheric data system; DLR is the data loading recorder; CNI is the communication navigation and identification system; EGI is the inertial navigation; DL is the airborne data link.

[0023] It includes the core processor and various devices / subsystems, including the video processor, display terminal, data loading recorder and electromechanical management computing system. The video processor, display terminal, data loading recorder and electromechanical management computing system are all connected to the core processor to realize the information transmission and control management of the avionics system.

[0024] The core processor includes a first core processor and a second core processor. The first core processor and the second core processor serve as hot backups for each other. Both the first core processor and the second core processor are interconnected with various devices / subsystems through buses such as AFDX, 1553B, and RS422 to achieve bus network management, navigation solution, mode control, and full-machine alarm processing. It collects data from inertial navigation, electromechanical management computers, parameter collectors, flight control systems, engines, etc., and realizes comprehensive display and control on various display terminals after comprehensive processing.

[0025] The first core processor is the main processor, and the second core processor is the sub-processor. The first core processor and the second core processor both obtain data from each device / subsystem at the same time. At the same time, the first core processor obtains its own working data in the second core processor and the data of each device / subsystem, and the second core processor obtains its own working data in the first core processor and the data of each device / subsystem. The first core processor determines whether the operation of the second core processor is abnormal through its own working data in the second core processor and the data of each device / subsystem. If abnormal, an alarm is issued; the second core processor determines whether the operation of the first core processor is abnormal through its own working data in the first core processor and the data of each device / subsystem. If abnormal, the first core processor is switched and the second core processor is converted to the main processor.

[0026] Through the above design, when any core processor has an error, the core processor in normal state can work, which will not affect the normal mission of each device / subsystem, nor will it spread to the entire combat flight software, ensuring the normal operation of the waypoint system. And through the aviation Ethernet bus network, the avionics system's integrated display, mission management, navigation, radio communication / navigation, air traffic control and identification of friend or foe, aircraft status monitoring and other functions and corresponding equipment / subsystems are integrated into an organic whole, achieving a high degree of sharing of system resources, so as to achieve high utilization of aircraft data and high cost-effectiveness of equipment use.

[0027] Preferably, the specific method for judging abnormalities of the first core processor and the second core processor is as follows: the first core processor stores the operating standard data of the second core processor under different working states, obtains the second core processor's own working data in real time, and compares the data with the operating standard data; if they are different, the second core processor is judged to be abnormal; the second core processor stores the operating standard data of the first core processor under different working states, obtains the first core processor's own working data in real time, and compares the data with the operating standard data; if they are different, the first core processor is judged to be abnormal.

[0028] Preferably, a switching unit is also provided on the first core processor and the second core processor. When any core processor sends an abnormal information to the switching unit, the corresponding core processor is turned off and the other core processor is turned on; if the two core processors send abnormal information at the same time, the first core processor and the second core processor are cut off at the same time, and an alarm is issued.

[0029] Preferably, the video processor is used to process the video information. In the operation of the avionics system, the video processor stores information such as digital maps, and transmits it to the core processor after processing. The core processor determines the data type and transmits it to the display terminal for display.

[0030] Preferably, the display terminal includes a first display terminal and a second display terminal. The first display terminal adopts a touch-type large-screen LCD display, which is used to undertake the comprehensive control management and comprehensive display functions of the system. The display terminal is interconnected with the core processor through the AFDX bus, and receives data such as various system states, various system parameters, state information, and control information collected by the core processor. A classification display processing module is provided on the display terminal. After receiving the data sent by the core processor, the data type is judged and then its display position on the touch-type large-screen LCD display is determined, and finally displayed.

[0031] After modifying the equipment parameters and system status through the touch-screen large-screen LCD display, the modified data will be fed back to the core processor to achieve comprehensive control and management capabilities of the system. The touch-screen large-screen LCD display receives the digital map video signal transmitted by the video processor through the video line to provide video display capabilities, etc.; at the same time, it transmits the video signal to the data loading recorder for recording.

[0032] The second display terminal receives the parameters of each system and generates a character display screen. It can bind or modify the working parameters of the avionics system, select the working mode of the avionics system, display the status, working mode and related data of each system of the aircraft, and connect with the core processor through the AFDX bus. The core processor provides the status data of each system and equipment parameters for display.

[0033] Preferably, the data loading recorder is connected to the core processor via the AFDX bus, and can load and record data. The core processor receives data sent by each device / subsystem, including AFDX bus data, 1553B bus data, all switch signals in the cockpit, alarm data, maintenance data, etc.; sends it to the data loading recorder for data processing. The data loading recorder sends the data of ground mission planning to the core processor, and then loads it to each subsystem / device in the form of a data card, including but not limited to navigation data, radio data, data link data, etc. The data loading recorder is connected to the video processor via Ethernet and is used to load digital maps, Jeppesen charts, and electronic checklists. The data loading recorder can collect the front cabin HUD, front / rear cabin LAD, and UFCP video signals through the video line to realize the video recording function; the audio signal of the CNI is recorded through the audio line, and the recorded data is provided for ground analysis and ground review.

[0034] Preferably, the electromechanical management computing system is responsible for the control and management of the landing gear system retraction and extension, and the fuel system refueling control and management. Specifically, the electromechanical management computing system collects various signals of non-avionics systems such as fuel, hydraulics, landing gear, and engines, and connects to the core processor of the avionics system through the 1553B bus for display; at the same time, the electromechanical management computing system collects signal parameters of the flight control computer, inertial navigation, atmospheric data, engine, power supply, hydraulic / fuel system, etc. on the aircraft, and sends them to the core processor. After determining the data type, the core processor sends it to the data loading recorder and the protection recorder for recording.

[0035] Preferably, each device / subsystem also includes an atmospheric data system, a communication navigation and identification system, an inertial navigation system and an airborne data link.

[0036] The atmospheric data system collects total temperature signals, calculates standard pressure altitude, relative pressure altitude, true airspeed, indicated airspeed, vertical speed and field pressure, and sends them to the core processor. After receiving the data collected by the atmospheric data system, the core processor classifies the data and sends the data to the avionics system through the electromechanical system for use.

[0037] The communication, navigation and identification system can perform airborne ultra-short wave communication, whole-machine audio management, VOR, TCN, DME, radio altimeter, instrument landing, beacon, air traffic control / friend-or-foe identification reply, ADS-B and data link clear / secret communication, etc. The communication, navigation and identification system is connected to the core processor through the AFDX bus and sends the internal data to the core processor. The core processor sends the data to the display terminal after determining the data type, and realizes the interaction with the air and ground crew through the display terminal.

[0038] The inertial navigation system can obtain the aircraft's position information, attitude information and time information. The inertial navigation system transmits the position, attitude information and time information to the core processor through the AFDX bus. After determining the data type, the core processor sends different data to different locations of the avionics system.

[0039] After receiving the data summarized by the avionics system, the airborne data link sends it to the core processor. After the core processor determines the data type, it sends the data to the ground node or the air node to realize data sharing. After the ground receives the data, security monitoring can be realized.

[0040] Finally, it should be noted that: the drawings of the embodiments disclosed in the present invention only involve structures related to the embodiments disclosed in the present invention, and other structures can refer to the general design. In the absence of conflict, the same embodiment and different embodiments of the present invention can be combined with each other;

[0041] Finally: The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A trainer aircraft avionics system bus architecture based on aviation Ethernet, characterized by: It includes a core processor and various devices / subsystems, and each device / subsystem includes a video processor, a display terminal, a data loading recorder, and an electromechanical management computing system; the video processor, the display terminal, the data loading recorder, and the electromechanical management computing system are all connected to the core processor; The core processor includes a first core processor and a second core processor, the first core processor and the second core processor are hot backup for each other, and the first core processor and the second core processor are interconnected with each device / subsystem through a bus; The first core processor is the main processor, and the second core processor is the sub-processor. The first core processor and the second core processor both obtain data of each device / subsystem at the same time. At the same time, the first core processor obtains its own working data and data of each device / subsystem in the second core processor, and the second core processor obtains its own working data and data of each device / subsystem in the first core processor. The first core processor determines whether the operation of the second core processor is abnormal through the data of the second core processor and the data of each device / subsystem. If abnormal, an alarm is issued; the second core processor determines whether the operation of the first core processor is abnormal through the data of the first core processor and the data of each device / subsystem. If abnormal, the first core processor is switched, and the second core processor is converted to the main processor.

2. The trainer aircraft avionics system bus architecture based on aviation Ethernet as claimed in claim 1, characterized in that: The specific method for the first core processor and the second core processor to perform abnormality judgment is as follows: the first core processor stores the operating standard data of the second core processor in different working states, obtains the own working data of the second core processor in real time, and compares the data with the operating standard data. If they are different, it is judged that the second core processor is abnormal; The second core processor stores the standard operating data of the first core processor in different working states, and obtains its own working data in the first core processor in real time, and compares it with the standard operating data. If they are different, it is determined that the first core processor is abnormal.

3. The trainer aircraft avionics system bus architecture based on aviation Ethernet as claimed in claim 1, characterized in that: The first core processor and the second core processor are also provided with a switching unit. When any core processor sends an abnormal information to the switching unit, the corresponding core processor is turned off and the other core processor is turned on. If the two core processors send abnormal information at the same time, the first core processor and the second core processor are cut off at the same time, and an alarm is issued.

4. The trainer aircraft avionics system bus architecture based on aviation Ethernet as claimed in claim 1, characterized in that: The video processor stores digital map information and transmits it to the core processor after processing. The core processor determines the data type and transmits it to the display terminal for display.

5. The trainer aircraft avionics system bus architecture based on aviation Ethernet as claimed in claim 1, characterized in that: The display end includes a first display end and a second display end. The first display end adopts a touch-type large-screen LCD display, which is used to undertake the comprehensive control management and comprehensive display functions of the system; the display end is interconnected with the core processor through the AFDX bus, and receives various system states, system parameters, status information, and control information collected by the core processor; the display end is provided with a classification display processing module, after receiving the data sent by the core processor, it judges the data type and then determines its display position on the touch-type large-screen LCD display; the second display end receives various system parameters and generates a character display screen.

6. The trainer aircraft avionics system bus architecture based on aviation Ethernet as claimed in claim 1, characterized in that: The data loading recorder is connected to the core processor via the AFDX bus and can load and record data; the core processor receives data sent by each device / subsystem, including AFDX bus data, 1553B bus data, all switch signals in the cockpit, alarm data, and maintenance data; The data is sent to the data loading recorder for data processing. The data loading recorder sends the ground mission planning data to the core processor, and then loads it to each subsystem / equipment in the form of a data card, including but not limited to navigation data, radio data, and data link data.

7. The trainer aircraft avionics system bus architecture based on aviation Ethernet as claimed in claim 1, characterized in that: The electromechanical management computing system collects various signals from non-avionics systems such as fuel, hydraulics, landing gear, and engines, and connects to the core processor of the avionics system through the 1553B bus for display; at the same time, the electromechanical management computing system collects the onboard flight control computer, inertial navigation, atmospheric data, engine, power supply, and hydraulic / fuel system parameters, and sends them to the core processor. After determining the data type, the core processor sends it to the data loading recorder and protection recorder for recording.

8. The trainer aircraft avionics system bus architecture based on aviation Ethernet as claimed in claim 1, characterized in that: The equipment / subsystem also includes an atmospheric data system, a communication navigation and identification system, an inertial navigation system and an airborne data link; the atmospheric data system collects total temperature signals, calculates standard pressure altitude, relative pressure altitude, true airspeed, indicated airspeed, vertical speed and field pressure, and sends them to the core processor; after receiving the data collected by the atmospheric data system, the core processor classifies the data and sends the data to the avionics system through the electromechanical system for its use.

9. The trainer aircraft avionics system bus architecture based on aviation Ethernet as claimed in claim 8, characterized in that: The communication, navigation and identification system is capable of performing airborne ultra-short wave communication, whole-aircraft audio management, VOR, TCN, DME, radio altimetry, instrument landing, beacon, air traffic control / friend-or-foe identification response, ADS-B and data link clear / confidential communication; the communication, navigation and identification system is connected to the core processor via the AFDX bus and sends internal data to the core processor, which sends the data to the display terminal after determining the data type, and interacts with air and ground crew through the display terminal.

10. The trainer aircraft avionics system bus architecture based on aviation Ethernet as claimed in claim 8, characterized in that: The inertial navigation system can obtain the aircraft's position information, attitude information and time information. The inertial navigation system transmits the position, attitude information and time information to the core processor through the AFDX bus. The core processor sends different data to different locations of the avionics system after determining the data type; the airborne data link sends the data summarized by the avionics system to the core processor after receiving it. The core processor sends the data to the ground node or the air node for data sharing after determining the data type.

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