Port control in parallel multi-port system
By using multiple processors independently to control ports and share software code in a parallel multi-port charging system, the problems of response delay and code redundancy under single processor control are solved, improving the robustness and efficiency of the system and reducing costs .
Patent Information
- Application Number
- CN202410932218.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-07-14
- Filing Date
- 2024-07-12
- Publication Date
- 2025-01-14
AI Technical Summary
In existing parallel multi-port charging systems, a single processor controls all ports resulting in delayed response time, redundant software code, increased memory requirements and insufficient system robustness.
Multiple parallel and independent processors are adopted, each processor controls the corresponding port controller and shares common software code, retaining only port-specific configuration codes to improve system performance and robustness.
Reduces processor performance requirements, reduces code memory size and development complexity, improves system robustness and efficiency, and reduces costs.
Smart Images
Figure CN119311610A_ABST
Abstract
Description
background 1. Technical Field
[0001] The present disclosure relates to parallel multi-port systems. In particular, the present disclosure relates to controlling ports in a parallel multi-port system. 2. Background technology
[0002] In a parallel multi-port charging system, multiple charging ports can be connected in parallel to a power source or power supply unit to provide a shared power pool that can be distributed between the individual charging ports. This allows multiple devices (e.g., in the case of a Universal Serial Bus (USB) charging system, a smartphone, tablet, smartwatch, or any other USB-powered device) to be charged simultaneously. Thus, each port can independently deliver its maximum rated power output, ensuring efficient and fast charging of each connected device.
[0003] Each port of a parallel multi-port charging system typically operates independently and is typically controlled by a dedicated port controller. The port controller is typically controlled by a single processor that is programmed by software to control the activities of all ports according to the capabilities of each respective port. Summary of the invention
[0004] The following describes an overview of aspects of certain examples disclosed herein. It should be understood that these aspects are presented only to provide the reader with a brief overview of these specific embodiments, and these aspects are not intended to limit the scope of the present disclosure. In fact, the present disclosure may include multiple aspects and / or combinations of aspects that may not be described.
[0005] A typical prior art parallel multi-port charging system uses one processor to control all activities of all charging ports, i.e., by controlling a port controller for each port. Using a single processor to control all ports has many disadvantages. First, the processor may be required to operate at a relatively high speed to ensure a timely response to each port, which may result in a delay in the port response time, especially when the processor handles all ports in a serial sequence. Second, the software program running on the processor typically includes specific function code for each port, and since the software code is repeated for each port, a relatively large code memory is required. Third, a failure of one port may cause a system failure or affect the normal operation of other ports. Fourth, when the number of ports in the system is expanded, more software code needs to be added to the program, which requires a larger memory size and software development (human) resources.
[0006] The present disclosure is intended to overcome the above-mentioned drawbacks of the known parallel multi-port charging system. Thus, the parallel multi-port system according to the present disclosure includes multiple processors working in parallel and independently, each processor controlling a port controller of a port. The software code common to different port controllers and / or ports can be shared by multiple processors, and in addition to the shared software code, only the port-specific, preferably non-shareable configuration code is left.
[0007] The parallel multi-port system according to the present disclosure can be advantageously used to control charging ports in a parallel multi-port charging system. Alternatively or additionally, the parallel multi-port system according to the present disclosure can be used to control data ports.
[0008] With multiple processors operating in parallel and independently, the performance requirements for each processor may be lower than for one processor in known systems. In addition, by using multiple processors, the robustness of the system may be improved by removing single points of failure in a single processor. By using common program code for multiple processors (and therefore for multiple port controllers and / or ports), code memory size may be reduced by removing duplicate software code, the complexity of software development may be reduced, chip size may be reduced (e.g., due to reduced memory size due to smaller firmware size), and the cost of parallel multi-port systems may be reduced.
[0009] According to one aspect of the present disclosure, a parallel multi-port system is presented. The parallel multi-port system may include multiple ports. The parallel multi-port system may include multiple processors. The parallel multi-port system may include a memory storing software code that causes the processor to control multiple ports when executed by multiple processors. A first processor among the multiple processors may be configured to control a first port among the multiple ports. A second processor among the multiple processors that is different from the first processor may be configured to control a second port among the multiple ports that is different from the first port. The software code may include a common software code portion that is associated with the multiple ports and is executed by the multiple processors. The software code may also include a port-specific code portion that includes first configuration data for the first port and executed by the first processor. The port-specific code portion may also include second configuration data for the second port and executed by the second processor.
[0010] In an embodiment, the parallel multi-port system may include a plurality of port controllers. Each port controller may be configured to control one of the plurality of ports. A plurality of processors may be configured to control the ports through the plurality of port controllers.
[0011] In an embodiment, the first processor may be configured to control a first subset of the plurality of ports. The second processor may be configured to control a second subset of the plurality of ports.
[0012] In an embodiment, the common software code portion may include a startup code. The startup code may link each processor to a memory address in the port-specific code portion. The memory address may point to configuration data for a port.
[0013] In an embodiment, the common software code portion may include functional code. The functional code may include a generic program for a parallel multi-port system without processor or port identification.
[0014] In an embodiment, the port may be a charging port.
[0015] In an embodiment, the parallel multi-port system may further include multiple power loops. Each power loop may be configured to supply power to one of the charging ports.
[0016] In an embodiment, the port may be a USB port.
[0017] According to one aspect of the present disclosure, a computer program is presented. The computer program may include instructions that, when the program is executed by multiple processors of a parallel multi-port system, cause multiple processors to control multiple ports, cause a first processor among the multiple processors to control a first port, and cause a second processor different from the first processor among the multiple processors to control a second port different from the first port. The program may include a common software code portion that is associated with multiple ports and is executed by multiple processors. The program may also include a port-specific code portion that includes first configuration data for a first port and executed by a first processor, and the port-specific code portion also includes second configuration data for a second port and executed by a second processor.
[0018] In an embodiment, the common software code portion of the computer program may include a startup code. The startup code may link each processor to a memory address in the port-specific code portion. The memory address may be linked to configuration data for a port.
[0019] In an embodiment, the common software code portion may include functional code. The functional code may include a generic program for a parallel multi-port system without processor or port identification. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] Embodiments of the present disclosure will now be described, by way of example only, with reference to the accompanying schematic drawings, wherein corresponding reference characters indicate corresponding parts, and wherein:
[0021] Figure 1 A conventional (prior art) structure of a parallel multi-port charging system is shown.
[0022] Figure 2 The structure of a parallel multi-port system according to an exemplary embodiment of the present disclosure is shown.
[0023] Figure 3 The structure of a parallel multi-port system according to another exemplary embodiment of the present disclosure is shown.
[0024] Figure 4 An alternative memory configuration of a parallel multi-port system according to another exemplary embodiment of the present disclosure is shown.
[0025] Figure 5 The structure of the software code of the exemplary embodiment of the present disclosure is shown.
[0026] Figure 6 An exemplary embodiment of a computing system is shown.
[0027] The drawings are for illustration purposes only and do not limit the scope of protection defined by the claims. DETAILED DESCRIPTION
[0028] It will be readily appreciated that the components of the embodiments as generally described herein and illustrated in the accompanying drawings may be arranged and designed in a variety of different configurations. Therefore, the following more detailed description of various embodiments, as shown in the drawings, is not intended to limit the scope of the present disclosure, but is merely representative of various embodiments. Although various aspects of the embodiments are presented in the drawings, the drawings are not necessarily drawn to scale unless specifically noted.
[0029] The embodiments are to be considered in all respects as illustrative only and not restrictive. Therefore, the scope of the present disclosure is indicated by the appended claims rather than this detailed description. All changes within the meaning and scope of the equivalents of the claims are included within the scope of the claims.
[0030] References to features, advantages, or similar language in this specification do not imply that all features and advantages that can be achieved by the present disclosure are or should be present in any single example of the present disclosure. Instead, language referring to features and advantages is understood to mean that a particular feature, advantage, or characteristic described in conjunction with an embodiment is included in at least one embodiment of the present disclosure. Therefore, throughout this specification, discussions of features and advantages and similar language may, but do not necessarily, refer to the same example.
[0031] In addition, the features, advantages and characteristics of the present disclosure may be combined in any suitable manner in one or more embodiments. According to the description herein, those skilled in the relevant art will recognize that the present disclosure may be practiced without one or more specific features or advantages of a particular embodiment. In other cases, additional features and advantages that may not be present in all embodiments of the present disclosure may be recognized in certain embodiments. Throughout this specification, references to "one embodiment", "embodiment" or similar language mean that the specific features, structures or characteristics described in conjunction with the illustrated embodiment are included in at least one embodiment of the present disclosure. Therefore, throughout this specification, the phrases "in one embodiment", "in an embodiment" and similar language may but may not all refer to the same embodiment.
[0032] Figure 1 A conventional (prior art) structure of a parallel multi-port charging system 100 is shown. Charging ports 150 to 154 are shown, each of which is controlled by a port controller 130 to 134 and includes a power loop 140 to 144. A single processor 120 controls all of the charging ports 150 to 154 through the port controllers 130 to 134. The processor operates based on software code 110. The dots indicate that there may be any number of port controllers / power loops / charging ports.
[0033] One processor 120 of the conventional system 100 typically controls the activities of multiple ports in a serial sequence. In a serial sequence, one task is processed or one instruction is executed at a time, and each task or instruction must be completed before the next task or instruction begins (i.e., sequentially). The processor 120 typically operates at a relatively high speed (i.e., higher than each processor in the parallel multi-port charging system according to the present disclosure) to ensure timely response on the port, which may require a higher-end and more expensive processor.
[0034] The software code 110 generally includes specific function codes for each of the ports 150 to 154 and / or the port controllers 130 to 134, resulting in duplicate code in the software code 110. The software code 110 generally includes all possible combination scenarios for all ports 150 to 154 and / or the port controllers 130 to 134. Therefore, when the number of ports increases, the complexity of the software code 110 may also increase. Even when adding a port having similar or identical functions to an existing port, it may be necessary to add the function code of the new port to the software code 110 and modify the existing software code in the software code 110.
[0035] All ports 150 to 154 and port controllers 130 to 134 are controlled by a single processor 120, and a failure of one port or port controller may cause the entire system 100 to fail and thus affect other ports.
[0036] The exemplary software code 110 for the N ports 150 to 254 may be constructed as follows:
[0037]
[0038] Figure 2 The structure of the parallel multi-port system 200 of the exemplary embodiment of the present disclosure is shown. Ports 250 to 254 are shown, each of which is controlled by a port controller 230 to 234. In the case where the port is a charging port, each port may include a power loop 240 to 244. The power loop may be part of the port controller. Multiple processors 220 to 224 control ports 250 to 254 through port controllers 230 to 234, and in this example, each port and port controller is equipped with a processor. The processor operates based on software code 210. The difference between software code 210 and software code 110 is that it has been changed to include a common software code portion shared by all processors 220 to 224 (and therefore shared by all ports 250 to 254 and port controllers 230 to 234) and a port-specific code portion including port-specific software code. The dots indicate that there may be any number of processors / port controllers / power loops / ports.
[0039] In the parallel multi-port system 200, each processor 220 to 224 can control the activity of the corresponding port in parallel and can operate independently. This allows the processors 220 to 224 to operate at a lower speed than the processor 120 of the conventional system 100, thereby reducing processor requirements.
[0040] Processors 220 to 224 may execute the same software code 210 (including unified (ie, shared) function codes and port-specific configuration data), thereby enabling smaller code memory sizes and saving chip area even with the use of additional processors.
[0041] exist Figure 2 In the example of FIG. 2 , each processor 220 to 224 controls a single port 250 to 254 and / or port controller 230 to 234. Thus, the software code 210 does not need to include complex scenarios for controlling multiple ports, and the software code can remain relatively simple as the number of ports increases. When adding ports with existing functionality to the system 200, it may not be necessary to modify the unified function code in the shared software code portion. When adding ports to the system 200, it may be sufficient to add port-specific configuration data for the additional port to the port-specific code portion of the software code 210.
[0042] The processors 220 to 224 can operate independently of each other. A failure in one port 250 to 254 or a failure in one port controller 230 to 234 may cause the corresponding processor 220 to 224 to restart or shut down without affecting other ports and port controllers controlled by other processors. Therefore, the entire system 200 is more robust than the conventional system 100.
[0043] Exemplary software code 210 for the N ports 250 to 254 may be constructed as follows:
[0044]
[0045] Figure 3 The structure of a parallel multi-port system 300 of another exemplary embodiment of the present disclosure is shown. Ports 350 to 356 are shown, each of which is controlled by a port controller 330 to 336. In the case where the port is a charging port, each port may include a power supply circuit 340 to 346. The power supply circuit may be part of the port controller. Multiple processors 320 to 322 control ports 350 to 356 through port controllers 330 to 336. In this example, a first processor 320 is used for ports 350 to 352 and port controllers 330 to 332, and a second processor 322 is used for ports 354 to 356 and port controllers 334 to 336. The processor operates based on software code 310. Similar to software code 210, software code 310 differs from software code 110 in that it has been modified to include a common software code portion common to all processors 320 to 322 (and therefore common to all ports 350 to 356 and port controllers 330 to 336) and a port specific code portion including port specific software code. The dots indicate that there may be any number of processors / port controllers / power loops / ports.
[0046] In the parallel multi-port system 300, each processor 320 to 322 can control the activity of the corresponding port in parallel and can operate independently. This allows the processors 320 to 322 to operate at a lower speed than the processor 120 of the conventional system 100, thereby reducing processor requirements.
[0047] The processors 320 to 322 may execute the same software code 310 (including unified (ie, shared) function codes and port-specific configuration data), thereby enabling a smaller size code memory and saving chip area even with the use of additional processors.
[0048] exist Figure 3In the example of FIG. 3 , each processor 320 to 322 controls a subsection of a port 350 to 356 and / or a port controller 330 to 336. When adding a port with an existing function to the system 300, it may not be necessary to modify the unified function code in the common software code portion. When adding a port to the system 300, it may be sufficient to add port-specific configuration data for the additional port to the port-specific code portion of the software code 310.
[0049] The processors 320 to 322 can operate independently of each other. A failure in one port 350 to 356 or a failure in one port controller 330 to 336 may cause the corresponding processor 320 to 322 to restart or shut down without affecting the ports and port controllers controlled by other processors. Therefore, the entire system 300 is more robust than the conventional system 100.
[0050] Preferably, the processors 220 to 224, 320 to 322 utilize a single software code, such as Figure 2 The software code 210 or Figure 3 Alternatively, multiple software codes may be used for multiple processors, such as Figure 4 As shown, in this figure, a part of the structure of a parallel multi-port system 400 is shown, showing processors 420, 422 and two software codes 410, 420. The software code 410 includes, for example, a common software code portion for a first processor 420 and a port and / or port controller-specific software code portion for one or more ports controlled by the first processor 420. The software code 412 includes, for example, a common software code portion for a second processor 422 and a port and / or port controller-specific software code portion for one or more ports controlled by the second processor 422.
[0051] The software code 210, 310, 410, 412 may be stored in non-volatile memory (NVM). NVM is commonly used in microcontrollers, embedded systems, and other devices that require permanent storage of program code. It allows the system to retain code after a power cycle or reset, thereby ensuring that program instructions are not lost. The software code 210, 310, 410, 412 may be part of the firmware of the parallel multi-port system 200, 300, 400.
[0052] Figure 5 A more detailed example of the structure of software code 500 is shown, which may be used for software code 210, 310, 410, 412. Software code 500 may include common software code portions 510 and port and / or port controller specific software code portions 520.
[0053] The common software code portion 510 may include a startup code 511 and / or a functional code 512 that can be executed by multiple processors, such as Figure 2 The processors 220 to 224 in the example or Figure 3 Processors 320 to 322 in the example.
[0054] The port / port controller specific code portion 520 may include port specific and / or port controller specific configuration data 521 to 523. Figure 2 In the example of , port / port controller specific configuration data 521 defines configuration data related to port 250, for example, port / port controller specific configuration data 522 defines configuration data related to port 252, for example, and port / port controller specific configuration data 523 defines configuration data related to port 254, for example. Figure 3 In the example of FIG. 5 , port / port controller specific configuration data 521 defines, for example, configuration data related to port 350, port / port controller specific configuration data 522 defines, for example, configuration data related to port 352, port / port controller specific configuration data 523 defines, for example, configuration data related to port 354, and another port / port controller specific configuration data ( Figure 5 ) defines, for example, configuration data related to port 356.
[0055] The boot code 511 may include code to identify a configuration area in the code memory based on the processor identification. In the example of a parallel multi-port system with four ports controlled by four processors, the boot code 511 (pseudo code) may be constructed as follows:
[0056]
[0057] Preferably, function code 512 comprises the main general program without processor or port identification. In the example where four ports are controlled by four processors, function code 512 (pseudocode) can be constructed as follows:
[0058]
[0059] In an example where four ports are controlled by four processors, the port / port controller specific code portion 520 may be structured as follows:
[0060] Configuration data for port 4 at NVM addresses 0xFF40 to 0xFF4F Configuration data for port 3 at NVM addresses 0xFF30 to 0xFF3F Configuration data for port 2 at NVM addresses 0xFF20 to 0xFF2F Configuration data for port 1 at NVM addresses 0xFF10 to 0xFF1F
[0061] In the above example, adding a processor and additional ports / port controllers to the system 500 is as simple as adding a configuration start address to the boot code 511 and adding port specific configuration data to the port / port controller specific code section 520 at the configured configuration start address. The unused configuration start address may already exist in the boot code 511, so that when a processor / port controller / port is added to the system 500, only the configuration data needs to be added to the controller specific code section 520.
[0062] The parallel multi-port systems 200, 300, 400 of the present disclosure can be advantageously used in a multi-port USB adapter that includes different types of ports, such as a Type-C USB port and a Type-A USB port. The present disclosure is not limited to USB adapters or these specific USB type ports, and can be used in any electronic device with multiple ports, such as a charger, power pack, docking station, etc.
[0063] Figure 6 An exemplary embodiment of a computing system 600 for implementing certain aspects of the present technology is shown. In various examples, the computing system 600 can be any computing device that forms any part of the parallel multiprocessor systems 200, 300, 400 described herein.
[0064] In some implementations, computing system 600 can implement the methods described herein.
[0065] Computing system 600 may include any of the components of the computing systems described herein, the components of which communicate with each other using connection 605. Connection 605 may be a physical connection via a bus, or a direct connection into processor 610, such as in a chipset architecture. Connection 605 may also be a virtual connection, a network connection, or a logical connection.
[0066] Exemplary system 600 includes at least one processing unit (CPU or processor) 610 and connections 605 that connect various system components, such as read-only memory (ROM) 620 and random access memory (RAM) 625, including system memory 615, to processor 610. Computing system 600 may include a cache 612 of high-speed memory that is directly connected to processor 610, proximate to the processor, or integrated as part of the processor.
[0067] Processor 610 may include any general purpose processor and hardware or software services configured to control processor 610, such as services 632, 634, and 636 stored in storage 630, as well as special purpose processors where software instructions are incorporated into the actual processor design. Processor 610 may essentially be a completely independent computing system, including multiple cores or processors, buses, memory controllers, caches, etc. Multi-core processors may be symmetric or asymmetric.
[0068] To enable user interaction, the computing system 600 may include an input device 645, which may represent any number of input mechanisms, such as a microphone for voice, a touch-sensitive screen for gesture or graphic input, a keyboard, a mouse, motion input, voice, etc. The computing system 600 may also include an output device 635, which may be one or more of a variety of output mechanisms known to those skilled in the art. In some cases, a multimodal system may enable a user to provide multiple types of input / output to communicate with the computing system 600. The computing system 600 may include a communication interface 640, which generally may command and manage user input and system output. There is no limitation on operation on any particular hardware configuration, and thus the basic features herein may be easily replaced by improved hardware or firmware configurations developed.
[0069] The storage device 630 may be a non-volatile storage device and may be a hard disk or other type of computer-readable medium that can store computer-accessible data, such as a magnetic tape cartridge, a flash memory card, a solid-state storage device, a digital versatile disk, a cassette, a random access memory (RAM), a read-only memory (ROM), and / or some combination of these devices.
[0070] Storage device 630 may include software services, servers, services, etc., which, when executed by processor 610, cause the system to perform a function. In some embodiments, hardware services that perform a particular function may include software components stored in a computer-readable medium and necessary hardware components, such as processor 610, connection 605, output device 635, etc., to perform the function.
Claims
1. A parallel multi-port system comprising: Multiple ports; Multiple processors; as well as a memory storing software codes which, when executed by the plurality of processors, cause the processors to control the plurality of ports, wherein the plurality of processors has a first processor configured to control a first port of the plurality of ports, wherein the plurality of processors has a second processor that is different from the first processor and is configured to control a second port of the plurality of ports that is different from the first port, wherein the software code includes a common software code portion associated with the plurality of ports and executed by the plurality of processors, and The software code further comprises a port-specific code portion comprising first configuration data for the first port and executed by the first processor, and the port-specific code portion further comprises second configuration data for the second port and executed by the second processor.
2. The parallel multi-port system according to claim 1, further comprising: a plurality of port controllers, wherein each port controller is configured to control one of the plurality of ports, and The plurality of processors are configured to control the ports through the plurality of port controllers.
3. A parallel multi-port system according to any one of the preceding claims, wherein the first processor is configured to control a first subset of the plurality of ports, and Wherein the second processor is configured to control a second subset of the plurality of ports.
4. A parallel multi-port system according to any one of the preceding claims, wherein the common software code portion includes a startup code, and The boot code links each processor to a memory address in the port-specific code portion, wherein the memory address points to configuration data for a port.
5. A parallel multi-port system according to any one of the preceding claims, wherein the common software code portion includes function codes, and The function code includes a generic program of the parallel multi-port system without processor or port identification.
6. A parallel multi-port system according to any one of the preceding claims, wherein the ports are charging ports.
7. The parallel multi-port system of claim 6, further comprising a plurality of power loops, wherein each power loop is configured to supply power to one of the charging ports.
8. A parallel multi-port system according to claim 6 or claim 7, wherein the ports are USB ports.
9. A computer program comprising instructions that, when executed by a plurality of processors of a parallel multi-port system, cause the plurality of processors to control a plurality of ports, cause a first processor of the plurality of processors to control a first port, and cause a second processor of the plurality of processors different from the first processor to control a second port different from the first port, wherein the program includes a common software code portion associated with the plurality of ports and executed by the plurality of processors, and The program further comprises a port specific code portion comprising first configuration data for the first port and executed by the first processor, and the port specific code portion further comprises second configuration data for the second port and executed by the second processor.
10. The computer program according to claim 9, The common software code portion includes a startup code, Wherein the boot code links each processor to a memory address in the port specific code portion, and wherein the memory address is linked to configuration data for a port.
11. A computer program according to claim 9 or claim 10, wherein the common software code portion includes function codes, and The function code includes a generic program of the parallel multi-port system without processor or port identification.