Solid state disk storage module

Abstract

A solid state disk storage module comprises more than two storage particles, and comprises a storage controller integrating a first storage control bare chip and a second storage control bare chip; the first storage control bare chip and the second storage control bare chip comprise corresponding bare chip interconnection controllers, and the bare chip interconnection controllers of the first storage control bare chip and the second storage control bare chip establish communication between the chips and are used for exchanging data between the chips so as to read and write data of more than two storage particles; the data exchange between the chips comprises the following steps: a bare chip interconnection controller of a first storage control bare chip forwards data to a second storage control bare chip; or the bare chip interconnection controller of the second storage control bare chip forwards the data to the first storage control bare chip. According to the embodiment of the invention, the first storage control bare chip and the second storage control bare chip which establish the communication connection are integrated in the storage controller, so that the performance of the storage controller is improved, and the application requirements of multiple read-write channels are met.

Description

Technical Field

[0001] This article relates to memory chip technology, and in particular to a solid-state drive memory module. Background Art

[0002] Related Technology When designing storage modules including solid-state drives, in order to meet storage capacity requirements, multiple storage particles are often integrated in the same storage module, and a single storage control chip is set to control the large-capacity multi-read and write channels of the storage module. When the number of storage particles increases, the performance of the storage control chip will not be able to meet the performance requirements of the multiple read and write channels, affecting the working performance of the storage module. How to improve the working performance of the storage module has become a technical problem to be solved. Summary of the invention

[0003] The embodiment of the present application provides a solid-state hard disk storage module, comprising two or more storage particles, including: a storage controller integrating a first storage control bare chip chip and a second storage control bare chip chip, the storage particles and the storage controller are integrated on the same circuit board; the first storage control bare chip chip and the second storage control bare chip chip respectively comprise corresponding bare chip interconnection controllers, the bare chip interconnection controller of the first storage control bare chip chip and the bare chip interconnection controller of the second storage control bare chip chip establish communication between the chips for exchanging data between the chips, and then perform data reading and writing of the two or more storage particles; The data exchange between the chips includes: the die interconnect controller of the first storage control die chip forwards the data to the second storage control die chip; or, the die interconnect controller of the second storage control die chip forwards the data to the first storage control die chip.

[0004] The disclosed embodiment improves the performance of the storage controller and meets the application requirements of multiple read and write channels by integrating a first storage control bare chip and a second storage control bare chip that establish a communication connection in the storage controller.

[0005] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or be understood by implementing the present application. Other advantages of the present application can be realized and obtained by the schemes described in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0007] Figure 1 This is a structural block diagram of a solid state drive storage module according to an embodiment of the present disclosure; Figure 2 A physical connection diagram of a storage controller according to an embodiment of the present disclosure; Figure 3 is a schematic diagram of a bare chip according to an embodiment of the present disclosure; Figure 4 A schematic diagram of a storage controller according to an embodiment of the present disclosure; Figure 5 The present invention is a communication flow diagram of a storage controller according to an embodiment of the present invention. DETAILED DESCRIPTION

[0008] The present application describes multiple embodiments, but the description is exemplary rather than restrictive, and it is obvious to those skilled in the art that there may be more embodiments and implementations within the scope of the embodiments described in the present application. Although many possible feature combinations are shown in the drawings and discussed in the specific embodiments, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with any other feature or element in any other embodiment, or may replace any other feature or element in any other embodiment.

[0009] The present application includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The embodiments, features and elements disclosed in the present application may also be combined with any conventional features or elements to form a unique invention scheme. Any features or elements of any embodiment may also be combined with features or elements from other invention schemes to form another unique invention scheme. Therefore, it should be understood that any feature shown and / or discussed in the present application may be implemented individually or in any appropriate combination. Therefore, except for the limitations made according to the attached claims and their equivalents, the embodiments are not subject to other restrictions. In addition, various modifications and changes may be made within the scope of protection of the attached claims.

[0010] In addition, when describing representative embodiments, the specification may have presented the method and / or process as a specific sequence of steps. However, to the extent that the method or process does not rely on the specific order of the steps described herein, the method or process should not be limited to the steps of the specific order described. As will be understood by those of ordinary skill in the art, other sequences of steps are also possible. Therefore, the specific sequence of the steps set forth in the specification should not be interpreted as a limitation to the claims. In addition, the claims for the method and / or process should not be limited to the steps of performing them in the order written, and those skilled in the art can easily understand that these sequences can be changed and still remain within the spirit and scope of the embodiments of the present application.

[0011] Figure 1is a structural block diagram of a solid state drive storage module according to an embodiment of the present disclosure, such as Figure 1 As shown, a solid-state hard disk storage module (also called a solid-state hard disk module) includes more than two storage particles; a storage controller integrating a first storage control bare chip chip and a second storage control bare chip chip, the storage particles and the storage controller are integrated on the same circuit board, the first storage control bare chip chip and the second storage control bare chip chip respectively include corresponding bare chip interconnection controllers, the bare chip interconnection controller of the first storage control bare chip chip and the bare chip interconnection controller of the second storage control bare chip chip establish communication between chips for exchanging data between chips, and then read and write data of more than two storage particles.

[0012] The disclosed embodiment integrates a first storage control bare chip and a second storage control bare chip in a storage controller, establishes a communication connection between the integrated first storage control bare chip and the second storage control bare chip based on a bare chip interconnect controller, realizes the expansion of the storage controller, improves the performance of the storage controller, and meets the application requirements of multiple read and write channels.

[0013] In an exemplary embodiment, the die interconnect controller of the first storage control die chip and the die interconnect controller of the second storage control die chip are physically connected; Figure 2 FIG. 1 is a schematic diagram of the physical connection of the storage controller according to an embodiment of the present disclosure. Figure 2 As shown, the die interconnect controller of the first storage control die chip and the die interconnect controller of the second storage control die chip can be connected through metal wires.

[0014] Figure 3 Schematic diagram of a bare chip according to an embodiment of the present disclosure, which may be a first storage control bare chip or a second storage control bare chip, such as Figure 3 As shown, in addition to the bare chip interconnect controller, the first storage control bare chip and the second storage control bare chip also include the following corresponding components: a host interface module, a data processing module, a cache module and a FLASH management interface module; wherein, The host interface is configured to: receive a command message from an external module for accessing the storage controller, and send the received command message to the data processing module; reply to the external module according to the completion of data caching of the cache module or the reply of the data processing module to the command message; The data processing module is configured to: process the data written by the host and / or the data from the FLASH management interface module according to the command message, and send the processed data to the cache module; The cache module is configured to: cache received data and manage a queue pointer of the data cache; The FLASH management interface module is configured to send the read data from the storage particles to the cache module or write the data in the cache module into the storage particles.

[0015] In an exemplary embodiment, under the control of the bare die interconnect controller, the embodiment of the present disclosure sends the data input by the host to the data processing module for processing and then sends it to the cache module cache, or sends the data from the storage particles in the Flash management interface to the data processing module for processing and then sends it to the cache module cache. In the embodiment of the present disclosure, the bare die interconnect controller of the first storage control bare die chip can forward the data in its own cache module to the second storage control bare die chip, or the bare die interconnect controller of the second storage control bare die chip can forward the data in its own cache module to the first storage control bare die chip.

[0016] See also Figure 3 As shown in the architecture, the bare die interconnect controller of the embodiment of the present disclosure is located in the data flow path to perform data reading or writing processing in the first storage control bare die chip or the second storage control bare die chip.

[0017] The data flow branch point of the first storage control bare chip or the second storage control bare chip is set between the data processing module and the cache module.

[0018] In an exemplary instance, the data processing module of the embodiment of the present disclosure is configured to: determine the data flow direction according to a command message; process the data written by the host and / or the data from the FLASH management interface module according to the determined data flow direction, and send the processed data to the cache module.

[0019] In an exemplary embodiment, the command message of the embodiment of the present disclosure includes a logical cluster address LCA, and LCA includes flow field information for identifying whether the data is handed over to the first storage control bare chip or the second storage control bare chip for processing. For example: LCA[0] == 1'b0 indicates that the data processing module sends and receives data streams to be processed by the first storage control bare chip, and LCA[0] == 1'b1 indicates that the data processing module sends and receives data streams to be processed by the second storage control bare chip.

[0020] In an exemplary embodiment, the data flow between the data processing module and the cache module of the embodiment of the present disclosure is processed in the following form: Command messages, queue pointers and DMA data; Among them, the command message includes a logical cluster address LCA, and LCA includes flow field information used to identify that data is handed over to the first storage control bare chip chip or the second storage control bare chip chip for processing; the queue pointer is issued by the cache module, which is a parameter used for command information processing. The queue pointer is synchronized to the first storage control bare chip chip and the second storage control bare chip chip, and the first storage control bare chip chip or the second storage control bare chip chip is determined to perform data transmission and reception based on the flow field information; DMA data is used to determine the switching data direction based on the flow field information.

[0021] Figure 4 Schematic diagram of a storage controller according to an embodiment of the present disclosure, Figure 4 As shown, the first storage control die chip and the second storage control die chip both include a die interconnect controller, and the data flows of the first storage control die chip and the second storage control die chip are processed by the die interconnect controller and then enter the cache module; the data flows in the disclosed embodiment include: host write data and host read data; wherein, the host read data includes data read and pre-read.

[0022] The host writes data in the disclosed embodiment. The only command messages involved are all with LCA, and all data streams can be split and processed according to LCA; The command message and queue pointer involved in reading data in the embodiment of the present disclosure, wherein the command message carries LCA and can be processed in a branching manner according to LCA; the queue pointer carries a direction mark after being transmitted through the bare chip interconnect controller.

[0023] In the embodiment of the present disclosure, the first storage control die chip and the second storage control die chip need to perform data flow processing through a die interconnect controller for command communication and state synchronization between the first storage control die chip and the second storage control die chip, and a communication mechanism including interrupts and caches needs to be set. In the embodiment of the present disclosure, the following interrupts are added to the die interconnect controller:

[0024] Communication message received interrupt (Mailbox RX Intr, including read and write message and other message received interrupts except management messages), management message received interrupt (Mailbox ADM RX Intr), communication message sent interrupt (Mailbox TX_Done Intr) and management message sent interrupt (Mailbox ADM TX_Done Intr).

[0025] In an exemplary embodiment, the above interrupt signal of the embodiment of the present disclosure can refer to the relevant technology and be generated by a signal with a level change; for example, Mailbox RX intr can be generated by an upward jump of the Flag signal, Mailbox TX_Done Intr can be generated by a downward jump of the Flag signal, and the bare chip interconnect controller obtains the Mailbox RX intr of the opposite end flag register; the first storage control bare chip notifies the second storage control bare chip to receive data by setting its own flag register, and the second storage control bare chip notifies the first storage control bare chip that the data transmission is completed by resetting the flag register of the first storage control bare chip. The actual data to be sent is written by (the first storage control bare chip or the second storage control bare chip) to the receiving end cache through the bare chip interconnect controller. The first storage control bare chip and the second storage control bare chip of the embodiment of the present disclosure can add transceiver flags, transceiver parameters, cache base address and cache size registers for communication and data exchange.

[0026] Figure 5 FIG. 1 is a schematic diagram of the communication process of the storage controller according to an embodiment of the present disclosure. Figure 5 As shown, the first storage control bare chip first sends the data to be sent into the cache, then sets the Flag, and then receives an interrupt. The second storage control bare chip takes out the data to be sent from the cache and sends it. Conversely, the second storage control bare chip sends the data to be sent into the cache, then sets the Flag, and then receives an interrupt. The first storage control bare chip takes out the data to be sent from the cache and sends it.

[0027] It will be appreciated by those skilled in the art that all or some of the steps, systems, and functional modules / units in the methods disclosed above may be implemented as software, firmware, hardware, and appropriate combinations thereof. In hardware implementations, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed by several physical components in cooperation. Some or all components may be implemented as software executed by a processor, such as a digital signal processor or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or transient medium). As is known to those skilled in the art, the term "computer storage medium" includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, it is well known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

Claims

1. A solid state hard disk storage module, comprising two or more storage particles, characterized in that: include: A storage controller integrating a first storage control bare chip and a second storage control bare chip, wherein the storage particles and the storage controller are integrated on the same circuit board; The first storage control bare chip and the second storage control bare chip respectively include corresponding bare chip interconnection controllers, and the bare chip interconnection controller of the first storage control bare chip and the bare chip interconnection controller of the second storage control bare chip establish communication between chips for exchanging data between chips, thereby performing data reading and writing of two or more storage particles; The data exchange between the chips includes: the die interconnect controller of the first storage control die chip forwards the data to the second storage control die chip; or, the die interconnect controller of the second storage control die chip forwards the data to the first storage control die chip.

2. The solid state hard disk storage module according to claim 1, characterized in that: The die interconnect controller of the first storage control die chip and the die interconnect controller of the second storage control die chip are physically connected.

3. The solid state hard disk storage module according to claim 1, characterized in that: The first storage control bare chip and the second storage control bare chip both further include the following corresponding components: a host interface module, a data processing module, a cache module and a FLASH management interface module; wherein, The host interface is configured to: receive a command message of an external module accessing the storage controller, and send the received command message to the data processing module; and reply to the external module according to the data cache completion status of the cache module or the reply status of the data processing module to the command message; The data processing module is configured to: process the data written by the host and / or the data from the FLASH management interface module according to the command message, and send the processed data to the cache module; The cache module is configured to: cache received data and manage a queue pointer of the data cache; The FLASH management interface module is configured to send read data from the storage particles to the cache module or write data in the cache module into the storage particles.

4. The solid state hard disk storage module according to claim 3, characterized in that: The data processing module is configured as follows: Determine the data flow direction according to the command message; process the data written by the host and / or the data from the FLASH management interface module according to the determined data flow direction, and send the processed data to the cache module.

5. The solid state hard disk storage module according to claim 4, characterized in that: The command message includes a logical cluster address LCA, and the LCA includes flow field information for identifying that data is handed over to the first storage control bare chip or the second storage control bare chip for processing.

6. The solid state hard disk storage module according to any one of claims 1 to 5, characterized in that: The data flow between the data processing module and the cache module is processed in the following form: Command messages, queue pointers and DMA data; Among them, the command message includes a logical cluster address LCA, and the LCA includes flow field information for identifying that the data is handed over to the first storage control bare chip chip or the second storage control bare chip chip for processing; the queue pointer is issued by the cache module, which is a parameter for processing the command information, and the queue pointer is synchronized to the first storage control bare chip chip and the second storage control bare chip chip, and it is determined whether the first storage control bare chip chip or the second storage control bare chip chip executes data transmission and reception based on the flow field information; the DMA data is used to determine the switching data direction based on the flow field information.

7. The solid state disk storage module according to any one of claims 1 to 5, characterized in that: The following interrupts are added to the die interconnect controller: Communication message received interruption, management message received interruption, communication message sent interruption and management message sent interruption.

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