Communication system, communication method and SPI (Serial Peripheral Interface) equipment

Abstract

The invention relates to the field of communication, and discloses a communication system, a communication method and SPI equipment. The system comprises SPI master equipment, SPI slave equipment and an expansion control chip, wherein the SPI master equipment is connected with the last SPI slave equipment through a master equipment output line; the SPI slave devices are connected in series through slave device output lines, and the first SPI slave device is connected to a master device input pin of the SPI master device through the slave device output line; the first end of the expansion control chip is connected with the chip selection pin of the SPI master device, and the second end of the expansion control chip is connected with the chip selection pins of the SPI slave devices. The chip selection function is expanded by setting the expansion control chip, so that one SPI master device can synchronously control a plurality of SPI slave devices, synchronous communication with the plurality of SPI slave devices is realized, and the communication efficiency among the devices is effectively improved.

Description

Technical Field

[0001] The present application relates to the field of communications, and in particular to a communication system, a communication method and an SPI device. Background Art

[0002] In the SPI (Serial Peripheral Interface) bus protocol, the SS (Slave Select) signal is an important slave device selection signal, which allows the master device (Master) to selectively communicate with a slave device without interfering with other slave devices that may be connected to the same SPI bus. The SS signal is usually controlled by the master device. Before the SPI communication starts, the master device will send a chip select signal to all slave devices, that is, set the SS signal to a low level, which means that the master device is communicating with a specific slave device. Other unselected slave devices will remain silent during this period and will not try to respond to the master device's commands. After the communication is completed, the master device will set the SS signal to a high level again to release the selection state of the specific slave device and allow other slave devices to prepare for the next communication. Therefore, the SS signal is a key control signal in SPI communication, which enables the master device to select one of multiple connected slave devices for data transmission, thereby realizing point-to-point communication.

[0003] However, based on the SPI bus protocol, a master device can only communicate with one slave device at a time and cannot achieve synchronous communication with multiple slave devices, resulting in low communication efficiency. Summary of the invention

[0004] In view of this, in order to solve the problems existing in the prior art, the present application provides a communication system, a communication method and an SPI device.

[0005] In a first aspect, the present application provides a communication system, including an SPI master device, multiple SPI slave devices, and an expansion control chip;

[0006] The serial clock pin of the SPI master device is respectively connected to the serial clock pin of each of the SPI slave devices, and the SPI master device is connected to the last SPI slave device through a master device output line;

[0007] The SPI slave devices are connected in series via a slave device output line, and the first SPI slave device is connected to a master device input pin of the SPI master device via the slave device output line;

[0008] A first end of the expansion control chip is connected to a chip select pin of the SPI master device, and a second end of the expansion control chip is respectively connected to a chip select pin of each of the SPI slave devices;

[0009] The SPI master device is used to send a communication message to the last SPI slave device through the master device output line; the first SPI slave device is used to send a transmission message to the SPI master device through the slave device output line; the transmission message is obtained based on the communication message;

[0010] The SPI master device is also used to send a chip select signal to the extended control chip, and the chip select signal is used to instruct the extended control chip to enable the chip select pin of the target SPI slave device so that the target SPI slave device communicates with the SPI master device.

[0011] In a second aspect, the present application provides a communication method, which is applied to the SPI slave device in the communication system described in the aforementioned embodiment, and the method includes:

[0012] If it is determined that the chip select pin of the current SPI slave device is enabled, after receiving a first message sent by the SPI master device or the next SPI slave device, the first message is processed to obtain a second message, and the second message is transmitted to the previous SPI slave device or the SPI master device; wherein the first message is the original message sent by the SPI master device.

[0013] In an optional embodiment, it also includes:

[0014] Receive a third message sent by the next SPI slave device, and transmit the third message to the previous SPI slave device; wherein the third message includes tag information of a target SPI slave device; the target SPI slave device is an SPI slave device with a chip select pin enabled.

[0015] In an optional embodiment, it also includes:

[0016] If it is determined that the chip select pin of the current SPI slave device is not enabled, after receiving the first message and the second message, each message is directly transmitted to the previous SPI slave device.

[0017] In an optional implementation manner, before receiving the first message sent by the SPI master device or the next SPI slave device, the method further includes:

[0018] Receive a clock pulse sent by the SPI master device; wherein the clock pulse is used to indicate a sending rate when the current SPI slave device sends the first message and the second message.

[0019] In an optional implementation manner, if the current SPI slave device is not the first SPI slave device, after receiving the first message sent by the SPI master device or the next SPI slave device, the method further includes:

[0020] The first message is copied, and a first copy of the first message is forwarded to the previous SPI slave device to process a second copy of the first message.

[0021] In a third aspect, the present application provides a communication method, which is applied to the SPI master device in the communication system described in the aforementioned embodiment, and the method includes:

[0022] Sending a first chip select signal to the extended control chip, wherein the first chip select signal is used to instruct the extended control chip to enable a chip select pin of at least one target SPI slave device;

[0023] Sending a first message to the last SPI slave device; wherein, during the process of the first message being transmitted upward via the last SPI slave device, when the first message reaches the target SPI slave device, the target SPI slave device processes the first message to obtain a second message;

[0024] The transmitted second message is received.

[0025] In an optional embodiment, it also includes:

[0026] The message quantity of the second message received is equal to the quantity of the target SPI slave devices.

[0027] In an optional implementation manner, after the receiving of the transmitted second message, the method further includes:

[0028] A second chip select signal is sent to the extended control chip, where the second chip select signal is used to instruct the extended control chip to set the working state of the chip select pins of all SPI slave devices to a disabled state.

[0029] In a fourth aspect, the present application provides an SPI device, comprising a memory and a processor, wherein the memory stores a computer program, and the processor is configured to execute the computer program to implement the aforementioned communication method.

[0030] The embodiments of the present application have the following beneficial effects:

[0031] The embodiment of the present application provides a communication system, including an SPI master device, multiple SPI slave devices and an extended control chip; the serial clock pin of the SPI master device is respectively connected to the serial clock pin of each SPI slave device, and the SPI master device is connected to the last SPI slave device through the master device output line; the SPI slave devices are connected in series through the slave device output line, and the first SPI slave device is connected to the master device input pin of the SPI master device through the slave device output line; the first end of the extended control chip is connected to the chip select pin of the SPI master device, and the second end of the extended control chip is respectively connected to the chip select pins of each SPI slave device; the SPI master device is used to send a communication message to the last SPI slave device through the master device output line; the first SPI slave device is used to send a transmission message to the SPI master device through the slave device output line; the transmission message is obtained based on the communication message; the SPI master device is also used to send a chip select signal to the extended control chip, and the chip select signal is used to instruct the extended control chip to enable the chip select pin of the target SPI slave device so that the target SPI slave device communicates with the SPI master device. This embodiment expands the chip select function by setting an extended control chip, thereby expanding the chip select pin, so that an SPI master device can synchronously control multiple SPI slave devices through the extended control chip. While reducing the resource consumption of the master device, it can also synchronously realize communication with multiple SPI slave devices and batch read and write operations, effectively improving the communication efficiency between various devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solution of the present application, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present application and should not be regarded as limiting the scope of protection of the present application. In each of the drawings, similar components are numbered similarly.

[0033] Figure 1 A schematic diagram showing a conventional connection relationship between an SPI master device and an SPI slave device is shown;

[0034] Figure 2 A schematic diagram of a conventional interaction between an SPI master device and a single SPI slave device is shown;

[0035] Figure 3 A schematic diagram of the structure of a communication system in an embodiment of the present application is shown;

[0036] Figure 4 A schematic diagram showing a connection relationship of a communication system in an embodiment of the present application is shown;

[0037] Figure 5 A schematic diagram of interaction between an SPI master device and an SPI slave device in an embodiment of the present application is shown;

[0038] Figure 6 A schematic diagram of a scenario in which an SPI master device communicates with a single SPI slave device in an embodiment of the present application is shown;

[0039] Figure 7 A schematic diagram of a scenario in which an SPI master device communicates with all SPI slave devices in an embodiment of the present application is shown;

[0040] Figure 8 A schematic diagram of a flow chart of a communication method executed by an SPI master device in an embodiment of the present application is shown;

[0041] Fig. 9 A schematic diagram of a flow chart of a communication method executed by any SPI slave device in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0042] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments.

[0043] The components of the embodiments of the present application generally described and shown in the drawings herein may be arranged and designed in various configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application claimed for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present application.

[0044] Hereinafter, the terms "including", "having" and their cognates, which may be used in various embodiments of the present application, are intended only to indicate specific features, numbers, steps, operations, elements, components, or combinations of the foregoing items, and should not be understood as first excluding the existence of one or more other features, numbers, steps, operations, elements, components, or combinations of the foregoing items or adding the possibility of one or more features, numbers, steps, operations, elements, components, or combinations of the foregoing items.

[0045] Furthermore, the terms “first”, “second”, “third”, etc. are merely used for distinguishing descriptions and are not to be understood as indicating or implying relative importance.

[0046] Unless otherwise defined, all terms (including technical terms and scientific terms) used herein have the same meanings as those generally understood by those skilled in the art to which the various embodiments of the present application belong. The terms (such as those defined in generally used dictionaries) will be interpreted as having the same meanings as the contextual meanings in the relevant technical field and will not be interpreted as having idealized meanings or overly formal meanings unless clearly defined in the various embodiments of the present application.

[0047] SPI (Serial Peripheral Interface), a synchronous serial communication interface, is widely used between embedded systems, sensors, memory and other peripheral devices and microcontrollers.

[0048] The SPI standard interface usually includes the following four lines:

[0049] SCLK (Serial Clock), serial clock line, a clock signal generated by the master device, controls the rate of data transmission.

[0050] MISO (Master In Slave Out), master device output / slave device input line, used for master device to transmit data to slave device.

[0051] MOSI (Master Out Slave In), master device input / slave device output line, is used to transmit data from the slave device to the master device.

[0052] or (Slave Select / Chip Select): Slave device select line, controlled by the master device, used to select a specific slave device to communicate with it.

[0053] The conventional SPI master-slave structure consists of a SPI master device and multiple SPI slave devices, such as Figure 1 As shown, the various pins of an SPI master device (such as SCK pin, MOSI pin, MISO pin, Pins, Pins, ..., pins, etc.) are connected to the corresponding pins (such as SCK pin, SIMO pin, SOMI pin, Pin) connection, wherein the SPI master device controls the communication status with the SPI slave device accordingly through the chip select pin; based on the SPI master-slave structure, if the SPI master device needs to communicate with a certain SPI slave device, it needs to connect to the chip select pin of the SPI slave device. Since the SPI master device has only one chip select pin, therefore, one SPI master device can only be connected to the chip select pin of one SPI slave device, and then one SPI master device can only establish communication with one SPI slave device, and cannot establish communication with multiple SPI slave devices at the same time in batches, and thus cannot meet the batch reading and writing requirements.

[0054] like Figure 2 As shown, when the above SPI master-slave structure realizes interactive communication, the SPI master device sends a low-level chip select signal ( signal) to enable the SPI slave device and send a clock pulse signal (SCK signal) to the SPI slave device; then a communication message is input to the SIMO pin of the enabled SPI slave device through the MOSI pin, thereby realizing the master device output, so that the SPI slave device sends a response message (the response message is obtained based on the received communication message) to the SPI master device through the SOMI pin, thereby realizing the master device input.

[0055] Among them, the SPI slave device receives and sends the corresponding message according to the rising edge or falling edge of the SCK signal. That is, the SPI master device outputs the corresponding clock pulse, and then transmits the data to be transmitted in the form of 1 bit to the MOSI signal line one by one, so that it is transmitted to the SPI slave device, and when the enabled SPI slave device detects the edge signal of the clock pulse, it will immediately read the data on the MOSI signal line (that is, 1 bit of data); among them, if the SPI slave device needs to feedback data to the SPI master device, the SPI master device will continue to generate a predetermined number of clock pulses, and the SPI slave device will then send the data to be fed back to the SPI master device through the SOMI signal line according to the edge signal of the clock pulse.

[0056] The present application provides a communication system, which expands the chip select signal line by adding an expansion control chip, so that an SPI master device can simultaneously control the chip select pins of multiple SPI slave devices through the expansion control chip, thereby realizing batch data read and write operations.

[0057] For example, please refer to Figure 3, the communication system includes an SPI master device 100, a plurality of SPI slave devices 200 and an expansion control chip 300. The SPI master device 100, the expansion control chip 300 and the SPI slave device 200 are connected in sequence, and the SPI master device 100 is also directly connected to each SPI slave device 200. For the convenience of description, each SPI slave device 200 can be numbered (such as slave device 1, slave device 2, ..., slave device n, etc. shown in the figure).

[0058] Furthermore, if Figure 4 As shown in the figure, the serial clock pin (SCK pin) of the SPI master device is connected to the serial clock pin of each SPI slave device through the serial clock line (i.e., SCLK line) in the SPI bus. Then, after generating the clock signal, the SPI master device can send the clock signal to each SPI slave device to achieve clock synchronization between the master and slave devices, i.e., synchronize the data transmission rate. After receiving the clock signal, each SPI slave device must strictly follow the rising or falling edge of the clock signal to receive or send data. That is, the SPI master device can send a clock pulse to each SPI slave device; then, the clock pulse is used to indicate the sending rate of each SPI slave device when sending the corresponding message.

[0059] The output pin (MOSI pin) of the SPI master device is connected to the input pin (SIMO pin) of the last SPI slave device through the master device output line (MOSI line).

[0060] Starting from the last SPI slave device, the output pins (SOMI pins) of each SPI slave device are connected in series through the slave device output line, and the output pin of the first SPI slave device is connected to the master device input pin of the SPI master device through the slave device output line.

[0061] It can be understood that the SPI master device and each SPI slave device implement data output / input correspondingly through the output line / input line. Furthermore, the SPI master device and each SPI slave device form a transmission link in the corresponding direction through the above-mentioned connection relationship: the SPI master device can send a communication message to the last SPI slave device through the master device output line; and the communication message is transmitted between each SPI slave device through the slave device output line until it reaches the first SPI slave device; and each SPI slave device can process the communication message after receiving the communication message to obtain a corresponding transmission message, and the transmission message can also be transmitted between each SPI slave device through the slave device output line until it reaches the first SPI slave device; and the first SPI slave device can send a transmission message to the SPI master device through the slave device output line.

[0062] It is worth noting that, in this embodiment, the output pin of the SPI master device is connected to the input pin of the first SPI slave device through the master device output line, and then, starting from the first SPI slave device, the output pins of each SPI slave device are connected in series through the slave device output line, and the output pin of the last SPI slave device is connected to the master device input pin of the SPI master device through the slave device output line. Furthermore, in this embodiment, the connection relationship between the SPI master device and each SPI slave device can be adjusted accordingly, so as to form a transmission link different from the above transmission direction. That is, in this embodiment, the direction of the data transmission link between the SPI master device and each SPI slave device is not limited, and it can be adaptively set according to actual needs.

[0063] It should be noted that no matter which transmission direction of the data transmission link, only the SPI slave device with the chip select pin enabled can process the communication message sent by the SPI master device, that is, realize communication with the SPI master device, while the remaining SPI slave devices that are not enabled can only forward the corresponding message and cannot process the message.

[0064] Furthermore, this embodiment expands the chip select signal line by expanding the control chip, so that one SPI master device can enable multiple SPI slave devices at the same time, thereby realizing communication with multiple SPI slave devices at the same time.

[0065] The first end of the extended control chip is connected to the slave device selection line (i.e. The second end of the expansion control chip is connected to the chip select pin of each SPI slave device through the slave device select line.

[0066] Furthermore, the SPI master device may send a chip select signal to the extended control chip, where the chip select signal is used to instruct the extended control chip to enable the chip select pin of the target SPI slave device, so that the enabled target SPI slave device communicates with the SPI master device.

[0067] It can be understood that in this embodiment, the SPI master device can synchronously enable multiple SPI slave devices by expanding the control chip, thereby avoiding the situation where the SPI master device and the SPI slave device are connected separately through the slave device selection line, resulting in only one-to-one communication and the inability to implement read and write operations of multiple SPI slave devices in batches.

[0068] Optionally, the extended control chip includes but is not limited to a complex programmable logic device chip (CPLD chip) and other chips used to implement the function of the extended chip select signal line; the chip type selected by the extended control chip can be set accordingly according to actual needs, and this embodiment does not limit this.

[0069] Among them, after the SPI master device and the SPI slave device are powered on, the SPI master device can obtain the identification numbers of all SPI slave devices through a static method (such as receiving and recording the identification numbers (ID) of all SPI slave devices input by the user, and the identification number of each SPI slave device is unique), and can subsequently use the identification number to indicate communication with the corresponding SPI slave device.

[0070] by Figure 4 Taking the connection relationship diagram shown in the figure as an example, the interaction process is that the SPI master device sends a chip select signal to the extended control chip, and the chip select signal is used to indicate the enablement of the target SPI slave device; then, after receiving the chip select signal, the extended control chip enables the target SPI slave device to work according to the chip select signal; then the SPI master device can send a communication message to the last connected SPI slave device through the MOSI pin, and after the communication message is input by the last SPI slave device, it flows between each SPI slave device until it reaches the pre-enabled target SPI slave device, and the target SPI slave device then processes the communication message and transmits a corresponding response message to the SPI master device.

[0071] In some examples, such as Figure 5 As shown, when the SPI master device sends a message to each SPI slave device or when the SPI slave device sends a message to the SPI master device, a corresponding address bit can be added to the header of the message. The address bit is used to identify the SPI slave device that receives or sends the message; wherein, the length of the address bit can be adaptively set according to actual needs, such as 5 bits, 10 bits, etc.

[0072] Furthermore, the SPI master device sends a chip select signal to the extended control chip, and the extended control chip enables the target SPI slave device according to the chip select signal, so that the target SPI slave device has the ability to communicate with the SPI master device, and then the enabled target SPI slave device can execute the corresponding operation commands (such as data read commands and data write commands, etc.) carried in the communication message sent by the SPI master device.

[0073] In one example, if Figure 6 As shown, when accessing and reading and writing data of a single SPI slave device is realized, the SPI master device sends a chip select signal to the extended control chip, and the extended control chip enables the chip select pin of a single target SPI slave device according to the chip select signal, thereby enabling the target SPI slave device to have the function of communicating with the SPI master device.

[0074] Further, the communication process in this case is that the SPI master device sends a first message to the last SPI slave device; wherein, after the first message is input by the last SPI slave device, it flows between the SPI slave devices, that is, the last SPI slave device transmits the first message upward; and during the message transmission process, if the SPI slave device through which the message passes is not the target SPI slave device, the SPI slave device does not process the first message, and only performs a forwarding operation on the first message to forward the first message to the previous SPI slave device; if the message reaches the enabled target SPI slave device, the target SPI slave device processes the first message; wherein the processing process is to process the original message (that is, the first message) to obtain a second message, and transmit the second message to the previous SPI slave device or the SPI master device.

[0075] Optionally, before transmitting the second message, the current target SPI master device may add marking information of the current SPI slave device in the second message, so that after receiving the second message, the subsequent SPI master device can identify and mark the data in the second message according to the marking information, which is convenient for subsequent data recording and processing, and can also quickly determine whether abnormal problems such as missing message reception occur.

[0076] It can be understood that the first message received by each target SPI slave device is the original message sent by the SPI master device; after receiving the first message, each target SPI slave device can process the first message, wherein the processing includes parsing the first message, and then executing the operation command carried in the first message to obtain a corresponding response message (i.e., the second message).

[0077] In some examples, if multiple target SPI slave devices are enabled synchronously, after each target SPI slave device receives the first message, in order to ensure that the remaining other target SPI slave devices (i.e., the target SPI slave devices that have not processed the original message) can receive the unprocessed original message and process the original message, the first message can be copied first and one of the copied first messages can be transparently transmitted upward.

[0078] Then, the other retained first message is processed, and optionally, the tag information of the current target SPI slave device can be added to the second message, and then the second message is transparently transmitted upward.

[0079] Among them, if the target SPI slave device is an intermediate slave device or the last slave device, one of the first message and the second message is transparently transmitted to the previous slave device; if the target SPI slave device is the first slave device, the first message and the second message are forwarded to the SPI master device.

[0080] In another example, similarly, if access and data reading and writing of multiple SPI slave devices are implemented, the SPI master device sends a chip select signal to the extended control chip, and the extended control chip enables the chip select pins of multiple target SPI slave devices according to the chip select signal, thereby enabling the multiple target SPI slave devices to have the function of communicating with the SPI master device.

[0081] Furthermore, the communication process in this case is that the SPI master device sends a first message to the last SPI slave device; wherein, after the first message is input by the last SPI slave device, it flows between the SPI slave devices, that is, the last SPI slave device transmits the first message upward; and during the message transmission process, if the SPI slave device through which the message passes is not the target SPI slave device, the SPI slave device does not process the first message, and only performs a forwarding operation on the first message to forward the first message to the previous SPI slave device; if the message reaches the enabled target SPI slave device, the target SPI slave device processes the first message; wherein, the processing process is consistent with the processing process of the aforementioned enabled single target SPI slave device, so it is not repeated here.

[0082] That is, after enabling multiple target SPI slave devices, each target SPI slave device performs the copying and forwarding of the original message, and after processing the reserved original message, the response message (i.e., the second message) with its own tag information added is transparently transmitted to the previous SPI slave device or SPI master device. Among them, if the first SPI slave device is the target SPI slave device, it is not necessary to perform the copying operation of the original message, and the received original message can be directly processed.

[0083] It can be seen that the unprocessed first message needs to pass through each SPI slave device, so that each target SPI slave device processes the original message.

[0084] In addition, since each message is transmitted upward in sequence during the transparent transmission process, some target SPI slave devices may receive the third message transmitted by the next SPI slave device, which is the second message obtained after other target SPI slave devices process the original message.

[0085] Furthermore, the current target SPI slave device does not process the received third message, and directly transparently transmits the third message to the previous SPI slave device or the SPI master device.

[0086] Furthermore, if there are multiple target SPI slave devices, each target SPI slave device only processes the received original message, and directly transparently transmits an unprocessed original message and other received messages (third message) to the previous SPI slave device and the SPI master device.

[0087] In another example, similarly, Figure 7 As shown, when access and data reading and writing of all SPI slave devices are realized, the SPI master device sends a chip select signal to the extended control chip, and the extended control chip enables the chip select pins of all SPI slave devices according to the chip select signal, thereby enabling the multiple target SPI slave devices to have the function of communicating with the SPI master device.

[0088] Similar to the above-mentioned process of enabling the chip select pins of multiple target SPI slave devices so that the multiple target SPI slave devices can all communicate with the SPI master device, after enabling the chip select pins of all SPI slave devices, each SPI slave device only processes the received original message, and directly transparently transmits an unprocessed original message and other received messages (the third message) to the previous SPI slave device and the SPI master device. This embodiment does not elaborate on this communication process.

[0089] In addition, after the SPI master device receives the second message and / or the third message, the SPI master device can send a second chip select signal to the extended control chip, and the second chip select signal is used to instruct the extended control chip to set the working state of the chip select pins of all SPI slave devices to a disabled state, thereby indicating that the communication process has been completed; that is, after receiving feedback from the target SPI slave device, the SPI master device can completely disable chip selection of all SPI slave devices to wait for the next communication.

[0090] It can be understood that based on the communication system, the present embodiment can realize the access of a single SPI slave device, the synchronous access of multiple SPI slave devices and the synchronous access of all SPI slave devices, and when accessing a single SPI slave device, the SPI master device sends a chip select signal to a specific SPI slave device, and the specific SPI slave device processes the communication message after receiving it and returns the result; when accessing multiple SPI slave devices synchronously, the SPI master device sends a chip select signal to some specific SPI slave devices, and some specific SPI slave devices process the communication messages sent by the SPI master device in turn and return the result; when accessing all SPI slave devices synchronously, the SPI master device sends a chip select signal to all SPI slave devices, and all SPI slave devices process the communication messages sent by the SPI master device in turn and return the result.

[0091] For ease of understanding, this embodiment illustrates the communication processes in the above different situations by using examples.

[0092] For example, when accessing a single SPI slave device, taking access to the first SPI slave device as an example (i.e., only enabling the first SPI slave device); the communication process is that the SPI master device sends a chip select signal to the extended control chip (wherein, the form of the chip select signal is not limited in this embodiment, for example, the chip select signal can be set to 0x00000001), and the 0x00000001 signal instructs the extended control chip to enable the first SPI slave device to work, and then after the extended control chip is enabled, in the current state, only the first SPI slave device can communicate with the SPI master device; and the working states of the chip select pins of the remaining SPI slave devices are all in a disabled state, and cannot communicate with the SPI master device.

[0093] Furthermore, the SPI master device sends a serial clock signal to each SPI slave device to ensure time synchronization between each SPI slave device and the SPI master device.

[0094] Then, the SPI master device sends the first message to the last SPI slave device through the master device output line; in addition, in this embodiment, the address of the first message can also be set to 0x1F.

[0095] Assuming that the communication system includes N SPI slave devices, and the original message, that is, the first message, is message A, the last slave device is numbered N, so the last slave device can be set as slave device N, and the numbers of other slave devices can be obtained by analogy.

[0096] Furthermore, after receiving the message A, the last SPI slave device (i.e., slave device N) first determines whether its own chip select pin is enabled. Since the last SPI slave device is not enabled, it cannot communicate with the SPI master device and thus cannot process the message A. Therefore, slave device N forwards the message A to the previous SPI slave device (i.e., slave device N-1) through the slave device output line. After receiving the message A, slave device N-1 also first determines whether its own chip select pin is enabled. If not enabled, it forwards the message A to the previous SPI slave device (i.e., slave device N-2).

[0097] Similarly, since slave devices N-2 to slave device 2 are not enabled, these slave devices all execute the same processing flow as the aforementioned slave device N or slave device N-1, and directly transmit the message A upward until it reaches the first enabled SPI slave device (i.e., slave device 1). After receiving the message A, slave device 1 processes the message A according to an internal preset mechanism, such as parsing the message A and executing the data read command or data write command carried in the message A, and obtaining a corresponding response message, to which the tag information of slave device 1 may be added; wherein, in this embodiment, for the convenience of distinction, the response message transmitted by slave device 1 is used as the second message (which may be called message B), and then, slave device 1 transmits message B to the SPI master device through the slave device output line.

[0098] After receiving the message B, the SPI master device can process the message B accordingly according to the preset mechanism, and send a chip select signal to the extended control chip again. The extended control chip sets the working state of the chip select pins of all SPI slave devices to a disabled state according to the chip select signal, thereby completing the access process of a single slave device. Among them, this embodiment does not limit the form of the chip select signal for disabling the chip select pins of all SPI slave devices. For example, the chip select signal can be set to 0x00000000.

[0099] In one embodiment, implementing synchronous access to multiple SPI slave devices includes synchronously accessing all SPI slave devices and synchronously accessing some SPI slave devices.

[0100] Similar to the above-mentioned access to a single SPI slave device, if all SPI slave devices are accessed in batches, the communication process is that the SPI master device sends a chip select signal (for example, 0xFFFFFFFF) to the extended control chip, and the chip select signal instructs the extended control chip to enable all SPI slave devices to work. After the extended control chip completes the enabling, in the current state, all SPI slave devices can communicate with the SPI master device.

[0101] Furthermore, the SPI master device sends a serial clock signal to each SPI slave device to ensure time synchronization between each SPI slave device and the SPI master device.

[0102] Then, the SPI master device sends the first message (message A) to the last SPI slave device (slave device N) through the master device output line, wherein the address of the first message can be set to 0x1F.

[0103] Furthermore, after receiving the message A, the slave device N first copies the message A and transmits the first copy of the message A to the slave device N-1; after processing the second copy of the message A according to the preset mechanism, a response message is obtained, and the tag information of the current target SPI slave device (slave device N) can be added to the response message to obtain the message B, and then the message B is transmitted to the slave device N-1.

[0104] Similarly, after receiving the message A and the message B, the slave device N-1 copies the message A and transmits the first message A and the first message B to the slave device N-2 respectively. Since the time when the slave device N-1 receives the two messages may be different, the transmission actions can be completed one after another.

[0105] The slave device N-1 then processes the retained second copy of message A to obtain a response message, wherein the response message may be added with the tag information of the slave device N-1, and transmits the response message to the slave device N-2. At this time, the response message may be recorded as message C.

[0106] Furthermore, slave device N-2 can receive three different messages (message A, message B containing the tag information of slave device N, and message C containing the tag information of slave device N-1). Then, the same processing logic as slave device N-1 is executed, the original message (i.e., message A) is copied, and then one original message is left, and the other received messages (another message A, message B, and message C) are all transmitted upward, and then the remaining original message is processed to obtain message D containing the tag information of slave device N-2.

[0107] Obviously, after all SPI slave devices are enabled, during the communication process, each SPI slave device can receive |XN-1| different messages (including the original message), where X represents the number of the current SPI slave device.

[0108] Then, at the first SPI slave device, slave device 1 receives message A and (|XN-1|-1) different response messages; slave device 1 directly forwards (|XN-1|-1) different response messages to the SPI master device, processes the received message A to obtain a response message with the tag information of slave device 1 added, and then transmits the response message to the SPI master device. Among them, since slave device 1 is the last SPI slave device to process the original message, there is no need to perform the copying of message A, and message A can be directly processed.

[0109] Thus, the SPI master device can receive N messages, and each message contains the tag information of a corresponding SPI slave device. That is, the message volume of the response message (ie, the second message) received by the SPI master device is equal to the number of the target SPI slave devices.

[0110] Optionally, the SPI master device may also send a chip select signal (0x00000000) to the extended control chip again, and the extended control chip sets the working state of the chip select pins of all SPI slave devices to a disabled state according to the chip select signal, thereby completing the synchronous access process of all slave devices.

[0111] For example, if batch access is implemented to multiple SPI slave devices, the communication process is that the SPI master device sends a chip select signal (for example, 0x0000000F) to the extended control chip, and the 0x0000000F signal instructs the extended control chip to enable slave devices 1 to 4 to work. After the extended control chip completes the enabling, in the current state, only slave devices 1 to 4 can communicate with the SPI master device.

[0112] Similar to the above-mentioned batch access to all SPI slave devices, the SPI master device sends the first message (message A) to the last SPI slave device (slave device N) through the master device output line. After receiving message A, slave device N first determines whether its own chip select pin is enabled. Among them, since slave devices N to 5 are not enabled, they cannot communicate with the SPI master device, and thus cannot process message A. Therefore, slave devices N to 5 do not process message A, but forward message A to the previous SPI slave device through the slave device output line until it reaches slave device 4.

[0113] Among them, since slave devices 4 to 2 are all enabled, after receiving message A, slave devices 4 to 2 process message A according to internal preset mechanisms and obtain response messages with their own tag information added.

[0114] Then, at the first SPI slave device (slave device 1), slave device 1 receives message A, message E containing the tag information of slave device 4, message F containing the tag information of slave device 3, and message G containing the tag information of slave device 2; slave device 1 directly forwards message E, message F, and message G to the SPI master device, and processes the received message A to obtain a response message with the tag information of slave device 1 added, and then transmits the response message to the SPI master device; thus, the SPI master device can receive four messages.

[0115] Optionally, the SPI master device may also send a chip select signal (0x00000000) to the extended control chip again, and the extended control chip sets the working state of the chip select pins of all SPI slave devices to a disabled state according to the chip select signal, thereby completing the synchronous access process of some slave devices.

[0116] This embodiment expands the chip select function by adding an extended control chip, thereby expanding the chip select pins, so that an SPI master device can synchronously control multiple SPI slave devices through the extended control chip, while reducing the resource consumption of the master device, and can also synchronously realize communication with multiple SPI slave devices and batch read and write operations; and can also ensure through the message transparent transmission mechanism that the message sent by the SPI master device can pass through each SPI slave device and finally return to the SPI master device.

[0117] Correspondingly, based on the aforementioned communication system, the embodiment of the present application may further provide a communication method to be applied to the SPI master device in the aforementioned communication system.

[0118] For example, Figure 8 As shown, the SPI master device may include the following steps in the process of executing the communication method:

[0119] S110, sending a first chip selection signal to the extended control chip.

[0120] S120, sending a first message to the last SPI slave device.

[0121] S130, receiving a transmitted second message.

[0122] It can be understood that the SPI master device can send a first chip select signal to the extended control chip so that the extended control chip enables the chip select pin of at least one target SPI slave device according to the first chip select signal; wherein, if the SPI master device needs to enable a single SPI slave device, the first chip select signal can instruct the extended control chip to enable a corresponding SPI slave device; if the SPI master device needs to enable multiple SPI slave devices, the first chip select signal can instruct the extended control chip to enable the corresponding multiple SPI slave devices.

[0123] Then, the SPI master device sends a first message to the last connected SPI slave device through the MOSI pin according to the connection structure in the communication system, and the first message is transmitted upward and passes through each SPI slave device in turn; during the transmission of the first message, the enabled target SPI slave device can process the first message to obtain a second message. The second message can include the tag information corresponding to the target SPI slave device.

[0124] Furthermore, the second message is transmitted upward in sequence until it reaches the SPI master device; and the number of the second messages received by the SPI master device is consistent with the number of enabled target SPI slave devices.

[0125] This embodiment flexibly enables multiple SPI slave devices through the extended control chip, thereby realizing synchronous communication and batch read and write operations between the SPI master device and multiple SPI slave devices, and ensuring efficient and reliable communication between multiple devices.

[0126] Correspondingly, based on the aforementioned communication system, the embodiment of the present application may further provide a communication method to be applied to the SPI slave device in the aforementioned communication system.

[0127] For example, Fig. 9 As shown, the SPI slave device may include the following steps in the process of executing the communication method:

[0128] S210, if it is determined that the chip select pin of the current SPI slave device is enabled, after receiving a first message sent by the SPI master device or the next SPI slave device, the first message is processed to obtain a second message.

[0129] S220, transmitting the second message to the previous SPI slave device or SPI master device.

[0130] It can be understood that if the chip select pin of the current SPI slave device is determined to be enabled, it means that the current SPI device can communicate with the SPI master device, and then after receiving the first message sent by the SPI master device or the next SPI slave device, the first message can be processed according to the preset mechanism to obtain a response message (i.e., the second message); and then the second message is transmitted to the previous SPI slave device or SPI master device.

[0131] If multiple target SPI slave devices are enabled synchronously, and the currently enabled SPI slave device is not the first SPI slave device, the received first message may be copied first, and then one of the first messages is transparently transmitted upward, and then the other reserved first message is processed. If the currently enabled SPI slave device is the first SPI slave device, the copy operation is not performed, and the received first message is directly processed.

[0132] In addition, if the enabled current SPI slave device receives the third message transmitted by the next SPI slave device, the third message can be directly transparently transmitted to the previous SPI slave device or SPI master device, wherein the third message is the response message obtained after other target SPI slave devices process the first message.

[0133] That is, each enabled SPI slave device only processes the original message sent by the received SPI master device, and does not process other received messages.

[0134] Furthermore, if the chip select pin of the current SPI slave device is not enabled, all received messages are directly transparently transmitted to the previous SPI slave device or SPI master device.

[0135] This embodiment can realize efficient communication between the SPI master device and the SPI slave device, and through the transparent transmission mechanism of SOMI, it can be determined that the message sent by the SPI master device can pass through each SPI slave device, thereby realizing reliable message transmission.

[0136] An embodiment of the present application also provides an SPI device, which includes but is not limited to a communication device (such as an Ethernet controller, etc.), a data converter, a memory, a sensor, a microprocessor, a microcontroller, etc.; illustratively, the SPI device includes a processor and a memory, wherein the memory stores a computer program, and the processor runs the computer program to enable the SPI device to execute the communication method of the present application.

[0137] Among them, the processor can be an integrated circuit chip with signal processing capabilities. The processor can be a general-purpose processor, including a central processing unit (CPU), a graphics processing unit (GPU) and a network processor (NP), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. At least one of the general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc., which can implement or execute the disclosed methods, steps and logic block diagrams in the embodiments of the present application.

[0138] The memory may be, but is not limited to, a random access memory (RAM), a read only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable read-only memory (EEPROM), etc. The memory is used to store a computer program, and the processor may execute the computer program accordingly after receiving an execution instruction.

[0139] In addition, the present application also provides a computer storage medium for storing the computer program used in the above-mentioned SPI device, wherein when the computer program is executed on a processor, the communication method of the above-mentioned embodiment is implemented.

[0140] It can be understood that the options in the communication method of the above embodiment are also applicable to this embodiment, so they will not be described repeatedly here.

[0141] The computer storage medium may be a non-volatile storage medium or a volatile storage medium. For example, the computer storage medium may include, but is not limited to, a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and other media that can store program codes.

[0142] In several embodiments provided in the present application, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely schematic. For example, the flowcharts and structure diagrams in the accompanying drawings show the possible architecture, functions and operations of the devices, methods and computer program products according to multiple embodiments of the present application. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of a code, and the module, a program segment or a part of a code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in an alternative implementation, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the structure diagram and / or the flow diagram, and the combination of boxes in the structure diagram and / or the flow diagram, can be implemented with a dedicated hardware-based system that performs a specified function or action, or can be implemented with a combination of dedicated hardware and computer instructions.

[0143] In addition, the functional modules or units in the various embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

[0144] If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for a computer device (which can be a smart phone, a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in the various embodiments of the present application.

[0145] The above description is only a specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application.

Claims

1. A communication system, characterized in that: Including SPI master device, multiple SPI slave devices and expansion control chip; The serial clock pin of the SPI master device is respectively connected to the serial clock pin of each of the SPI slave devices, and the SPI master device is connected to the last SPI slave device through a master device output line; The SPI slave devices are connected in series via a slave device output line, and the first SPI slave device is connected to a master device input pin of the SPI master device via the slave device output line; A first end of the expansion control chip is connected to a chip select pin of the SPI master device, and a second end of the expansion control chip is respectively connected to a chip select pin of each of the SPI slave devices; The SPI master device is used to send a communication message to the last SPI slave device through the master device output line; the first SPI slave device is used to send a transmission message to the SPI master device through the slave device output line; the transmission message is obtained based on the communication message; The SPI master device is also used to send a chip select signal to the extended control chip, and the chip select signal is used to instruct the extended control chip to enable the chip select pin of the target SPI slave device so that the target SPI slave device communicates with the SPI master device.

2. A communication method, characterized in that: The method applied to the SPI slave device in the communication system of claim 1 comprises: If it is determined that the chip select pin of the current SPI slave device is enabled, after receiving a first message sent by the SPI master device or the next SPI slave device, the first message is processed to obtain a second message, and the second message is transmitted to the previous SPI slave device or the SPI master device; wherein the first message is the original message sent by the SPI master device.

3. The communication method according to claim 2, characterized in that: Also includes: Receive a third message sent by the next SPI slave device, and transmit the third message to the previous SPI slave device; wherein the third message includes tag information of a target SPI slave device; the target SPI slave device is an SPI slave device with a chip select pin enabled.

4. The communication method according to claim 2, characterized in that: Also includes: If it is determined that the chip select pin of the current SPI slave device is not enabled, after receiving the first message and the second message, each message is directly transmitted to the previous SPI slave device.

5. The communication method according to claim 2, characterized in that: Before receiving the first message sent by the SPI master device or the next SPI slave device, the method further includes: Receive a clock pulse sent by the SPI master device; wherein the clock pulse is used to indicate a sending rate when the current SPI slave device sends the first message and the second message.

6. The communication method according to claim 2, characterized in that: If the current SPI slave device is not the first SPI slave device, after receiving the first message sent by the SPI master device or the next SPI slave device, the method further includes: The first message is copied, and a first copy of the first message is forwarded to the previous SPI slave device to process a second copy of the first message.

7. A communication method, characterized in that: The SPI master device applied to the communication system of claim 1, the method comprising: Sending a first chip select signal to the extended control chip, wherein the first chip select signal is used to instruct the extended control chip to enable a chip select pin of at least one target SPI slave device; Sending a first message to the last SPI slave device; wherein, during the process of the first message being transmitted upward via the last SPI slave device, when the first message reaches the target SPI slave device, the target SPI slave device processes the first message to obtain a second message; The transmitted second message is received.

8. The communication method according to claim 7, characterized in that: Also includes: The message quantity of the second message received is equal to the quantity of the target SPI slave devices.

9. The communication method according to claim 7 or 8, characterized in that: After the receiving of the second transmitted message, the method further includes: A second chip select signal is sent to the extended control chip, where the second chip select signal is used to instruct the extended control chip to set the working state of the chip select pins of all SPI slave devices to a disabled state.

10. An SPI device, characterized in that: The method comprises a memory and a processor, wherein the memory stores a computer program, and the processor is configured to execute the computer program to implement the communication method according to any one of claims 2 to 9.

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