Gate drive circuit and display panel

Abstract

The invention provides a gate drive circuit and a display panel, the gate drive circuit comprises a plurality of cascaded gate drive sub-circuits, each gate drive sub-circuit comprises a first output module and a second output module, and the first output module and the second output module are both controlled by the same clock signal. And a second output end electrically connected with the second output module is electrically connected with the first power supply end through the pull-down maintenance module, so as to realize control on a gate control signal output by the same gate drive sub-circuit, and reduce the layout space occupied by the gate drive circuit.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a gate drive circuit and a display panel. Background Art

[0002] The more transistors included in the gate driving circuit, the larger the layout space occupied by the gate driving circuit. When the gate driving circuit is applied to a display panel, it is more disadvantageous for the display panel to realize a narrow frame design. Summary of the invention

[0003] The embodiments of the present invention provide a gate driving circuit and a display panel, which can reduce the layout space occupied by the gate driving circuit.

[0004] An embodiment of the present invention provides a gate driving circuit, comprising a plurality of cascaded gate driving sub-circuits, wherein the gate driving sub-circuits include a node control module, a level transmission module, a first output module, a second output module, and a pull-down maintenance module. The node control module is electrically connected to the first node and the second node of the gate driving sub-circuit of the same level, and the node control module is configured to control the signal transmitted to the first node and the second node according to the start signal. The level transmission module is electrically connected to the first node, and the level transmission module is configured to control the first clock signal to be transmitted to the level transmission output terminal of the gate driving sub-circuit of the same level according to the signal of the first node. The first output module is electrically connected to the level transmission output terminal and the first output terminal of the gate driving sub-circuit of the same level, and the first output module is configured to receive the second clock signal and the third clock signal to control the signal transmission between the level transmission output terminal and one of the first power supply terminal and the first output terminal. The second output module is electrically connected to the level transmission output terminal and the second output terminal of the gate driving sub-circuit of the same level, and the second output module is configured to control the signal transmission between the level transmission output terminal and the second output terminal according to the third clock signal. The pull-down maintaining module is electrically connected to the second node, and the pull-down maintaining module is configured to control signal transmission between the first power supply end and the second output end according to a signal of the second node.

[0005] An embodiment of the present invention provides a display panel, comprising any of the above-mentioned gate driving circuits.

[0006] The present invention provides a gate driving circuit and a display panel. The gate driving circuit includes a plurality of cascaded gate driving sub-circuits. The gate driving sub-circuit includes a first output module and a second output module. Both the first output module and the second output module are controlled by the same clock signal. A second output terminal electrically connected to the second output module is electrically connected to a first power supply terminal through a pull-down maintenance module to achieve control of a gate control signal output by the same gate driving sub-circuit, which is beneficial to reducing the layout space occupied by the gate driving circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0008] Figure 1A to Figure 1B is a schematic structural diagram of a gate driving circuit provided by an embodiment of the present invention;

[0009] Figure 2A to Figure 2C is a schematic structural diagram of a gate driving sub-circuit provided in an embodiment of the present invention;

[0010] Figure 3A to Figure 3B is a timing diagram of a gate control signal provided by an embodiment of the present invention;

[0011] Figure 4A to Figure 4B is a schematic structural diagram of a display panel provided by an embodiment of the present invention;

[0012] Figure 5 Schematic diagram of the charging duration of the sub-pixel Spi provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0013] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present invention, and are not used to limit the present invention. In the present invention, unless otherwise specified, the directional words used, such as "upper" and "lower", generally refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the drawings; while "inside" and "outside" refer to the outline of the device.

[0014] Specifically, Figure 1A to Figure 1B1 is a schematic diagram of the structure of a gate drive circuit provided by an embodiment of the present invention. The present application provides a gate drive circuit, comprising a plurality of cascaded gate drive sub-circuits GA, each gate drive sub-circuit GA comprising a stage transmission output terminal OutS, a first output terminal Out1 and a second output terminal Out2, the stage transmission output terminal OutS is configured to output a stage transmission signal ST, the first output terminal Out1 is configured to output a first gate control signal Scan1, and the second output terminal Out2 is configured to output a second gate control signal Scan2.

[0015] Among them, the level transmission signal ST output by the gate driving circuit includes the N-4th level transmission signal ST(N-4) output by the N-4th level gate driving sub-circuit GA(N-4) to the N+5th level transmission signal ST(N+5) output by the N+5th level gate driving sub-circuit GA(N+5). The first gate control signal Scan1 output by the gate driving circuit includes the N-4th level first gate control signal Scan1(N-4) output by the N-4th level gate driving sub-circuit GA(N-4) to the N+5th level first gate control signal Scan1(N+5) output by the N+5th level gate driving sub-circuit GA(N+5). The second gate control signal Scan2 output by the gate driving circuit includes the N-4th level second gate control signal Scan2(N-4) output by the N-4th level gate driving sub-circuit GA(N-4) to the N+5th level second gate control signal Scan2(N+5) output by the N+5th level gate driving sub-circuit GA(N+5). The gate control signal output by the gate driving circuit includes a first gate control signal Scan1 and a second gate control signal Scan2.

[0016] Figure 2A to Figure 2C Schematic diagram of the structure of the gate drive sub-circuit provided by the embodiment of the present invention. Figure 1A to Figure 1B and Figure 2A to Figure 2B The gate driving sub-circuit GA includes a node control module 100 , a stage transmission module 200 , a first output module 300 , a second output module 400 and a pull-down maintaining module 500 .

[0017] The node control module 100 is electrically connected to the first node QN and the second node KN of the gate driving sub-circuit GA at this level, and the node control module 100 is configured to control the signals transmitted to the first node QN and the second node KN according to the start signal.

[0018] The stage transmission module 200 is electrically connected to the first node QN, and the stage transmission module 200 is configured to control the first clock signal CKa to be transmitted to the stage transmission output terminal OutS of the current stage gate driving sub-circuit GA according to the signal of the first node QN.

[0019] The first output module 300 is electrically connected to the stage transmission output terminal OutS and the first output terminal Out1 of the gate driving sub-circuit GA of this stage. The first output module 300 is configured to receive the second clock signal CKb and the third clock signal CKc to control the signal transmission between the stage transmission output terminal OutS and one of the first power supply terminal VGL and the first output terminal Out1.

[0020] The second output module 400 is electrically connected to the stage transmission output terminal OutS and the second output terminal Out2 of the current stage gate driving sub-circuit GA, and is configured to control signal transmission between the stage transmission output terminal OutS and the second output terminal Out2 according to the third clock signal CKc.

[0021] The pull-down maintaining module 500 is electrically connected to the second node KN, and the pull-down maintaining module 500 is configured to control signal transmission between the first power terminal VGL and the second output terminal Out2 according to a signal of the second node KN.

[0022] By making the gate driving sub-circuit GA include a level transmission module 200, a first output module 300 and a second output module 400, and the first output module 300 and the second output module 400 are both controlled by the third clock signal CKc, the second output terminal Out2 realizes signal transmission control with the first power supply terminal VGL through the pull-down maintenance module 500, so that the same gate driving sub-circuit GA can simultaneously output the level transmission signal ST, the first gate control signal Scan1 and the second gate control signal Scan2, and realize the control of the level transmission signal ST, the first gate control signal Scan1 and the second gate control signal Scan2 output by the gate driving sub-circuit GA, the number of gate driving sub-circuits GA included in the gate driving circuit can be reduced, and then the layout space occupied by the gate driving circuit can be reduced.

[0023] Optionally, the first output module 300 is configured to control the signal transmission between the stage transmission output terminal OutS and the first output terminal Out1 according to the second clock signal CKb, and is configured to control the signal transmission between the first power supply terminal VGL and the first output terminal Out1 according to the third clock signal CKc, so that when the signal transmission path between the stage transmission output terminal OutS and the second output terminal Out2 is turned on, the signal transmission path between the stage transmission output terminal OutS and the first output terminal Out1 is disconnected, so that the effective level of the first gate control signal Scan1 output by the same gate drive sub-circuit GA does not overlap with the effective level of the second gate control signal Scan2.

[0024] It should be noted that the effective level of the first gate control signal Scan1 output by the same gate drive sub-circuit GA does not overlap with the effective level of the second gate control signal Scan2, including: the falling edge (or rising edge) of the first gate control signal Scan1 overlaps with the rising edge (or falling edge) of the first gate control signal Scan1. When the transistor controlled by the first gate control signal Scan1 is a P-type transistor, the effective level of the first gate control signal Scan1 is a low level; when the transistor controlled by the first gate control signal Scan1 is an N-type transistor, the effective level of the first gate control signal Scan1 is a high level. Similarly, the effective levels of the second gate control signal Scan2 and the stage transfer signal ST can also be determined according to the type of transistors controlled by the second gate control signal Scan2 and the stage transfer signal ST.

[0025] Optionally, the first output module 300 can also be configured to control the signal transmission between the first power supply terminal VGL and the first output terminal Out1 according to the fourth clock signal, so as to make the effective level of the first gate control signal Scan1 output by the same gate drive sub-circuit GA overlap with the effective level of the second gate control signal Scan2 by adjusting the timing of the fourth clock signal.

[0026] Please continue reading Figure 2A to Figure 2B The node control module 100 may include a pull-up control unit 101, which is electrically connected to the first node QN and the second power supply terminal VGH. The pull-up control unit 101 is configured to control signal transmission between the second power supply terminal VGH and the first node QN according to a start signal.

[0027] Optionally, the pull-up control unit 101 includes a first switch transistor Ts1 including a control terminal configured to receive a start signal, a first source-drain terminal electrically connected to the second power terminal VGH, and a second source-drain terminal electrically connected to the first node QN.

[0028] Among them, in multiple cascaded gate driving sub-circuits GA, the start signal received by the first Z-level gate driving sub-circuit GA can correspond to the starting signal, and the start signal received by the N-th level gate driving sub-circuit GA(N) cascaded after the Z-th level gate driving sub-circuit GA(Z) can be the signal generated by the NX-th level gate driving sub-circuit GA(NX), Z≥1, N>Z, X>1.

[0029] Optionally, the start signal received by the Nth-stage gate driving sub-circuit GA(N) may be the NXth-stage stage transfer signal ST(NX) generated by the NXth-stage gate driving sub-circuit GA(NX), so that the stage transfer control function of the gate driving circuit is no longer controlled by the gate control signal.

[0030] For example, when Z=2 and X=2, in the multiple cascaded gate drive sub-circuits GA, the start signal received by the first-stage gate drive sub-circuit GA(1) is the first start signal, the start signal received by the second-stage gate drive sub-circuit GA(2) is the second start signal, and the start signal received by the third-stage gate drive sub-circuit GA(3) may be the stage transmission signal ST(3) generated by the first-stage gate drive circuit, and so on, to obtain the start signals received by the multiple cascaded gate drive sub-circuits GA. The start signal may be generated by a device such as a timing controller.

[0031] Please continue reading Figure 2A to Figure 2B The node control module 100 also includes an inverting unit 102, which is electrically connected to the first node QN, the second node KN, the first power supply terminal VGL and the second power supply terminal VGH. The inverting unit 102 is configured to control one of the first power supply terminal VGL and the second power supply terminal VGH to be electrically connected to the second node KN according to the signal of the first node QN, so that when the stage transmission module 200 controls the signal transmission path between the first clock signal CKa and the stage transmission output terminal OutS to be turned on according to the signal of the first node QN, the second node KN is controlled to be electrically connected to the first power supply terminal VGL through the inverting unit 102, thereby controlling the working state of the pull-down maintenance module 500.

[0032] Optionally, the inverting unit 102 includes a second switch transistor Ts2, a third switch transistor Ts3, a fourth switch transistor Ts4 and a fifth switch transistor Ts5.

[0033] The second switch transistor Ts2 includes a control terminal electrically connected to the second power supply terminal VGH, a first source-drain terminal electrically connected to the second power supply terminal VGH, and a second source-drain terminal electrically connected to the control terminal of the third switch transistor Ts3. The third switch transistor Ts3 includes a first source-drain terminal electrically connected to the second power supply terminal VGH, and a second source-drain terminal electrically connected to the second node KN. The fourth switch transistor Ts4 includes a control terminal electrically connected to the first node QN, a first source-drain terminal electrically connected to the first power supply terminal VGL, and a second source-drain terminal electrically connected to the control terminal of the third switch transistor Ts3. The fifth switch transistor Ts5 includes a control terminal electrically connected to the first node QN, a first source-drain terminal electrically connected to the first power supply terminal VGL, and a second source-drain terminal electrically connected to the second node KN.

[0034] Optionally, in order to prevent the first clock signal CKa from being transmitted to the stage transmission output terminal OutS at a desired time, the node control module 100 includes a pull-down control unit 103, such as Figure 2A to Figure 2BThe pull-down control unit 103 is electrically connected to the first node QN and the first power terminal VGL, and the pull-down control unit 103 is configured to control signal transmission between the first power terminal VGL and the first node QN according to a pull-down control signal.

[0035] Optionally, the pull-down control unit 103 includes a sixth switch transistor Ts6, which includes a control terminal configured to receive a pull-down control signal, a first source-drain terminal electrically connected to the first power terminal VGL, and a second source-drain terminal electrically connected to the first node QN.

[0036] Among the multiple cascaded gate drive sub-circuits GA, the pull-down control signal corresponding to the M-th gate drive sub-circuit GA(M) is the level transfer signal ST(M+Y) generated by the M+Y-th level gate drive sub-circuit GA(M+Y), M≥1, Y>1. For example, taking Y=2 as an example, the pull-down control signal corresponding to the M-th level gate drive sub-circuit GA(M) is the M+2-th level transfer signal ST(M+2) generated by the M+2-th level gate drive sub-circuit GA(M+2).

[0037] To prevent the second gate control signal Scan2 output by the gate driving sub-circuit GA from having no valid level, the starting time of the valid level of the pull-down control signal applied by the gate driving sub-circuit GA can be made later than the ending time of the valid level of the first clock signal CKa applied by the gate driving sub-circuit GA.

[0038] Optionally, the voltage supplied by the first power supply terminal VGL may be lower than the voltage supplied by the second power supply terminal VGH. Accordingly, the pull-up control unit 101 may control the potential of the first node QN to be pulled up according to the start signal, and the pull-down control unit 103 may control the potential of the first node QN to be pulled down according to the pull-down control signal.

[0039] Please continue reading Figure 2A to Figure 2B In order to realize the output control of the effective level of the stage transmission signal ST, the stage transmission module 200 may include a stage transmission output transistor Tst and a first capacitor Cbt. The stage transmission output transistor Tst includes a control terminal electrically connected to the first node QN, a first source-drain terminal configured to receive the first clock signal CKa, and a second source-drain terminal electrically connected to the stage transmission output terminal OutS. The first capacitor Cbt is connected in series between the control terminal of the stage transmission output transistor Tst and the stage transmission output terminal OutS.

[0040] Please continue reading Figure 2A to Figure 2BIn order to realize the output control of the effective level of the first gate control signal Scan1, the first output module 300 includes a first output transistor To1 and a second output transistor To2. The first output transistor To1 includes a control terminal configured to receive the second clock signal CKb, a first source-drain terminal electrically connected to the stage transmission output terminal OutS, and a second source-drain terminal electrically connected to the first output terminal Out1. The second output transistor To2 includes a control terminal configured to receive the third clock signal CKc or the fourth clock signal, a first source-drain terminal electrically connected to the first power supply terminal VGL, and a second source-drain terminal electrically connected to the first output terminal Out1.

[0041] Please continue reading Figure 2A to Figure 2B In order to realize the output control of the effective level of the second gate control signal Scan2, the second output module 400 includes a third output transistor To3, and the third output transistor To3 includes a control end configured to receive the third clock signal CKc, a first source-drain end electrically connected to the stage transmission output end OutS, and a second source-drain end electrically connected to the second output end Out2.

[0042] Please continue reading Figure 2A to Figure 2B In order to realize the on-off control of the signal transmission path between the first power supply terminal VGL and the second output terminal Out2, the pull-down maintenance module 500 includes a first transistor T1, and the first transistor T1 includes a control terminal electrically connected to the second node KN, a first source-drain terminal electrically connected to the first power supply terminal VGL, and a second source-drain terminal electrically connected to the second output terminal Out2.

[0043] Since the level states of the third clock signal CKc and the fourth clock signal both have switching between the valid level and the invalid level, the on-off control of the signal transmission path between the first power supply terminal VGL and the first output terminal Out1 by the second output transistor To2 is periodic. Therefore, in the stage where the first gate control signal Scan1 needs to continuously output the invalid level, there will be a partial period of time when the signal transmission path between the first power supply terminal VGL and the first output terminal Out1 is disconnected, so that the ability of the potential of the second output terminal Out2 to maintain stability during the period is reduced. To this end, the pull-down maintenance module 500 can also be electrically connected to the first output terminal Out1, and the pull-down maintenance module 500 is configured to control the signal transmission between the first power supply terminal VGL and the first output terminal Out1 according to the signal of the second node KN, so as to realize the on-off control of the signal transmission channel between the first power supply terminal VGL and the first output terminal Out1 through the pull-down maintenance module 500, so as to maintain a stable invalid level state in the stage where the first gate control signal Scan1 needs to continuously output the invalid level.

[0044] Accordingly, the pull-down sustaining module 500 may include a second transistor T2 including a control terminal electrically connected to the second node KN, a first source-drain terminal electrically connected to the first power terminal VGL, and a second source-drain terminal electrically connected to the first output terminal Out1.

[0045] Similarly, the pull-down maintaining module 500 can also be used to implement on-off control of the signal transmission channel between the first power supply terminal VGL and the stage transmission output terminal OutS, so that the stage where the stage transmission signal ST needs to continuously output the invalid level has a stable invalid level state.

[0046] Accordingly, the pull-down maintaining module 500 is electrically connected to the stage transmission output terminal OutS, and the pull-down maintaining module 500 is configured to control the electrical connection between the first power supply terminal VGL and the stage transmission output terminal OutS according to the signal of the second node KN.

[0047] Optionally, the pull-down sustaining module 500 includes a third transistor T3, which includes a control terminal electrically connected to the second node KN, a first source-drain terminal electrically connected to the first power terminal VGL, and a second source-drain terminal electrically connected to the stage transmission output terminal OutS.

[0048] In order to reduce the probability of erroneous output of the gate driving sub-circuit GA due to changes in the potential of the first node QN during the period when the stage transmission signal ST continues to output an invalid level, the pull-down maintenance module 500 can also be electrically connected to the first node QN. The pull-down maintenance module 500 is configured to control the electrical connection between the first power supply terminal VGL and the first node QN according to the signal of the second node KN, so that the pull-down maintenance module 500 can realize the on-off control of the signal transmission channel between the first power supply terminal VGL and the stage transmission output terminal OutS, so as to maintain the potential of the first node QN stable during the period when the stage transmission signal ST continues to output an invalid level.

[0049] Optionally, the pull-down sustaining module 500 includes a fourth transistor T4, which includes a control terminal electrically connected to the second node KN, a first source-drain terminal electrically connected to the first power terminal VGL, and a second source-drain terminal electrically connected to the first node QN.

[0050] Optionally, the gate drive sub-circuit GA may also include a reset module 600, which is electrically connected to the first power supply terminal VGL and the first node QN. The reset module 600 is configured to control the signal transmission between the first power supply terminal VGL and the first node QN according to a reset control signal, so that when the gate drive circuit is started, the potential of the first node QN is reset by controlling the reset module 600.

[0051] Accordingly, the reset module 600 includes a first reset transistor TrQ including a control terminal configured to receive a reset control signal, a first source-drain terminal electrically connected to the first power terminal VGL, and a second source-drain terminal electrically connected to the first node QN.

[0052] Optionally, the reset module 600 is electrically connected to the stage transmission output terminal OutS, and the reset module 600 is configured to control the signal transmission between the first power supply terminal VGL and the stage transmission output terminal OutS according to the reset control signal, so that when the gate driving circuit is started, the potential of the stage transmission output terminal OutS is reset by controlling the reset module 600.

[0053] Accordingly, the reset module 600 includes a second reset transistor TrG including a control terminal configured to receive a reset control signal, a first source-drain terminal electrically connected to the first power terminal VGL, and a second source-drain terminal electrically connected to the stage transmission output terminal OutS.

[0054] Please continue reading Figure 2A to Figure 2C , if adopted Figure 2C The gate drive subcircuit GA shown in the figure is designed. Then, one gate drive subcircuit GA outputs one gate control signal (such as the Nth gate drive subcircuit GA(N) outputs the Nth gate control signal Scan(N)). To output two gate control signals, two gate drive subcircuits GA need to be set. The gate drive subcircuit GA that outputs two gate control signals needs to be set with 22 transistors. Figure 2A to Figure 2B The gate drive sub-circuit GA shown in the figure is designed because one gate drive sub-circuit GA can simultaneously output the stage transfer signal ST and two gate control signals (i.e., the first gate control signal Scan1 and the second gate control signal Scan2). Therefore, the gate drive sub-circuit GA corresponding to the output of the two gate control signals only needs to be provided with 16 transistors. Figure 2C The design shown in the figure uses the gate drive subcircuit GA Figure 2A to Figure 2B The design shown can correspondingly reduce the number of transistors included in the gate driving circuit, thereby reducing the layout space occupied by the gate driving circuit.

[0055] In addition, the gate driving sub-circuit GA can still output the level transmission signal ST while outputting the gate control signal. Moreover, the level transmission control is realized between the cascaded gate driving sub-circuits GA through the level transmission signal ST. Therefore, the working state of the first output terminal Out1 and the second output terminal Out2 of the gate driving sub-circuit GA will not affect the level transmission control between the multi-stage gate driving sub-circuits GA. For example, when the gate driving circuit is applied to a display panel, and a short circuit occurs between the scanning line SL electrically connected to the first output terminal Out1 or the second output terminal Out2 of some gate driving sub-circuits GA and a signal line such as a common wiring in the display panel, since the cascade control between the multi-stage gate driving sub-circuits GA is realized through level transmission, the cascade control between the multi-stage gate driving sub-circuits GA will not be affected by the short circuit factor, so that the gate driving circuit can still provide the required gate control signal to the display panel, so that the partial area of ​​the display panel without the short circuit problem can still receive the corresponding gate control signal, thereby reducing the impact caused by the short circuit problem.

[0056] In order to further reduce the layout space occupied by the gate driving circuit, the clock signals provided by the multiple clock lines can be shared to provide the required clock signals to the multi-stage gate driving sub-circuit GA. Accordingly, the gate driving circuit includes multiple clock lines, the multiple clock lines are electrically connected to the multi-stage gate driving sub-circuit GA, and the multiple clock lines are configured to transmit the corresponding first clock signal CKa, the second clock signal CKb and the third clock signal CKc to the multi-stage gate driving sub-circuit GA.

[0057] Optionally, the gate driving circuit may include L clock lines to provide the required clock signals for the multi-stage gate driving sub-circuit GA, where L≥4.

[0058] Please continue to read Figure 1A to Figure 1B and Figure 2A to Figure 2B Taking L=4 as an example, the design of the clock signal provided by the multi-stage gate driving sub-circuit GA sharing multiple clock lines is described. The L clock lines include a first clock line CKL1, a second clock line CKL2, a third clock line CKL3 and a fourth clock line CKL4.

[0059] The first clock line CKL1 is configured to transmit the corresponding first clock signal CKa to the 4K+1-level gate driver sub-circuit GA (4K+1), is configured to transmit the corresponding second clock signal CKb to the 4K+2-level gate driver sub-circuit GA (4K+2), and is configured to transmit the corresponding third clock signal CKc to the 4K+4-level gate driver sub-circuit GA (4K+4).

[0060] The second clock line CKL2 is configured to transmit the corresponding third clock signal CKc to the 4K+1-th gate driver sub-circuit GA(4K+1), and is configured to transmit the corresponding first clock signal CKa to the 4K+2-th gate driver sub-circuit GA(4K+2), and is configured to transmit the corresponding second clock signal CKb to the 4K+3-th gate driver sub-circuit GA(4K+3);

[0061] The third clock line CKL3 is configured to transmit the corresponding third clock signal CKc to the 4K+2-level gate driver sub-circuit GA (4K+2), and is configured to transmit the corresponding first clock signal CKa to the 4K+3-level gate driver sub-circuit GA (4K+3), and is configured to transmit the corresponding second clock signal CKb to the 4K+4-level gate driver sub-circuit GA (4K+4).

[0062] The fourth clock line CKL4 is configured to transmit the corresponding second clock signal CKb to the 4K+1-th level gate driver sub-circuit GA(4K+1), and is configured to transmit the corresponding third clock signal CKc to the 4K+3-th level gate driver sub-circuit GA(4K+3), and is configured to transmit the corresponding first clock signal CKa to the 4K+4-th level gate driver sub-circuit GA(4K+4). Wherein, K≥0.

[0063] In addition, the multi-stage gate driving sub-circuits GA may also be divided into different groups, and different groups of gate driving sub-circuits GA are matched with different clock lines to generate gate control signals.

[0064] Please continue to read Figure 1B and Figure 2A to Figure 2B , multiple clock lines are divided into a first group of clock lines and a second group of clock lines, and the gate drive circuit includes a first cascade group GM1 and a second cascade group GM2, and the first cascade group GM1 and the second cascade group GM2 respectively include multiple cascaded gate drive sub-circuits GA. Among them, the first group of clock lines is configured to transmit the corresponding first clock signal CKa, the second clock signal CKb and the third clock signal CKc to the multiple gate drive sub-circuits GA in the first cascade group GM1; the second group of clock lines is configured to transmit the corresponding first clock signal CKa, the second clock signal CKb and the third clock signal CKc to the multiple gate drive sub-circuits GA in the second cascade group GM2. In this way, the gate drive sub-circuits GA of the first cascade group GM1 and the second cascade group GM2 generate gate control signals according to independent clock signals.

[0065] Optionally, the first cascade group GM1 includes odd-numbered gate driver sub-circuits GA, and the second cascade group GM2 includes even-numbered gate driver sub-circuits GA, so as to control the phase difference between the gate control signals output by the odd-numbered gate driver sub-circuit GA and the even-numbered gate driver sub-circuit GA according to the clock signals transmitted by the first group of clock lines and the second group of clock lines.

[0066] Optionally, L1 clock lines among the L clock lines are used as the first group of clock lines, and L2 clock lines among the L clock lines are used as the second group of clock lines, so as to reduce the layout space occupied by the gate drive circuit while meeting the requirements of the clock signals required by the first cascade group GM1 and the second cascade group GM2. Wherein, L>L1≥4, L>L2≥4.

[0067] Please continue to read Figure 1B Taking L1=4 as an example, the design relationship between the first group of clock lines and the first cascade group GM1 is described. The first group of clock lines includes a first clock line CKL1, a second clock line CKL2, a third clock line CKL3 and a fourth clock line CKL4.

[0068] The first clock line CKL1 is configured to transmit the corresponding first clock signal CKa to the 4K+1-th gate driver sub-circuit GA(4K+1) in the first cascade group GM1, and is configured to transmit the corresponding second clock signal CKb to the 4K+2-th gate driver sub-circuit GA(4K+2), and is configured to transmit the corresponding third clock signal CKc to the 4K+4-th gate driver sub-circuit GA(4K+4); the second clock line CKL2 is configured to transmit the corresponding third clock signal CKc to the 4K+1-th gate driver sub-circuit GA(4K+1) in the first cascade group GM1, and is configured to transmit the corresponding first clock signal CKa to the 4K+2-th gate driver sub-circuit GA(4K+2), and is configured to transmit the corresponding second clock signal CKb to the 4K+3-th gate driver sub-circuit GA(4K+3); the third clock line CKL2 is configured to transmit the corresponding third clock signal CKc to the 4K+1-th gate driver sub-circuit GA(4K+1) in the first cascade group GM1, and is configured to transmit the corresponding first clock signal CKa to the 4K+2-th gate driver sub-circuit GA(4K+2), and is configured to transmit the corresponding second clock signal CKb to the 4K+3-th gate driver sub-circuit GA(4K+3); The clock line CKL3 is configured to transmit the corresponding third clock signal CKc to the 4K+2-level gate driver sub-circuit GA(4K+2) in the first cascade group GM1, and is configured to transmit the corresponding first clock signal CKa to the 4K+3-level gate driver sub-circuit GA(4K+3), and is configured to transmit the corresponding second clock signal CKb to the 4K+4-level gate driver sub-circuit GA(4K+4); the fourth clock line CKL4 is configured to transmit the corresponding second clock signal CKb to the 4K+1-level gate driver sub-circuit GA(4K+1) in the first cascade group GM1, and is configured to transmit the corresponding third clock signal CKc to the 4K+3-level gate driver sub-circuit GA(4K+3), and is configured to transmit the corresponding first clock signal CKa to the 4K+4-level gate driver sub-circuit GA(4K+4); wherein, K≥0.

[0069] Optionally, the first group of clock lines and the second group of clock lines may include the same number of clock lines, such as L2=4.

[0070] Optionally, the design relationship between the second cascade group GM2 and the second group of clock lines can be obtained by referring to the setting of the first cascade group GM1 and the first group of clock lines. That is, the second group of clock lines can include the fifth clock line CKL5, the sixth clock line CKL6, the seventh clock line CKL7 and the eighth clock line CKL8. Among them, the fifth clock line CKL5 is configured to transmit the corresponding first clock signal CKa to the 4K+1-level gate driver sub-circuit GA(4K+1) in the second cascade group GM2, and is configured to transmit the corresponding second clock signal CKb to the 4K+2-level gate driver sub-circuit GA(4K+2), and is configured to transmit the corresponding third clock signal CKc to the 4K+4-level gate driver sub-circuit GA(4K+4); the sixth clock line CKL6 is configured to transmit the corresponding third clock signal CKc to the 4K+1-level gate driver sub-circuit GA(4K+1) in the second cascade group GM2, and is configured to transmit the corresponding first clock signal CKa to the 4K+2-level gate driver sub-circuit GA(4K+2), and is configured to transmit the corresponding second clock signal CK to the 4K+3-level gate driver sub-circuit GA(4K+3). b; the seventh clock line CKL7 is configured to transmit the corresponding third clock signal CKc to the 4K+2-level gate driver sub-circuit GA(4K+2) in the second cascade group GM2, and is configured to transmit the corresponding first clock signal CKa to the 4K+3-level gate driver sub-circuit GA(4K+3), and is configured to transmit the corresponding second clock signal CKb to the 4K+4-level gate driver sub-circuit GA(4K+4); the eighth clock line CKL8 is configured to transmit the corresponding second clock signal CKb to the 4K+1-level gate driver sub-circuit GA(4K+1) in the second cascade group GM2, and is configured to transmit the corresponding third clock signal CKc to the 4K+3-level gate driver sub-circuit GA(4K+3), and is configured to transmit the corresponding first clock signal CKa to the 4K+4-level gate driver sub-circuit GA(4K+4).

[0071] Optionally, the phase difference design between the clock signals transmitted by the first group of clock lines can be used by the clock signals transmitted by the second group of clock lines to reduce the control difficulty and maintain the consistency of the phase difference of multiple gate control signals output by the gate driving circuit.

[0072] For example, the phase difference between the clock signals transmitted by two adjacent clock lines in the first group of clock lines is equal to the phase difference between the clock signals transmitted by two adjacent clock lines in the second group of clock lines, so that the phase difference between the multiple gate control signals output by the first cascade group GM1 is consistent with the phase difference between the multiple gate control signals output by the second cascade group GM2.

[0073] Correspondingly, when the first group of clock lines includes the first clock line CKL1 to the fourth clock line CKL4, and the second group of clock lines includes the fifth clock line CKL4 to the eighth clock line, the phase difference between the first clock signal CK1 transmitted by the first clock line CKL1 and the second clock signal CK2 transmitted by the second clock line CKL2 is equal to the phase difference between the second clock signal CK2 and the third clock signal CK3 transmitted by the third clock line CKL3, and is also equal to the phase difference between the third clock signal CK3 and the fourth clock signal CK4 transmitted by the fourth clock line CKL4, and is also equal to the phase difference between the fifth clock signal CK5 transmitted by the fifth clock line and the sixth clock signal CK6 transmitted by the sixth clock line, and is also equal to the phase difference between the sixth clock signal CK6 and the seventh clock signal CK7 transmitted by the seventh clock line, and is also equal to the phase difference between the seventh clock signal CK7 and the eighth clock signal CK8 transmitted by the eighth clock line.

[0074] Optionally, the timing of the clock signals transmitted by the first group of clock lines and the second group of clock lines can be controlled so that the multiple gate driving sub-circuits GA in the first cascade group GM1 and the multiple gate driving sub-circuits GA in the second cascade group GM2 can alternately output gate control signals. For example, the clock signals transmitted by the first clock line CKL1, the fifth clock line CKL5, the second clock line CKL2, the sixth clock line CKL6, the third clock line CKL3, the seventh clock line CKL7, the fourth clock line CKL4, and the eighth clock line CKL8 can be controlled to have valid levels in sequence, thereby making the multiple gate driving sub-circuits GA in the first cascade group GM1 and the multiple gate driving sub-circuits GA in the second cascade group GM2 alternately output gate control signals.

[0075] Optionally, in order to make the intervals of the multiple gate control signals jumping from the effective level to the ineffective level tend to be consistent when the multiple gate drive sub-circuits GA in the first cascade group GM1 and the multiple gate drive sub-circuits GA in the second cascade group GM2 alternately output gate control signals, the first clock signal CK1 transmitted by the first clock line CKL1 and the fifth clock signal CK5 transmitted by the fifth clock line CKL5 can have a first phase difference, and the fifth clock signal CK5 transmitted by the fifth clock line CKL5 and the second clock signal CK2 transmitted by the second clock line CKL2 can have a second phase difference. The first phase difference is smaller than the second phase difference.

[0076] It should be noted that, in order to avoid the second gate control signal Scan2 output by the gate driving sub-circuit GA having no valid level, when only four clock lines are used to transmit the corresponding clock signals to the cascaded multiple gate driving sub-circuits GA in the gate driving circuit, X and Y can be set to 2. Figure 1A In the design shown, the start signal received by the Nth-stage gate driver subcircuit GA(N) is the stage transmission signal ST(N-2) output by the N-2th-stage gate driver subcircuit GA(N-2), and the pull-down control signal received by the Nth-stage gate driver subcircuit GA(N) is the stage transmission signal ST(N+2) output by the N+2th-stage gate driver subcircuit GA(N+2). Figure 1B In the design shown, the start signal received by the Nth gate driver subcircuit GA(N) in the first cascade group GM1 is the level transmission signal ST(N-2) output by the N-2th gate driver subcircuit GA(N-2) in the first cascade group GM1, and the pull-down control signal received by the Nth gate driver subcircuit GA(N) in the first cascade group GM1 is the level transmission signal ST(N+2) output by the N+2th gate driver subcircuit GA(N+2) in the first cascade group GM1. Here, N can be equal to the number of cascaded gate driver subcircuits GA at most. The gate driver subcircuit GA in the first cascade group GM1 and the gate driver subcircuit GA in the second cascade group GM2 are not cascaded.

[0077] If the first cascade group GM1 includes an odd number of gate driving sub-circuits GA, the second cascade group GM2 includes an even number of gate driving sub-circuits GA, and the first cascade group GM1 and the second cascade group GM2 output gate control signals alternately, then, in order to avoid the second gate control signal Scan2 output by the gate driving sub-circuit GA having no valid level, when only eight clock lines are used to transmit the corresponding clock signals for the cascaded multiple gate driving sub-circuits GA in the gate driving circuit, X and Y can be set to 4. That is, corresponding to Figure 1B In the design, the start signal received by the Nth gate sub-drive circuit GA(N) in the gate drive circuit (i.e., including both the first cascade group GM1 and the second cascade group GM2) is the level transmission signal ST(N-4) output by the N-4th gate drive sub-circuit GA(N-4) in the gate drive circuit, and the pull-down control signal received by the Nth gate drive sub-circuit GA(N) in the gate drive circuit is the level transmission signal ST(N+4) output by the N+4th gate drive sub-circuit GA(N+4) in the gate drive circuit. Wherein, N here can be equal to the maximum number of all gate drive sub-circuits GA included in the gate drive circuit.

[0078] Figure 3A to Figure 3BIt is a timing diagram of the gate control signal provided by an embodiment of the present invention. Taking the transistors included in the gate driving sub-circuit GA as N-type transistors, the third clock line CKL3 is configured as the N-th gate driving sub-circuit GA(N) transmitting the first clock signal CKa, the second clock line CKL2 is configured as the N-th gate driving sub-circuit GA(N) transmitting the second clock signal CKb, the fourth clock line CKL4 is configured as the N-th gate driving sub-circuit GA(N) transmitting the third clock signal CKc, the start signal corresponding to the N-th gate driving sub-circuit GA(N) is the N-2-th level transmission signal ST(N-2)(N-2) output by the N-2-th level gate driving sub-circuit GA(N-2), and the pull-down control signal corresponding to the N-th level gate driving sub-circuit GA(N) is the N+2-th level transmission signal ST(N+2)(N+2) output by the N+2-th level gate driving sub-circuit GA(N+2) as an example, the working principle of multiple cascaded gate driving sub-circuits GA in the gate driving circuit is described.

[0079] Please continue reading Figure 1A , Figure 2A to Figure 2B and Figure 3A In the first stage t1, the N-2 stage transmission signal ST(N-2) is high, the N+2 stage transmission signal ST(N+2) is low, the first clock signal CK1 transmitted by the first clock line CKL1 and the fourth clock signal CK4 transmitted by the fourth clock line CKL4 are high, the second clock signal CK2 transmitted by the second clock line CKL2 and the third clock signal CK3 transmitted by the third clock line CKL3 are low. The first switch transistor Ts1, the fourth switch transistor Ts4, the fifth switch transistor Ts5, the stage transmission transistor Tst, the second output transistor To2 and the third output transistor To3 in the N-stage gate driving sub-circuit GA(N) are turned on; the sixth switch transistor Ts6, the first transistor T1 to the fourth transistor T4, the first output transistor To1, the first reset transistor TrQ and the second reset transistor TrG are turned off. The Nth stage transmission signal ST(N), the Nth stage first gate control signal Scan1(N) and the Nth stage second gate control signal Scan2(N) output by the Nth stage gate driving sub-circuit GA(N) are at low level.

[0080] In the second stage t2, the N-2 stage transmission signal ST(N-2) is high, the N+2 stage transmission signal ST(N+2) is low, the first clock signal CK1 is high, and the second clock signal CK2 to the fourth clock signal CK4 are low. The first switch transistor Ts1, the fourth switch transistor Ts4, the fifth switch transistor Ts5, and the stage transmission output transistor Tst in the N-stage gate driving sub-circuit GA(N) are turned on; the sixth switch transistor Ts6, the first transistor T1 to the fourth transistor T4, the first output transistor To1 to the third output transistor To3, the first reset transistor TrQ, and the second reset transistor TrG are turned off. The N-stage transmission signal ST(N), the N-stage first gate control signal Scan1(N), and the N-stage second gate control signal Scan2(N) output by the N-stage gate driving sub-circuit GA(N) are low.

[0081] In the third stage t3, the N-2 stage transmission signal ST(N-2) and the N+2 stage transmission signal ST(N+2) are at a low level, the first clock signal CK1 and the fourth clock signal CK4 are at a low level, and the second clock signal CK2 and the third clock signal CK3 are at a high level. The fourth switch transistor Ts4, the fifth switch transistor Ts5, the stage transmission output transistor Tst, and the first output transistor To1 in the N-stage gate driving sub-circuit GA(N) are turned on; the first switch transistor Ts1, the sixth switch transistor Ts6, the first transistor T1 to the fourth transistor T4, the second output transistor To2, the third output transistor To3, the first reset transistor TrQ, and the second reset transistor TrG are turned off. The N-stage transmission signal ST(N) and the N-stage first gate control signal Scan1(N) are at a high level, and the N-stage second gate control signal Scan2(N) is at a low level.

[0082] In the fourth stage t4, the N-2 stage transmission signal ST(N-2) and the N+2 stage transmission signal ST(N+2) are at a low level, the first clock signal CK1 and the second clock signal CK2 are at a low level, and the third clock signal CK3 and the fourth clock signal CK4 are at a high level. The fourth switch transistor Ts4, the fifth switch transistor Ts5, the stage transmission output transistor Tst, the second output transistor To2 and the third output transistor To3 in the N-stage gate driving sub-circuit GA(N) are turned on; the first switch transistor Ts1, the sixth switch transistor Ts6, the first transistor T1 to the fourth transistor T4, the first output transistor To1, the first reset transistor TrQ and the second reset transistor TrG are turned off. The N-stage transmission signal ST(N) and the N-stage second gate control signal Scan2(N) are at a high level, and the N-stage first gate control signal Scan1(N) is at a low level.

[0083] In the fifth stage t5, the N-2 stage transmission signal ST(N-2) and the N+2 stage transmission signal ST(N+2) are at a low level, the first clock signal CK1 to the third clock signal CK3 are at a low level, and the fourth clock signal CK4 is at a high level. The fourth switch transistor Ts4, the fifth switch transistor Ts5, the stage transmission output transistor Tst, the second output transistor To2 and the third output transistor To3 in the N-stage gate driving sub-circuit GA(N) are turned on; the first switch transistor Ts1, the sixth switch transistor Ts6, the first transistor T1 to the fourth transistor T4, the first output transistor To1, the first reset transistor TrQ and the second reset transistor TrG are turned off. The N-stage transmission signal ST(N), the N-stage first gate control signal Scan1(N) and the N-stage second gate control signal Scan2(N) are at a low level.

[0084] In the sixth stage t6, the N-2 stage transmission signal ST(N-2) is at a low level, the N+2 stage transmission signal ST(N+2) is at a high level, the first clock signal CK1 and the fourth clock signal CK4 are at a high level, and the second clock signal CK2 and the third clock signal CK3 are at a low level. The first switch transistor Ts1, the second switch transistor Ts2, the third switch transistor Ts3, the sixth switch transistor Ts6, the first transistor T1 to the fourth transistor T4, the second output transistor To2 and the third output transistor To3 in the N-stage gate driving sub-circuit GA(N) are turned on; the fourth switch transistor Ts4, the fifth switch transistor Ts5, the stage transmission output transistor Tst, the first output transistor To1, the first reset transistor TrQ and the second reset transistor TrG are turned off. The N-stage transmission signal ST(N), the N-stage first gate control signal Scan1(N) and the N-stage second gate control signal Scan2(N) are at a low level.

[0085] Similarly, it can be obtained that the gate drive circuit adopts Figure 1B The design working principle shown in the figure and the corresponding timing are as follows Figure 3B As shown, no further description is given here.

[0086] It can be understood that by adjusting the phases of the clock signals transmitted by the multiple clock lines, the pulse widths of the effective levels of the first gate control signal Scan1 and the second gate control signal Scan2 output by the same gate drive sub-circuit GA can be adjusted. Therefore, by adjusting the duty cycle, phase and other parameters of the clock signal, the first gate control signal Scan1 and the second gate control signal Scan2 can have the same pulse width of effective level.

[0087] The inventors adopt Figure 2BThe gate driving circuit of the gate driving subcircuit GA shown in the figure is experimentally verified. When the gate driving circuit is applied to the display panel, the rising edge of the first gate control signal Scan1 output by the gate driving subcircuit GA corresponds to the rising edge of the first clock signal CKa applied thereto, the falling edge of the first gate control signal Scan1 output by the gate driving subcircuit GA corresponds to the rising edge of the third clock signal CKc applied thereto, the rising edge of the second gate control signal Scan2 output by the gate driving subcircuit GA corresponds to the rising edge of the third clock signal CKc applied thereto, and the falling edge of the second gate control signal Scan2 output by the gate driving subcircuit GA corresponds to the falling edge of the first clock signal CKa applied thereto; and in order to meet the requirements of charging the sub-pixel Spi or pixel by the data signal and realizing the charging uniformity, and reducing the problem of display difference, the display panel requires that the falling edge interval time difference between the two adjacent gate control signals output by the gate driving circuit is 1H. To this end, it is necessary to set the period of the clock signal to 8H, and the duty cycle of the clock signal transmitted by the clock line is <50%. Practical verification results show that setting the duty cycle of the clock signal transmitted by the clock line to 37.5% can meet the display panel's requirements for the gate control signal and reduce the probability of display difference problems on the display panel.

[0088] In addition, when the gate driving circuit is applied to a display panel, in order to meet the display panel's demand for gate control signals, the gate driving circuit can also be improved by increasing the number of clock lines included in the gate driving circuit. Figure 1A In the design shown in FIG. 1 , the period of the clock signal is set to 8H, and the falling edge intervals of the Nth level first gate control signal Scan1(N), the Nth level second gate control signal Scan2(N), the N+1th level first gate control signal Scan1, and the N+1th level second gate control signal Scan2 are 1H. Figure 3A As shown. However, because the pulse widths of the effective levels of the first gate control signal Scan1 and the second gate control signal Scan2 are different, the sub-pixel Spi or pixel corresponding to the first gate control signal Scan1 has a pre-charging phase of 1H, while the sub-pixel Spi or pixel corresponding to the second gate control signal does not have a pre-charging phase. Therefore, there will be a display difference between the sub-pixel Spi or pixel applying the first gate control signal Scan1 and the sub-pixel Spi or pixel applying the second gate control signal Scan2. To this end, the gate drive circuit can be made to adopt Figure 1B The structure shown is designed and applied Figure 2BThe timing design shown is to make the falling edge interval of the first gate control signal Scan1 and the second gate control signal Scan2 output by the same gate drive circuit become 2H, the pulse width of the effective level of the first gate control signal Scan1 becomes 4H, and the pulse width of the effective level of the second gate control signal Scan2 becomes 2H, so that the sub-pixel Spi or pixel using the first gate control signal Scan1 has a pre-charging stage of 3H, and the sub-pixel Spi or pixel using the second gate control signal Scan2 has a pre-charging stage of 1H. After the sub-pixel Spi or pixel has the pre-charging stage, the charging difference between the sub-pixels Spi or pixels can be reduced, thereby improving the display difference problem caused by uneven charging of the sub-pixels Spi or pixels.

[0089] Figure 4A to Figure 4B is a schematic diagram of the structure of a display panel provided by an embodiment of the present invention. The present application also provides a display panel, comprising any of the above-mentioned gate drive circuits. Figure 4A to Figure 4B The STV in the above corresponds to the receiving start signal, and the Dcs corresponds to the receiving pull-down control signal.

[0090] Please continue reading Figure 4A to Figure 4B The display panel includes a plurality of sub-pixels Spi, and the plurality of sub-pixels Spi are electrically connected to the gate driving circuit. The sub-pixels Spi may include transistors (such as Figure 4A Ts shown in the figure, so as to control the working state of the sub-pixel Spi through the transistor controlled by the corresponding gate control signal.

[0091] It should be noted that the sub-pixel Spi may also include components such as a storage capacitor Cs. The structure of the sub-pixel Spi is not limited to Figure 4A The form shown.

[0092] Optionally, the first gate control signal Scan1 and the second gate control signal Scan2 output by the same gate driving sub-circuit GA may be used to control two transistors in the same sub-pixel Spi, or may be used to control two transistors in different sub-pixels Spi.

[0093] It should be noted that when the first gate control signal Scan1 and the second gate control signal Scan2 output by the same gate driving sub-circuit GA are used to control two transistors in different sub-pixels Spii, it may mean that the first gate control signal Scan1 and the second gate control signal Scan2 output by the same gate driving sub-circuit GA are used to control transistors with the same function in different sub-pixels Spi, or it may mean that they are used to control transistors with different functions in different sub-pixels Spi.

[0094] It can be understood that the display panel may include a plurality of pixels, and each pixel may include at least one sub-pixel Spi.

[0095] Figure 5 Schematic diagram of sub-pixel charging duration provided by an embodiment of the present invention. Optionally, the first gate control signal Scan1 outputted from the first output terminal Out1 of the gate driving sub-circuit GA can control the corresponding sub-pixel Spi to have a pre-charging period of the first duration tA, and the second gate control signal Scan2 outputted from the second output terminal Out2 of the gate driving sub-circuit GA can control the corresponding sub-pixel Spi to have a pre-charging period of the second duration tB; the first duration tA is greater than or equal to the second duration tB, so as to reduce the charging difference between the sub-pixels Spi, and then improve the display difference problem caused by uneven charging of the sub-pixels Spi.

[0096] Optionally, the gate driving circuit may be disposed in the non-display area NA, the sub-pixel Spi may be disposed in the display area AA, and the non-display area NA is located on one side of the display area AA. Figure 4A to Figure 4B As shown, the influence of the gate drive circuit on the resolution can be reduced.

[0097] Optionally, the first cascade group GM1 and the second cascade group GM2 may be arranged on opposite sides of the display area AA to reduce the layout space occupied by the gate driving circuit in the single-side frame. Figure 4B shown.

[0098] Optionally, the 4H+1th row of sub-pixels Spi and the 4H+2th row of sub-pixels Spi receive gate control signals output by the first cascade group GM1, and the 4H+3th row of sub-pixels Spi and the 4H+4th row of sub-pixels Spi receive gate control signals output by the second cascade group GM2, so that the first cascade group GM1 and the second cascade group GM2 cross-drive the sub-pixels Spi in the display panel. Wherein, H≥0.

[0099] Optionally, the 4H+1th row of sub-pixels Spii receives the first gate control signal Scan1 output by the first cascade group GM1, and the 4H+2th row of sub-pixels Spii receives the second gate control signal Scan2 output by the first cascade group GM1; the 4H+3th row of sub-pixels Spii receives the first gate control signal Scan1 output by the second cascade group GM2, and the 4H+4th row of sub-pixels Spii receives the second gate control signal Scan2 output by the second cascade group GM2, so that the gate control signals received by the odd-numbered rows of sub-pixels Spii are all the first gate control signal Scan1, and the gate control signals received by the even-numbered rows of sub-pixels Spii are all the second gate control signal Scan2, so as to weaken the display difference problem.

[0100] In addition, the 4H+1th row sub-pixel Spi and the 4H+3th row sub-pixel Spi can receive the gate control signal output by the first cascade group GM1, and the 4H+2th row sub-pixel Spi and the 4H+4th row sub-pixel Spi can receive the gate control signal output by the second cascade group GM2, so that the first cascade group GM1 and the second cascade group GM2 can cross-drive the sub-pixels Spi in the display panel. Wherein, H≥0.

[0101] Correspondingly, the 4H+1th row sub-pixel Spii can receive the first gate control signal Scan1 output by the first cascade group GM1, and the 4H+2th row sub-pixel Spii can receive the first gate control signal Scan1 output by the second cascade group GM2; the 4H+3th row sub-pixel Spii can receive the second gate control signal Scan2 output by the first cascade group GM1, and the 4H+4th row sub-pixel Spii can receive the second gate control signal Scan2 output by the second cascade group GM2, so that the gate control signals received by the 4H+1th row sub-pixel Spii and the 4H+2th row sub-pixel Spii are both the first gate control signal Scan1, and the gate control signals received by the 4H+3th row sub-pixel Spii and the 4H+4th row sub-pixel Spii are both the second gate control signal Scan2, so as to improve the display difference problem.

[0102] Please continue reading Figure 4A to Figure 4B The display panel further includes a scan line SL and a data line DL, and the sub-pixel Spi is electrically connected to the corresponding scan line SL and data line DL. The scan line SL is electrically connected to the gate driving circuit, and the scan line SL is configured to transmit a corresponding gate control signal. The data line DL is configured to transmit a data signal to the sub-pixel Spi, so as to charge the sub-pixel Spi using the data signal.

[0103] The gate drive circuit and display panel provided by the present application can reduce the number of gate drive sub-circuits GA included in the gate drive circuit and reduce the layout space occupied by the gate drive circuit. When the gate drive circuit is used in the display panel, it helps the display panel to achieve a narrow frame design. In addition, since the factor pixel Spi receives the gate control signal but does not receive the level transmission signal ST, when there is a signal short circuit in the display area of ​​the display panel, it will not reversely affect the level transmission control function of the gate drive circuit, thereby improving the stability of the operation of the gate drive circuit.

[0104] Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A gate drive circuit, characterized in that: The invention comprises a plurality of cascaded gate driving sub-circuits, wherein the gate driving sub-circuit comprises: a node control module, electrically connected to a first node and a second node of the gate driving sub-circuit at this level, and configured to control signals transmitted to the first node and the second node according to a start signal; a stage transmission module, electrically connected to the first node, and configured to control the transmission of the first clock signal to the stage transmission output terminal of the gate driving sub-circuit of the current stage according to the signal of the first node; a first output module, electrically connected to the stage transmission output terminal and the first output terminal of the gate driving sub-circuit of the same stage, and configured to receive a second clock signal and a third clock signal to control signal transmission between the stage transmission output terminal and one of the first power supply terminal and the first output terminal; a second output module, electrically connected to the stage transmission output terminal and the second output terminal of the current stage gate driving sub-circuit, and configured to control signal transmission between the stage transmission output terminal and the second output terminal according to the third clock signal; and The pull-down maintaining module is electrically connected to the second node and is configured to control signal transmission between the first power supply end and the second output end according to a signal of the second node.

2. The gate driving circuit according to claim 1, characterized in that: The first output module comprises: a first output transistor, comprising a control terminal configured to receive the second clock signal, a first source-drain terminal electrically connected to the stage transmission output terminal, and a second source-drain terminal electrically connected to the first output terminal; The second output transistor includes a control terminal configured to receive the third clock signal, a first source-drain terminal electrically connected to the first power terminal, and a second source-drain terminal electrically connected to the first output terminal.

3. The gate driving circuit according to claim 1, characterized in that: The second output module comprises: The third output transistor includes a control terminal configured to receive the third clock signal, a first source-drain terminal electrically connected to the stage transmission output terminal, and a second source-drain terminal electrically connected to the second output terminal.

4. The gate driving circuit according to claim 1, characterized in that: The pull-down maintaining module comprises: The first transistor includes a control terminal electrically connected to the second node, a first source-drain terminal electrically connected to the first power terminal, and a second source-drain terminal electrically connected to the second output terminal.

5. The gate driving circuit according to claim 1, characterized in that: The pull-down maintaining module is electrically connected to the first output terminal, and is configured to control signal transmission between the first power terminal and the first output terminal according to a signal of the second node.

6. The gate driving circuit according to claim 1, characterized in that: The pull-down maintaining module is electrically connected to the first node and the stage transmission output terminal, and is configured to control the electrical connection between the first power supply terminal and the first node and the stage transmission output terminal according to the signal of the second node.

7. The gate driving circuit according to claim 1, characterized in that: The node control module includes: a pull-up control unit, electrically connected to the first node and the second power supply terminal, and configured to control signal transmission between the second power supply terminal and the first node according to the start signal; an inverting unit, electrically connected to the first node, the second node, the first power supply terminal and the second power supply terminal, and configured to control one of the first power supply terminal and the second power supply terminal to be electrically connected to the second node according to a signal of the first node; Among them, the start signal corresponding to the first-level gate driving subcircuit in the multiple cascaded gate driving subcircuits is the start signal, and the start signal corresponding to the Nth-level gate driving subcircuit is the level transmission signal generated by the NXth-level gate driving subcircuit, N>1, X>1.

8. The gate driving circuit according to claim 1, characterized in that: The node control module includes: a pull-down control unit, electrically connected to the first node and the first power supply terminal, and configured to control signal transmission between the first power supply terminal and the first node according to a pull-down control signal; The pull-down control signal corresponding to the Mth gate driving sub-circuit in the plurality of cascaded gate driving sub-circuits is a level transmission signal generated by the M+Yth gate driving sub-circuit, where M≥1 and Y>1.

9. The gate driving circuit according to claim 1, characterized in that: include: A plurality of clock lines are electrically connected to the plurality of gate driving sub-circuits and are configured to transmit the corresponding first clock signal, the second clock signal and the third clock signal to the plurality of gate driving sub-circuits.

10. The gate driving circuit according to claim 9, characterized in that: The plurality of clock lines include: a first clock line, configured to transmit the corresponding first clock signal to the 4K+1-th level gate driver sub-circuit, configured to transmit the corresponding second clock signal to the 4K+2-th level gate driver sub-circuit, and configured to transmit the corresponding third clock signal to the 4K+4-th level gate driver sub-circuit; a second clock line, configured to transmit the corresponding third clock signal to the 4K+1-th level gate driver sub-circuit, configured to transmit the corresponding first clock signal to the 4K+2-th level gate driver sub-circuit, and configured to transmit the corresponding second clock signal to the 4K+3-th level gate driver sub-circuit; a third clock line configured to transmit the corresponding third clock signal to the 4K+2-stage gate driver sub-circuit, configured to transmit the corresponding first clock signal to the 4K+3-stage gate driver sub-circuit, and configured to transmit the corresponding second clock signal to the 4K+4-stage gate driver sub-circuit; and The fourth clock line is configured to transmit the corresponding second clock signal to the 4K+1-level gate driver sub-circuit, and is configured to transmit the corresponding third clock signal to the 4K+3-level gate driver sub-circuit, and is configured to transmit the corresponding first clock signal to the 4K+4-level gate driver sub-circuit; wherein K≥0.

11. The gate driving circuit according to claim 9, characterized in that: The plurality of clock lines are divided into a first group of clock lines and a second group of clock lines, the gate driving circuit comprises a first cascade group and a second cascade group, the first cascade group and the second cascade group respectively comprising a plurality of cascaded gate driving sub-circuits; Among them, the first group of clock lines is configured to transmit the corresponding first clock signal, the second clock signal and the third clock signal to the multiple gate driving sub-circuits in the first cascade group; the second group of clock lines is configured to transmit the corresponding first clock signal, the second clock signal and the third clock signal to the multiple gate driving sub-circuits in the second cascade group.

12. The gate driving circuit according to claim 11, characterized in that: The first cascade group includes an odd number of gate driving sub-circuits, and the second cascade group includes an even number of gate driving sub-circuits.

13. The gate driving circuit according to claim 11, characterized in that: The first group of clock lines includes a first clock line, a second clock line, a third clock line and a fourth clock line; The first clock line is configured to transmit the corresponding first clock signal to the 4K+1-level gate driver sub-circuit in the first cascade group, and is configured to transmit the corresponding second clock signal to the 4K+2-level gate driver sub-circuit, and is configured to transmit the corresponding third clock signal to the 4K+4-level gate driver sub-circuit; the second clock line is configured to transmit the corresponding third clock signal to the 4K+1-level gate driver sub-circuit in the first cascade group, and is configured to transmit the corresponding first clock signal to the 4K+2-level gate driver sub-circuit, and is configured to transmit the corresponding second clock signal to the 4K+3-level gate driver sub-circuit; the third clock line is configured to transmit the corresponding third clock signal to the 4K+2-level gate driver sub-circuit in the first cascade group, and is configured to transmit the corresponding first clock signal to the 4K+3-level gate driver sub-circuit, and is configured to transmit the corresponding second clock signal to the 4K+4-level gate driver sub-circuit; The fourth clock line is configured to transmit the corresponding second clock signal to the 4K+1-level gate driver sub-circuit in the first cascade group, and is configured to transmit the corresponding third clock signal to the 4K+3-level gate driver sub-circuit, and is configured to transmit the corresponding first clock signal to the 4K+4-level gate driver sub-circuit; wherein, K≥0.

14. The gate driving circuit according to claim 13, characterized in that: The second group of clock lines includes a fifth clock line, a sixth clock line, a seventh clock line and an eighth clock line; The fifth clock line is configured to transmit the corresponding first clock signal to the 4K+1-stage gate driver sub-circuit in the second cascade group, and is configured to transmit the corresponding second clock signal to the 4K+2-stage gate driver sub-circuit, and is configured to transmit the corresponding third clock signal to the 4K+4-stage gate driver sub-circuit; the sixth clock line is configured to transmit the corresponding third clock signal to the 4K+1-stage gate driver sub-circuit in the second cascade group, and is configured to transmit the corresponding first clock signal to the 4K+2-stage gate driver sub-circuit, and is configured to transmit the corresponding second clock signal to the 4K+3-stage gate driver sub-circuit; The seventh clock line is configured to transmit the corresponding third clock signal to the 4K+2-stage gate driving sub-circuit in the second cascade group, and is configured to transmit the corresponding first clock signal to the 4K+3-stage gate driving sub-circuit, and is configured to transmit the corresponding second clock signal to the 4K+4-stage gate driving sub-circuit; The eighth clock line is configured to transmit the corresponding second clock signal to the 4K+1-level gate driver sub-circuit in the second cascade group, and is configured to transmit the corresponding third clock signal to the 4K+3-level gate driver sub-circuit, and is configured to transmit the corresponding first clock signal to the 4K+4-level gate driver sub-circuit.

15. The gate driving circuit according to claim 14, characterized in that: The phase difference between the clock signals transmitted by two adjacent clock lines in the first group of clock lines is equal to the phase difference between the clock signals transmitted by two adjacent clock lines in the second group of clock lines.

16. The gate driving circuit according to claim 15, characterized in that: There is a first phase difference between the clock signal transmitted by the first clock line and the clock signal transmitted by the fifth clock line, and there is a second phase difference between the clock signal transmitted by the fifth clock line and the clock signal transmitted by the second clock line; The first phase difference is smaller than the second phase difference.

17. The gate driving circuit according to claim 9 or 11, characterized in that: The duty cycle of the clock signal transmitted by the clock line is 37.5%.

18. A display panel, characterized in that: It comprises the gate driving circuit as claimed in any one of claims 1 to 17.

19. The display panel according to claim 18, characterized in that: The display panel includes a plurality of sub-pixels, and the plurality of sub-pixels are electrically connected to the gate driving circuit; Among them, the first gate control signal outputted from the first output terminal of the gate driving subcircuit controls the corresponding sub-pixel to have a pre-charging period of a first duration, and the second gate control signal outputted from the second output terminal of the gate driving subcircuit controls the corresponding sub-pixel to have a pre-charging period of a second duration; the first duration is greater than the second duration.

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