Memory array and memory
By designing independent bit line connections and structures in which multiple active regions intersect bit lines in the memory array, the complex problem of non-volatile memory read control is solved, and the operation is simplified and the memory cell density is improved.
Patent Information
- Application Number
- CN202310847579.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-07-11
- Publication Date
- 2025-01-14
AI Technical Summary
The read control of existing nonvolatile memory is relatively complex and difficult to simplify.
A memory array is designed, by in pairs of adjacent two memory cells in the first direction, the bit lines are connected independently without sharing, and a structure in which multiple active regions intersect the bit lines, using the second and third controls. The signal line is connected to the gate of the memory cell pair, simplifying reading and programming operations.
The read and programming operations of the memory array are simplified, the operation complexity is reduced, and the density of memory cell pairs is improved.
Smart Images
Figure CN119314538A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of memory technology, and in particular to a memory array and a memory. Background Art
[0002] Non-volatile memory (NVM) is widely used in personal computers and electronic devices because it can store, read and erase data multiple times, and the stored data will not disappear after power failure. However, some non-volatile memories currently have the problem of complex read control.
[0003] Therefore, it is necessary to propose a technical solution to improve the more complex problems such as the read control of non-volatile memory. Summary of the invention
[0004] The purpose of the present application is to provide a memory array and a memory to simplify operations such as reading and programming of the memory.
[0005] In a first aspect, the present application provides a memory array, comprising:
[0006] a plurality of first control signal lines extending along a first direction;
[0007] a plurality of bit lines extending along a second direction, the first direction intersecting the second direction; and
[0008] A plurality of active regions, wherein the active regions are provided with memory cell pairs, wherein the memory cell pairs include a first region, a second region, a channel region, and a first gate, wherein the first region and the second region are respectively connected to opposite sides of the channel region, wherein the first gate is located at one side of the channel region and overlaps with the channel region, wherein the plurality of memory cell pairs provided in the plurality of active regions include a plurality of rows of memory cell pairs, wherein a row of the memory cell pairs includes at least two memory cell pairs arranged along a first direction, wherein the first gates of at least two memory cell pairs in a row of the memory cell pairs are connected to the first control signal line, and one memory cell pair is connected to two bit lines;
[0009] Among the two adjacent memory cell pairs in the first direction, any one of the two bit lines connected to one memory cell pair is different from the two bit lines connected to the other memory cell pair.
[0010] In some embodiments, among two adjacent pairs of memory cells in the first direction, two bit lines connected to one memory cell pair and two bit lines connected to another memory cell pair are disposed adjacent to each other.
[0011] In some embodiments, a plurality of the active regions intersect a plurality of the bit lines.
[0012] In some embodiments, an angle between the active region and the bit line is greater than or equal to 10 degrees and less than or equal to 90 degrees.
[0013] In some embodiments, the memory array further includes: a plurality of contacts located at the intersection of the active area and the bit line, wherein the opposite ends of a portion of the contacts are in contact with the bit line and the first region respectively, and the opposite ends of another portion of the contacts are in contact with the bit line and the second region respectively.
[0014] In some embodiments, an extension direction of the active region intersects both the first direction and the second direction.
[0015] In some embodiments, the first direction is perpendicular to the second direction.
[0016] In some embodiments, a plurality of active regions extend in a straight line.
[0017] In some embodiments, the plurality of bit lines extend in a straight line.
[0018] In some embodiments, the memory cell pair further includes a second gate and a third gate disposed at intervals, wherein the second gate and the third gate are located at one side of the channel region and overlap with the channel region;
[0019] The memory array further comprises:
[0020] a plurality of second control signal lines, wherein one of the second control signal lines is connected to the second gates of at least two of the memory cell pairs in a row of the memory cell pairs;
[0021] A plurality of third control signal lines are provided, wherein one of the third control signal lines is connected to the third gates of at least two of the memory cell pairs in a row of the memory cell pairs.
[0022] In some embodiments, the memory array comprises:
[0023] A semiconductor layer, wherein the semiconductor layer includes a plurality of active regions;
[0024] A first conductive layer, located at one side of the semiconductor layer in a thickness direction of the semiconductor layer, and comprising a plurality of the first control signal lines;
[0025] A second conductive layer, located at one side of the semiconductor layer in the thickness direction of the semiconductor layer, and comprising a plurality of the bit lines;
[0026] Wherein, in the thickness direction of the semiconductor layer, the first conductive layer is located on a side of the second conductive layer away from the semiconductor layer; or,
[0027] In a thickness direction of the semiconductor layer, the second conductive layer is located on a side of the first conductive layer away from the semiconductor layer.
[0028] In a second aspect, the present application provides a memory, comprising the memory array of any of the above embodiments.
[0029] The beneficial effects of some embodiments of the present application include: since in two adjacent memory cell pairs in the first direction, any one of the two bit lines connected to one memory cell pair is different from the two bit lines connected to the other memory cell pair, the two bit lines respectively connected to the two adjacent memory cells in the first direction are independent of each other without sharing any bit lines, and when operations such as reading and programming are required for any one of the two adjacent memory cell pairs, the operation is simpler. BRIEF DESCRIPTION OF THE DRAWINGS
[0030] Figure 1 A schematic diagram of the structure of a memory array in some embodiments of the present application;
[0031] Figure 2 For along Figure 1 A schematic diagram of a first cross-sectional structure of the memory array taken along line ZZ;
[0032] Figure 3 For along Figure 1 A second cross-sectional structural schematic diagram of the memory array taken along line ZZ;
[0033] Figure 4 for Figure 1 A schematic circuit diagram of the memory array shown;
[0034] Figure 5 A schematic block diagram of a storage device according to some embodiments of the present application. DETAILED DESCRIPTION
[0035] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.
[0036] Please refer to Figures 1 to 4 As shown, Figure 1 is a schematic diagram of the structure of a memory array in some embodiments of the present application, Figure 2 For along Figure 1The first cross-sectional structure diagram of the memory array taken along line ZZ is shown, Figure 3 For along Figure 1 A second cross-sectional structural diagram of the memory array taken along line ZZ shown in FIG. Figure 4 for Figure 1 Schematic circuit of the memory array shown.
[0037] like Figure 1 As shown, the memory array 100 includes a plurality of active areas AA, a plurality of first control signal lines WL, a plurality of second control signal lines CgA, a plurality of third control signal lines CgB, a plurality of bit lines BL, and a plurality of contacts CT.
[0038] like Figure 2 and Figure 3 As shown, the memory array 100 includes a semiconductor layer 10, a first conductive layer 11, and a second conductive layer 12. In the thickness direction z of the semiconductor layer 10, the first conductive layer 11 and the second conductive layer 12 are located on the same side of the semiconductor layer 10 and an insulating layer is disposed between the two. Figure 2 As shown, in the thickness direction z of the semiconductor layer 10, the second conductive layer 12 is located on the side of the first conductive layer 11 away from the semiconductor layer 10. Figure 3 As shown, in the thickness direction z of the semiconductor layer 10 , the first conductive layer 11 is located on a side of the second conductive layer 12 away from the semiconductor layer 10 .
[0039] The semiconductor layer 10 includes a plurality of active areas AA, and the semiconductor layer 10 also includes an isolation area GA located between two adjacent active areas AA. The first conductive layer 11 includes a plurality of first control signal lines WL, and the first conductive layer 11 may also include a plurality of second control signal lines CgA and a plurality of third control signal lines CgB. The second conductive layer 12 includes a plurality of bit lines BL.
[0040] In some embodiments, the semiconductor layer 10 includes but is not limited to a silicon substrate. The first conductive layer 11 and the second conductive layer 12 include conductive materials, including metals and polysilicon, etc. The metals include but are not limited to tungsten, copper, aluminum and combinations thereof.
[0041] like Figure 1 As shown, multiple active areas AA extend along the third direction w and are arranged at intervals along the first direction x, and the first direction x intersects the third direction w. Each active area AA is provided with multiple memory cell pairs U, and each memory cell pair U includes two memory cells, which are respectively a first memory cell U1 and a second memory cell U2.
[0042] The plurality of memory cell pairs U arranged in the plurality of active areas AA include a plurality of rows of memory cell pairs U arranged at intervals along the second direction y, and a row of memory cell pairs U includes at least two memory cell pairs U arranged along the first direction x, and the first direction x intersects the second direction y. For example, Figure 1 A row of memory cell pairs U in the dashed box HU includes four memory cell pairs.
[0043] like Figure 1 As shown, in some embodiments, the first direction x is perpendicular to the second direction y, and the third direction w intersects the first direction x and the second direction y, but is not limited thereto.
[0044] In other embodiments, the angle between the first direction x and the second direction y may also be an obtuse angle or an acute angle. In other embodiments, the third direction w may also be parallel to the first direction x, in which case the plurality of active areas AA are arranged at intervals along the second direction y.
[0045] Exemplarily, the plurality of active areas AA include an active area AA0 , an active area AA1 , an active area AA2 , and an active area AA3 arranged at intervals along the first direction x.
[0046] like Figure 2 and Figure 3 As shown, each memory cell pair U includes a first region 10a, a second region 10b, a channel region 10c, a first gate WG, a second gate CG1, a third gate CG2, a first floating gate FG1 and a second floating gate FG2.
[0047] In the third direction w, the first region 10a and the second region 10b are respectively connected to opposite sides of the channel region 10c. The first region 10a and the second region 10b are both P-type doped regions or N-type doped regions.
[0048] In the thickness direction z of the semiconductor layer 10, the first gate WG, the second gate CG1 and the third gate CG2 are all located on one side of the channel region 10c and overlap with the channel region 10c. In the extension direction of the active area AA, that is, in the third direction w, the second gate CG1 and the third gate CG2 are respectively located on opposite sides of the first gate WG.
[0049] The first floating gate FG1 and the second floating gate FG2 are also located on one side of the channel region 10c and overlap with the channel region 10c. In the thickness direction z of the semiconductor layer 10, the first floating gate FG1 overlaps with the second gate CG1 and is located between the channel region 10c and the second gate CG1. The first floating gate FG1, the second gate CG1 and the channel region 10c are insulated from each other. The first storage unit U1 includes the first floating gate FG1 and the second gate CG1, that is, the first storage unit U1 is a storage transistor. In the thickness direction z of the semiconductor layer 10, the second floating gate FG2 overlaps with the third gate CG2 and is located between the channel region 10c and the third gate CG2. The second floating gate FG2, the third gate CG2 and the channel region 10c are insulated from each other. The second storage unit U2 includes the second floating gate FG2 and the third gate CG2, that is, the second storage unit U2 is also a storage transistor. The first storage unit U1 and the second storage unit U2 share the first gate WG, the first region 10a and the second region 10b.
[0050] In some embodiments, the plurality of active areas AA extend in a straight line, but are not limited thereto, so as to simplify the process of forming the plurality of active areas AA.
[0051] In other embodiments, at least part of the multiple active areas AA may also extend in a zigzag shape, so that the multiple active areas AA intersect with the multiple bit lines BL, reducing the difficulty of connecting the memory cell pairs U with the bit lines BL.
[0052] In some embodiments, multiple active areas AA are arranged at equal intervals in the first direction x to simplify the preparation process of the multiple active areas AA. Exemplarily, the spacing between two adjacent active areas AA is greater than or equal to 0.05 microns and less than or equal to 0.1 microns. The width of each active area AA is greater than or equal to 0.05 microns and less than or equal to 0.2 microns.
[0053] like Figure 1 As shown, a plurality of first control signal lines WL extend along the first direction x and are arranged at intervals along the second direction y. The first gates WG of at least two memory cell pairs U in a row of memory cell pairs U are connected to one first control signal line WL.
[0054] In some embodiments, the first gate WG is a word line gate, and the first control signal line WL includes a word line selection signal line, but is not limited thereto.
[0055] In some other embodiments, the first gate WG may be an erase gate, and the first control signal line WL may also include an erase gate line.
[0056] In some embodiments, the plurality of first control signal lines WL extend in a straight line shape to simplify the manufacturing process of the plurality of first control signal lines WL.
[0057] For example, Figure 1 As shown, the plurality of first control signal lines WL include first control signal lines WL arranged in sequence along the second direction y. <0> , the first control signal line WL <1> , first control signal line WL <2> and a first control signal line WL <3> wait.
[0058] A plurality of second control signal lines CgA extend along the first direction x and are arranged at intervals along the second direction y. A second control signal line CgA is adjacent to and spaced from a first control signal line WL. A second control signal line CgA is connected to the second gates CG1 of at least two storage cell pairs U in a row of storage cell pairs U. Correspondingly, a second control signal line CgA controls the conduction and closing of at least two first storage cells U1 in a row of storage cell pairs U.
[0059] In some embodiments, the plurality of second control signal lines CgA extend in a straight line to simplify the manufacturing process of the plurality of second control signal lines CgA.
[0060] Exemplarily, the plurality of second control signal lines CgA include second control signal lines CgA sequentially arranged along the second direction y. <0> , the second control signal line CgA <1> , the second control signal line CgA <2> and the second control signal line CgA <3> wait.
[0061] In the second direction y, the second control signal line CgA <0> The first control signal line WL <0> The second control signal line CgA is adjacent to <0> Located on the first control signal line WL <0> Close to the first control signal line WL <1> In the second direction y, the second control signal line CgA <1> The first control signal line WL <1> The second control signal line CgA is adjacent to <1> Located on the first control signal line WL <1> Close to the first control signal line WL <0> In the second direction y, the second control signal line CgA <2> The first control signal line WL <2> The second control signal line CgA is adjacent to <2> Located on the first control signal line WL <2> Away from the first control signal line WL <1> In the second direction y, the second control signal line CgA <3> The first control signal line WL <3> The second control signal line CgA is adjacent to <3> Located on the first control signal line WL <3> Close to the first control signal line WL <2> side.
[0062] A plurality of third control signal lines CgB extend along the first direction x and are arranged at intervals along the second direction y. In the second direction y, a third control signal line CgB is adjacent to and spaced from a first control signal line WL. A third control signal line CgB is connected to the third gates CG2 of at least two storage cell pairs U in a row of storage cell pairs U, and correspondingly, a third control signal line CgB controls the opening and closing of at least two second storage cells U2 in a row of storage cell pairs U.
[0063] In some embodiments, the plurality of third control signal lines CgB extend along a straight line to simplify the manufacturing process of the plurality of third control signal lines CgB.
[0064] An adjacent third control signal line CgB, a second control signal line CgA, and a first control signal line WL form a gate signal line group K, and a plurality of gate signal line groups K are arranged at intervals along the second direction y. In a gate signal line group K, in the second direction y, a third control signal line CgB and a second control signal line CgA are respectively located on opposite sides of a first control signal line WL.
[0065] Exemplarily, the interval d between two adjacent gate signal line groups K is greater than or equal to 0.1 micrometer and less than or equal to 0.4 micrometer. In addition, the dimension c occupied by one gate signal line group K in the second direction y is greater than 0.1 micrometer and less than or equal to 0.4 micrometer.
[0066] Exemplarily, the plurality of third control signal lines CgB include third control signal lines CgB sequentially arranged along the second direction y. <0> , the third control signal line CgB <1> , the third control signal line CgB <2> and the third control signal line CgB <3> .
[0067] Among them, the third control signal line CgB <0> The first control signal line WL <0> The third control signal line CgB is adjacently arranged. <0> Located on the first control signal line WL <0> Away from the first control signal line WL <1> The third control signal line CgB <1> The first control signal line WL <1> The third control signal line CgB is adjacently arranged. <1> Located on the first control signal line WL <1> Close to the first control signal line WL <2> The third control signal line CgB <2> The first control signal line WL <2> The third control signal line CgB is adjacently arranged. <2> Located on the first control signal line WL <2> Away from the first control signal line WL <3> The third control signal line CgB <3> The first control signal line WL <3> The third control signal line CgB is adjacently arranged. <3> and the first control signal line WL <3> Away from the first control signal line WL <2> side.
[0068] The plurality of bit lines BL extend along the second direction y and are arranged at intervals along the first direction x. A memory cell pair U is connected to two bit lines BL, so the two bit lines BL and a first control signal line WL can be controlled to implement a selection operation on a memory cell pair U. Moreover, a memory cell pair U is connected to two bit lines BL, and the ground terminal of each memory cell pair U can also be omitted, thereby increasing the layout space of the memory cell pair U and improving the density of the memory cell pair U.
[0069] In two adjacent memory cell pairs U in the first direction x, any one of the two bit lines BL connected to one memory cell pair U is different from the two bit lines BL connected to the other memory cell pair U. In other words, the two adjacent memory cell pairs U connected to the same first control signal line WL in the first direction x do not have a common bit line BL, and the bit lines BL connected to the two adjacent memory cell pairs U in the first direction x are independent of each other, which can simplify the selection operations such as reading and programming of the memory array 100.
[0070] It should be noted that in some related technologies, when a memory cell pair is connected to two bit lines, two adjacent memory cell pairs in a row of memory cell pairs share a bit line. When one of the memory cell pairs needs to be selected for operation, the bit line connected to the other memory cell pair needs to be specially controlled, which increases the difficulty of selecting and controlling the memory cell pair. In the present application, since two adjacent memory cell pairs U in the first direction x do not share a common bit line BL, the bit lines BL connected to two adjacent memory cell pairs U in the first direction x are independent of each other, which simplifies the selection control of the memory array 100, such as reading and programming.
[0071] In some embodiments, during a read operation on a memory cell in the selected memory cell pair U,
[0072] The first control signal line WL connected to one memory cell of the selected one memory cell pair U transmits a first read control voltage, one of the second control signal line CgA and the third control signal line CgB connected to one memory cell of the selected one memory cell pair U transmits a second read control voltage, the other of the second control signal line CgA and the third control signal line CgB connected to the other memory cell of the selected one memory cell pair U transmits a first voltage, the first read control voltage and the first voltage are both positive voltages, and the second read control voltage is greater than or equal to 0V;
[0073] The first control signal line WL, the second control signal line CgA and the third control signal line CgB connected to other non-selected memory cell pairs U are all connected to zero voltage;
[0074] A bit line BL connected to one memory cell in a selected memory cell pair U is connected to a zero voltage, and a bit line BL connected to another memory cell in the selected memory cell pair U transmits a read voltage, which is a positive voltage;
[0075] The bit lines connected to other non-selected memory cell pairs are connected to zero voltage. It can be seen that in some embodiments of the present application, during a read operation on a memory cell in a selected memory cell pair U, only one bit line transmits a read voltage, and the other bit lines are connected to zero voltage, which can simplify the read operation of the memory array.
[0076] In some embodiments of the present application, during a programming operation on a memory cell in a selected memory cell pair U,
[0077] A first control signal line WL connected to one memory cell in a selected memory cell pair U transmits a first programming control voltage, one of a second control signal line CgA and a third control signal line CgB connected to one memory cell in a selected memory cell pair U transmits a second programming control voltage, and the other of the second control signal line CgA and the third control signal line CgB connected to the other memory cell in the selected memory cell pair U transmits a first voltage, and the first programming control voltage, the second programming control voltage, and the first voltage are all positive voltages;
[0078] The first control signal line WL, the second control signal line CgA and the third control signal line CgB connected to other non-selected memory cell pairs U are connected to zero voltage;
[0079] The bit line BL connected to one memory cell in the selected memory cell pair U transmits a programming voltage, the bit line BL connected to the other memory cell in the selected memory cell pair U is connected to a zero voltage, and the programming voltage is a positive voltage; and
[0080] The bit lines connected to other non-selected memory cell pairs are connected to zero voltage.
[0081] It can be seen that in some embodiments of the present application, during the programming operation of a selected memory cell pair U, only one bit line transmits the programming voltage and the other bit lines are connected to zero voltage, which simplifies the programming operation of the memory array.
[0082] In some embodiments of the present application, during an erase operation on a selected storage unit in a storage unit pair U,
[0083] The first control signal line WL connected to the selected memory cell pair U transmits a first erasure control voltage, and the second control signal line CgA and the third control signal line CgB connected to the selected memory cell pair U both transmit a second erasure control voltage, the first erasure control voltage is a positive voltage, and the second erasure control voltage is a negative voltage;
[0084] The first control signal line WL, the second control signal line CgA and the third control signal line CgB connected to other non-selected memory cell pairs U are all connected to zero voltage;
[0085] All bit lines are connected to zero voltage.
[0086] It can be seen that in some embodiments of the present application, during the erasing operation on a memory cell in a selected memory cell pair U, the first control signal line WL connected to the selected memory cell pair U transmits a first erasing control voltage, the second control signal line CgA and the third control signal line CgB connected to the selected memory cell pair U both transmit a second erasing control voltage, and the other control signal lines and all bit lines are connected to zero voltage, which can realize the erasing of a row of memory cell pairs and simplify the erasing operation of the memory array.
[0087] In some embodiments, in two adjacent memory cell pairs U in the first direction x, two bit lines BL connected to one memory cell pair U and two bit lines BL connected to another memory cell pair U are arranged adjacent to each other to simplify the connection method between the memory cell U and the two bit lines BL and simplify the manufacturing process of the memory array.
[0088] Exemplarily, the plurality of bit lines BL include bit lines BL0, BL1, BL2, BL3, BL4, BL5, BL6, BL7, BL8, BL9 and BL10 sequentially arranged along the first direction x.
[0089] Exemplarily, in the first direction x, the memory cell pair Ua and the memory cell pair Ub are arranged adjacent to each other and both are connected to the first control signal line WL <0> The memory cell pair Ua is connected to the bit line BL0 and the bit line BL1, and the memory cell pair Ub is connected to the bit line BL2 and the bit line BL3. Either of the bit line BL0 and the bit line BL1 is different from the bit line BL2 and the bit line BL3, and the bit line BL0 and the bit line BL1 are arranged adjacent to the bit line BL2 and the bit line BL3.
[0090] For example, when a read operation is required on a storage unit in the storage unit pair Ua, the first control signal line WL <0> Transmits the first read control voltage, the third control signal line CgB <0> and the second control signal line CgA <0> One of them transmits the second read control voltage, and the third control signal line CgB <0> and the second control signal line CgA <0> The other one of the bit lines transmits the first voltage, one of the bit lines BL0 and the bit line BL1 transmits the read voltage, the other of the bit line BL0 and the bit line BL1 is connected to zero voltage, and the other first control signal line WL, the third control signal line CgB, the second control signal line CgA and the bit line BL are connected to zero voltage without the need for special control, and the read operation selection control of the memory array 100 becomes simpler.
[0091] For example, when a programming operation needs to be performed on a memory cell in the memory cell pair Ua, the first control signal line WL <0> Transmits the first programming control voltage, the third control signal line CgB <0> and the second control signal line CgA <0> One of them transmits the second programming control voltage, and the third control signal line CgB <0> and the second control signal line CgA <0> The other one of the bit lines transmits the first voltage, one of the bit lines BL0 and BL1 transmits the programming voltage, the other one of the bit lines BL0 and BL1 is connected to zero voltage, and the other first control signal line WL, the third control signal line CgB, the second control signal line CgA and the bit line BL are connected to zero voltage without the need for special control.
[0092] For example, when an erase operation needs to be performed on a storage unit in the storage unit pair Ua, the first control signal line WL <0> Transmits the first erase control voltage, the third control signal line CgB <0> and the second control signal line CgA <0> The second erasing control voltage is transmitted, and the other first control signal line WL, the third control signal line CgB, the second control signal line CgA and all the bit lines BL are connected to zero voltage without special control.
[0093] In some embodiments, the plurality of bit lines BL extend in a straight line to simplify the fabrication process of the plurality of bit lines BL.
[0094] In other embodiments, at least a portion of the bit line BL may extend in a zigzag shape to facilitate the intersection of the bit line BL with the active area AA, thereby facilitating direct connection between the bit line BL and the memory cell pair U in the active area AA through the contact CT, thereby reducing the number of conductive layers required for the memory array 100 and simplifying the preparation process of the memory array 100.
[0095] Exemplarily, in the first direction x, a distance between two adjacent bit lines BL is greater than or equal to 0.05 micrometers and less than or equal to 0.2 micrometers.
[0096] In some embodiments, multiple active areas AA intersect multiple bit lines BL to save the conductive layer connecting the memory cell pairs U in the active areas AA and the corresponding bit lines BL, simplify the manufacturing process of the memory array, and reduce the manufacturing cost of the memory array. In addition, multiple active areas AA intersect multiple bit lines BL, which can also save the plane space required for arranging other conductive layers, and there is more space to set the bit lines BL, increase the number of bit lines BL, and help improve the density of the memory cell pairs U in the memory array 100.
[0097] In some embodiments, the angle α between the active area AA and the bit line BL is greater than or equal to 10 degrees and less than or equal to 90 degrees to ensure that multiple active areas AA intersect multiple bit lines BL while ensuring the density of memory cell pairs U in the memory array 100 .
[0098] It is understandable that the angle α between the active area AA and the bit line BL may also be greater than or equal to 15 degrees and less than or equal to 80 degrees. Alternatively, the angle α between the source area AA and the bit line BL may also be greater than or equal to 20 degrees and less than or equal to 50 degrees.
[0099] For example, the angle α between the active area AA and the bit line BL is 10 degrees, 15 degrees, 20 degrees, 25 degrees, 30 degrees, 35 degrees, 40 degrees, 45 degrees, 50 degrees, 55 degrees, 60 degrees, 65 degrees, 70 degrees, 75 degrees, 80 degrees, 85 degrees or 90 degrees.
[0100] In some other embodiments, the plurality of active areas AA and the plurality of bit lines BL may also be parallel and not intersecting.
[0101] In some embodiments, when multiple active areas AA intersect multiple bit lines BL and the angle between the two is greater than 0 degree and less than 90 degrees, in the first direction x, the spacing between adjacent active areas AA is smaller than the spacing between two adjacent bit lines BL, which is beneficial to increase the density of storage cells in the memory array 100.
[0102] Multiple contacts CT are located at the intersection of the active area AA and the bit line BL, and opposite ends of a portion of the contacts CT are in contact with the bit line BL and the first region 10a, respectively, and opposite ends of another portion of the contacts CT are in contact with the bit line BL and the second region 10b, respectively, so that the memory cell pair U is directly connected to the two bit lines BL through the two contacts CT, thereby reducing the connection resistance.
[0103] In some related technologies, the contact CT is connected to the bit line BL through an independent metal layer. The independent metal layer not only occupies an independent wiring space, thereby reducing the storage density, but also increases the difficulty of manufacturing the memory array.
[0104] For example, in combination Figures 1 to 3 As shown, the plurality of contacts CT include a contact CT1 and a contact CT2, wherein opposite ends of the contact CT1 are respectively connected to the bit line BL9 and the second region 10b, and opposite ends of the contact CT2 are respectively in contact with the bit line BL8 and the first region 10a.
[0105] Please also refer to Figure 1 and Figure 4 As shown, along Figure 4 There is a memory string 200 in the direction of the line L shown. A memory string 200 includes a plurality of memory cell pairs U connected in series. A memory string 200 is arranged obliquely with respect to the bit line BL.
[0106] like Figure 5 As shown, the present application also provides a memory 300, which is a non-volatile memory. The memory 300 includes the memory array 100 and the peripheral circuit 400 of any of the above embodiments. The peripheral circuit 400 is connected to the memory array 100, and the peripheral circuit 400 includes a control circuit 500.
[0107] In some embodiments of the present application, for the memory array 100, during a read operation on a memory cell in a selected memory cell pair U, the control circuit 500 is configured to perform the following operations:
[0108] Applying a first read control voltage to a first control signal line WL connected to one memory cell of a selected memory cell pair U, applying a second read control voltage to one of a second control signal line CgA and a third control signal line CgB connected to one memory cell of the selected memory cell pair U, applying a first voltage to the other of the second control signal line CgA and the third control signal line CgB connected to the other memory cell of the selected memory cell pair U, the first read control voltage and the first voltage are both positive voltages, and the second read control voltage is greater than or equal to 0V;
[0109] Applying a zero voltage to the first control signal line WL, the second control signal line CgA, and the third control signal line CgB connected to other non-selected memory cell pairs U;
[0110] Applying a zero voltage to a bit line BL connected to one memory cell in the selected memory cell pair U, and applying a read voltage to a bit line BL connected to the other memory cell in the selected memory cell pair U, wherein the read voltage is a positive voltage; and
[0111] Zero voltage is applied to the bit lines connected to other non-selected memory cell pairs.
[0112] In some embodiments of the present application, during a programming operation on a selected storage cell in the storage cell pair U, the control circuit 500 is further configured to perform the following operations:
[0113] Applying a first programming control voltage to a first control signal line WL connected to a memory cell of a selected memory cell pair U, applying a second programming control voltage to one of a second control signal line CgA and a third control signal line CgB connected to a memory cell of the selected memory cell pair U, and applying a first voltage to the other of the second control signal line CgA and the third control signal line CgB connected to the other memory cell of the selected memory cell pair U, wherein the first programming control voltage, the second programming control voltage, and the first voltage are all positive voltages;
[0114] Applying a zero voltage to the first control signal line WL, the second control signal line CgA, and the third control signal line CgB connected to other non-selected memory cell pairs U;
[0115] Applying a programming voltage to a bit line BL connected to one memory cell in the selected memory cell pair U, and applying a zero voltage to a bit line BL connected to the other memory cell in the selected memory cell pair U, wherein the programming voltage is a positive voltage; and
[0116] Zero voltage is applied to the bit lines connected to other non-selected memory cell pairs.
[0117] In some embodiments of the present application, during the erasing operation on a selected storage unit in the storage unit pair U, the control circuit 400 is configured to perform the following operations:
[0118] Apply a first erasing control voltage to a first control signal line WL connected to a selected memory cell pair U, and apply a second erasing control voltage to a second control signal line CgA and a third control signal line CgB connected to a selected memory cell pair U, wherein the first erasing control voltage is a positive voltage and the second erasing control voltage is a negative voltage;
[0119] Applying a zero voltage to the first control signal line WL, the second control signal line CgA, and the third control signal line CgB connected to other non-selected memory cell pairs U;
[0120] Zero voltage is applied to all bit lines.
[0121] In combination with the above-mentioned memory array reading and programming method, it can be known that when a memory cell in a memory cell pair needs to be read and programmed, only the operating voltage needs to be applied to the two bit lines connected to the selected memory cell pair, and the other bit lines connected to the non-selected memory cell pairs are all applied with zero voltage without special control. Therefore, the memory array of the present application has simple reading and programming operations.
[0122] As shown in Table 1, Table 2 and Table 3, Table 1 is for Figure 1 Table 2 is a voltage table for the memory array to perform a read operation. Figure 1 The voltage table of the memory array for programming operation is shown in FIG. Figure 3 For Figure 1 The voltage table of the memory array for erase operation is shown. In Table 1, Vbl_rd = 0.6V ~ 1V, Vwl_rd = 4V ~ 5V, Vcg_pass = 4.5V ~ 6V, Vcg_rd = 0V ~ 0.5V; in Table 2, Vbl_pgm = 5V ~ 6V, Vwl_pgm = 1V ~ 2V, Vcg_pass = 4.5V ~ 6V, Vcg_pgm = 7V ~ 9V; in Table 3, Vwl_ers = 8V ~ 10V, Vcg_ers = -6V ~ -10V.
[0123] Table 1
[0124]
[0125] Table 2
[0126]
[0127] Table 3
[0128]
[0129] Regarding Table 1, taking the first row of data in Table 1 as an example, it is necessary to control the second control signal line CgA in the storage unit pair Ua. <0> When a memory cell connected to the active area AA0 is read, the memory cell connected to the active area AA0 and connected to the second control signal line CgA <0> When a memory cell connected to the first control signal line WL performs a read operation. <0> Write the first read control voltage Vwl_rd, the second control signal line CgA <0> Write the second read control voltage Vcg_rd, the third control signal line CgB <0> Write the first voltage Vcg_pass, write 0V to the other first control signal line WL, the second control signal line CgA and the third control signal line CgB; write the read voltage Vbl_rd to the bit line BL0, and write 0V to the other bit lines BL. The data in other rows of Table 1 can be deduced in the same way, which will not be repeated here.
[0130] Regarding Table 2, taking the first row of data in Table 2 as an example, we need to Figure 1 The memory cell pair Ua shown in FIG. <0> When a memory cell connected to the first control signal line WL is programmed, <0> Write the first programming control voltage Vwl_pgm, the second control signal line CgA <0> Write the second programming control voltage Vcg_pgm, the third control signal line CgB <0> The first voltage Vcg_pass is written, and 0V is written to the other first control signal lines WL, the second control signal line CgA, and the third control signal line CgB; the programming voltage Vbl_pgm is written to the bit line BL1, 0V is written to the bit line BL0, and 0V is also written to the other bit lines BL. The data in other rows in Table 2 can be deduced in the same way, and will not be repeated here.
[0131] Regarding Table 3, taking the first row of data in Table 3 as an example, we need to Figure 1 The memory cell pair Ua shown in FIG. <0> When a memory cell connected to the first control signal line WL is erased, <0> Write the first erase control voltage Vwl_ers, the second control signal line CgA <0> and the third control signal line CgB <0> The second erasing control voltage Vcg_ers is written into all bit lines BL and other control signal lines are written into 0 V. The data in other rows in Table 3 can be deduced in the same way, which will not be described here.
[0132] It can be seen from Table 1, Table 2 and Table 3 that when a memory cell of the memory array 100 is read and a memory cell of U is programmed, the operation is simple.
[0133] The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technical personnel in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.
Claims
1. A memory array, characterized in that: include: a plurality of first control signal lines extending along a first direction; a plurality of bit lines extending along a second direction, the first direction intersecting the second direction; as well as A plurality of active regions, wherein the active regions are provided with memory cell pairs, wherein the memory cell pairs include a first region, a second region, a channel region, and a first gate, wherein the first region and the second region are respectively connected to opposite sides of the channel region, wherein the first gate is located at one side of the channel region and overlaps with the channel region, wherein the plurality of memory cell pairs provided in the plurality of active regions include a plurality of rows of memory cell pairs, wherein a row of the memory cell pairs includes at least two memory cell pairs arranged along a first direction, wherein the first gates of at least two memory cell pairs in a row of the memory cell pairs are connected to the first control signal line, and one memory cell pair is connected to two bit lines; Among the two adjacent memory cell pairs in the first direction, any one of the two bit lines connected to one memory cell pair is different from the two bit lines connected to the other memory cell pair.
2. The memory array according to claim 1, wherein: Of the two memory cell pairs adjacent to each other in the first direction, the two bit lines connected to one memory cell pair and the two bit lines connected to the other memory cell pair are disposed adjacent to each other.
3. The memory array according to claim 1, wherein: A plurality of the active regions intersect a plurality of the bit lines.
4. The memory array according to claim 3, characterized in that: An included angle between the active region and the bit line is greater than or equal to 10 degrees and less than or equal to 90 degrees.
5. The memory array according to claim 3, wherein: The memory array further includes: a plurality of contacts located at the intersection of the active area and the bit line, wherein opposite ends of a portion of the contacts are in contact with the bit line and the first region respectively, and opposite ends of another portion of the contacts are in contact with the bit line and the second region respectively.
6. The memory array according to any one of claims 1 to 5, characterized in that: An extension direction of the active region intersects both the first direction and the second direction.
7. The memory array according to any one of claims 1 to 5, characterized in that: The first direction is perpendicular to the second direction.
8. The memory array according to any one of claims 1 to 5, characterized in that: The plurality of active regions extend in a straight line.
9. The memory array according to any one of claims 1 to 5, characterized in that: The plurality of bit lines extend in a straight line.
10. The memory array according to any one of claims 1 to 5, characterized in that: The memory cell pair further includes a second gate and a third gate which are arranged at intervals, wherein the second gate and the third gate are located at one side of the channel region and overlap with the channel region; The memory array further comprises: a plurality of second control signal lines, wherein one of the second control signal lines is connected to the second gates of at least two of the memory cell pairs in a row of the memory cell pairs; A plurality of third control signal lines are provided, wherein one of the third control signal lines is connected to the third gates of at least two of the memory cell pairs in a row of the memory cell pairs.
11. The memory array according to any one of claims 1 to 5, characterized in that: The memory array comprises: A semiconductor layer, wherein the semiconductor layer includes a plurality of active regions; A first conductive layer, located at one side of the semiconductor layer in a thickness direction of the semiconductor layer, and comprising a plurality of the first control signal lines; A second conductive layer, located at one side of the semiconductor layer in the thickness direction of the semiconductor layer, and comprising a plurality of the bit lines; Wherein, in the thickness direction of the semiconductor layer, the first conductive layer is located on a side of the second conductive layer away from the semiconductor layer; or, In a thickness direction of the semiconductor layer, the second conductive layer is located on a side of the first conductive layer away from the semiconductor layer.
12. A memory, characterized in that: The memory comprises a memory array as claimed in any one of claims 1 to 11.