Method for increasing height of long-channel metal gate

Abstract

The invention provides a method for increasing the height of a long-channel metal gate, and the method comprises the steps: providing a semiconductor structure which comprises a substrate, a dummy gate, an etching barrier layer, and an interlayer dielectric layer; grinding the interlayer dielectric layer by using a first chemical mechanical grinding process until the etching barrier layer formed on the surface of the dummy gate is exposed; the etching barrier layer formed on the surface of the dummy gate structure is ground through a second chemical mechanical grinding process until the dummy gate is exposed, and at the moment, the height of the dummy gate in the long channel device region is larger than that of the dummy gate in the short channel device region; removing the dummy gate to form a gate opening; filling the gate opening with a metal layer; and grinding the metal layer by using a third chemical mechanical grinding process to form a metal gate. According to the invention, the problem that the gate height of the long-channel device region formed by the existing process is too low is solved.

Description

Technical Field

[0001] The invention relates to the technical field of semiconductor manufacturing, and in particular to a method for increasing the height of a long channel metal gate. Background Art

[0002] At present, the interlayer dielectric layer zero chemical mechanical polishing (ILD0_CMP) process of the 22nm&28nm process platform is to first polish the silicon dioxide layer with a high-selectivity polishing liquid and stop at the surface of the silicon nitride layer, and then use a non-selectivity polishing liquid to polish away the silicon nitride layer. After the ILD0_CMP process, the height difference between the short trench polysilicon gate and the long trench polysilicon gate can be achieved at a considerable level, but the interlayer dielectric layer area with a large line width will produce dishing defects of more than 100 angstroms (such as Figure 1 As shown in FIG. 1 ), aluminum residues will be formed on the surface of the metal gate when the metal gate is subsequently formed (as shown in FIG. Figure 2 As shown). The metal gate chemical mechanical polishing (MG_CMP) process uses a high selectivity polishing liquid (AL:OX≈100:1, AL is the material used to form the metal gate, OX is the material used to form the interlayer dielectric layer). Therefore, the polishing rate of the long channel area is faster than that of the short channel area, causing the metal gate in the long channel area to be polished to a lower position (the metal gate in the long channel area is about 70 angstroms lower than the metal gate in the short channel area) (as shown Figure 2 As shown in the figure, the height of the metal gate in the long channel area is too low, which will cause abnormal electrical properties of the device. In addition, in order to ensure that the metal aluminum above the interlayer dielectric layer can be ground cleanly, the adjustment window of the MG_CMP process grinding time is small, and it is impossible to take into account both the clean removal of aluminum and the height control of the long channel metal gate. Summary of the invention

[0003] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a method for increasing the height of a long channel metal gate, so as to solve the problem that the gate height of a long channel device region formed by the existing process is too low.

[0004] To achieve the above objectives and other related objectives, the present invention provides a method for increasing the height of a long channel metal gate, the method comprising:

[0005] A semiconductor structure is provided, comprising a substrate, a dummy gate, an etch stop layer and an interlayer dielectric layer, wherein the substrate is divided into a short channel device region and a long channel device region, the dummy gate is formed on the substrate in the short channel device region and the long channel device region, the etch stop layer is formed on the surface, the sidewall of the dummy gate and the substrate between each of the dummy gates, the interlayer dielectric layer is formed on the surface of the etch stop layer between each of the dummy gates and extends to above the dummy gate, and the interlayer dielectric layer formed in the long channel device region has a larger width;

[0006] The interlayer dielectric layer is polished by a first chemical mechanical polishing process until the etch stop layer formed on the surface of the dummy gate is exposed, wherein during polishing, the selectivity ratio of the polishing liquid to the interlayer dielectric layer and the etch stop layer is greater than 20;

[0007] The etch stop layer formed on the surface of the dummy gate structure is polished by a second chemical mechanical polishing process until the dummy gate is exposed, wherein the height of the dummy gate in the long channel device region is higher than the height of the dummy gate in the short channel device region, and during polishing, the selectivity ratio of the polishing liquid to the etch stop layer and the dummy gate and the selectivity ratio of the polishing liquid to the etch stop layer and the interlayer dielectric layer are both greater than 20;

[0008] removing the dummy gate to form a gate opening;

[0009] Filling the gate opening with a metal layer, wherein the metal layer extends to the surface of the interlayer dielectric layer;

[0010] The metal layer is polished by a third chemical mechanical polishing process to form a metal gate, wherein the height of the metal gate formed in the short channel device region is substantially flush with the height of the metal gate formed in the long channel device region.

[0011] Optionally, after the etch stop layer is polished by a second chemical mechanical polishing process, the height of the dummy gate in the long channel device region is 60 angstroms to 80 angstroms higher than the height of the dummy gate in the short channel device region.

[0012] Optionally, the interlayer dielectric layer formed in the long channel device region has a width ranging from 0.9 μm to 1.1 μm.

[0013] Optionally, the material of the dummy gate includes polysilicon.

[0014] Optionally, the material of the etch stop layer includes silicon nitride.

[0015] Optionally, the material of the interlayer dielectric layer includes silicon oxide.

[0016] Optionally, the material of the metal layer includes metal aluminum.

[0017] Optionally, sidewall spacers are formed on both sides of the dummy gate, and in this case, the etch stop layer covers the sidewall spacers.

[0018] Optionally, the metal gate formed in the short channel device region includes a metal gate for forming an N-channel field effect transistor and a metal gate for forming a P-channel field effect transistor.

[0019] Optionally, the applicable technology node is less than or equal to 28 nm.

[0020] As described above, the method of increasing the height of the long channel metal gate of the present invention adopts a grinding liquid with a high selectivity ratio for the etch barrier layer (SiN) for grinding, which can increase the relative height of the metal gate in the long channel device area, so that the height difference between the metal gate in the short channel device area and the metal gate in the long channel device area is improved by 84%, and the dish-shaped defects of the large line width interlayer dielectric layer are reduced. After aluminum grinding, the process window of aluminum residue is expanded (that is, there is no aluminum residue on the surface of the interlayer dielectric layer). BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 The diagram shows a semiconductor structure in which a butterfly defect is formed in a conventional long channel region.

[0022] Figure 2 A schematic diagram of a semiconductor structure showing a height difference between a metal gate in a conventional long channel region and a metal gate in a short channel region.

[0023] Figure 3 to Figure 8 It is a cross-sectional structural schematic diagram showing the process of increasing the height of the long channel metal gate according to the present invention.

[0024] Fig. 9 The flowchart of the method for increasing the height of the long channel metal gate of the present invention is shown.

[0025] Description of Figure Numbers

[0026] 10: semiconductor structure; 11: substrate; 12: pseudo gate; 13: etching barrier layer; 14: interlayer dielectric layer; 15: sidewall; 16: source and drain doping region; 20: gate opening; 30: metal layer; 31: metal gate DETAILED DESCRIPTION

[0027] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0028] See also Figures 1 to 7 It should be noted that the illustrations provided in this embodiment are only schematic illustrations of the basic concept of the present invention. Although the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation, the form, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the component layout may also be more complicated.

[0029] like Fig. 9 As shown, this embodiment provides a method for increasing the height of a long channel metal gate, the method comprising:

[0030] A semiconductor structure 10 is provided, comprising a substrate 11, a dummy gate 12, an etch stop layer 13 and an interlayer dielectric layer 14, wherein the substrate 11 is divided into a short channel device region A and a long channel device region B, the dummy gate 12 is formed on the substrate 11 in the short channel device region A and the long channel device region B, the etch stop layer 13 is formed on the surface, sidewall and substrate 11 between the dummy gates 12, the interlayer dielectric layer 14 is formed on the surface of the etch stop layer 13 between the dummy gates 12 and extends to above the dummy gates 12, and the interlayer dielectric layer 14 formed in the long channel device region B has a larger width;

[0031] The interlayer dielectric layer 14 is polished by a first chemical mechanical polishing process until the etch stop layer 13 formed on the surface of the dummy gate 12 is exposed, wherein during the polishing, the selectivity ratio of the polishing liquid to the interlayer dielectric layer 14 and the etch stop layer 13 is greater than 20;

[0032] The etch stop layer 13 formed on the surface of the dummy gate 12 structure is polished by a second chemical mechanical polishing process until the dummy gate 12 is exposed, at which time, the height of the dummy gate 12 in the long channel device region B is higher than the height of the dummy gate 12 in the short channel device region A, wherein, during polishing, the selectivity ratio of the polishing liquid to the etch stop layer 13 and the dummy gate 12 and the selectivity ratio of the polishing liquid to the etch stop layer 13 and the interlayer dielectric layer 14 are both greater than 20;

[0033] removing the dummy gate 12 to form a gate opening 20;

[0034] Filling the gate opening 20 with a metal layer 30 , wherein the metal layer 30 extends to the surface of the interlayer dielectric layer 14 ;

[0035] The metal layer 30 is polished by a third chemical mechanical polishing process to form a metal gate 31 , wherein the height of the metal gate 31 formed in the short channel device region A is substantially the same as the height of the metal gate 31 formed in the long channel device region B.

[0036] Specifically, after the etch stop layer 13 is polished by the second chemical mechanical polishing process, the height of the dummy gate 12 of the long channel device region B is higher than the height of the dummy gate 12 of the short channel device region A by 60 angstroms to 80 angstroms.

[0037] In this embodiment, after the interlayer dielectric layer 14 is polished, the height of the pseudo gate 12 in the long channel region B is raised by 65 angstroms, that is, the height of the pseudo gate 12 in the long channel region B is 65 angstroms higher than the height of the pseudo gate 12 in the short channel device region A.

[0038] Specifically, the width of the interlayer dielectric layer 14 formed in the long channel device region B has a value ranging from 0.9 μm to 1.1 μm.

[0039] In this embodiment, since the interlayer dielectric layer 14 of the long channel device region B has a large width, severe dish-shaped defects (butterfly defects greater than 100 angstroms) are prone to occur during grinding. However, by using a grinding liquid with a selectivity ratio of the etch stop layer 13 to the interlayer dielectric layer 14 greater than 20 for grinding, the butterfly defects can be improved by 48%.

[0040] Specifically, the material of the dummy gate 12 includes polysilicon.

[0041] Specifically, the material of the etching stop layer 13 includes silicon nitride.

[0042] Specifically, the material of the interlayer dielectric layer 14 includes silicon oxide.

[0043] Specifically, the material of the metal layer 30 includes metal aluminum.

[0044] Specifically, sidewall spacers 15 are formed on both sides of the dummy gate 12 , and at this time, the etching stop layer 13 covers the sidewall spacers 15 .

[0045] Furthermore, in this embodiment, the semiconductor structure 10 further includes source and drain doping regions 16 .

[0046] Specifically, the metal gate 31 formed in the short channel device region A includes a metal gate 31 for forming an N-channel field effect transistor and a metal gate 31 for forming a P-channel field effect transistor.

[0047] Specifically, the applicable technology node is less than or equal to 28nm.

[0048] In summary, the method of increasing the height of the long channel metal gate of the present invention adopts a polishing liquid with a high selectivity ratio for the etching barrier layer (SiN) for polishing, which can increase the relative height of the metal gate in the long channel device area, so that the height difference between the metal gate in the short channel device area and the metal gate in the long channel device area is improved by 84%, and the dish-shaped defect of the large line width interlayer dielectric layer is reduced. After aluminum polishing, the process window of aluminum residue is expanded (that is, there is no aluminum residue on the surface of the interlayer dielectric layer). Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0049] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for increasing the height of a long channel metal gate, characterized in that: The method comprises: A semiconductor structure is provided, comprising a substrate, a dummy gate, an etch stop layer and an interlayer dielectric layer, wherein the substrate is divided into a short channel device region and a long channel device region, the dummy gate is formed on the substrate in the short channel device region and the long channel device region, the etch stop layer is formed on the surface, the sidewall of the dummy gate and the substrate between each of the dummy gates, the interlayer dielectric layer is formed on the surface of the etch stop layer between each of the dummy gates and extends to above the dummy gate, and the interlayer dielectric layer formed in the long channel device region has a larger width; The interlayer dielectric layer is polished by a first chemical mechanical polishing process until the etch stop layer formed on the surface of the dummy gate is exposed, wherein during polishing, the selectivity ratio of the polishing liquid to the interlayer dielectric layer and the etch stop layer is greater than 20; The etch stop layer formed on the surface of the dummy gate structure is polished by a second chemical mechanical polishing process until the dummy gate is exposed, wherein the height of the dummy gate in the long channel device region is higher than the height of the dummy gate in the short channel device region, and during polishing, the selectivity ratio of the polishing liquid to the etch stop layer and the dummy gate and the selectivity ratio of the polishing liquid to the etch stop layer and the interlayer dielectric layer are both greater than 20; removing the dummy gate to form a gate opening; Filling the gate opening with a metal layer, wherein the metal layer extends to the surface of the interlayer dielectric layer; The metal layer is polished by a third chemical mechanical polishing process to form a metal gate, wherein the height of the metal gate formed in the short channel device region is substantially flush with the height of the metal gate formed in the long channel device region.

2. The method for increasing the height of a long channel metal gate according to claim 1, characterized in that: After the etching stop layer is polished by the second chemical mechanical polishing process, the height of the dummy gate in the long channel device region is 60 angstroms to 80 angstroms higher than the height of the dummy gate in the short channel device region.

3. The method for increasing the height of a long channel metal gate according to claim 1, characterized in that: The width of the interlayer dielectric layer formed in the long channel device region ranges from 0.9 μm to 1.1 μm.

4. The method for increasing the height of a long channel metal gate according to claim 1, characterized in that: The material of the dummy gate includes polysilicon.

5. The method for increasing the height of a long channel metal gate according to claim 1, characterized in that: The material of the etching stop layer includes silicon nitride.

6. The method for increasing the height of a long channel metal gate according to claim 1, characterized in that: The material of the interlayer dielectric layer includes silicon oxide.

7. The method for increasing the height of a long channel metal gate according to claim 1, characterized in that: The material of the metal layer includes metal aluminum.

8. The method for increasing the height of a long channel metal gate according to claim 1, characterized in that: Sidewall spacers are formed on both sides of the dummy gate, and at this time, the etching stop layer covers the sidewall spacers.

9. The method for increasing the height of a long channel metal gate according to claim 1, characterized in that: The metal gate formed in the short channel device region includes a metal gate for forming an N-channel field effect transistor and a metal gate for forming a P-channel field effect transistor.

10. The method for increasing the height of a long channel metal gate according to claim 1, characterized in that: Applicable technology nodes are less than or equal to 28nm.

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