A nine-level inverter topology and its modulation method

Abstract

The present invention provides a nine-level inverter topology and its modulation method. The topology includes a load terminal, a first DC voltage source, a second DC voltage source, and a third DC voltage source, which are respectively connected to the load terminal. The output voltage ratio among the first DC voltage source, the second DC voltage source, and the third DC voltage source is 2:1:1. By configuring insulated gate bipolar transistors and power diodes, the number of switching tubes is reduced, and it is ensured that there is no power reverse flow and instantaneous spike voltage problem in the inverter, so as to avoid the power reverse flow phenomenon caused by the reverse current of the high-voltage power unit flowing into the low-voltage power unit and the instantaneous spike voltage during inductive load, ensure the stability of the circuit output power and simplify the design. A hybrid modulation method of stepped wave + carrier stacking is used to ensure low switching losses of the high-voltage power unit and excellent harmonic characteristics of the inverter output voltage.

Description

Technical Field

[0001] The present invention relates to the technical field of multilevel inverter modulation, and particularly relates to a nine-level inverter topology structure and a modulation method thereof. Background Art

[0002] The topology structure and modulation strategy of an inverter are key factors affecting the quality and performance of the output voltage waveform of the inverter. In the field of multilevel inverters, although the NPC (Neutral Point Clamped) type inverter, FC (Flying Capacitor) type inverter, and CHB (Cascaded H-Bridge) type inverter each have their applications, they all have significant limitations. The NPC type inverter has a complex topology structure and is not easy to expand, and the problem of unbalanced DC bus capacitor voltage division is prominent; the FC type inverter requires a large number of DC capacitors, the problem of unbalanced voltage division is prominent, and an additional pre-charge circuit needs to be designed, increasing the complexity and cost of the system.

[0003] In the prior art, a traditional asymmetric CHB type inverter requires a large number of switching tubes to obtain a multilevel output voltage. For example, the topology structure of a traditional nine-level CHB type inverter is composed of 4 cascaded H-bridges, which consists of 4 independent DC voltage sources and 16 switching tubes (IGBTs); moreover, there are problems such as power imbalance, power reverse flow, and uneven heating, seriously affecting the stability and reliability of the inverter; in addition, the existing modulation strategy is complex and difficult to implement, and there are deficiencies such as a long cycle required for power balance in the existing modulation strategy, making it difficult to meet the actual application needs. Summary of the Invention

[0004] Aiming at the deficiencies of the prior art, the purpose of the present invention is to provide a nine-level inverter topology structure and a modulation method thereof, aiming to solve the technical problems that in the prior art, the traditional nine-level inverter topology structure has problems such as power imbalance, power reverse flow, and uneven heating, seriously affecting the stability and reliability of the inverter.

[0005] To achieve the above purpose, the present invention is realized through the following technical solutions: A nine-level inverter topology structure includes a load terminal, and a first DC voltage source, a second DC voltage source, and a third DC voltage source respectively connected to the load terminal, and the output voltage ratio among the first DC voltage source, the second DC voltage source, and the third DC voltage source is: 2:1:1;

[0006] The nine-level inverter topology further includes a first switching transistor and a second switching transistor disposed between the positive and negative electrodes of the second DC voltage source and the load terminal, a third switching transistor and a fourth switching transistor disposed between the first DC voltage source and the second DC voltage source, a fifth switching transistor and a sixth switching transistor disposed between the first DC voltage source and the third DC voltage source, and a seventh switching transistor and an eighth switching transistor disposed between the positive and negative electrodes of the third DC voltage source and the load terminal;

[0007] The nine-level inverter topology further includes a ninth switching transistor disposed between the fifth switching transistor and the sixth switching transistor, and a tenth switching transistor disposed between the second DC voltage source and the third DC voltage source;

[0008] The third switching transistor, the fourth switching transistor, the fifth switching transistor, and the sixth switching transistor are all connected to the load terminal; the third switching transistor, the fourth switching transistor, the fifth switching transistor, and the sixth switching transistor each include a switching transistor body, a first power diode and a second power diode disposed on the emitter side of the switching transistor body, and a third power diode and a fourth power diode disposed on the collector side of the switching transistor body; the switching transistor body, the first power diode, the second power diode, the third power diode, and the fourth power diode form a bidirectional current switch.

[0009] According to one aspect of the above technical solution, the first switching transistor, the second switching transistor, the seventh switching transistor, the eighth switching transistor, the ninth switching transistor, and the tenth switching transistor are all insulated gate bipolar transistors.

[0010] According to one aspect of the above technical solution, the output level u 1 of the first DC voltage source is: 0, -2E, and +2E; the output level u 2 of the second DC voltage source is: 0, -E, and +E; the output level u 3 of the third DC voltage source is: 0, -E, and +E;

[0011] The output voltage u AN of the load terminal satisfies: u AN =(u 1 +u 2 +u 3 ) = .

[0012] On the other hand, the present invention also provides a modulation method for a nine-level inverter topology, which is used to modulate the output voltage of the nine-level inverter topology in the above technical solution. The method includes:

[0013] The output of the first DC voltage source is modulated by a stepped wave, and the outputs of the second and third DC voltage sources are modulated by carrier stacking;

[0014] The expression of the first modulation wave output by the first DC voltage source is:

[0015] ;

[0016] In the formula, is the first modulation wave output by the first DC voltage source, is the modulation index, is the fundamental angular frequency, is the time variable;

[0017] The expression of the second modulation wave output by the second and third DC voltage sources is:

[0018] ;

[0019] In the formula, is the second modulation wave output by the second or third DC voltage source.

[0020] According to one aspect of the above technical solution, the modulation method further includes:

[0021] On the basis of using carrier stacking modulation for the second and third DC voltage sources, reduce the number of carrier signals of the second and third DC voltage sources and output a target modulation wave signal to reduce the difficulty of implementing the modulation strategy;

[0022] Among them, the expression of the target modulation wave signal is:

[0023] ;

[0024] In the formula, is the target modulation wave signal.

[0025] According to one aspect of the above technical solution, the modulation method further includes:

[0026] Reconstruct the second modulation wave and control the conduction angle of the output of the first DC voltage source to achieve power balance among the first, second, and third DC voltage sources within a quarter of the fundamental wave period;

[0027] The second modulation wave includes a first waveform and a second waveform. The steps of reconstructing the second modulation wave specifically include:

[0028] Every single triangular wave signal period, the positions of the first waveform and the second waveform are interchanged, and the working period of the second modulated wave after reconstruction is twice that before reconstruction;

[0029] Among them, the expression of the relationship between the working periods and frequencies of the second modulated wave before and after reconstruction is:

[0030] ;

[0031] In the formula, and are respectively the single triangular wave signal period and frequency of the carrier wave, and are the working periods of the carrier signal before reconstruction, and are the frequencies of the carrier signal before reconstruction, and are the working periods of the carrier signal after reconstruction, and are the frequencies of the carrier signal after reconstruction.

[0032] According to one aspect of the above technical solution, the expression of the control signal of the conduction angle output by the first DC voltage source is as follows:

[0033] ;

[0034] In the formula, and are the control signals, is the modulation degree, is the conduction angle.

[0035] According to one aspect of the above technical solution, the expression of the control signal of the voltage component output by the first DC voltage source is:

[0036] ;

[0037] In the formula, represents the control signal of the voltage component output by the first DC voltage source when the time variable is t, and n is the harmonic order;

[0038] The fundamental wave expression of the voltage component output by the first DC voltage source is:

[0039]

[0040] In the formula, represents the fundamental wave of the voltage component output by the first DC voltage source when the time variable is t, and E is the unit output level.

[0041] According to one aspect of the above technical solution, the expression of the control signal of the output voltage after the superposition of the second DC voltage source and the third DC voltage source is:

[0042] ;

[0043] In the formula, represents the control signal of the output voltage component after the superposition of the second DC voltage source and the third DC voltage source when the time variable is t;

[0044] The expression of the fundamental wave of the output voltage component after the superposition of the second DC voltage source and the third DC voltage source is:

[0045] ;

[0046] In the formula, represents the fundamental wave of the output voltage component after the superposition of the second DC voltage source and the third DC voltage source when the time variable is t.

[0047] According to one aspect of the above technical solution, in the power balance state, the relational expression between the conduction angle and the modulation degree is:

[0048] .

[0049] Compared with the prior art, the beneficial effects of the present invention are as follows: By configuring IGBT (Insulated Gate Bipolar Transistor) and power diodes, the number of switching tubes is reduced and it is ensured that there is no power reverse flow and instantaneous spike voltage problem in the inverter, so as to avoid the power reverse flow phenomenon caused by the reverse current of the high-voltage power unit flowing into the low-voltage power unit and the instantaneous spike voltage in the case of inductive loads, ensure the stability of the circuit output power and simplify the design. In terms of the modulation strategy, first, a hybrid modulation method of stepped wave + carrier stacking is used to ensure low switching loss of the high-voltage power unit and excellent harmonic characteristics of the output voltage of the inverter; secondly, on the basis of the hybrid carrier stacking modulation method, the modulation wave signal of the low-voltage power unit is improved, and an improved hybrid carrier stacking modulation strategy is introduced, reducing the number of carriers of the low-voltage power unit by half, optimizing the distribution of the switching device frequencies, reducing the difficulty of modulation implementation and reducing the loss difference of each switching tube; finally, by reconstructing the carrier signal of the low-voltage power unit, power balance between the low-voltage power units is achieved, and then by controlling the conduction angle of the high-voltage power unit, power balance between the high- and low-voltage power units is achieved. The improved hybrid carrier stacking modulation strategy for power balance is used to achieve coordinated control of all power units, realize power balance within a quarter of the fundamental wave period, and effectively improve the safety and reliability of the inverter operation. Description of the Drawings

[0050] Figure 1 Schematic diagram of the circuit structure of the nine-level inverter topology in the first embodiment of the present invention;

[0051] Figure 2 Ring diagram showing the relationship between the output levels and switch states of the inverter in the first embodiment of the present invention;

[0052] Figure 3 Schematic diagram of the principle of the traditional HLS-PWM (Hybrid Level Shifted Pulse Width Modulation) hybrid carrier stacking modulation strategy;

[0053] Figure 4 Schematic diagram of the principle of the improved hybrid level shifted pulse width modulation (IHLS-PWM) modulation strategy in the second embodiment of the present invention;

[0054] Figure 5 Waveform diagram of the carrier signals of the low-voltage power unit in the second embodiment of the present invention. In the figure, (a) is the waveform of the traditional carrier signal, and (b) is the waveform of the reconstructed carrier signal;

[0055] Figure 6 Schematic diagram of the modulation principle of the low-voltage power unit after the reconstruction of the carrier signal in the second embodiment of the present invention;

[0056] Figure 7 Schematic diagram of the modulation principle between the high- and low-voltage power units for controlling the conduction angle in the second embodiment of the present invention;

[0057] Figure 8 Relationship curve diagram between the conduction angle and the modulation degree under the condition of power balance in the second embodiment of the present invention;

[0058] Figure 9 Pulse signal diagram of each level output by the inverter in the second embodiment of the present invention;

[0059] Figure 10 Pulse signal diagram of the conduction state combination of the switching tubes when the inverter outputs each level within a complete fundamental wave period in the second embodiment of the present invention. In the figure, (a) is the pulse signal diagram of the positive half cycle, and (b) is the pulse signal diagram of the negative half cycle;

[0060] Figure 11 Waveform diagram of the output voltage components of each power unit when the inverter adopts the traditional HLS-PWM modulation strategy under different modulation degrees in the second embodiment of the present invention;

[0061] Figure 12Waveform diagram of the output voltage components of each power unit when the inverter adopts the power - balanced IHLS - PWM modulation strategy under different modulation degrees in the second embodiment of the present invention;

[0062] Figure 13 Waveform diagram of the output power of each power unit when the inverter adopts the traditional HLS - PWM modulation strategy under different modulation degrees in the second embodiment of the present invention;

[0063] Figure 14 Waveform diagram of the output power of each power unit when the inverter adopts the power - balanced IHLS - PWM modulation strategy under different modulation degrees in the second embodiment of the present invention;

[0064] Figure 15 Relationship diagram between the output power of each power unit and the modulation degree in the second embodiment of the present invention. In the figure, (a) is the average output power curve graph of each power unit under the condition of the traditional HLS - PWM modulation strategy, and (b) is the average output power curve graph of each power unit under the condition of the power - balanced IHLS - PWM modulation strategy;

[0065] Figure 16 Output voltage spectrum diagram of the inverter in the second embodiment of the present invention. In the figure, (a) is the output voltage spectrum diagram of the inverter under the condition of the traditional HLS - PWM modulation strategy, and (b) is the output voltage spectrum diagram of the inverter under the condition of the power - balanced IHLS - PWM modulation strategy;

[0066] Figure 17 Comparison curve graph of the relationship between the output voltage THD of the inverter and the modulation degree under the condition of the traditional HLS - PWM modulation strategy and the power - balanced IHLS - PWM modulation strategy in the second embodiment of the present invention;

[0067] Figure 18 Output voltage waveform, current waveform and output voltage harmonic spectrum diagram at the load end in the second embodiment of the present invention. In the figure, (a) is the output voltage waveform, current waveform and output voltage harmonic spectrum diagram at the load end when the modulation degree is 0.9, and (b) is the output voltage waveform, current waveform and output voltage harmonic spectrum diagram at the load end when the modulation degree is 0.6;

[0068] Figure 19 Waveform diagram of the output voltage components of each power unit in the second embodiment of the present invention. In the figure, (a) is the waveform diagram of the output voltage components of each power unit when the modulation degree is 0.9, and (b) is the waveform diagram of the output voltage components of each power unit when the modulation degree is 0.6;

[0069] Figure 20This is the output power waveform diagram of each power unit in the second embodiment of the present invention. In the figure, (a) is the output power waveform diagram of each power unit when the modulation index is 0.9, and (b) is the output power waveform diagram of each power unit when the modulation index is 0.6;

[0070] The following specific embodiments will further illustrate the present invention in conjunction with the above-mentioned drawings. Specific Embodiments

[0071] To facilitate the understanding of the present invention, the present invention will be described more comprehensively below with reference to the relevant drawings. Several embodiments of the present invention are shown in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present invention more thorough and comprehensive.

[0072] It should be noted that when an element is referred to as being "fixedly provided on" another element, it can be directly on the other element or there may also be an intermediate element. When an element is considered to be "connected" to another element, it can be directly connected to the other element or there may be an intermediate element at the same time. The terms "vertical", "horizontal", "left", "right" and similar expressions used herein are for illustrative purposes only.

[0073] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which the present invention belongs. The terms used in the description of the present invention herein are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0074] Please refer to Figure 1 , which shows the schematic diagram of the nine-level inverter topology structure in the first embodiment of the present invention. As shown in the figure, the topology structure includes:

[0075] A load terminal 10, and a first DC voltage source 11, a second DC voltage source 12, and a third DC voltage source 13 respectively connected to the load terminal 10. The output voltage ratios between the first DC voltage source 11, the second DC voltage source 12, and the third DC voltage source 13 are: 2:1:1;

[0076] The nine-level inverter topology further includes a first switching tube 21 and a second switching tube 22 disposed between the positive and negative electrodes of the second DC voltage source 12 and the load terminal 10, a third switching tube 23 and a fourth switching tube 24 disposed between the first DC voltage source 11 and the second DC voltage source 12, a fifth switching tube 25 and a sixth switching tube 26 disposed between the first DC voltage source 11 and the third DC voltage source 13, and a seventh switching tube 27 and an eighth switching tube 28 disposed between the positive and negative electrodes of the third DC voltage source 13 and the load terminal 10;

[0077] The nine-level inverter topology further includes a ninth switching tube 29 disposed between the fifth switching tube 25 and the sixth switching tube 26, and a tenth switching tube 210 disposed between the second DC voltage source 12 and the third DC voltage source 13;

[0078] The third switching tube 23, the fourth switching tube 24, the fifth switching tube 25, and the sixth switching tube 26 are all connected to the load terminal 10; the third switching tube 23, the fourth switching tube 24, the fifth switching tube 25, and the sixth switching tube 26 each include a switching tube body, a first power diode 31 and a second power diode 32 disposed on the emitter side of the switching tube body, and a third power diode 33 and a fourth power diode 34 disposed on the collector side of the switching tube body; the switching tube body, the first power diode 31, the second power diode 32, the third power diode 33, and the fourth power diode 34 form a bidirectional current switch.

[0079] For easy understanding, the traditional nine-level CHB type inverter topology is composed of 4 cascaded H-bridges, which consists of 4 independent DC voltage sources and 16 switching tubes (IGBTs). The nine-level inverter topology in this solution reduces 6 switching tubes compared with the traditional nine-level CHB type inverter topology.

[0080] Preferably, in this embodiment, the above-mentioned first switching tube 21, second switching tube 22, seventh switching tube 27, eighth switching tube 28, ninth switching tube 29, and tenth switching tube 210 are all insulated gate bipolar transistors.

[0081] Further, in this embodiment, the output level u of the above-mentioned first DC voltage source 11 1 is: 0, -2E, and +2E; the output level u of the second DC voltage source 12 2 is: 0, -E, and +E; the output level u of the third DC voltage source 13 3 is: 0, -E, and +E;

[0082] The output voltage u of the load terminal 10 AN satisfies: uAN = (u 1 + u 2 + u 3 ) = .

[0083] According to the conduction states of each switching device, the high-voltage power unit H 1 (including the first DC voltage source 11 and the switching device in its corresponding conduction state) can output three levels: 0, +2E, and -2E. The low-voltage power unit L 2 (including the second DC voltage source 12 and the switching device in its corresponding conduction state) and the low-voltage power unit L 3 (including the third DC voltage source 13 and the switching device in its corresponding conduction state) can both output three levels: 0, +E, and -E. There are a total of E 1 (the first DC voltage source 11), E 2 (the second DC voltage source 12), E 3 (the third DC voltage source 13), E 2 + E 3 , E 1 + E 2 , E 1 + E 3 , E 1 + E 2 + E 3 The superposition combination of seven power sources can output nine levels: 0, ±E, ±2E, ±3E, and ±4E. For easy understanding, each power unit in the text is the above-mentioned first DC voltage source 11, second DC voltage source 12, and third DC voltage source 13.

[0084] As Figure 2 shown, it is a circular diagram of the relationship between the output levels and switching states of the inverter, indicating that there are a total of 18 switching state combinations in one power cycle of the inverter. Figure 2 In it, "1, 2,..., 10" represent the switching devices in the conduction state corresponding to the current level (0, ±E, ±2E, ±3E, ±4E). 1 means the first switching device 21 is conducting, 2 means the second switching device 22 is conducting, and so on. 10 means the tenth switching device 210 is conducting, and the switching devices not shown are in the off state.

[0085] According to the conduction switching devices and output characteristics in the inverter topology, there is no reverse current of the high-voltage power unit flowing into the low-voltage power unit in the level of all redundant switching state combinations of the inverter. Therefore, there is no problem of power reverse flow between the electric powers proposed in this article. In the case of a resistive-inductive load, the lagging inductive current can flow back to the power source of the corresponding voltage level. Therefore, there is no problem of instantaneous peak voltage at the resistive-inductive load terminal 10.

[0086] In summary, in the nine-level inverter topology structure of the above embodiments of the present invention, by configuring IGBTs (Insulated Gate Bipolar Transistors) and power diodes, the number of switching tubes is reduced and it is ensured that there is no power reverse flow and instantaneous spike voltage problem in the inverter, so as to avoid the power reverse flow phenomenon caused by the reverse flow of the current of the high-voltage power unit into the low-voltage power unit and the instantaneous spike voltage during inductive load, and ensure the stability of the circuit output power and simplify the design.

[0087] Based on the nine-level inverter topology structure in the above first embodiment, the second embodiment of the present invention provides a modulation method for a nine-level inverter topology structure, and the method includes:

[0088] Perform stepped wave modulation on the output of the first DC voltage source, and perform carrier stacking modulation on the outputs of the second DC voltage source and the third DC voltage source.

[0089] For an inverter with a power supply voltage ratio of 2:1:1, the high-voltage power unit H 1 adopts stepped wave modulation, and the low-voltage power units L 2 and L 3 adopt carrier stacking modulation. The principle of the traditional HLS-PWM (Hybrid Level Shifted Pulse Width Modulation HLS-PWM) hybrid carrier stacking modulation strategy is as Figure 3 shown. v H is the modulation wave signal of the high-voltage power unit H1, v C1+ = +2, v C1- = -2 are the carrier signals of the high-voltage power unit; v L are the modulation wave signals of the low-voltage power units L2 and L3, v C2+ , v C2- , v C3+ , v C3- (isosceles triangular carriers with a frequency of f CR and a peak-to-peak value of 1, and the vertical offset between adjacent two carriers is 1) are the carrier signals of the low-voltage power unit.

[0090] The expression of the first modulation wave output by the first DC voltage source is:

[0091] (1);

[0092] In the formula, is the first modulation wave output by the first DC voltage source, To adjust the system, is the fundamental angular frequency, is the time variable;

[0093] The expression of the second modulation wave output by the second DC voltage source and the third DC voltage source is:

[0094] (2);

[0095] In the formula, It is the second modulation wave output by the second DC voltage source or the third DC voltage source.

[0096] The output voltage component u of the high voltage power unit H1 1 for:

[0097] when v H ≥ v C1+ When 1 =+2E; when v C1 -< v H < v C1+ When 1 =0; when v H ≤ v C1- When 1 = -2E. Low voltage power unit L 2 The output voltage component u 2 For: When v L ≥ v C2+ When 2 =+E;when v C2- < v L < v C2+ When 2 =0; when v L ≤ v C2- When 2 =-E. Low voltage power unit L 3 The output voltage component u 3 For: When v L ≥ v C3+ When 3= +E; When v C3- < v L < v C3+ When, u 3 = 0; When v L ≤ v C3- When, u 3 = -E.

[0098] Within a complete power cycle, the high-voltage power unit H1 operates at a low frequency and the output level is -2E, 0, +2E, and the output waveform is a square wave; the low-voltage power units L 2 , L 3 Both operate at a high frequency and the output level is -E, 0, +E, and the output waveforms are all high-frequency PWM waves. The output voltage components of the high-voltage power unit and the low-voltage power unit are superimposed to obtain the output voltage u AN of the nine-level inverter. The inverter adopts the traditional HLS-PWM modulation strategy. Within a complete working cycle, the polarities of the output voltage components of each unit are not different, that is, there is no problem of power reverse injection in the inverter power unit; this modulation method can also reduce the switching frequency of the switching tubes of the high-voltage power unit to reduce the switching loss, and the output voltage of the inverter maintains good harmonic characteristics.

[0099] Preferably, in this embodiment, the modulation method further includes:

[0100] On the basis of adopting carrier stacking modulation for the second DC voltage source and the third DC voltage source, reduce the number of carrier signals of the second DC voltage source and the third DC voltage source, and output a target modulation wave signal to reduce the implementation difficulty of the modulation strategy.

[0101] For easy understanding, this solution proposes an improved hybrid carrier stacking (Improved Hybrid Level Shifted Pulse Width Modulation IHLS-PWM) modulation strategy for the traditional HLS-PWM modulation strategy. The principle of the IHLS-PWM modulation strategy is as Figure 4 shown. is the improved modulation wave signal for the low-voltage power units L 2 , L 3 , v C2+ , v C3+ is the carrier signal of the low-voltage power unit. The original modulation wave signal v LAfter the negative half-cycle part is translated upward by "+2" units, an improved modulation wave signal is obtained. Within a complete power cycle of the inverter, the number of carrier signals of the improved low-voltage power unit is reduced by half.

[0102] High-voltage power unit H 1 The carrier signal, modulation wave signal, and output voltage component u 1 all remain unchanged.

[0103] Low-voltage power unit L 2 、L 3 The carrier signals v C2+ 、 v C3+ remain unchanged, and the expression of the modulation wave signal within a complete power cycle is:

[0104] (3);

[0105] In the formula, is the target modulation wave signal.

[0106] Specifically, the output voltage component u 2 of the low-voltage power unit L 2 is: within the half-cycle of , when ≥ v C2+ , u 2 = +E, when < v C2+ , u 2 = 0; within the half-cycle of , when ≥ v C2+ , u 2 = 0, when < v C2+ , u 2 = -E. The output voltage component u 3 of the low-voltage power unit L 3 is: within the half-cycle of , when ≥ v C3+ , u 3 = +E, when < v C3+ , u 3 = 0; within the half-cycle of , when ≥ vC3+ When u 3 = 0, when < v C3+ When u 3 = -E.

[0107] The IHLS-PWM modulation strategy is adopted to control the conduction state of the switching tubes. The modulation wave and carrier signal are optimized for the low-voltage power unit, reducing the implementation difficulty of the control signal. During a complete power cycle of the inverter, the control signals of some of the improved switching tubes change, narrowing the gap in the pulse signal frequencies between the low-voltage power units, that is, reducing the difference in the switching losses of some of the switching tubes. However, there is still a large gap in the operating time of each power unit, that is, there is a power imbalance problem between the low-voltage power units and between the high- and low-voltage power units.

[0108] Furthermore, in this embodiment, the modulation method further includes:

[0109] Reconstruct the second modulation wave and control the conduction angle output by the first DC voltage source to achieve power balance among the first DC voltage source, the second DC voltage source, and the third DC voltage source within a quarter of the fundamental wave period;

[0110] The second modulation wave includes a first waveform and a second waveform. The steps of reconstructing the second modulation wave specifically include:

[0111] Every single triangular wave signal period, swap the positions of the first waveform and the second waveform. After reconstruction, the working period of the second modulation wave is twice that before reconstruction.

[0112] Aiming at the problem that the IHLS-PWM modulation strategy cannot achieve power balance among the power units, the carrier signals of the low-voltage power units are reconstructed on the basis of this modulation strategy. The principle of carrier reconstruction for the low-voltage power unit is as Figure 5 shown, Figure 5 (a) in is the waveform of the traditional carrier signal, Figure 5 and (b) in is the waveform of the reconstructed carrier signal.

[0113] Assume that the single triangular wave signal period of the carrier is T CR , and the frequency is f CR . The working period of the carrier signal before reconstruction is T C2+ , T C3+ , and the frequency is f C2+ , f C3+, the duty cycle of the reconstructed carrier signal is 、 , the frequency is 、 , the period of the improved modulation wave signal of the low-voltage power unit is T , the frequency is f .

[0114] Starting from time 0, every T CR time, v C2+ and v C3+ the waveform positions are interchanged to obtain the waveform of the reconstructed carrier signal 、 . The duty cycle of the reconstructed carrier signal is twice that of the original carrier signal, and the relationship between its period and frequency can be expressed as:

[0115] (4);

[0116] In the formula, and are the period and frequency of a single triangular wave signal of the carrier respectively, and are the duty cycles of the original carrier signal, and are the frequencies of the original carrier signal, and are the duty cycles of the reconstructed carrier signal, and are the frequencies of the reconstructed carrier signal.

[0117] Define t on2+ 、 t on3+ as the times when the low-voltage power units L 2 、L 3 output voltage of level +E within a positive half-cycle respectively; t on2- 、 t on3- as the times when the low-voltage power units L 2 、L 3 output voltage of level -E within a negative half-cycle respectively; P 2+ 、 P 3+ as the average output powers of the low-voltage power units L 2 、L 3 within a positive half-cycle respectively; P 2- 、P 3- are the low-voltage power units L 2 、L 3 The average output power within a negative half-cycle. The modulation schematic diagram of the low-voltage power unit after carrier reconstruction is as shown in Figure 6 Figure

[0118] Since the reconstructed carrier is completely rotationally symmetric in both the positive and negative half-cycles, that is, the voltage components u 2 、u 3 The waveforms are also completely symmetric about the midpoint in the positive or negative half-cycle. Therefore, the time expressions for the low-voltage power units L 2 、L 3 to output a voltage of +E level within a positive half-cycle and a voltage of -E level within a negative half-cycle are:

[0119] (5);

[0120] Since the amplitudes of the voltage components u 2 、u 3 are both E, combining with Equation (5), the average voltage output by the low-voltage power units L 2 、L 3 within a positive half-cycle, a negative half-cycle, that is, is:

[0121] (6);

[0122] In the formula, 、 are the average voltages output by the low-voltage power unit L 2 in the positive and negative half-cycles respectively, 、 are the average voltages output by the low-voltage power unit L 3 in the positive and negative half-cycles respectively.

[0123] The low-voltage power units L 2 、L 3 of the inverter are in a series structure. When outputting the same level, the power supplies E 2 、E 3 alternate in operation, and the magnitude and direction of the output current are the same. Therefore, the average output active powers of the low-voltage power units L 2 、L 3 within a positive half-cycle and a negative half-cycle are equal, and their expression is:

[0124] (7);

[0125] Compared with the IHLS-PWM modulation strategy, by reconstructing the carrier wave of the low-voltage power unit, the low-voltage power unit L 2 、L 3 After the series superposition, the output voltage component u 2+3 The waveform remains unchanged after the carrier wave reconstruction, and the switching signals of some switching devices are further optimized, reducing the switching frequency gap of some switching tubes during the operation of the low-voltage power unit again. Through the carrier wave reconstruction, power balance is achieved for each low-voltage power unit within 1 / 4 of a fundamental wave period.

[0126] On the basis of reconstructing the carrier wave of the low-voltage power unit L 2 、L 3 to achieve power balance between low-voltage power units, by controlling the conduction angle 1 of the switching tube of the high-voltage power unit H , to achieve power balance between the high- and low-voltage power units, the modulation principle between the high- and low-voltage power units controlling the conduction angle is as Figure 7 shown.

[0127] According to Figure 7 it can be known that the conduction angle of the switching tube is related to the modulation degree m a . From Figure 7 the control signal of the conduction angle output by the first DC voltage source can be deduced, and are respectively:

[0128] (8);

[0129] In the formula, and are the control signals, is the modulation degree, is the conduction angle.

[0130] Define the control signal of the output voltage component of the high-voltage power unit H 1 as v 1 , v 1 is a square wave. When the modulation degree , the v 1 Fourier decomposition expression of the control signal of the output voltage component of the first DC voltage source is:

[0131] (9);

[0132] Define the control signal of the output voltage after the superposition of the low-voltage power units L 2 、L 3 asv 2+3 , v 2+3 It is a segmented mixed waveform. When the second DC voltage source and the third DC voltage source are superimposed, the control signal of the output voltage is The Fourier decomposition expression of is:

[0133] (10).

[0134] According to formula (1), the output voltage can be obtained u AN Fundamental u AN(1) The expression is:

[0135] (11);

[0136] According to formula (9), the high-voltage power unit H 1 Output voltage component u 1 Fundamental u 1(1) The expression is:

[0137] (12);

[0138] According to formula (10), the low voltage power unit L 2 , L 3 Output voltage u after superposition 2+3 The fundamental wave u 2+3(1) The expression is:

[0139] (13);

[0140] In the adjustment system When the modulation index is 100,000, the carrier reconstruction technology is used between the low-voltage power units to achieve power balance between the low-voltage power units; When the output voltage fundamental wave of the high-voltage power unit and the low-voltage power unit is superimposed, the magnitude is equal, that is, u 1(1) =u 2+3(1) =0.5u AN(1) , power balance between high and low voltage power units can be achieved.

[0141] Combining formula (11), formula (12) and formula (13), we can get the conduction angle Modulation The relationship is:

[0142] (14);

[0143] Conduction angle of the switching tube under power balance and modulation depth The relationship curve is as Figure 8 shown.

[0144] Based on the IHLS-PWM modulation strategy, this scheme proposes an improved IHLS-PWM modulation strategy for power balance. This modulation strategy uses carrier reconstruction between low-voltage power units and controls the conduction angle of the high-voltage power unit H 1 switching tube method to achieve power balance among all power units of the inverter under full modulation depth. According to Figure 6 and Figure 7 it can be seen that power balance is achieved among low-voltage power units and between high- and low-voltage power units within 1 / 4 fundamental wave period, further reducing the switching loss gap of some switching tubes and effectively improving the safety and reliability of the inverter operation.

[0145] According to Figure 7 the output voltage waveform u of the inverter in AN and Figure 2 the relationship diagram between the output level and the switching state combination of the inverter in, under the condition of the power balance IHLS-PWM modulation strategy, the pulse signals A 1 ~A 12 for controlling all output levels of the inverter can be obtained, as Figure 9 shown. Among them, A 1 ~A 3 are the pulse signals for outputting E 1 , E 2 , E 3 levels respectively; A 4 is the pulse signal corresponding to the output zero level; A 5 ~A 8 are the pulse signals corresponding to the output -E~ -4E levels respectively; A 9 ~A 12 are the pulse signals corresponding to the output +E~ +4E levels respectively.

[0146] The inverter has two output modes of E 2 , E 3 when outputting "±E" levels; it has two output modes of "E 1 , E 2 +E 3 " when outputting "±2E" levels; it has two output modes of "E 1 +E 2 , E 1 +E 3 " when outputting "±3E"; it has "E 1 +E 2 +E3 "An output mode."

[0147] The pulse signal of the on - state combination of the switching tubes within a complete fundamental wave period is as Figure 10 shown, where "S x1，x2，… (x 1 is 1 or 2, …, or 10; x 2 is 1 or 2, …, or 10; …)" represents that the switching tubes in the on - state for the corresponding output level are the x 1 th switching tube and the x 2 th switching tube. All redundant switching state combinations are used for non - zero levels, and the switching state combination of S 1 , 2 i.e., the combination of the first switching tube and the second switching tube, is selected for zero level. From Figure 10 it can be obtained that the logical expression of the pulse signal of the switching tubes S 1 ~ S 10 in the on - state is as the following formula (15):

[0148] (15);

[0149] For easy understanding, refers to the non - of the pulse signal A 1 of the level. When the pulse signal A 1 is at a high level, is at a low level; when the pulse signal A 1 is at a low level, is at a high level.

[0150] To further verify the feasibility of the novel nine - level inverter topology and its power - balanced IHLS - PWM modulation strategy, the inverter is simulated and analyzed using Matlab2018b / Simulink. The simulation parameters are set as shown in Table 1 below.

[0151] Table 1

[0152]

[0153] Figure 11 are the simulation waveforms of the output voltage components of each power unit of the inverter when using the traditional HLS - PWM modulation strategy under different modulation degrees. When the modulation degree is 0.3, the waveform of the output voltage component u 1 of the high - voltage power unit H1 fluctuates near zero, that is, it does not participate in the operation of the inverter output. The output voltage components u 2 of the low - voltage power units L 3 , L 2 , u 3The waveforms are all three-level PWM waves, but there are significant differences in the pulse widths and frequencies of the waveforms; when the modulation index is 0.6 and 0.9, the waveform of u1 is a symmetric square wave, u 2 、u 3 The waveforms are always three-level PWM waves with significant frequency differences. When the modulation index changes from "0.3 → 0.6 → 0.9", the number of output voltage levels of the inverter is a PWM wave that changes from "5 → 7 → 9". The voltage peak value of the nine-level waveform is approximately 311V, and the effective value is approximately 220V. The time for it to output a complete waveform is 0.02s.

[0154] Figure 12 are the simulation waveforms of the output voltage components of each power unit when the inverter adopts the power-equalizing IHLS-PWM modulation strategy under different modulation indices. When the modulation indices are 0.3, 0.6, and 0.9, the output voltage component u 1 of the high-voltage power unit H 1 The waveforms are all symmetric square waves and all participate in the output work of the inverter; the low-voltage power units L 2 、L 3 The output voltage components u 2 、u 3 The waveforms are all three-level PWM waves, and the pulse widths and frequencies of the waveforms are basically the same. When the modulation index changes from "0.3 → 0.6 → 0.9", the number of output voltage levels of the inverter is a PWM wave that changes from "5 → 7 → 9".

[0155] Figure 13 are the simulation waveforms of the output powers of each power unit when the inverter adopts the traditional HLS-PWM modulation strategy under different modulation indices. As shown in the figure, at the same modulation index, the ratio of the output powers of each power unit is far from the ratio of the corresponding power supply voltages, and power equalization cannot be achieved among the power units under different modulation indices.

[0156] Figure 14 are the simulation waveforms of the output powers of each power unit when the inverter adopts the power-equalizing IHLS-PWM modulation strategy under different modulation indices. At the same modulation index, the instantaneous output power waveforms of the low-voltage power units L2 and L3 are consistent. Under different modulation indices, the ratio of the output powers among the power units is basically the same as the ratio of the corresponding power supply voltages, achieving power equalization.

[0157] From Figure 15 (a) in it can be seen that under the traditional HLS-PWM modulation strategy condition of the inverter, there are always significant differences in the average output powers of each power unit under different modulation indices. When the modulation index < 0.5, the high-voltage power unit H 1 has no power output; from Figure 15As can be seen from (b) in [reference], under the condition of the power balance IHLS-PWM modulation strategy of the inverter, the low-voltage power unit L 2 and L 3 have basically the same average output power curve, and the average output power curves of each power unit satisfy P 1 :P 2 :P 3 =2:1:1 power balance condition, that is, the power balance among each power unit is achieved under the full modulation degree.

[0158] Figure 16 In (a) of [reference] and Figure 16 In (b) of [reference] are the output voltage spectrum diagrams of the inverter when adopting two modulation strategies respectively. Under the two modulation strategies, the fundamental amplitude of the output voltage of the inverter is positively correlated with the modulation degree, and the total harmonic distortion THD value of the output voltage is negatively correlated with the modulation degree. The main harmonic frequencies of the output voltage of the inverter under the two modulation strategies are concentrated around 5 kHz and its vicinity, and a low THD can be maintained under the full modulation degree, indicating that the output voltage of the inverter has good harmonic characteristics under the two modulation strategies.

[0159] Figure 17 is the relationship curve between the output voltage THD of the inverter and the modulation degree under the two modulation strategies. According to Figure 16 and Figure 17 it can be known that within the full modulation degree range, the output voltage THD of the inverter under the two modulation strategies is basically the same; moreover, the inverter adopts the power balance IHLS-PWM modulation strategy to achieve the power balance of each power unit under the full modulation degree.

[0160] To further verify the feasibility of the novel nine-level inverter topology and its power balance IHLS-PWM modulation strategy, experiments were carried out by building an experimental prototype of the inverter. The parameters of the experimental prototype are shown in Table 2. The inverter was experimented under the conditions that the modulation degree ma is 0.9 and 0.6 respectively.

[0161] Table 2

[0162]

[0163] Modulation degree When it is 0.9 and 0.6, the output voltage u AN waveform, current i AN waveform and the output voltage harmonic spectrum are as shown in Figure 18 . The output voltage is a stepped wave and the output current is approximately a sine wave. When =0.9, the number of output levels is 9, the peak value of the output voltage is 48 V, and the peak value of the output current is 0.9 A; When = 0.6, the number of output levels is 7, the peak output voltage is 36V, and the peak output current is 0.6A. The main harmonic frequencies of the output voltage are concentrated around 5kHz and its vicinity, and the harmonic distribution pattern is near integer multiples of the carrier frequency f CR nearby.

[0164] Figure 19 For each power unit at the modulation depth Figures (a) and (b) in are the waveforms of the output voltage components of each power unit under the conditions of modulation depths of 0.9 and 0.6 respectively. At different modulation depths, the high-voltage power unit H1 operates at the fundamental frequency and the waveform of the output voltage component is a symmetric square wave; the waveforms of the output voltage components of the low-voltage power units L2 and L3 are both three-level PWM waves, and their frequencies are basically the same.

[0165] Figure 20 in (a) and Figure 20 in (b) are the waveforms of the output power of each power unit under the modulation depths of 0.9 and 0.6 respectively. When = 0.9, the average powers output by the power units H1, L2, and L3 in one cycle are 9.419W, 4.684W, and 4.723W respectively; When = 0.6, the average powers are 4.094W, 2.051W, and 2.002W respectively. Under the two modulation depths, the output power ratios of each power unit basically satisfy 2:1:1, that is, power balance among each power unit is achieved.

[0166] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope recorded in this specification.

[0167] The above-described embodiments only represent several implementation manners of the present application. The description is relatively specific and detailed, but it cannot be understood as a limitation to the scope of the invention patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several deformations and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A nine-level inverter topology structure, characterized in that: It includes a load end, a first DC voltage source, a second DC voltage source and a third DC voltage source, wherein the output voltage ratio among the first DC voltage source, the second DC voltage source and the third DC voltage source is 2:1:1; The nine-level inverter topology structure further includes a first switch tube provided between the negative electrode of the second DC voltage source and the positive electrode of the load end, a second switch tube provided between the negative electrode of the second DC voltage source and the negative electrode of the load end, a third switch tube provided between the negative electrode of the first DC voltage source and the positive electrode of the load end, a fourth switch tube provided between the negative electrode of the first DC voltage source and the negative electrode of the load end, a fifth switch tube provided between the negative electrode of the third DC voltage source and the positive electrode of the load end, a sixth switch tube provided between the negative electrode of the third DC voltage source and the negative electrode of the load end, a seventh switch tube provided between the positive electrode of the third DC voltage source and the positive electrode of the load end, and an eighth switch tube provided between the positive electrode of the third DC voltage source and the negative electrode of the load end; The third switch tube, the fourth switch tube, the fifth switch tube and the sixth switch tube each include a switch tube body, a first power diode and a second power diode arranged on the emitter side of the switch tube body, and a third power diode and a fourth power diode arranged on the collector side of the switch tube body; the switch tube body, the first power diode, the second power diode, the third power diode and the fourth power diode constitute a bidirectional current switch; The nine-level inverter topology structure further includes a ninth switch tube provided between the positive electrode of the first DC voltage source and the negative electrode of the third DC voltage source, and a tenth switch tube provided between the positive electrode of the second DC voltage source and the negative electrode of the third DC voltage source, wherein the negative electrode of the first DC voltage source is connected to the positive electrode of the second DC voltage source; The emitter of the first switch tube and the emitter of the second switch tube are connected to the negative electrode of the second DC voltage source, the collector of the first switch tube is connected to the positive electrode of the load end, the collector of the second switch tube is connected to the negative electrode of the load end, the collector of the seventh switch tube and the collector of the eighth switch tube are connected to the positive electrode of the third DC voltage source, the emitter of the seventh switch tube is connected to the positive electrode of the load end, and the emitter of the eighth switch tube is connected to the negative electrode of the load end.

2. The nine-level inverter topology structure according to claim 1, characterized in that: The first switch tube, the second switch tube, the seventh switch tube, the eighth switch tube, the ninth switch tube, and the tenth switch tube are all insulated gate bipolar transistors.

3. The nine-level inverter topology structure according to claim 1, characterized in that: The output level u1 of the first DC voltage source is: 0, -2E and +2E; the output level u2 of the second DC voltage source is: 0, -E and +E; the output level u3 of the third DC voltage source is: 0, -E and +E, where E is the unit output level; The output voltage u at the load end AN Satisfy:u AN =(u1+u2+u3)= .

4. A modulation method for a nine-level inverter topology structure, characterized in that: For modulating the output voltage of the nine-level inverter topology structure according to any one of claims 1 to 3, the method comprising: The output of the first DC voltage source is modulated by a step wave, and the output of the second DC voltage source and the third DC voltage source are modulated by a carrier stacking wave; The expression of the first modulation wave output by the first DC voltage source is: ； In the formula, is the first modulation wave output by the first DC voltage source, To adjust the system, is the fundamental angular frequency, is the time variable; The expression of the second modulation wave output by the second DC voltage source and the third DC voltage source is: ； In the formula, It is the second modulation wave output by the second DC voltage source or the third DC voltage source.

5. The modulation method of the nine-level inverter topology structure according to claim 4, characterized in that: The modulation method further comprises: On the basis of adopting carrier stacking modulation for the second DC voltage source and the third DC voltage source, reducing the number of carrier signals of the second DC voltage source and the third DC voltage source, and outputting a target modulated wave signal; Among them, the expression of the target modulation wave signal is: ； In the formula, is the target modulation wave signal.

6. The modulation method of the nine-level inverter topology structure according to claim 5, characterized in that: The modulation method further comprises: Reconstructing the carrier and controlling the conduction angle of the first DC voltage source output to achieve power balance among the first DC voltage source, the second DC voltage source, and the third DC voltage source within a quarter of the fundamental wave period; The carrier wave includes a first waveform and a second waveform, and the step of reconstructing the carrier wave specifically includes: The positions of the first waveform and the second waveform are interchanged every single triangular wave signal period, so that the working period of the carrier after reconstruction is twice that before reconstruction; The relationship between the duty cycle and frequency before and after the carrier reconstruction is expressed as follows: ； In the formula, and are the single triangle wave signal period and frequency of the carrier respectively, and are the duty cycles of the carrier signals of the first waveform and the second waveform before reconstruction, and are the frequencies of the carrier signals of the first waveform and the second waveform before reconstruction, and are the duty cycles of the carrier signals of the reconstructed first waveform and the second waveform, respectively, and are the frequencies of the carrier signals of the reconstructed first waveform and second waveform respectively.

7. The modulation method of the nine-level inverter topology structure according to claim 6, characterized in that: The expression of the control signal of the conduction angle output by the first DC voltage source is as follows: ； In the formula, and is the control signal, To adjust the system, is the conduction angle.

8. The modulation method of the nine-level inverter topology structure according to claim 7, characterized in that: The expression of the control signal of the output voltage component of the first DC voltage source is: ； In the formula, represents the control signal of the voltage component output by the first DC voltage source when the time variable is t, and n is the harmonic order; The expression of the fundamental wave of the output voltage component of the first DC voltage source is: ； In the formula, It represents the fundamental wave of the voltage component output by the first DC voltage source when the time variable is t, and E is the unit output level.

9. The modulation method of the nine-level inverter topology structure according to claim 8, characterized in that: The expression of the control signal of the output voltage after the second DC voltage source and the third DC voltage source are superimposed is: ； In the formula, represents a control signal of a voltage component outputted by the second DC voltage source and the third DC voltage source after superposition when the time variable is t; The expression of the fundamental wave of the output voltage component after the second DC voltage source and the third DC voltage source are superimposed is: ； In the formula, It represents the fundamental wave of the output voltage component after the second DC voltage source and the third DC voltage source are superimposed when the time variable is t.

10. The modulation method of the nine-level inverter topology structure according to claim 9, characterized in that: In the power balance state, the relationship between the conduction angle and the modulation degree is: 。

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