Internal soft start circuit

Abstract

The invention belongs to the field of integrated circuits, and relates to an internal soft start circuit which comprises an integral amplification circuit and a ring oscillator circuit. The integral amplification circuit comprises four NMOS (N-channel metal oxide semiconductor) tubes M1 to M4, two capacitors C2 to C3 and an amplifier; grid electrodes of the M1 and the M3 are connected to a clock signal first output end of the ring oscillator circuit, a source electrode of the M1 is connected with the ring oscillator circuit, and a drain electrode of the M1 is respectively connected with a drain electrode of the M2 and a positive electrode of the C2; grid electrodes of the M2 and the M4 are connected to a second clock signal output end of the ring oscillator circuit, and a source electrode of the M2 is grounded; the negative electrode of the C2 is respectively connected with the drain electrode of the M3 and the source electrode of the M4; the source electrode of the M3 is grounded; the drain electrode of the M4 is respectively connected to the negative electrode input end of the amplifier and the positive electrode of the C3; the anode input end of the amplifier is grounded, and the output end C3 of the amplifier is connected with the cathode and serves as the output end of the integral amplification circuit; the soft start time is greatly prolonged under the condition that the charging current is not excessively reduced.

Description

Technical Field

[0001] The invention belongs to the field of integrated circuits, and in particular relates to an internal soft start circuit. Background Art

[0002] The internal soft start circuit is a circuit that controls the voltage and current of the power supply output through electronic components, so that the motor can accelerate smoothly when starting to avoid impact and damage. It is usually integrated into the motor control device, such as the soft starter, and has functions such as soft start, soft stop, light load energy saving and multi-function protection; in the power management chip, the internal soft start circuit is used to provide a longer internal soft start circuit and save the internal capacitor area.

[0003] The existing internal soft start circuit is as follows Figure 1 As shown, a conventional voltage reference circuit with a wide input voltage range is provided, and its structure includes a constant current source Idc and a capacitor C. The principle is that the capacitor is charged by the constant current source so that the SS output voltage VOUT continues to rise and finally reaches the internal start-up voltage. The final SS output voltage VOUT formula is: V OUT =I·t / C; I is the current generated by the constant current source.

[0004] According to the above prior art, it can be known that the traditional soft start circuit can only make the soft start time very long (more than ms) by making the charging current very small or the capacitor very large. If the current is too small, the internal MOS tube will not be fully turned on, and if the capacitor is too large, the chip area will be consumed. It cannot be used in fields that require a long internal soft start time. Summary of the invention

[0005] In order to solve the problems existing in the above prior art, the present invention proposes an internal soft start circuit, the circuit structure of which includes: an integral amplifier circuit and a ring oscillator circuit, the integral amplifier circuit is used to output a signal, and the ring oscillator circuit is used to generate a clock signal and a triangular pulse signal; the integral amplifier circuit includes four NMOS tubes M1-M4, two capacitors C2-C3 and an amplifier AMP; the gate of M1 is connected to the first output terminal of the clock signal of the ring oscillator circuit, the source of M1 is connected to the ring oscillator circuit, and the drain of M1 is respectively connected to the drain of M2 and the positive electrode of the capacitor C2; The gate of M2 is connected to the second output terminal of the clock signal of the ring oscillator circuit, and the source of M2 is grounded; the negative electrode of capacitor C2 is respectively connected to the drain of M3 and the source of M4; the gate of M3 is connected to the first output terminal of the clock signal of the ring oscillator circuit, and the source of M3 is grounded; the gate of M4 is connected to the second output terminal of the clock signal of the ring oscillator circuit, and the drain of M4 is respectively connected to the negative input terminal of the amplifier AMP and the positive electrode of capacitor C3; the positive input terminal of the amplifier AMP is grounded, and the output terminal of the amplifier AMP is connected to the negative electrode of capacitor C3, and serves as the output terminal of the integrating amplifier circuit.

[0006] Beneficial effects of the present invention:

[0007] The present invention cleverly applies a switched capacitor integral amplifier circuit in a soft start circuit, so that the soft start time is increased compared with a traditional soft start circuit, thereby significantly extending the soft start time without excessively reducing the charging current; the circuit structure of the present invention is simple and can reduce the occupied area of ​​the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order to make the purpose, technical solution and beneficial effects of the present invention clearer, the present invention provides the following drawings for illustration:

[0009] Figure 1 A conventional soft start circuit;

[0010] Figure 2 The internal soft start circuit of the present invention;

[0011] Figure 3 The internal voltage waveform of the ring oscillator of the present invention;

[0012] Figure 4 The internal soft-start voltage curve of the present invention. DETAILED DESCRIPTION

[0013] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0014] An internal soft-start circuit, such as Figure 2 As shown, the circuit structure includes an integral amplifier circuit and a ring oscillator circuit. The integral amplifier circuit is used to output a signal, and the ring oscillator circuit is used to generate a clock signal and a triangular pulse signal.

[0015] In this embodiment, the integration amplifier circuit includes four NMOS tubes M1-M4, two capacitors C2-C3 and an amplifier AMP; the gate of M1 is connected to the first output terminal of the clock signal of the ring oscillator circuit, the source of M1 is connected to the ring oscillator circuit, and the drain of M1 is respectively connected to the drain of M2 and the positive electrode of the capacitor C2; the gate of M2 is connected to the second output terminal of the clock signal of the ring oscillator circuit, and the source of M2 is grounded; the negative electrode of the capacitor C2 is respectively connected to the drain of M3 and the source of M4; the gate of M3 is connected to the first output terminal of the clock signal of the ring oscillator circuit, and the source of M3 is grounded; the gate of M4 is connected to the second output terminal of the clock signal of the ring oscillator circuit, and the drain of M4 is respectively connected to the negative input terminal of the amplifier AMP and the positive electrode of the capacitor C3; the positive input terminal of the amplifier AMP is grounded, and the output terminal of the amplifier AMP is connected to the negative electrode of the capacitor C3 and serves as the output terminal of the integration amplifier circuit.

[0016] The ring oscillator circuit includes a constant current source Idc, an NMOS tube M0, a capacitor C1, a comparator CMP, a hysteresis inverter INV1, a pass gate BUF, a D flip-flop DFF, an inverter INV2 and two NAND gates NAND1-NAND2; the positive electrode of the constant current source Idc is connected to the power supply VDD, and the negative electrode of the constant current source Idc is respectively connected to the positive electrode of the capacitor C1, the negative input terminal of the comparator CMP, the drain of M0 and the source of the amplifier circuit M1; the negative electrode of the capacitor C1 is grounded; the source of M0 is grounded, and the gate of M0 is connected to the output terminal of the pass gate BUF; the positive input terminal of the comparator CMP is connected to the VREF voltage, and the output terminal of the comparator CMP is connected to the positive input terminal of the hysteresis inverter INV1. The output end of the hysteresis inverter INV1 is respectively connected to the input end of the pass gate BUF and the input end of the D flip-flop DFF; the output end of the D flip-flop DFF is respectively connected to the first input end of the NAND gate NAND1 and the input end of the inverter INV2; the output end of the inverter INV2 is connected to the second input end of the NOT gate NAND2; the second input end of the NOT gate NAND1 is connected to the output end of the NOT gate NAND2, the output end of the NOT gate NAND1 is connected to the first input end of the NOT gate NAND2, and the output end of the NOT gate NAND1 serves as the first output end S1 of the clock signal of the ring oscillator circuit, and the output end of the NOT gate NAND2 serves as the second output end S2 of the clock signal of the ring oscillator circuit.

[0017] The principle of the present invention is: Figure 2 As shown, the structure of the present invention consists of two parts: a ring oscillator and an integrating amplifier circuit.

[0018] Regarding the ring oscillator circuit, the power supply VDD, the constant current source Idc, the NMOS tube M0, the capacitor C1, the comparator CMP, the hysteresis inverter INV1, the pass gate BUF, the D flip-flop DFF, the inverter INV2, and the NAND gates NAND1 and NAND2 together constitute a ring oscillator circuit, which provides a clock pulse signal and a triangular pulse signal for the integral amplifier circuit, point A generates a triangular pulse signal, S1 and S2 generate clock pulse signals, and S1 and S2 have the same period but opposite phases.

[0019] The constant current source Idc charges the capacitor C1, and the voltage at point A rises. When it reaches the VREF voltage, the CMP output changes from a high level to a low level. After being shaped by the hysteresis inverter and BUF, the high level is output to the M0 gate. The M0 tube is turned on, and the charge on C1 is discharged. The voltage at point A drops rapidly to a low level, and finally a periodic triangular pulse is generated at point A. The output of INV1 is extended by one cycle through the DFF trigger and output as a pulse square wave with the same high and low level time. After passing through the inverter and the NOR gate, the S1 and S2 clock pulse signals are finally output. S1 and S2 have the same cycle but opposite phases. Figure 3 Figure 2 is the waveform diagram of point A, S1 and S2 of the ring oscillator.

[0020] Regarding the integral amplifier circuit, the integral amplifier circuit is composed of NMOS switches M1 to M4, capacitors C2 and C3, an amplifier AMP and GND, and finally generates a slowly rising soft-start output voltage VOUT.

[0021] When S1 is high level, S2 is low level, then M1 and M3 MOS tubes are turned on, M2 and M4 MOS tubes are turned off, the voltage at point A is transferred to point B through M1 tube, and the charge accumulated at point B during the pulse rising period is:

[0022]

[0023] Where T is one cycle of S1 and S2, and also two cycles of the pulse at point A; I is the magnitude of the input current; ΔV B is the voltage that rises at point B when S1 is closed in one cycle, and C1 is the capacitance of capacitor C1.

[0024] At this time, the voltage at point C is 0. When S1 is low level, S2 is high level, at this time, M1 and M3 MOS tubes are turned off, and M2 and M4 MOS tubes are turned on. The voltage at point B is short-circuited to 0. Since the charge at both ends of capacitor C2 cannot change suddenly, the voltage at point C drops to a negative voltage, and the reduced voltage is:

[0025]

[0026] Where, ΔV C is the voltage drop at point C.

[0027] The gain of the amplifier AMP in the integral amplifier circuit is:

[0028] A v =ΔV OUT / ΔV D =-C2 / C3

[0029] Among them, A v is the gain of the amplifier AMP, ΔV OUT The voltage added by the soft-start output during one cycle, ΔV D is the change (voltage reduction) of the negative input terminal of the AMP amplifier within one cycle, C2 is the capacitance of capacitor C2, and C3 is the capacitance of capacitor C3.

[0030] SS output voltage V OUT for:

[0031]

[0032] The final soft start time is:

[0033]

[0034] Among them, V OUT is the output signal of the internal soft start circuit, C1 is the capacitance of capacitor C1, C2 is the capacitance of capacitor C2, C3 is the capacitance of capacitor C3, and I is the input current.

[0035] Traditional soft start circuit, If the soft start time is to be longer than ms, the capacitor needs to be nF level or the charging current needs to be higher than 100μA, which greatly increases the chip area or circuit power consumption.

[0036] The present invention cleverly applies the switch capacitor integral amplifier circuit in the soft start circuit, which increases the soft start time by 10% compared with the traditional soft start circuit. times, the soft start time can be greatly increased by simply increasing the ratio of capacitor C3 to capacitor C2.

[0037] Figure 4 This is the internal soft start voltage curve of the present invention, wherein the capacitance of C1 is 2.52pF, the capacitance of C2 is 53fF, the capacitance of C3 is 10.43pF, the charging current of C1 is about 0.29μA, and the internal soft start time reaches about 4.6ms.

[0038] The internal soft start circuit of the present invention is widely used in integrated circuits, especially in power management chips, to provide an internal soft start circuit for a relatively long time and greatly save the internal capacitor area.

[0039] The above embodiments further illustrate the purpose, technical solutions and advantages of the present invention in detail. It should be understood that the above embodiments are only preferred implementation modes of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made to the present invention within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. An internal soft start circuit, comprising: An integrating amplifier circuit and a ring oscillator circuit, wherein the integrating amplifier circuit is used for outputting signals, and the ring oscillator circuit is used for generating clock signals and triangular pulse signals; the integrating amplifier circuit comprises four NMOS tubes M1-M4, two capacitors C2-C3 and an amplifier AMP; the gate of M1 is connected to the first output terminal of the clock signal of the ring oscillator circuit, the source of M1 is connected to the ring oscillator circuit, and the drain of M1 is respectively connected to the drain of M2 and the positive electrode of the capacitor C2; the gate of M2 is connected to the second output terminal of the clock signal of the ring oscillator circuit, and the source of M2 is grounded; the negative electrode of the capacitor C2 is respectively connected to the drain of M3 and the source of M4; the gate of M3 is connected to the first output terminal of the clock signal of the ring oscillator circuit, and the source of M3 is grounded; the gate of M4 is connected to the second output terminal of the clock signal of the ring oscillator circuit, and the drain of M4 is respectively connected to the negative input terminal of the amplifier AMP and the positive electrode of the capacitor C3; the positive input terminal of the amplifier AMP is grounded, and the output terminal of the amplifier AMP is connected to the negative electrode of the capacitor C3, and serves as the output terminal of the integrating amplifier circuit.

2. An internal soft start circuit according to claim 1, characterized in that: The gain of the amplifier AMP in the integral amplifier circuit is: A v =ΔV OUT / ΔV D =-C2 / C3 Among them, A v is the gain of the amplifier AMP, ΔV OUT The voltage added by the soft-start output during one cycle, ΔV D is the change of the negative input terminal of the AMP amplifier within one cycle, C2 is the capacitance of capacitor C2, and C3 is the capacitance of capacitor C3.

3. An internal soft start circuit according to claim 2, characterized in that: The capacitance of capacitor C2 is 53fF, and the capacitance of capacitor C3 is 10.43pF.

4. An internal soft start circuit according to claim 1, characterized in that: The ring oscillator circuit includes a constant current source Idc, an NMOS tube M0, a capacitor C1, a comparator CMP, a hysteresis inverter INV1, a pass gate BUF, a D flip-flop DFF, an inverter INV2 and two NAND gates NAND1-NAND2; the positive electrode of the constant current source Idc is connected to the power supply VDD, and the negative electrode of the constant current source Idc is respectively connected to the positive electrode of the capacitor C1, the negative input terminal of the comparator CMP, the drain of M0 and the source of the amplifier circuit M1; the negative electrode of the capacitor C1 is grounded; the source of M0 is grounded, and the gate of M0 is connected to the output terminal of the pass gate BUF; the positive input terminal of the comparator CMP is connected to the VREF voltage, and the output terminal of the comparator CMP is connected to the positive input terminal of the hysteresis inverter INV1. The output end of the hysteresis inverter INV1 is respectively connected to the input end of the pass gate BUF and the input end of the D flip-flop DFF; the output end of the D flip-flop DFF is respectively connected to the first input end of the NAND gate NAND1 and the input end of the inverter INV2; the output end of the inverter INV2 is connected to the second input end of the NOT gate NAND2; the second input end of the NOT gate NAND1 is connected to the output end of the NOT gate NAND2, the output end of the NOT gate NAND1 is connected to the first input end of the NOT gate NAND2, and the output end of the NOT gate NAND1 serves as the first output end S1 of the clock signal of the ring oscillator circuit, and the output end of the NOT gate NAND2 serves as the second output end S2 of the clock signal of the ring oscillator circuit.

5. An internal soft start circuit according to claim 4, characterized in that: The positive electrode of capacitor C1 in the ring oscillator circuit generates a triangular pulse signal.

6. An internal soft start circuit according to claim 5, characterized in that: The capacitance of capacitor C1 is 2.52pF.

7. An internal soft start circuit according to claim 4, characterized in that: The clock signals generated by the first clock signal output terminal S1 and the second clock signal output terminal S2 have the same period but opposite phases.

8. An internal soft start circuit according to claim 1, characterized in that: The soft start time of the internal soft start circuit is: Among them, V OUT is the output signal of the internal soft-start circuit, ΔV OUT is the voltage increased by the soft start output within one cycle, T is one cycle of the clock signal, C1 is the capacitance of capacitor C1, C2 is the capacitance of capacitor C2, C3 is the capacitance of capacitor C3, and I is the input current.

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