Analog front-end circuit and offset voltage correction method thereof

Abstract

The invention provides an analog front-end circuit and an offset voltage correction method. The offset voltage correction method comprises the following steps: acquiring a first offset voltage generated by a differential input pair of a first amplifier in the analog front-end circuit, and generating first information according to the first offset voltage; acquiring a second offset voltage of a tail current source of the first amplifier in the analog front-end circuit, and generating second information according to the second offset voltage and the first information; obtaining a predetermined first direct current gain and a predetermined second direct current gain, and performing arithmetic operation according to the first direct current gain, the second direct current gain, the first information and the second information to generate first compensation information; and correcting the output voltage generated by the first amplifier according to the first compensation information.

Description

Technical Field

[0001] The present invention relates to an analog front-end circuit and a method for correcting its offset voltage, and in particular to an analog front-end circuit capable of saving circuit area and a method for correcting its offset voltage. Background Art

[0002] There are two common methods for correcting the offset voltage of analog front end (AFE) circuits. One method can be applied to analog front end circuits with programmable capabilities to correct the offset voltage by programming various gain settings. This method usually takes a long time to train each gain setting, which reduces the training speed of the circuit.

[0003] Another method can be applied to analog front-end circuits that do not have programmable capabilities. The test machine performs correction operations on the analog front-end circuit corresponding to various gain settings of the offset voltage, and generates multiple corresponding correction codes, so that the analog front-end circuit performs correction operations according to the correction codes. This method requires a long test time before the chip leaves the factory, resulting in an increase in test costs. In addition, this method will generate a large number of correction codes, and a large amount of storage space is required to store the correction codes, resulting in a waste of circuit area. Summary of the invention

[0004] The invention is directed to an analog front-end circuit and a correction method for its offset voltage, which can reduce the area required for the circuit.

[0005] According to an embodiment of the present invention, a method for correcting an offset voltage is applicable to an analog front-end circuit. The method for correcting an offset voltage includes: obtaining a first offset voltage generated by a differential input transistor pair of a first amplifier in the analog front-end circuit, and generating first information according to the first offset voltage; obtaining a second offset voltage generated by a tail current source of the first amplifier in the analog front-end circuit, and generating second information according to the second offset voltage and the first information; obtaining a predetermined first DC gain and a second DC gain, and generating first compensation information according to the first DC gain, the second DC gain, the first information, and the second information; and correcting the output voltage generated by the first amplifier according to the first compensation information.

[0006] According to an embodiment of the present invention, an analog front-end circuit includes a first amplifier, a first compensation circuit, and a compensation information generator. The first compensation circuit is coupled to the output end of the first amplifier, and corrects the first output voltage generated by the first amplifier according to the first compensation information. The compensation information generator is coupled to the first compensation circuit, and generates the first compensation information according to the first DC gain, the second DC gain, the first information, and the second information. The first information is generated according to the first offset voltage generated by the differential input transistor pair of the first amplifier, and the second information is generated according to the second offset voltage generated by the tail current source of the first amplifier. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 A flow chart of a method for correcting an offset voltage according to an embodiment of the present invention is shown.

[0008] Figure 2 Schematic diagram showing why offset voltage occurs in an amplifier.

[0009] Figure 3 A schematic diagram showing an analog front-end circuit according to an embodiment of the present invention is shown.

[0010] Figure 4 A schematic diagram showing a compensation information generator in an analog front-end circuit according to an embodiment of the present invention.

[0011] Figure 5 A schematic diagram showing an analog front-end circuit according to another embodiment of the present invention.

[0012] Figure 6 A flow chart showing a method for correcting an offset voltage according to an embodiment of the present invention is shown.

[0013] Figure 7 A circuit diagram showing an analog front end circuit according to another embodiment of the present invention.

[0014] Figure 8 A schematic diagram showing an implementation of a compensation information generating circuit of an analog front-end circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0015] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0016] Please refer to Figure 1 , Figure 1A flow chart of a method for correcting an offset voltage according to an embodiment of the present invention is shown. The method for correcting an offset voltage according to the present embodiment is applicable to an analog front-end circuit. The analog front-end circuit may be provided in a signal receiver, for example. The analog front-end circuit may include one or more amplifiers. In step S110, a first offset voltage generated by a differential input transistor pair of a first amplifier in the analog front-end circuit is obtained, and first information is generated according to the first offset voltage. Furthermore, in step S120, a second offset voltage generated by a tail current source of the first amplifier in the analog front-end circuit is obtained, and second information is generated according to the second offset voltage and the first information. Next, in step S130, a first DC gain and a second DC gain which are set in advance are obtained, and first compensation information is generated according to the first DC gain, the second DC gain, the first information and the second information. Furthermore, in step S140, the output voltage generated by the first amplifier is corrected according to the first compensation information.

[0017] For details on the above calibration method, please refer to Figure 2 , Figure 2 A schematic diagram of an amplifier of an embodiment of the present application is shown below. Figure 2 The causes of the first offset voltage and the second offset voltage are described below. Figure 2 In the embodiment, the amplifier 200 includes transistors T1 and T2, tail current sources It1, It2, a source resistor Rs and a load resistor RL. The transistors T1 and T2 form a differential input transistor pair, and the gates of the transistors T1 and T2 receive input signals Vin+ and Vin-, respectively. The tail current source It1 is coupled between the source of the transistor T1 and the reference ground terminal VSS, and the tail current source It2 is coupled between the source of the transistor T2 and the reference ground terminal VSS. The tail current source It1 is used to generate a tail current I1. The tail current source It2 is used to generate a tail current I2.

[0018] In addition, the amplifier 200 has a source resistor Rs. The source resistor Rs is coupled between the source of the transistor T1 and the source of the transistor T2. The source resistor Rs can be a variable resistor. The amplifier 200 also has a load resistor RL, which is coupled between the drain of the transistor T2 and the power supply terminal VPP. In this embodiment, the substrates of the transistors T1 and T2 are, for example, coupled to the reference ground terminal VSS.

[0019] The offset voltage of the amplifier 200 may come from its differential input transistor pair and from the tail current sources It1 and It2. The first offset voltage generated by the change in the threshold voltage of the transistors T1 and T2 (due to the change in the threshold voltage relative to the standard value caused by the process manufacturing adaptation) may be equal to Wherein, gm is the transconductance value of transistors T1 and T2, and Vth_mis is the change of the threshold voltage of transistors T1 and T2 relative to the standard value. It is related to the design structure of the circuit, while Vth_mis is related to the manufacturing process. In addition, the second offset voltage caused by the tail current sources It1 and It2 is equal to Where Imis is the change in the tail current. It is related to the design structure of the circuit, while Imis is related to the manufacturing process.

[0020] In this embodiment, Figure 1 The first DC gain value mentioned in the embodiment can be based on to determine, and the second DC gain value can be determined according to To determine. When the circuit structure is determined, the first DC gain and the second DC gain are fixed values. The overall offset voltage of the amplifier 200 can be equal to Pa1×Vos1+Pb1×Vos2, where Pa1 and Pb1 are the first DC gain and the second DC gain, respectively, and Vos1 and Vos2 are the first information and the second information, respectively. The first DC gain Pa1 and the second DC gain Pb1 can be calculated in advance after the design is completed. Pa1 and Pb1 are controlled by the amplifier gain setting digital code. Different gain settings correspond to different Pa1 and Pb1. The specific values ​​are determined and guaranteed by the design.

[0021] Please refer to the following Figure 3 , Figure 3 A schematic diagram of an analog front-end circuit of an embodiment of the present invention is shown. The analog front-end circuit 300 includes an amplifier 310 and a compensation circuit 320. The amplifier 310 includes transistors T1, T2, a source resistor Rs, a load resistor RL, a resistor R1, a capacitor C1, and tail current sources It1, It2. Transistors T1 and T2 constitute a differential input transistor pair. The tail current source It1 is coupled between the source of transistor T1 and the reference ground terminal VSS, and the tail current source It2 is coupled between the source of transistor T2 and the reference ground terminal VSS. The source resistor Rs is coupled between the source of transistor T1 and the source of transistor T2. The capacitor C1 is coupled in parallel with the source resistor Rs. In this embodiment, the source resistor Rs can be a variable resistor, and the capacitor C1 can be a variable capacitor.

[0022] In addition, the load resistor RL is coupled between the drain of the transistor T2 and the power supply terminal VPP, and the resistor R1 is coupled between the drain of the transistor T1 and the power supply terminal VPP. The coupling point between the resistor R1 and the transistor T1 can be used as the first output terminal of the amplifier 310, and the coupling point between the load resistor RL and the transistor T2 can be used as the second output terminal of the amplifier 310. The first output terminal and the second output terminal are output terminals that are opposite to each other, and together form a differential output signal.

[0023] The compensation circuit 320 is coupled to the first output terminal and the second output terminal. The compensation circuit 320 includes current sources IC1 and IC2. The current source IC1 is coupled between the first output terminal and the reference ground terminal VSS, and the current source IC2 is coupled between the second output terminal and the reference ground terminal VSS.

[0024] In this embodiment, the current source IC1 provides a first compensation current for the first output terminal of the amplifier 310 according to the first compensation information, and the current source IC2 provides a second compensation current for the second output terminal of the amplifier 310 according to the first compensation information. The compensation circuit 320 can compensate the output voltage of the amplifier 310 through the first compensation current and the second compensation current. Figure 1 It should also be noted that the embodiments of the present application are described using the current compensation method as an example, but those skilled in the art can understand that the present application can also use the voltage method for compensation, and the present application does not limit this.

[0025] Please refer to the following Figure 4 , Figure 4 A schematic diagram showing a compensation information generator in an analog front-end circuit according to an embodiment of the present invention is shown. Figure 4 In the embodiment, the compensation information generator 400 includes a memory 411, multipliers 412, 413 and an adder 414. The memory 411 is used to store the first information Vos1 and the second information Vos2. Figure 1 In the embodiment of the present invention, the first information Vos1 can be obtained according to the first offset voltage generated by the differential input transistor pair of the amplifier, and the second information Vos2 can be obtained according to the second offset voltage generated by the tail current source and the first information Vos1. The multipliers 412 and 413 are coupled to the memory 411. The multiplier 412 receives the first information Vos1 and the first DC gain Pa1, and multiplies the first information Vos1 and the first DC gain Pa1 to generate the first data D1. The multiplier 413 receives the second information Vos2 and the second DC gain Pa2, and multiplies the second information Vos2 and the second DC gain Pa2 to generate the second data D2.

[0026] The adder 414 is coupled to the multiplier 412 and the multiplier 413. The adder 414 adds the first data D1 and the second data D2 and generates the first compensation information CIF1. In this embodiment, the first compensation information CIF1 may be provided to Figure 3 The compensation circuit 320 of the embodiment includes current sources IC1 and IC2, and enables the current sources IC1 and IC2 to compensate the output voltage.

[0027] Please refer to the following Figure 5 , Figure 5 A schematic diagram of an analog front-end circuit of another embodiment of the present invention is shown. The analog front-end circuit 500 includes a first amplifier 510, a second amplifier 520, and a comparator 530. The second amplifier 520 is coupled to the input end of the first amplifier 510, and the comparator 530 is coupled to the output end of the first amplifier 510. In this embodiment, the second amplifier 520 can be a continuous time linear equalizer (CTLE), and the first amplifier 510 can be a variable gain amplifier (VGA).

[0028] Regarding the method for correcting the offset voltage of the analog front end circuit 500, please refer to Figure 6 An embodiment wherein Figure 6 The flowchart of the method for correcting the offset voltage of the embodiment of the present invention is shown. In step S610, the output of the first amplifier 510 can be short-circuited, and the output voltage of the comparator 530 can be corrected. Then, in step S620, the tail current provided by the tail current source of the second amplifier 520 can be turned off, and the source resistance of the first amplifier 510 can be short-circuited. Through this, the offset voltage contributed by the differential input transistor pair of the first amplifier 510 can be corrected. In step S620, the offset voltage contributed by the differential input transistor pair of the first amplifier 510 can be obtained, and the first information can be obtained according to the offset voltage.

[0029] In step S630, the sum of the offset voltage contributed by the differential input transistor pair of the first amplifier 510 and the offset voltage contributed by the tail current source can be obtained, and the offset voltage contributed by the tail current source can be obtained according to the offset voltage contributed by the differential input transistor pair obtained in step S620, and the second information can be obtained according to the offset voltage contributed by the tail current source and the first information. In this embodiment, the first information, the second information, the first DC gain, the second DC gain, the first compensation information, and the second compensation information can all be digital values ​​(for example, binary integers with signed bits) and can be written into any form of memory.

[0030] In step S640, the second amplifier 520 is started, and the input terminal of the second amplifier 520 is short-circuited, and the source resistance of the first amplifier is kept at a maximum value. Then, in step S650, the source resistance Rs of the second amplifier 520 is opened (i.e., the source resistance Rs circuit between the sources of the transistor T1 and the transistor T2 is disconnected), and the offset voltage contributed by the tail current source of the second amplifier 520 is corrected. The third information can be obtained according to the offset voltage contributed by the tail current source of the second amplifier 520 and the second information.

[0031] In step S660, the source resistance of the second amplifier 520 is turned on (i.e., the source resistance Rs circuit between the sources of the transistors T1 and T2 is connected), so that the DC gain of the second amplifier 520 is maximized (or the source resistance is minimized), and the offset voltage contributed by the differential input transistor pair of the second amplifier 520 is corrected. The fourth information can be obtained according to the offset voltage contributed by the differential input transistor pair of the second amplifier 520 and the second information.

[0032] Similarly, in this embodiment, the third information and the fourth information can both be digital values ​​and can be written into any form of memory.

[0033] Regarding the above steps S610 to S660, the test machine can be used to obtain the values ​​of the above offset voltages, and the states of the first amplifier and the second amplifier in the analog front-end circuit can be controlled by sending a test command, so as to perform the measurement operations of the offset voltages, and obtain the required information according to the measured offset voltages. Alternatively, in other embodiments of the present invention, a self-test circuit can be built into the chip, and the measurement operations of the offset voltages can be completed by means of built-in self-test, which is not limited in the embodiments of the present invention.

[0034] Please refer to Figure 7 , Figure 7 FIG. 7 is a circuit diagram of an analog front-end circuit according to another embodiment of the present invention. The analog front-end circuit 700 includes a first amplifier 710, a second amplifier 720, a compensation circuit 730, and a compensation circuit 740. The first amplifier 710 is coupled to the rear end of the second amplifier 720. The compensation circuit 730 is coupled to the output end of the second amplifier 720, and the compensation circuit 740 is coupled to the output end of the second amplifier 710. The second amplifier 720 is, for example, a continuous time linear equalizer, and the first amplifier 710 is, for example, a variable gain amplifier.

[0035] correspond Figure 6According to the first information and the second information generated in steps S620 and S630, and the first DC gain and the second DC gain calculated in advance, the first compensation information corresponding to the first amplifier 710 is calculated. The compensation circuit 740 can compensate the output voltage of the first amplifier 710 according to the first compensation information. In addition, according to the third information and the fourth information generated in steps S650 and S650, and the third DC gain and the fourth DC gain calculated in advance, the second compensation information corresponding to the second amplifier 720 is calculated. The compensation circuit 730 can compensate the output voltage of the second amplifier 720 according to the second compensation information.

[0036] In other embodiments of the present invention, the analog front-end circuit 700 may not be provided with the compensation circuit 730, but only with the compensation circuit 740. The third compensation information may be generated according to the first compensation information and the second compensation information. The compensation circuit 740 may perform a one-time compensation operation on the output voltage of the analog front-end circuit 700 according to the third compensation information, thereby effectively saving circuit area.

[0037] Those skilled in the art will appreciate that the method of the present application is not intended to Figure 1 and Figure 6 The specific order described above is a limitation, and it should be understood that in other embodiments, the order of some steps can be interchanged according to actual needs, or some of the steps can be omitted or deleted.

[0038] For the method of generating the compensation information in the above embodiment, please refer to Figure 8 ,in Figure 8 The schematic diagram of the compensation information generating circuit of the analog front-end circuit of the embodiment of the present invention is shown. The compensation information generating circuit 800 includes a memory 810, multipliers 821, 822, 831, 832 and adders 823, 833 and 840. The memory 810 is used to store Figure 6 The first information Vos1 , the second information Vos2 , the third information Vos3 and the fourth information Vos4 of the embodiment. The multipliers 821 , 822 , 831 , 832 are coupled to the memory 810 .

[0039] In operation details, the multiplier 821 receives the first information Vos1 and the first DC gain Pa1, and multiplies the first information Vos1 and the DC gain Pa1 to generate the first data. The multiplier 822 receives the second information Vos2 and the DC gain Pb2, and multiplies the second information Vos2 and the DC gain Pb2 to generate the second data. The adder 823 is coupled to the multipliers 821 and 822. The adder 823 adds the first data and the second data to generate the first compensation information CIF1.

[0040] On the other hand, the multiplier 831 receives the third information Vos3 and the DC gain Pa2, and multiplies the third information Vos3 and the DC gain Pa2 to generate third data. The multiplier 832 receives the fourth information Vos4 and the DC gain Pb2, and multiplies the fourth information Vos4 and the DC gain Pb2 to generate fourth data. The adder 833 is coupled to the multipliers 831 and 832. The adder 833 adds the third data and the fourth data to generate the second compensation information CIF2.

[0041] The adder 840 is coupled to the adders 823 and 833 , and is used for adding the first compensation information CIF1 and the second compensation information CIF2 to generate the compensation information CIF3 .

[0042] In this embodiment, the multipliers 821 , 822 , 831 , 832 and the adders 823 , 833 , and 840 may be multiplication circuits and addition circuits of common digital circuits, without any specific limitation.

[0043] In summary of the above description, the analog front-end circuit of the present invention obtains various parameters by respectively obtaining the offset voltages contributed by the differential input transistor pairs and tail current sources of each amplifier stage, and generates multiple compensation information accordingly. The compensation information can effectively complete the correction of the offset voltage under different gain settings of the analog front-end circuit. The analog front-end circuit of the embodiment of the present invention does not need to use a large amount of storage space to store the correction information corresponding to a variety of different gains, which can effectively reduce the circuit space. In addition, the analog front-end circuit of the embodiment of the present invention does not need to spend a lot of time to perform training actions, which is conducive to improving the efficiency of circuit operation.

[0044] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for correcting an offset voltage, applicable to an analog front-end circuit, characterized in that: include: Acquire a first offset voltage generated by a differential input transistor pair of a first amplifier in the analog front-end circuit, and generate first information according to the first offset voltage; Acquire a second offset voltage generated by a tail current source of the first amplifier in the analog front-end circuit, and generate second information according to the second offset voltage and the first information; Acquire a predetermined first DC gain and a second DC gain, and generate first compensation information according to the first DC gain, the second DC gain, the first information, and the second information; and An output voltage generated by the first amplifier is corrected according to the first compensation information.

2. The calibration method according to claim 1, characterized in that: The method further comprises: The first amplifier is turned off and the output voltage of the comparator is compensated. The comparator is coupled to the rear end of the first amplifier.

3. The calibration method according to claim 1, characterized in that: Generating the first compensation information according to the first DC gain, the second DC gain, the first information, and the second information includes: multiplying the first DC gain by the first information to obtain first data; multiplying the second DC gain and the second information to obtain second data; and The first data and the second data are added together to obtain the first compensation information.

4. The calibration method according to claim 1, characterized in that: The first DC gain is equal to The second DC gain is equal to Wherein gm is the transconductance value of the first amplifier, Rs is the source resistance value in the first amplifier, and RL is the load resistance value of the first amplifier.

5. The calibration method according to claim 1, characterized in that: The method further comprises: Acquire a third offset voltage generated by a tail current source of a second amplifier in the analog front-end circuit, and generate third information according to the third offset voltage and the second information; Acquire a fourth offset voltage generated by a differential input transistor pair of the second amplifier in the analog front-end circuit, and generate fourth information according to the fourth offset voltage and the second information; generating second compensation information according to a predetermined third DC gain, a fourth DC gain, the third information and the fourth information; correcting an output voltage generated by the second amplifier according to the second compensation information, The second amplifier is coupled to the front end of the first amplifier.

6. The calibration method according to claim 5, characterized in that: The method further comprises: The first information, the second information, the third information and the fourth information are written into a memory.

7. An analog front-end circuit, characterized in that: include: First amplifier; A first compensation circuit, coupled to an output terminal of the first amplifier, correcting an output voltage generated by the first amplifier according to first compensation information; as well as a compensation information generator, coupled to the first compensation circuit, generating the first compensation information according to the first DC gain, the second DC gain, the first information and the second information, The first information is generated according to a first offset voltage generated by a differential input transistor pair of the first amplifier, and the second information is generated according to a second offset voltage generated by a tail current source of the first amplifier.

8. The analog front-end circuit according to claim 7, characterized in that: The first compensation circuit comprises: a first current source, coupled between the first output terminal of the first amplifier and a reference ground terminal, and providing a first compensation current to the first output terminal of the first amplifier according to the first compensation information; and The second current source is coupled between the second output terminal of the first amplifier and the reference ground terminal, and provides a second compensation current for the second output terminal of the first amplifier according to the first compensation information.

9. The analog front-end circuit according to claim 7, characterized in that: The compensation information generator comprises: A memory for storing the first information and the second information; a first multiplier, coupled to the memory, multiplying the first DC gain and the first information to generate first data; a second multiplier, coupled to the memory, multiplying the second DC gain and the second information to generate second data; A first adder adds the first data and the second data to generate the first compensation information.

10. The analog front-end circuit according to claim 9, characterized in that: The analog front end circuit also includes: A second amplifier; a second compensation circuit, coupled to the output terminal of the second amplifier, for correcting an output voltage generated by the second amplifier according to second compensation information; and The compensation information generator is coupled to the second compensation circuit and generates the second compensation information according to the third DC gain, the fourth DC gain, the third information and the fourth information. The third information is generated according to a third offset voltage generated by a tail current source of the second amplifier and the second information, and the fourth information is generated according to a fourth offset voltage generated by a differential input transistor pair of the second amplifier and the second information.

11. The analog front-end circuit according to claim 10, characterized in that: The compensation information generator also includes: a third multiplier, coupled to the memory, multiplying the third DC gain and the third information to generate third data; a fourth multiplier, coupled to the memory, and multiplying the fourth DC gain and the fourth information to generate fourth data; and A second adder adds the third data and the fourth data to generate the second compensation information.

12. The analog front-end circuit according to claim 10, characterized in that: The analog front end circuit also includes: A comparator coupled to a rear end of the first amplifier, The second amplifier is coupled to the front end of the first amplifier.

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