Signal processing method and device, equipment and storage medium

Abstract

The invention discloses a signal processing method and device, equipment and a storage medium. The method comprises the following steps: acquiring an input clock signal and a data signal; an input clock signal and a data signal are sampled based on a sampling clock with a set sampling frequency, first sampling data of the input clock signal and second sampling data of the data signal are obtained, the first sampling data and the second sampling data are correspondingly divided into a plurality of point sets, and each point set comprises a plurality of sampling points; overlapping sampling points are included between adjacent point sets; and processing the first sampling data and the second sampling data by adopting a plurality of interpolation engines, wherein a single interpolation engine is used for detecting a specified edge zero crossing point in a partial point set of the first sampling data and calculating a data value at a position corresponding to the specified zero crossing point in the second sampling data. According to the technical scheme, the sampling data is divided into the point sets, the zero crossing points of all the point sets can be rapidly and efficiently positioned through the multiple interpolation engines, the corresponding data values are determined, and therefore real-time signal processing is achieved.

Description

Technical Field

[0001] The present invention relates to the field of signal processing technology, and in particular to a signal processing method, device, equipment and storage medium. Background Art

[0002] For most applications, the signal is sampled in a uniform manner. However, in some specific areas, the sampling clock of the signal is provided in another way and the frequency / period is in a changing state.

[0003] Taking the field of swept frequency optical coherence tomography (OCT) as an example, the output of the photoelectric balanced amplifier is divided into two signals: OCT signal and K clock input signal, where the K clock signal is a sine wave or a square wave. In the running state, the frequency of the K clock signal is constantly changing. The K clock signal provides the most accurate information about the sampling time. The system should obtain the sampling value of the OCT signal at the moment of the K clock changing edge. The obtained OCT signal is subjected to subsequent Fast Fourier Transform (FFT) and other operations to complete the imaging of the image. The entire process of obtaining OCT signals based on the K clock changing edge is called K-space linearization.

[0004] The existing K-space linearization scheme usually samples the K clock signal and the OCT signal using two independent analog-to-digital conversion (ADC) chips (or two independent ADC channels on the same ADC chip) in a uniform sampling manner (satisfying the Nyquist sampling criterion, i.e., the sampling theorem). The sampling clock frequency is fixed and provided by an external clock circuit. The signal obtained by uniform sampling is subsequently processed, that is, the value of the OCT signal corresponding to the moment when the rising edge of the K clock passes through zero is restored by interpolation. This value is the K-space linearized data required for subsequent imaging. However, the existing schemes are inefficient and slow in application and cannot meet the needs of real-time signal processing. Summary of the invention

[0005] The present invention provides a signal processing method, device, equipment and storage medium to solve the problems of low signal processing efficiency, slow speed and inability to process in real time in the prior art.

[0006] In a first aspect, an embodiment of the present invention provides a signal processing method, including:

[0007] Obtain input clock signal and data signal;

[0008] The input clock signal and the data signal are sampled respectively based on a sampling clock with a set sampling frequency to obtain first sampling data of the input clock signal and second sampling data of the data signal, wherein the first sampling data and the second sampling data are correspondingly divided into a plurality of point sets, a single point set contains a plurality of sampling points, and adjacent point sets contain overlapping sampling points;

[0009] Multiple interpolation engines are used to process the first sampling data and the second sampling data, wherein a single interpolation engine is used to detect a specified edge zero crossing point in a partial point set of the first sampling data and calculate a data value at a position corresponding to the specified zero crossing point in the second sampling data.

[0010] Optionally, there is at most one designated edge zero crossing point in a single point set.

[0011] Optionally, the using a plurality of interpolation engines to process the first sampled data and the second sampled data includes:

[0012] A plurality of interpolation engines are used to perform the following operations in parallel to process the first sample data and the second sample data:

[0013] For a single point set, in a first pipeline of a single interpolation engine, the designated edge zero crossing point in the detection interval is obtained by performing multiple interpolations into the detection interval where the designated edge zero crossing point exists and gradually reducing the detection interval according to the results of the multiple interpolations;

[0014] In the second pipeline of the interpolation engine, interpolation is performed at a position in the data interval corresponding to the designated edge zero-crossing point to obtain a data value corresponding to the designated zero-crossing point.

[0015] Optionally, for a single point set, in a first pipeline of a single interpolation engine, obtaining a specified edge zero crossing point in the detection interval by performing multiple interpolations into the detection interval where the specified edge zero crossing point exists and gradually narrowing the detection interval according to the results of the multiple interpolations, comprises:

[0016] For a single point set, in a first pipeline of a single interpolation engine, determining a detection interval where a designated edge zero-crossing point exists in the point set;

[0017] Calculating the signal value at the middle time point of the detection interval according to the interpolation coefficient matrix;

[0018] updating the detection interval based on the signal value, and returning to perform the operation of calculating the signal value at the middle time point of the new detection interval until the detection interval is no greater than the detection time resolution of a single zero crossing point;

[0019] The sampling point closest to zero value in the detection interval is used as the designated edge zero-crossing point.

[0020] Optionally, the number of interpolation engines is greater than or equal to Wherein, L is the number of sampling points that need to be processed in each system operation clock cycle, P is the multiple of the set sampling frequency relative to the input clock signal frequency, Indicates rounding down;

[0021] Each interpolation engine is responsible for at least Zero-crossing detection in the sampling period interval area;

[0022] A single point set contains at least sampling points.

[0023] Optionally, before respectively sampling the input clock signal and the data signal based on a sampling clock with a set sampling frequency, the method further includes:

[0024] If the input clock signal is a square wave signal, the odd harmonic components of the input clock signal are filtered out, and the sinusoidal signal component (fundamental wave) is retained.

[0025] Optionally, the set sampling frequency is greater than twice the fundamental frequency of the input clock signal and greater than twice the bandwidth frequency of the data signal.

[0026] In a second aspect, an embodiment of the present invention provides a signal processing device, including:

[0027] An acquisition module, used for acquiring input clock signals and data signals;

[0028] A sampling module, configured to sample the input clock signal and the data signal respectively based on a sampling clock with a set sampling frequency, to obtain first sampling data of the input clock signal and second sampling data of the data signal, wherein the first sampling data and the second sampling data are correspondingly divided into a plurality of point sets, a single point set contains a plurality of sampling points, and adjacent point sets contain overlapping sampling points;

[0029] A processing module, used to use multiple interpolation engines to process the first sampling data and the second sampling data, wherein a single interpolation engine is used to detect a specified edge zero crossing point in a partial point set of the first sampling data and calculate a data value at a position corresponding to the specified zero crossing point in the second sampling data.

[0030] In a third aspect, an embodiment of the present invention provides a signal processing device, the signal processing device comprising:

[0031] at least one processor; and

[0032] a memory communicatively connected to the at least one processor; wherein,

[0033] The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can perform the signal processing method described in any embodiment of the present invention.

[0034] In a fourth aspect, an embodiment of the present invention provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the signal processing method described in any embodiment of the present invention when executed.

[0035] The technical solution of the embodiment of the present invention obtains an input clock signal and a data signal; samples the input clock signal and the data signal respectively based on a sampling clock with a set sampling frequency to obtain first sampling data of the input clock signal and second sampling data of the data signal, wherein the first sampling data and the second sampling data are correspondingly divided into multiple point sets, a single point set contains multiple sampling points, and adjacent point sets contain overlapping sampling points; multiple interpolation engines are used to process the first sampling data and the second sampling data, wherein a single interpolation engine is used to detect a designated edge zero crossing point in a part of the point sets of the first sampling data and calculate the data value at the position corresponding to the designated zero crossing point in the second sampling data, thereby solving the problems of low signal processing efficiency, slow speed, and inability to process in real time in the prior art. By dividing the sampling data into point sets, multiple interpolation engines can be used to quickly and efficiently locate the zero crossing point of each point set and determine the corresponding data value, thereby realizing real-time processing of the signal.

[0036] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0038] Figure 1 A flowchart of a signal processing method provided in Embodiment 1 of the present invention;

[0039] Figure 2A schematic diagram of point set allocation, zero-crossing point detection and interpolation of a signal processing method provided in Embodiment 1 of the present invention;

[0040] Figure 3 A flowchart of a signal processing method provided in Embodiment 2 of the present invention;

[0041] Figure 4 A zero-crossing point detection and interpolation pipeline diagram of a signal processing method provided in Embodiment 2 of the present invention;

[0042] Figure 5 A schematic diagram of the structure of a signal processing device provided in Embodiment 3 of the present invention;

[0043] Figure 6 A schematic structural diagram of a signal processing device 10 that can be used to implement an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0044] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0045] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0046] Embodiment 1

[0047] Figure 1 This is a flowchart of a signal processing method provided in Embodiment 1 of the present invention. This embodiment is applicable to signal processing. The method can be executed by a signal processing device, which can be implemented in the form of hardware and / or software. Figure 1 As shown, the method includes:

[0048] S110 , obtaining input clock signal and data signal.

[0049] Among them, the input clock signal can refer to a square wave or a sine wave signal, which provides information for the sampling time of the data signal. For example, the change edge of the K clock input signal is the optimal sampling time position of the OCT signal; the data signal can be divided into two types: analog signal and digital signal. In the communication system, the signal representing analog data is called an analog signal, and the signal representing digital data is called a digital signal. The two can be converted into each other.

[0050] In one embodiment, the data signal may be an OCT signal or other signals, as long as it contains valid data, and this embodiment does not limit this.

[0051] In one embodiment, taking the swept frequency OCT application as an example, the K clock signal and the OCT signal can be output by an optoelectronic balanced amplifier and sampled and acquired by a sampling device. Specifically, the sampling can be performed in a uniform sampling manner, which needs to satisfy the Nyquist sampling criterion, that is, the sampling theorem.

[0052] S120. Based on a sampling clock with a set sampling frequency, the input clock signal and the data signal are sampled respectively to obtain first sampling data of the input clock signal and second sampling data of the data signal, wherein the first sampling data and the second sampling data are correspondingly divided into multiple point sets, a single point set contains multiple sampling points, and adjacent point sets contain overlapping sampling points.

[0053] Among them, the set sampling frequency can be a pre-set fixed sampling frequency, which can be provided by an external clock circuit; the sampling clock can be used to sample the input signal; specifically, the input clock signal and the data signal can be sampled separately in a uniform sampling manner through a fixed sampling frequency.

[0054] In one embodiment, the first sampled data may be data obtained by sampling an input clock signal; and the second sampled data may be data obtained by sampling a data signal.

[0055] In one embodiment, the first sampled data and the second sampled data after sampling include a plurality of corresponding sampling points; the point set may be a collection of a plurality of sampling points, and the first sampled data and the second sampled data may be correspondingly divided into a plurality of point sets according to the numerical values ​​of the set sampling frequency and the fundamental frequency of the input clock signal, wherein a single point set includes a plurality of sampling points, and adjacent point sets include overlapping sampling points. For example, there may be 8 sampling points (0-1-2-3-4-5-6-7) in one cycle, and if 5 sampling points are divided into a group, they may be divided into a plurality of different point sets such as (0-1-2-3-4), (2-3-4-5-6), (4-5-6-7-0), etc., a single point set includes a plurality of sampling points, and adjacent point sets include overlapping sampling points.

[0056] S130. Use multiple interpolation engines to process the first sampling data and the second sampling data, wherein a single interpolation engine is used to detect a specified edge zero-crossing point in a partial point set of the first sampling data and calculate a data value at a position corresponding to the specified zero-crossing point in the second sampling data.

[0057] Among them, the interpolation engine can be responsible for zero-crossing monitoring and data value calculation, etc.; the specified edge zero-crossing point can refer to the rising edge zero-crossing point or the falling edge zero-crossing point of the input clock signal, and the data value can be the value of the second sampled data corresponding to the specified edge zero-crossing point in the partial point set of the first sampled data. The interpolation engine can (but is not limited to) use Field Programmable Gate Array (Field Programmable Gate Array, FPGA) logic resources, Graphics Processing Unit (Graphics Processing Unit, GPU) computing core or Central Processing Unit (Central Processing Unit, CPU) computing core implementation (including serial computing, parallel computing, distributed computing).

[0058] In one embodiment, multiple interpolation engines are used to process the first sampled data and the second sampled data. The zero-crossing point detection can be performed by step-by-step binary division to detect the designated edge zero-crossing point in the partial point set of the first sampled data. This not only reduces the amount of calculation, but also improves the calculation speed and data processing throughput. In addition, other interpolation methods are not excluded to determine the edge zero-crossing point, which is not limited in this embodiment. In the process of detecting the zero-crossing point, the area containing the zero-crossing point can be selected in turn by performing multiple interpolations between the sampling points, and the detection range can be gradually narrowed; and the value corresponding to each insertion point can be determined according to the interpolation coefficient matrix, so as to efficiently and quickly locate the time position of the designated edge zero-crossing point of the sampled input clock signal, and obtain the data value of the sampled data signal corresponding to the time position.

[0059] In this embodiment, the input clock signal and the data signal can be obtained; the input clock signal and the data signal are sampled based on a sampling clock with a set sampling frequency to obtain first sampling data of the input clock signal and second sampling data of the data signal, wherein the first sampling data and the second sampling data are correspondingly divided into multiple point sets, a single point set contains multiple sampling points, and adjacent point sets contain overlapping sampling points; multiple interpolation engines are used to process the first sampling data and the second sampling data, wherein a single interpolation engine is used to detect the designated edge zero crossing point in some point sets of the first sampling data and calculate the data value at the position corresponding to the designated zero crossing point in the second sampling data, which solves the problems of low signal processing efficiency, slow speed and inability to process in real time in the prior art. By dividing the sampling data into point sets, multiple interpolation engines can be used to quickly and efficiently locate the zero crossing point of each point set and determine the corresponding data value, thereby realizing real-time processing of the signal.

[0060] Optionally, there is at most one designated edge zero crossing point in a single point set.

[0061] Specifically, after the input clock signal and the data signal are sampled respectively based on the sampling clock of the set sampling frequency, multiple input clock signal sampling points (i.e., first sampling data) and data signal sampling points (i.e., second sampling data) will be received. The sampling data can be divided according to the numerical values ​​of the sampling clock frequency and the fundamental frequency of the input clock signal into multiple overlapping point sets. The principle of division is to ensure that at most one input clock signal rising edge zero crossing point is allowed in a single point. For example, the number of sampling points can be 8 or 16, which can be represented as L. In order to achieve the purpose of real-time processing, each system operation clock cycle should process data of L sampling cycles, which can include L input clock signal sampling values ​​(i.e., first sampling data values) and L data signal sampling values ​​(i.e., second sampling data values).

[0062] In one embodiment, based on the interpolation coefficient matrix, the value between the two middle points can be interpolated from the four points to perform zero-crossing detection and data signal interpolation. The interpolation between the last few data of the current cycle needs to be combined with the first few sampling points of the next cycle for processing. Figure 2 As shown, Figure 2 A schematic diagram of point set allocation, zero-crossing point detection and interpolation of a signal processing method provided in Embodiment 1 of the present invention is provided, wherein four zero-crossing point detection and interpolation modules (i.e., interpolation engines) are introduced, and each interpolation engine is responsible for zero-crossing point monitoring of two sections. Based on the Nyquist sampling criterion that needs to be satisfied, there can only be at most one section containing one rising edge zero-crossing point. Table 1 shows the sampling points and interpolation areas involved in the interpolation engine operation.

[0063] Table 1 Sampling points and interpolation areas involved in interpolation engine calculations

[0064]

[0065] Optionally, before respectively sampling the input clock signal and the data signal based on a sampling clock with a set sampling frequency, the method further includes:

[0066] If the input clock signal is a square wave signal, it is necessary to filter out the odd harmonic components of the input clock signal and retain the sinusoidal signal component (fundamental wave).

[0067] Among them, square wave signal can refer to a signal in a circuit system that can be transmitted from the source end to the receiving end without distortion within the required time; harmonic can refer to a signal with a frequency higher than the main signal frequency (that is, the fundamental frequency). Harmonic is a sine wave, each harmonic has a different frequency, and the harmonic frequency is an integer multiple of the fundamental frequency. Any repetitive waveform can be decomposed into a sine wave component containing the fundamental frequency and a series of harmonics that are multiples of the fundamental frequency. The sinusoidal signal can also be called the fundamental wave; when the frequency of the harmonic signal is an odd multiple of the fundamental signal frequency (such as 150 is three times 50, and three is an odd number), the harmonic is called an odd harmonic.

[0068] In one embodiment, before sampling the input clock signal and the data signal, it is necessary to pay attention to the characteristics of the original input clock signal. If it is a square wave signal, there will be an infinite number of odd harmonic components, such as a 300MHz K clock square wave signal, whose harmonic components are 300MHz (fundamental wave, first harmonic), 900MHz (third harmonic), 1500Mz (fifth harmonic), etc. In order to ensure the accuracy of the subsequent zero-crossing point detection, the input clock signal and the data signal can be first passed through a low-pass filter (Low Pass Filter, LPF) to retain the bandwidth of the useful signal and complete the anti-aliasing function; the stop band of the low-pass filter of the input clock signal can filter out harmonic components such as the third harmonic and the fifth harmonic, and the pass band retains the 300MHz sinusoidal signal component. Further, the useful signal bandwidth of the data signal will not exceed 1 / 2 of the input clock signal frequency to meet the requirements of the sampling theorem. Taking the above 300MHz K clock input signal as an example, the bandwidth of the data signal will be less than 150MHz (for example, 0 to 140MHz).

[0069] Optionally, the set sampling frequency is greater than twice the fundamental frequency of the input clock signal and greater than twice the bandwidth frequency of the data signal.

[0070] Among them, the fundamental frequency can refer to the frequency of the sinusoidal wave component equal to the longest period of signal oscillation; the frequency bandwidth can refer to the frequency corresponding to when the closed-loop amplitude-frequency characteristic drops to a specified value.

[0071] In one embodiment, the input clock signal and data signal after low-pass filtering are used as signal inputs for analog-to-digital conversion (ADC). The sampling clock of the analog-to-digital conversion ADC is a fixed-frequency sampling clock. In order to meet the requirements of the Nyquist criterion, the frequency of the sampling clock should be greater than twice the fundamental frequency of the input clock signal and the bandwidth frequency of the data signal. Taking a 300MHz input clock signal and a 0-140MHz data signal as an example, the sampling rate of the analog-to-digital conversion ADC should be higher than 600MSps to meet the requirements of the Nyquist criterion.

[0072] A signal processing method provided by an embodiment of the present invention comprises: a single point set contains at most one designated edge zero-crossing point, which can be guaranteed by the Nyquist sampling criterion; before the input clock signal and the data signal are sampled respectively based on a sampling clock with a set sampling frequency, the method further comprises: if the input clock signal is a square wave signal, the odd harmonic components of the input clock signal are filtered out, and the sinusoidal signal components are retained to complete the anti-aliasing function, thereby ensuring the accuracy of subsequent zero-crossing point detection; the set sampling frequency is greater than twice the fundamental frequency of the input clock signal, and greater than twice the bandwidth frequency of the data signal, also to meet the requirements of the Nyquist sampling criterion.

[0073] Embodiment 2

[0074] Figure 3 This is a flow chart of a signal processing method provided in Embodiment 2 of the present invention. The technical solution of this embodiment is further refined on the basis of the above embodiment. Figure 3 As shown, the method of this embodiment may include the following steps:

[0075] S210 , obtaining input clock signal and data signal.

[0076] S220, based on a sampling clock with a set sampling frequency, the input clock signal and the data signal are sampled respectively to obtain first sampling data of the input clock signal and second sampling data of the data signal, wherein the first sampling data and the second sampling data are correspondingly divided into multiple point sets, a single point set contains multiple sampling points, and adjacent point sets contain overlapping sampling points.

[0077] S230. Use multiple interpolation engines to process the first sampling data and the second sampling data, wherein a single interpolation engine is used to detect a specified edge zero-crossing point in a partial point set of the first sampling data and calculate a data value at a position corresponding to the specified zero-crossing point in the second sampling data.

[0078] Wherein, a plurality of interpolation engines are used to perform the following operations in parallel to process the first sampled data and the second sampled data:

[0079] S2310. For a single point set, in the first pipeline of a single interpolation engine, the specified edge zero crossing point in the detection interval is obtained by multiple interpolation into the detection interval where the specified edge zero crossing point exists and gradually narrowing the detection interval according to the results of the multiple interpolation.

[0080] Among them, the pipeline can be understood as a processing process, and the detection interval can refer to an interval that can detect the specified edge zero crossing point; the detection interval can be changed, and by multiple interpolation into the detection interval where the specified edge zero crossing point exists, the detection interval can be gradually narrowed according to the results of multiple interpolation, thereby determining the specified edge zero crossing point in the detection interval. Figure 4 A zero-crossing point detection and interpolation pipeline diagram of a signal processing method provided in Embodiment 2 of the present invention, such as Figure 4 As shown, at the beginning of the pipeline, by first judging the relationship between the input clock signal sampling points 1 / 2 / 3 and the 0 level, it is found that the value of sampling point 2 is less than 0 and the value of sampling point 3 is greater than 0. It can be judged that the rising edge zero crossing occurs in the time area between sampling points 2 and 3 (i.e., the detection interval is determined). In the next cycle, when the input clock signal pipeline (first pipeline) enters the c0 stage, sampling points 1 / 2 / 3 / 4 will be selected. Correspondingly, when the OCT (data) signal pipeline enters the d0 stage, sampling points 1 / 2 / 3 / 4 will also be selected. The two pipelines are parallel and corresponding. Through the first-level processing, the sampling points to be processed are reduced from 5 to 4, and the number of zero-crossing detection areas is halved. In the next step, the interpolation value I0 of the intermediate time point can be interpolated to determine whether I0 is greater than 0, and the new detection interval is determined again. Specifically, when I0 is greater than 0, the I0 time position point will become the upper limit of the new detection interval, otherwise, it will become the lower limit of the interval. The new detection interval range is always smaller than the original detection interval. Then, the middle time point of the new detection interval is interpolated again until it converges to the following constraint: upper_phase=low_phase+1, where low_phase and upper_phase are the lower and upper limits of the interval where the current zero-crossing point is located, and both are integers; the interpolation value of the corresponding position of low_phase and upper_phase is determined to be closer to zero, which is final_phase (the final position of the zero-crossing point).

[0081] S2320. In the second pipeline of the interpolation engine, interpolate to the position in the data interval corresponding to the designated edge zero-crossing point to obtain a data value corresponding to the designated zero-crossing point.

[0082] Because of parallel processing, Figure 4 As shown, when the input clock signal pipeline enters the c1 stage from the c0 stage, at the same time, the OCT signal pipeline (the second pipeline) enters the d1 stage from the d0 stage, and the OCT signal pipeline does not perform any processing (from d0, d1 to last_stage); when determining the final rising edge zero crossing point position (final_phase), the OCT signal pipeline at the last stage will interpolate the final_phase value to obtain the OCT signal value (final_oct_value) at the rising edge zero crossing point.

[0083] In this embodiment, multiple interpolation engines are used to process the first sampled data and the second sampled data in parallel, thereby further improving the bandwidth and making full use of the advantages brought by the highly parallel architecture of the Field-Programmable Gate Array (FPGA) / Graphics Processing Unit (GPU).

[0084] Optionally, for a single point set, in a first pipeline of a single interpolation engine, obtaining a specified edge zero crossing point in the detection interval by performing multiple interpolations into the detection interval where the specified edge zero crossing point exists and gradually narrowing the detection interval according to the results of the multiple interpolations, comprises:

[0085] For a single point set, in a first pipeline of a single interpolation engine, determining a detection interval where a designated edge zero-crossing point exists in the point set;

[0086] Calculating the signal value at the middle time point of the detection interval according to the interpolation coefficient matrix;

[0087] updating the detection interval based on the signal value, and returning to perform the operation of calculating the signal value at the middle time point of the new detection interval until the detection interval is no greater than the detection time resolution of a single zero crossing point;

[0088] The sampling point closest to zero value in the detection interval is used as the designated edge zero-crossing point.

[0089] Among them, the interpolation coefficient matrix can be constructed in many ways; the detection time resolution refers to the minimum time interval between two adjacent zero-crossing point detections in the same area; the number of rows in the interpolation coefficient matrix is ​​related to the detection resolution, and the number of columns is related to the number of sampling reference points used; for example, the matrix can be:

[0090] [a11,a12,a13,a14]

[0091] [a21,a22,a23,a24]

[0092] …

[0093] [a14,a13,a12,a11]

[0094] [a24,a23,a22,a21]

[0095] The interpolation value is calculated as follows: where Y k represents the interpolation result at the position corresponding to the kth row of the interpolation coefficient matrix, M kj is the element value of the kth row and jth column in the interpolation coefficient matrix, C j Represents the value of the jth sampling reference point.

[0096] For example, the detection interval with a specified edge zero crossing point should satisfy: the value of the starting point is greater than 0 and the value of the end point is less than 0, or the value of the starting point is less than 0 and the value of the end point is greater than 0. For example, if the input clock signal sampling points are ABCDE, the detection interval with a specified edge (taking the rising edge as an example) zero crossing point is selected based on the following principles:

[0097] When the value of sampling point B is less than or equal to 0 and the value of sampling point C is greater than or equal to 0, the area between sampling point B and sampling point C is selected for subsequent zero-crossing point detection (the points involved in the operation are ABCD);

[0098] When the value of sampling point C is less than or equal to 0 and the value of sampling point D is greater than or equal to 0, the area between sampling point C and sampling point D is selected for subsequent zero-crossing point detection (the points involved in the operation are ABCD);

[0099] If none of the above conditions are met, it is determined that there is no zero crossing point and the subsequent process is skipped without further processing.

[0100] Optionally, the (interpolation) time resolution (or accuracy) of zero-crossing detection is defined as the sampling period divided by (the number of interpolation points in a single sampling period + 1). Take the case of dividing adjacent sampling points into 16 equal parts (i.e., the time resolution is ΔT / 16) as an example. The interpolation coefficient matrix has 17 rows in total. The four numbers in the first row are multiplied by the ordinates of the sampling points A\B\C\D, respectively, to obtain the ordinate of point B; the four numbers in the last row are multiplied by the ordinates of the sampling points A\B\C\D, respectively, to obtain the ordinate of point C; taking binary interpolation as an example, each time the interpolation is performed in the middle of the current detection interval, then in the BC interval, the first interpolation is equivalent to multiplying the four numbers in the middle row (9th row) of the interpolation coefficient matrix by the ordinates of the sampling points A\B\C\D, respectively. , the obtained value is the ordinate of the midpoint of BC; the next interpolation is equivalent to multiplying the four numbers in the middle row (it may be the middle row between the first row and the 9th row, or the middle row between the 9th row and the last row, depending on whether the zero-crossing point is before or after the previous interpolation point) with the ordinates of the sampling points A\B\C\D respectively to obtain the interpolation result; and so on, until the detection interval is not greater than the minimum time interval for detecting a single zero-crossing point; the sampling point in the detection interval that is closest to zero is taken as the designated edge zero-crossing point.

[0101] In one embodiment, the number of interpolation engines is greater than or equal to Wherein, L is the number of sampling points that need to be processed in each system operation clock cycle, P is the multiple of the set sampling frequency relative to the input clock signal frequency, Indicates rounding down;

[0102] Each interpolation engine is responsible for at least Zero-crossing detection in the sampling period interval area;

[0103] A single point set contains at least sampling points.

[0104] It can be understood that if each system running clock cycle can generate L sampling points, under the premise of satisfying the Nyquist sampling theorem, to achieve the effect of real-time processing, when the sampling frequency Fs is greater than P times the clock frequency, at least Zero-crossing detection and interpolation modules, each interpolation engine is responsible for Furthermore, if the sampling frequency Fs is P times the input clock frequency (P>=2), the adjacent The interval area of ​​the segment sampling points (if P is not an integer, it is rounded down) can only have at most one rising edge zero crossing point. The zero crossing detection and interpolation can process at least one point set per clock cycle. sampling points.

[0105] A signal processing method provided in the second embodiment of the present invention further improves the bandwidth by using multiple interpolation engines to process the first sampling data and the second sampling data in parallel, and fully utilizes the advantages brought by the highly parallel computing architecture of the field programmable gate array (Field-Programmable Gate Array, FPGA) / graphics processing unit (Graphics Processing Unit, GPU); fully utilizes the position distribution constraint on the zero-crossing detection area guaranteed by the Nyquist sampling criterion, directly selects sampling points from the point set for subsequent pipeline processing, and reduces the detection and interpolation area required for each zero-crossing detection and interpolation to 1; in addition, due to the introduction of the step-by-step binary pipeline architecture, the hardware resource consumption and the required zero-crossing detection (interpolation) time resolution are in a log relationship: when the zero-crossing detection time resolution (precision) is ΔT / N, only log 2 The detection of the rising edge zero crossing point can be completed by updating the interval in N steps. Only one more stage of the pipeline is needed to double the accuracy (for example, from ΔT / 32 to ΔT / 64). At the same time, when dealing with a larger bandwidth (that is, when the number of sampling points to be processed in each system running clock cycle increases, such as from 8 points to 16 points or a higher number), it is only necessary to increase the number of zero crossing detection and interpolation engines accordingly. Through the above technical solution, real-time computing and processing are achieved with good scalability.

[0106] Embodiment 3

[0107] Figure 5 FIG. 1 is a schematic diagram of a signal processing device provided in Embodiment 3 of the present invention. Figure 5 As shown, the device comprises:

[0108] The acquisition module 310 is used to acquire input clock signals and data signals.

[0109] The sampling module 320 is used to sample the input clock signal and the data signal respectively based on a sampling clock with a set sampling frequency to obtain first sampling data of the input clock signal and second sampling data of the data signal, wherein the first sampling data and the second sampling data are correspondingly divided into multiple point sets, a single point set contains multiple sampling points, and adjacent point sets contain overlapping sampling points.

[0110] The processing module 330 is used to use multiple interpolation engines to process the first sampling data and the second sampling data, wherein a single interpolation engine is used to detect a specified edge zero crossing point in a partial point set of the first sampling data and calculate the data value at a position corresponding to the specified zero crossing point in the second sampling data.

[0111] Optionally, there is at most one designated edge zero crossing point in a single point set.

[0112] Optionally, the processing module 330 is specifically configured to:

[0113] A plurality of interpolation engines are used to perform the following operations in parallel to process the first sample data and the second sample data:

[0114] For a single point set, in a first pipeline of a single interpolation engine, the designated edge zero crossing point in the detection interval is obtained by performing multiple interpolations into the detection interval where the designated edge zero crossing point exists and gradually reducing the detection interval according to the results of the multiple interpolations;

[0115] In the second pipeline of the interpolation engine, interpolation is performed at a position in the data interval corresponding to the designated edge zero-crossing point to obtain a data value corresponding to the designated zero-crossing point.

[0116] Optionally, for a single point set, in a first pipeline of a single interpolation engine, obtaining a specified edge zero crossing point in the detection interval by performing multiple interpolations into the detection interval where the specified edge zero crossing point exists and gradually narrowing the detection interval according to the results of the multiple interpolations, comprises:

[0117] For a single point set, in a first pipeline of a single interpolation engine, determining a detection interval where a designated edge zero-crossing point exists in the point set;

[0118] Calculating the signal value at the middle time point of the detection interval according to the interpolation coefficient matrix;

[0119] updating the detection interval based on the signal value, and returning to perform the operation of calculating the signal value at the middle time point of the new detection interval until the detection interval is no greater than the detection time resolution of a single zero crossing point;

[0120] The sampling point closest to zero value in the detection interval is used as the designated edge zero-crossing point.

[0121] Optionally, the number of interpolation engines is greater than or equal to Wherein, L is the number of sampling points that need to be processed in each system operation clock cycle, P is the multiple of the set sampling frequency relative to the input clock signal frequency, Indicates rounding down;

[0122] Each interpolation engine is responsible for at least Zero-crossing detection in the sampling period interval area;

[0123] A single point set contains at least sampling points.

[0124] Optionally, before respectively sampling the input clock signal and the data signal based on a sampling clock with a set sampling frequency, the method further includes:

[0125] If the input clock signal is a square wave signal, it is necessary to filter out the odd harmonic components of the input clock signal and retain the sinusoidal signal components.

[0126] Optionally, the set sampling frequency is greater than twice the fundamental frequency of the input clock signal and greater than twice the bandwidth frequency of the data signal.

[0127] The signal processing device provided in the embodiment of the present invention can execute the signal processing method provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the execution method.

[0128] Embodiment 4

[0129] Figure 6 A schematic diagram of a signal processing device 10 that can be used to implement an embodiment of the present invention is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices (such as helmets, glasses, watches, etc.) and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present invention described and / or required herein.

[0130] like Figure 6 As shown, the signal processing device 10 includes at least one processor 11, and a memory connected to the at least one processor 11, such as a read-only memory (ROM) 12, a random access memory (RAM) 13, etc., wherein the memory stores a computer program executable by the at least one processor 11, and the computer program is executed by the at least one processor 11 so that the at least one processor 11 can execute the method provided by the present invention.

[0131] The processor 11 can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 12 or a computer program loaded from a storage unit 18 into a random access memory (RAM) 13. In the RAM 13, various programs and data required for the operation of the electronic device 10 can also be stored. The processor 11, the ROM 12, and the RAM 13 are connected to each other via a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0132] A number of components in the signal processing device 10 are connected to the I / O interface 15, including: an input unit 16, such as a keyboard, a mouse, etc.; an output unit 17, such as various types of displays, speakers, etc.; a storage unit 18, such as a disk, an optical disk, etc.; and a communication unit 19, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 19 allows the electronic device 10 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0133] The processor 11 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. The processor 11 performs the various methods and processes described above, such as a signal processing method.

[0134] In some embodiments, the signal processing method may be implemented as a computer program, which is tangibly contained in a computer-readable storage medium, such as a storage unit 18. In some embodiments, part or all of the computer program may be loaded and / or installed on the electronic device 10 via the ROM 12 and / or the communication unit 19. When the computer program is loaded into the RAM 13 and executed by the processor 11, one or more steps of the signal processing method described above may be performed. Alternatively, in other embodiments, the processor 11 may be configured to perform the signal processing method in any other appropriate manner (e.g., by means of firmware).

[0135] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard parts (ASSPs), systems on chips (SOCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0136] Computer programs for implementing the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that when the computer program is executed by the processor, the functions / operations specified in the flow chart and / or block diagram are implemented. The computer program may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0137] In the context of the present invention, a computer-readable storage medium stores computer instructions, which are used to implement the signal processing method provided by the present invention when the processor executes. The computer-readable storage medium can be a tangible medium, which can contain or store a computer program for use by an instruction execution system, device or equipment or used in combination with an instruction execution system, device or equipment. The computer-readable storage medium can include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices or equipment, or any suitable combination of the above. Alternatively, the computer-readable storage medium can be a machine-readable signal medium. A more specific example of a machine-readable storage medium can include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0138] To provide interaction with a user, the systems and techniques described herein may be implemented on an electronic device having: a display device (e.g., a cathode ray tube (CRT) or a liquid crystal display (LCD monitor)) for displaying information to the user; and a keyboard and a pointing device (e.g., a mouse or a trackball), through which the user may provide input to the electronic device. Other types of devices may also be used to provide interaction with the user; for example, the feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form (including acoustic input, voice input, or tactile input).

[0139] The systems and techniques described herein can be implemented in a computing system that includes backend components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes frontend components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such backend components, middleware components, or frontend components. The components of the system can be interconnected by digital data communication (e.g., a communication network) in any form or medium. Examples of communication networks include: Local Area Network (LAN), Wide Area Network (WAN), blockchain network, and the Internet.

[0140] A computing system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The relationship between the client and the server is generated by computer programs running on the corresponding computers and having a client-server relationship with each other. The server may be a cloud server, also known as a cloud computing server or cloud host, which is a host product in the cloud computing service system to solve the defects of difficult management and weak business scalability in traditional physical hosts and virtual private servers (VPS) services.

[0141] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0142] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A signal processing method, characterized in that: include: Obtain input clock signal and data signal; The input clock signal and the data signal are sampled respectively based on a sampling clock with a set sampling frequency to obtain first sampling data of the input clock signal and second sampling data of the data signal, wherein the first sampling data and the second sampling data are correspondingly divided into a plurality of point sets, a single point set contains a plurality of sampling points, and adjacent point sets contain overlapping sampling points; Multiple interpolation engines are used to process the first sampling data and the second sampling data, wherein a single interpolation engine is used to detect a specified edge zero crossing point in a partial point set of the first sampling data and calculate a data value at a position corresponding to the specified zero crossing point in the second sampling data.

2. The method according to claim 1, characterized in that There is at most one designated edge zero crossing point in a single said point set.

3. The method according to claim 1, characterized in that The using a plurality of interpolation engines to process the first sampled data and the second sampled data comprises: A plurality of interpolation engines are used to perform the following operations in parallel to process the first sample data and the second sample data: For a single point set, in a first pipeline of a single interpolation engine, the designated edge zero crossing point in the detection interval is obtained by performing multiple interpolations into the detection interval where the designated edge zero crossing point exists and gradually reducing the detection interval according to the results of the multiple interpolations; In the second pipeline of the interpolation engine, interpolation is performed at a position in the data interval corresponding to the designated edge zero-crossing point to obtain a data value corresponding to the designated zero-crossing point.

4. The method according to claim 3, characterized in that For a single point set, in a first pipeline of a single interpolation engine, by performing multiple interpolations into a detection interval where a specified edge zero crossing point exists and gradually reducing the detection interval according to the results of the multiple interpolations, the specified edge zero crossing point in the detection interval is obtained, including: For a single point set, in a first pipeline of a single interpolation engine, determining a detection interval where a designated edge zero-crossing point exists in the point set; Calculating the signal value at the middle time point of the detection interval according to the interpolation coefficient matrix; updating the detection interval based on the signal value, and returning to perform the operation of calculating the signal value at the middle time point of the new detection interval until the detection interval is no greater than the detection time resolution of a single zero crossing point; The sampling point closest to zero value in the detection interval is used as the designated edge zero-crossing point.

5. The method according to claim 3, characterized in that: The number of interpolation engines is greater than or equal to Wherein, L is the number of sampling points that need to be processed in each system operation clock cycle, P is the multiple of the set sampling frequency relative to the input clock signal frequency, Indicates rounding down; Each interpolation engine is responsible for at least Zero-crossing detection in the sampling period interval area; A single point set contains at least sampling points.

6. The method according to claim 1, characterized in that Before respectively sampling the input clock signal and the data signal based on a sampling clock with a set sampling frequency, the method further includes: If the input clock signal is a square wave signal, the odd harmonic components of the input clock signal are filtered out and the sinusoidal signal components are retained.

7. The method according to claim 1, characterized in that The set sampling frequency is greater than twice the fundamental frequency of the input clock signal and greater than twice the bandwidth frequency of the data signal.

8. A signal processing device, characterized in that: include: An acquisition module, used for acquiring input clock signals and data signals; A sampling module, configured to sample the input clock signal and the data signal respectively based on a sampling clock with a set sampling frequency, to obtain first sampling data of the input clock signal and second sampling data of the data signal, wherein the first sampling data and the second sampling data are correspondingly divided into a plurality of point sets, a single point set contains a plurality of sampling points, and adjacent point sets contain overlapping sampling points; A processing module, used to use multiple interpolation engines to process the first sampling data and the second sampling data, wherein a single interpolation engine is used to detect a specified edge zero crossing point in a partial point set of the first sampling data and calculate a data value at a position corresponding to the specified zero crossing point in the second sampling data.

9. A signal processing device, characterized in that: include: at least one processor; as well as a memory communicatively connected to the at least one processor; wherein, The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can perform the signal processing method according to any one of claims 1 to 7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the signal processing method according to any one of claims 1 to 7 is implemented.

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